1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
5 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
8 #include <linux/module.h>
9 #include <linux/of_device.h>
10 #include <linux/delay.h>
11 #include <linux/mmc/mmc.h>
12 #include <linux/pm_runtime.h>
13 #include <linux/slab.h>
14 #include <linux/iopoll.h>
15 #include <linux/regulator/consumer.h>
17 #include "sdhci-pltfm.h"
19 #define CORE_MCI_VERSION 0x50
20 #define CORE_VERSION_MAJOR_SHIFT 28
21 #define CORE_VERSION_MAJOR_MASK (0xf << CORE_VERSION_MAJOR_SHIFT)
22 #define CORE_VERSION_MINOR_MASK 0xff
24 #define CORE_MCI_GENERICS 0x70
25 #define SWITCHABLE_SIGNALING_VOLTAGE BIT(29)
27 #define HC_MODE_EN 0x1
28 #define CORE_POWER 0x0
29 #define CORE_SW_RST BIT(7)
30 #define FF_CLK_SW_RST_DIS BIT(13)
32 #define CORE_PWRCTL_BUS_OFF BIT(0)
33 #define CORE_PWRCTL_BUS_ON BIT(1)
34 #define CORE_PWRCTL_IO_LOW BIT(2)
35 #define CORE_PWRCTL_IO_HIGH BIT(3)
36 #define CORE_PWRCTL_BUS_SUCCESS BIT(0)
37 #define CORE_PWRCTL_IO_SUCCESS BIT(2)
38 #define REQ_BUS_OFF BIT(0)
39 #define REQ_BUS_ON BIT(1)
40 #define REQ_IO_LOW BIT(2)
41 #define REQ_IO_HIGH BIT(3)
44 #define CORE_DLL_LOCK BIT(7)
45 #define CORE_DDR_DLL_LOCK BIT(11)
46 #define CORE_DLL_EN BIT(16)
47 #define CORE_CDR_EN BIT(17)
48 #define CORE_CK_OUT_EN BIT(18)
49 #define CORE_CDR_EXT_EN BIT(19)
50 #define CORE_DLL_PDN BIT(29)
51 #define CORE_DLL_RST BIT(30)
52 #define CORE_CMD_DAT_TRACK_SEL BIT(0)
54 #define CORE_DDR_CAL_EN BIT(0)
55 #define CORE_FLL_CYCLE_CNT BIT(18)
56 #define CORE_DLL_CLOCK_DISABLE BIT(21)
58 #define CORE_VENDOR_SPEC_POR_VAL 0xa1c
59 #define CORE_CLK_PWRSAVE BIT(1)
60 #define CORE_HC_MCLK_SEL_DFLT (2 << 8)
61 #define CORE_HC_MCLK_SEL_HS400 (3 << 8)
62 #define CORE_HC_MCLK_SEL_MASK (3 << 8)
63 #define CORE_IO_PAD_PWR_SWITCH_EN (1 << 15)
64 #define CORE_IO_PAD_PWR_SWITCH (1 << 16)
65 #define CORE_HC_SELECT_IN_EN BIT(18)
66 #define CORE_HC_SELECT_IN_HS400 (6 << 19)
67 #define CORE_HC_SELECT_IN_MASK (7 << 19)
69 #define CORE_3_0V_SUPPORT (1 << 25)
70 #define CORE_1_8V_SUPPORT (1 << 26)
71 #define CORE_VOLT_SUPPORT (CORE_3_0V_SUPPORT | CORE_1_8V_SUPPORT)
73 #define CORE_CSR_CDC_CTLR_CFG0 0x130
74 #define CORE_SW_TRIG_FULL_CALIB BIT(16)
75 #define CORE_HW_AUTOCAL_ENA BIT(17)
77 #define CORE_CSR_CDC_CTLR_CFG1 0x134
78 #define CORE_CSR_CDC_CAL_TIMER_CFG0 0x138
79 #define CORE_TIMER_ENA BIT(16)
81 #define CORE_CSR_CDC_CAL_TIMER_CFG1 0x13C
82 #define CORE_CSR_CDC_REFCOUNT_CFG 0x140
83 #define CORE_CSR_CDC_COARSE_CAL_CFG 0x144
84 #define CORE_CDC_OFFSET_CFG 0x14C
85 #define CORE_CSR_CDC_DELAY_CFG 0x150
86 #define CORE_CDC_SLAVE_DDA_CFG 0x160
87 #define CORE_CSR_CDC_STATUS0 0x164
88 #define CORE_CALIBRATION_DONE BIT(0)
90 #define CORE_CDC_ERROR_CODE_MASK 0x7000000
92 #define CORE_CSR_CDC_GEN_CFG 0x178
93 #define CORE_CDC_SWITCH_BYPASS_OFF BIT(0)
94 #define CORE_CDC_SWITCH_RC_EN BIT(1)
96 #define CORE_CDC_T4_DLY_SEL BIT(0)
97 #define CORE_CMDIN_RCLK_EN BIT(1)
98 #define CORE_START_CDC_TRAFFIC BIT(6)
100 #define CORE_PWRSAVE_DLL BIT(3)
102 #define DDR_CONFIG_POR_VAL 0x80040873
105 #define INVALID_TUNING_PHASE -1
106 #define SDHCI_MSM_MIN_CLOCK 400000
107 #define CORE_FREQ_100MHZ (100 * 1000 * 1000)
109 #define CDR_SELEXT_SHIFT 20
110 #define CDR_SELEXT_MASK (0xf << CDR_SELEXT_SHIFT)
111 #define CMUX_SHIFT_PHASE_SHIFT 24
112 #define CMUX_SHIFT_PHASE_MASK (7 << CMUX_SHIFT_PHASE_SHIFT)
114 #define MSM_MMC_AUTOSUSPEND_DELAY_MS 50
116 /* Timeout value to avoid infinite waiting for pwr_irq */
117 #define MSM_PWR_IRQ_TIMEOUT_MS 5000
119 #define msm_host_readl(msm_host, host, offset) \
120 msm_host->var_ops->msm_readl_relaxed(host, offset)
122 #define msm_host_writel(msm_host, val, host, offset) \
123 msm_host->var_ops->msm_writel_relaxed(val, host, offset)
125 struct sdhci_msm_offset {
127 u32 core_mci_data_cnt;
129 u32 core_mci_fifo_cnt;
130 u32 core_mci_version;
132 u32 core_testbus_config;
133 u32 core_testbus_sel2_bit;
134 u32 core_testbus_ena;
135 u32 core_testbus_sel2;
136 u32 core_pwrctl_status;
137 u32 core_pwrctl_mask;
138 u32 core_pwrctl_clear;
140 u32 core_sdcc_debug_reg;
143 u32 core_vendor_spec;
144 u32 core_vendor_spec_adma_err_addr0;
145 u32 core_vendor_spec_adma_err_addr1;
146 u32 core_vendor_spec_func2;
147 u32 core_vendor_spec_capabilities0;
148 u32 core_ddr_200_cfg;
149 u32 core_vendor_spec3;
150 u32 core_dll_config_2;
151 u32 core_dll_config_3;
152 u32 core_ddr_config_old; /* Applicable to sdcc minor ver < 0x49 */
156 static const struct sdhci_msm_offset sdhci_msm_v5_offset = {
157 .core_mci_data_cnt = 0x35c,
158 .core_mci_status = 0x324,
159 .core_mci_fifo_cnt = 0x308,
160 .core_mci_version = 0x318,
161 .core_generics = 0x320,
162 .core_testbus_config = 0x32c,
163 .core_testbus_sel2_bit = 3,
164 .core_testbus_ena = (1 << 31),
165 .core_testbus_sel2 = (1 << 3),
166 .core_pwrctl_status = 0x240,
167 .core_pwrctl_mask = 0x244,
168 .core_pwrctl_clear = 0x248,
169 .core_pwrctl_ctl = 0x24c,
170 .core_sdcc_debug_reg = 0x358,
171 .core_dll_config = 0x200,
172 .core_dll_status = 0x208,
173 .core_vendor_spec = 0x20c,
174 .core_vendor_spec_adma_err_addr0 = 0x214,
175 .core_vendor_spec_adma_err_addr1 = 0x218,
176 .core_vendor_spec_func2 = 0x210,
177 .core_vendor_spec_capabilities0 = 0x21c,
178 .core_ddr_200_cfg = 0x224,
179 .core_vendor_spec3 = 0x250,
180 .core_dll_config_2 = 0x254,
181 .core_dll_config_3 = 0x258,
182 .core_ddr_config = 0x25c,
185 static const struct sdhci_msm_offset sdhci_msm_mci_offset = {
186 .core_hc_mode = 0x78,
187 .core_mci_data_cnt = 0x30,
188 .core_mci_status = 0x34,
189 .core_mci_fifo_cnt = 0x44,
190 .core_mci_version = 0x050,
191 .core_generics = 0x70,
192 .core_testbus_config = 0x0cc,
193 .core_testbus_sel2_bit = 4,
194 .core_testbus_ena = (1 << 3),
195 .core_testbus_sel2 = (1 << 4),
196 .core_pwrctl_status = 0xdc,
197 .core_pwrctl_mask = 0xe0,
198 .core_pwrctl_clear = 0xe4,
199 .core_pwrctl_ctl = 0xe8,
200 .core_sdcc_debug_reg = 0x124,
201 .core_dll_config = 0x100,
202 .core_dll_status = 0x108,
203 .core_vendor_spec = 0x10c,
204 .core_vendor_spec_adma_err_addr0 = 0x114,
205 .core_vendor_spec_adma_err_addr1 = 0x118,
206 .core_vendor_spec_func2 = 0x110,
207 .core_vendor_spec_capabilities0 = 0x11c,
208 .core_ddr_200_cfg = 0x184,
209 .core_vendor_spec3 = 0x1b0,
210 .core_dll_config_2 = 0x1b4,
211 .core_ddr_config_old = 0x1b8,
212 .core_ddr_config = 0x1bc,
215 struct sdhci_msm_variant_ops {
216 u32 (*msm_readl_relaxed)(struct sdhci_host *host, u32 offset);
217 void (*msm_writel_relaxed)(u32 val, struct sdhci_host *host,
222 * From V5, register spaces have changed. Wrap this info in a structure
223 * and choose the data_structure based on version info mentioned in DT.
225 struct sdhci_msm_variant_info {
227 bool restore_dll_config;
228 const struct sdhci_msm_variant_ops *var_ops;
229 const struct sdhci_msm_offset *offset;
232 struct sdhci_msm_host {
233 struct platform_device *pdev;
234 void __iomem *core_mem; /* MSM SDCC mapped address */
235 int pwr_irq; /* power irq */
236 struct clk *bus_clk; /* SDHC bus voter clock */
237 struct clk *xo_clk; /* TCXO clk needed for FLL feature of cm_dll*/
238 struct clk_bulk_data bulk_clks[4]; /* core, iface, cal, sleep clocks */
239 unsigned long clk_rate;
240 struct mmc_host *mmc;
241 bool use_14lpp_dll_reset;
243 bool calibration_done;
244 u8 saved_tuning_phase;
248 wait_queue_head_t pwr_irq_wait;
252 bool restore_dll_config;
253 const struct sdhci_msm_variant_ops *var_ops;
254 const struct sdhci_msm_offset *offset;
257 bool updated_ddr_cfg;
260 static const struct sdhci_msm_offset *sdhci_priv_msm_offset(struct sdhci_host *host)
262 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
263 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
265 return msm_host->offset;
269 * APIs to read/write to vendor specific registers which were there in the
270 * core_mem region before MCI was removed.
272 static u32 sdhci_msm_mci_variant_readl_relaxed(struct sdhci_host *host,
275 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
276 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
278 return readl_relaxed(msm_host->core_mem + offset);
281 static u32 sdhci_msm_v5_variant_readl_relaxed(struct sdhci_host *host,
284 return readl_relaxed(host->ioaddr + offset);
287 static void sdhci_msm_mci_variant_writel_relaxed(u32 val,
288 struct sdhci_host *host, u32 offset)
290 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
291 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
293 writel_relaxed(val, msm_host->core_mem + offset);
296 static void sdhci_msm_v5_variant_writel_relaxed(u32 val,
297 struct sdhci_host *host, u32 offset)
299 writel_relaxed(val, host->ioaddr + offset);
302 static unsigned int msm_get_clock_rate_for_bus_mode(struct sdhci_host *host,
305 struct mmc_ios ios = host->mmc->ios;
307 * The SDHC requires internal clock frequency to be double the
308 * actual clock that will be set for DDR mode. The controller
309 * uses the faster clock(100/400MHz) for some of its parts and
310 * send the actual required clock (50/200MHz) to the card.
312 if (ios.timing == MMC_TIMING_UHS_DDR50 ||
313 ios.timing == MMC_TIMING_MMC_DDR52 ||
314 ios.timing == MMC_TIMING_MMC_HS400 ||
315 host->flags & SDHCI_HS400_TUNING)
320 static void msm_set_clock_rate_for_bus_mode(struct sdhci_host *host,
323 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
324 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
325 struct mmc_ios curr_ios = host->mmc->ios;
326 struct clk *core_clk = msm_host->bulk_clks[0].clk;
329 clock = msm_get_clock_rate_for_bus_mode(host, clock);
330 rc = clk_set_rate(core_clk, clock);
332 pr_err("%s: Failed to set clock at rate %u at timing %d\n",
333 mmc_hostname(host->mmc), clock,
337 msm_host->clk_rate = clock;
338 pr_debug("%s: Setting clock at rate %lu at timing %d\n",
339 mmc_hostname(host->mmc), clk_get_rate(core_clk),
343 /* Platform specific tuning */
344 static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, u8 poll)
348 struct mmc_host *mmc = host->mmc;
349 const struct sdhci_msm_offset *msm_offset =
350 sdhci_priv_msm_offset(host);
352 /* Poll for CK_OUT_EN bit. max. poll time = 50us */
353 ck_out_en = !!(readl_relaxed(host->ioaddr +
354 msm_offset->core_dll_config) & CORE_CK_OUT_EN);
356 while (ck_out_en != poll) {
357 if (--wait_cnt == 0) {
358 dev_err(mmc_dev(mmc), "%s: CK_OUT_EN bit is not %d\n",
359 mmc_hostname(mmc), poll);
364 ck_out_en = !!(readl_relaxed(host->ioaddr +
365 msm_offset->core_dll_config) & CORE_CK_OUT_EN);
371 static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase)
374 static const u8 grey_coded_phase_table[] = {
375 0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4,
376 0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8
380 struct mmc_host *mmc = host->mmc;
381 const struct sdhci_msm_offset *msm_offset =
382 sdhci_priv_msm_offset(host);
387 spin_lock_irqsave(&host->lock, flags);
389 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
390 config &= ~(CORE_CDR_EN | CORE_CK_OUT_EN);
391 config |= (CORE_CDR_EXT_EN | CORE_DLL_EN);
392 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
394 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */
395 rc = msm_dll_poll_ck_out_en(host, 0);
400 * Write the selected DLL clock output phase (0 ... 15)
401 * to CDR_SELEXT bit field of DLL_CONFIG register.
403 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
404 config &= ~CDR_SELEXT_MASK;
405 config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT;
406 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
408 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
409 config |= CORE_CK_OUT_EN;
410 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
412 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */
413 rc = msm_dll_poll_ck_out_en(host, 1);
417 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
418 config |= CORE_CDR_EN;
419 config &= ~CORE_CDR_EXT_EN;
420 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
424 dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n",
425 mmc_hostname(mmc), phase);
427 spin_unlock_irqrestore(&host->lock, flags);
432 * Find out the greatest range of consecuitive selected
433 * DLL clock output phases that can be used as sampling
434 * setting for SD3.0 UHS-I card read operation (in SDR104
435 * timing mode) or for eMMC4.5 card read operation (in
436 * HS400/HS200 timing mode).
437 * Select the 3/4 of the range and configure the DLL with the
438 * selected DLL clock output phase.
441 static int msm_find_most_appropriate_phase(struct sdhci_host *host,
442 u8 *phase_table, u8 total_phases)
445 u8 ranges[MAX_PHASES][MAX_PHASES] = { {0}, {0} };
446 u8 phases_per_row[MAX_PHASES] = { 0 };
447 int row_index = 0, col_index = 0, selected_row_index = 0, curr_max = 0;
448 int i, cnt, phase_0_raw_index = 0, phase_15_raw_index = 0;
449 bool phase_0_found = false, phase_15_found = false;
450 struct mmc_host *mmc = host->mmc;
452 if (!total_phases || (total_phases > MAX_PHASES)) {
453 dev_err(mmc_dev(mmc), "%s: Invalid argument: total_phases=%d\n",
454 mmc_hostname(mmc), total_phases);
458 for (cnt = 0; cnt < total_phases; cnt++) {
459 ranges[row_index][col_index] = phase_table[cnt];
460 phases_per_row[row_index] += 1;
463 if ((cnt + 1) == total_phases) {
465 /* check if next phase in phase_table is consecutive or not */
466 } else if ((phase_table[cnt] + 1) != phase_table[cnt + 1]) {
472 if (row_index >= MAX_PHASES)
475 /* Check if phase-0 is present in first valid window? */
477 phase_0_found = true;
478 phase_0_raw_index = 0;
479 /* Check if cycle exist between 2 valid windows */
480 for (cnt = 1; cnt <= row_index; cnt++) {
481 if (phases_per_row[cnt]) {
482 for (i = 0; i < phases_per_row[cnt]; i++) {
483 if (ranges[cnt][i] == 15) {
484 phase_15_found = true;
485 phase_15_raw_index = cnt;
493 /* If 2 valid windows form cycle then merge them as single window */
494 if (phase_0_found && phase_15_found) {
495 /* number of phases in raw where phase 0 is present */
496 u8 phases_0 = phases_per_row[phase_0_raw_index];
497 /* number of phases in raw where phase 15 is present */
498 u8 phases_15 = phases_per_row[phase_15_raw_index];
500 if (phases_0 + phases_15 >= MAX_PHASES)
502 * If there are more than 1 phase windows then total
503 * number of phases in both the windows should not be
504 * more than or equal to MAX_PHASES.
508 /* Merge 2 cyclic windows */
510 for (cnt = 0; cnt < phases_0; cnt++) {
511 ranges[phase_15_raw_index][i] =
512 ranges[phase_0_raw_index][cnt];
513 if (++i >= MAX_PHASES)
517 phases_per_row[phase_0_raw_index] = 0;
518 phases_per_row[phase_15_raw_index] = phases_15 + phases_0;
521 for (cnt = 0; cnt <= row_index; cnt++) {
522 if (phases_per_row[cnt] > curr_max) {
523 curr_max = phases_per_row[cnt];
524 selected_row_index = cnt;
528 i = (curr_max * 3) / 4;
532 ret = ranges[selected_row_index][i];
534 if (ret >= MAX_PHASES) {
536 dev_err(mmc_dev(mmc), "%s: Invalid phase selected=%d\n",
537 mmc_hostname(mmc), ret);
543 static inline void msm_cm_dll_set_freq(struct sdhci_host *host)
545 u32 mclk_freq = 0, config;
546 const struct sdhci_msm_offset *msm_offset =
547 sdhci_priv_msm_offset(host);
549 /* Program the MCLK value to MCLK_FREQ bit field */
550 if (host->clock <= 112000000)
552 else if (host->clock <= 125000000)
554 else if (host->clock <= 137000000)
556 else if (host->clock <= 150000000)
558 else if (host->clock <= 162000000)
560 else if (host->clock <= 175000000)
562 else if (host->clock <= 187000000)
564 else if (host->clock <= 200000000)
567 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
568 config &= ~CMUX_SHIFT_PHASE_MASK;
569 config |= mclk_freq << CMUX_SHIFT_PHASE_SHIFT;
570 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
573 /* Initialize the DLL (Programmable Delay Line) */
574 static int msm_init_cm_dll(struct sdhci_host *host)
576 struct mmc_host *mmc = host->mmc;
577 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
578 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
580 unsigned long flags, xo_clk = 0;
582 const struct sdhci_msm_offset *msm_offset =
585 if (msm_host->use_14lpp_dll_reset && !IS_ERR_OR_NULL(msm_host->xo_clk))
586 xo_clk = clk_get_rate(msm_host->xo_clk);
588 spin_lock_irqsave(&host->lock, flags);
591 * Make sure that clock is always enabled when DLL
592 * tuning is in progress. Keeping PWRSAVE ON may
593 * turn off the clock.
595 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
596 config &= ~CORE_CLK_PWRSAVE;
597 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
599 if (msm_host->use_14lpp_dll_reset) {
600 config = readl_relaxed(host->ioaddr +
601 msm_offset->core_dll_config);
602 config &= ~CORE_CK_OUT_EN;
603 writel_relaxed(config, host->ioaddr +
604 msm_offset->core_dll_config);
606 config = readl_relaxed(host->ioaddr +
607 msm_offset->core_dll_config_2);
608 config |= CORE_DLL_CLOCK_DISABLE;
609 writel_relaxed(config, host->ioaddr +
610 msm_offset->core_dll_config_2);
613 config = readl_relaxed(host->ioaddr +
614 msm_offset->core_dll_config);
615 config |= CORE_DLL_RST;
616 writel_relaxed(config, host->ioaddr +
617 msm_offset->core_dll_config);
619 config = readl_relaxed(host->ioaddr +
620 msm_offset->core_dll_config);
621 config |= CORE_DLL_PDN;
622 writel_relaxed(config, host->ioaddr +
623 msm_offset->core_dll_config);
624 msm_cm_dll_set_freq(host);
626 if (msm_host->use_14lpp_dll_reset &&
627 !IS_ERR_OR_NULL(msm_host->xo_clk)) {
630 config = readl_relaxed(host->ioaddr +
631 msm_offset->core_dll_config_2);
632 config &= CORE_FLL_CYCLE_CNT;
634 mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 8),
637 mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 4),
640 config = readl_relaxed(host->ioaddr +
641 msm_offset->core_dll_config_2);
642 config &= ~(0xFF << 10);
643 config |= mclk_freq << 10;
645 writel_relaxed(config, host->ioaddr +
646 msm_offset->core_dll_config_2);
647 /* wait for 5us before enabling DLL clock */
651 config = readl_relaxed(host->ioaddr +
652 msm_offset->core_dll_config);
653 config &= ~CORE_DLL_RST;
654 writel_relaxed(config, host->ioaddr +
655 msm_offset->core_dll_config);
657 config = readl_relaxed(host->ioaddr +
658 msm_offset->core_dll_config);
659 config &= ~CORE_DLL_PDN;
660 writel_relaxed(config, host->ioaddr +
661 msm_offset->core_dll_config);
663 if (msm_host->use_14lpp_dll_reset) {
664 msm_cm_dll_set_freq(host);
665 config = readl_relaxed(host->ioaddr +
666 msm_offset->core_dll_config_2);
667 config &= ~CORE_DLL_CLOCK_DISABLE;
668 writel_relaxed(config, host->ioaddr +
669 msm_offset->core_dll_config_2);
672 config = readl_relaxed(host->ioaddr +
673 msm_offset->core_dll_config);
674 config |= CORE_DLL_EN;
675 writel_relaxed(config, host->ioaddr +
676 msm_offset->core_dll_config);
678 config = readl_relaxed(host->ioaddr +
679 msm_offset->core_dll_config);
680 config |= CORE_CK_OUT_EN;
681 writel_relaxed(config, host->ioaddr +
682 msm_offset->core_dll_config);
684 /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */
685 while (!(readl_relaxed(host->ioaddr + msm_offset->core_dll_status) &
687 /* max. wait for 50us sec for LOCK bit to be set */
688 if (--wait_cnt == 0) {
689 dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n",
691 spin_unlock_irqrestore(&host->lock, flags);
697 spin_unlock_irqrestore(&host->lock, flags);
701 static void msm_hc_select_default(struct sdhci_host *host)
703 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
704 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
706 const struct sdhci_msm_offset *msm_offset =
709 if (!msm_host->use_cdclp533) {
710 config = readl_relaxed(host->ioaddr +
711 msm_offset->core_vendor_spec3);
712 config &= ~CORE_PWRSAVE_DLL;
713 writel_relaxed(config, host->ioaddr +
714 msm_offset->core_vendor_spec3);
717 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
718 config &= ~CORE_HC_MCLK_SEL_MASK;
719 config |= CORE_HC_MCLK_SEL_DFLT;
720 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
723 * Disable HC_SELECT_IN to be able to use the UHS mode select
724 * configuration from Host Control2 register for all other
726 * Write 0 to HC_SELECT_IN and HC_SELECT_IN_EN field
727 * in VENDOR_SPEC_FUNC
729 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
730 config &= ~CORE_HC_SELECT_IN_EN;
731 config &= ~CORE_HC_SELECT_IN_MASK;
732 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
735 * Make sure above writes impacting free running MCLK are completed
736 * before changing the clk_rate at GCC.
741 static void msm_hc_select_hs400(struct sdhci_host *host)
743 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
744 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
745 struct mmc_ios ios = host->mmc->ios;
746 u32 config, dll_lock;
748 const struct sdhci_msm_offset *msm_offset =
751 /* Select the divided clock (free running MCLK/2) */
752 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
753 config &= ~CORE_HC_MCLK_SEL_MASK;
754 config |= CORE_HC_MCLK_SEL_HS400;
756 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
758 * Select HS400 mode using the HC_SELECT_IN from VENDOR SPEC
761 if ((msm_host->tuning_done || ios.enhanced_strobe) &&
762 !msm_host->calibration_done) {
763 config = readl_relaxed(host->ioaddr +
764 msm_offset->core_vendor_spec);
765 config |= CORE_HC_SELECT_IN_HS400;
766 config |= CORE_HC_SELECT_IN_EN;
767 writel_relaxed(config, host->ioaddr +
768 msm_offset->core_vendor_spec);
770 if (!msm_host->clk_rate && !msm_host->use_cdclp533) {
772 * Poll on DLL_LOCK or DDR_DLL_LOCK bits in
773 * core_dll_status to be set. This should get set
774 * within 15 us at 200 MHz.
776 rc = readl_relaxed_poll_timeout(host->ioaddr +
777 msm_offset->core_dll_status,
781 CORE_DDR_DLL_LOCK)), 10,
783 if (rc == -ETIMEDOUT)
784 pr_err("%s: Unable to get DLL_LOCK/DDR_DLL_LOCK, dll_status: 0x%08x\n",
785 mmc_hostname(host->mmc), dll_lock);
788 * Make sure above writes impacting free running MCLK are completed
789 * before changing the clk_rate at GCC.
795 * sdhci_msm_hc_select_mode :- In general all timing modes are
796 * controlled via UHS mode select in Host Control2 register.
797 * eMMC specific HS200/HS400 doesn't have their respective modes
798 * defined here, hence we use these values.
800 * HS200 - SDR104 (Since they both are equivalent in functionality)
801 * HS400 - This involves multiple configurations
802 * Initially SDR104 - when tuning is required as HS200
803 * Then when switching to DDR @ 400MHz (HS400) we use
804 * the vendor specific HC_SELECT_IN to control the mode.
806 * In addition to controlling the modes we also need to select the
807 * correct input clock for DLL depending on the mode.
809 * HS400 - divided clock (free running MCLK/2)
810 * All other modes - default (free running MCLK)
812 static void sdhci_msm_hc_select_mode(struct sdhci_host *host)
814 struct mmc_ios ios = host->mmc->ios;
816 if (ios.timing == MMC_TIMING_MMC_HS400 ||
817 host->flags & SDHCI_HS400_TUNING)
818 msm_hc_select_hs400(host);
820 msm_hc_select_default(host);
823 static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host)
825 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
826 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
827 u32 config, calib_done;
829 const struct sdhci_msm_offset *msm_offset =
832 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
835 * Retuning in HS400 (DDR mode) will fail, just reset the
836 * tuning block and restore the saved tuning phase.
838 ret = msm_init_cm_dll(host);
842 /* Set the selected phase in delay line hw block */
843 ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
847 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
848 config |= CORE_CMD_DAT_TRACK_SEL;
849 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
851 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
852 config &= ~CORE_CDC_T4_DLY_SEL;
853 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
855 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
856 config &= ~CORE_CDC_SWITCH_BYPASS_OFF;
857 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
859 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
860 config |= CORE_CDC_SWITCH_RC_EN;
861 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
863 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
864 config &= ~CORE_START_CDC_TRAFFIC;
865 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
867 /* Perform CDC Register Initialization Sequence */
869 writel_relaxed(0x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
870 writel_relaxed(0x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1);
871 writel_relaxed(0x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
872 writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1);
873 writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG);
874 writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG);
875 writel_relaxed(0x4E2, host->ioaddr + CORE_CSR_CDC_DELAY_CFG);
876 writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG);
877 writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG);
879 /* CDC HW Calibration */
881 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
882 config |= CORE_SW_TRIG_FULL_CALIB;
883 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
885 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
886 config &= ~CORE_SW_TRIG_FULL_CALIB;
887 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
889 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
890 config |= CORE_HW_AUTOCAL_ENA;
891 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
893 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
894 config |= CORE_TIMER_ENA;
895 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
897 ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_CSR_CDC_STATUS0,
899 (calib_done & CORE_CALIBRATION_DONE),
902 if (ret == -ETIMEDOUT) {
903 pr_err("%s: %s: CDC calibration was not completed\n",
904 mmc_hostname(host->mmc), __func__);
908 ret = readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0)
909 & CORE_CDC_ERROR_CODE_MASK;
911 pr_err("%s: %s: CDC error code %d\n",
912 mmc_hostname(host->mmc), __func__, ret);
917 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
918 config |= CORE_START_CDC_TRAFFIC;
919 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
921 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
926 static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host)
928 struct mmc_host *mmc = host->mmc;
929 u32 dll_status, config, ddr_cfg_offset;
931 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
932 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
933 const struct sdhci_msm_offset *msm_offset =
934 sdhci_priv_msm_offset(host);
936 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
939 * Currently the core_ddr_config register defaults to desired
940 * configuration on reset. Currently reprogramming the power on
941 * reset (POR) value in case it might have been modified by
942 * bootloaders. In the future, if this changes, then the desired
943 * values will need to be programmed appropriately.
945 if (msm_host->updated_ddr_cfg)
946 ddr_cfg_offset = msm_offset->core_ddr_config;
948 ddr_cfg_offset = msm_offset->core_ddr_config_old;
949 writel_relaxed(DDR_CONFIG_POR_VAL, host->ioaddr + ddr_cfg_offset);
951 if (mmc->ios.enhanced_strobe) {
952 config = readl_relaxed(host->ioaddr +
953 msm_offset->core_ddr_200_cfg);
954 config |= CORE_CMDIN_RCLK_EN;
955 writel_relaxed(config, host->ioaddr +
956 msm_offset->core_ddr_200_cfg);
959 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config_2);
960 config |= CORE_DDR_CAL_EN;
961 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config_2);
963 ret = readl_relaxed_poll_timeout(host->ioaddr +
964 msm_offset->core_dll_status,
966 (dll_status & CORE_DDR_DLL_LOCK),
969 if (ret == -ETIMEDOUT) {
970 pr_err("%s: %s: CM_DLL_SDC4 calibration was not completed\n",
971 mmc_hostname(host->mmc), __func__);
975 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec3);
976 config |= CORE_PWRSAVE_DLL;
977 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec3);
980 * Drain writebuffer to ensure above DLL calibration
981 * and PWRSAVE DLL is enabled.
985 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
990 static int sdhci_msm_hs400_dll_calibration(struct sdhci_host *host)
992 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
993 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
994 struct mmc_host *mmc = host->mmc;
997 const struct sdhci_msm_offset *msm_offset =
1000 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
1003 * Retuning in HS400 (DDR mode) will fail, just reset the
1004 * tuning block and restore the saved tuning phase.
1006 ret = msm_init_cm_dll(host);
1010 if (!mmc->ios.enhanced_strobe) {
1011 /* Set the selected phase in delay line hw block */
1012 ret = msm_config_cm_dll_phase(host,
1013 msm_host->saved_tuning_phase);
1016 config = readl_relaxed(host->ioaddr +
1017 msm_offset->core_dll_config);
1018 config |= CORE_CMD_DAT_TRACK_SEL;
1019 writel_relaxed(config, host->ioaddr +
1020 msm_offset->core_dll_config);
1023 if (msm_host->use_cdclp533)
1024 ret = sdhci_msm_cdclp533_calibration(host);
1026 ret = sdhci_msm_cm_dll_sdc4_calibration(host);
1028 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
1033 static bool sdhci_msm_is_tuning_needed(struct sdhci_host *host)
1035 struct mmc_ios *ios = &host->mmc->ios;
1038 * Tuning is required for SDR104, HS200 and HS400 cards and
1039 * if clock frequency is greater than 100MHz in these modes.
1041 if (host->clock <= CORE_FREQ_100MHZ ||
1042 !(ios->timing == MMC_TIMING_MMC_HS400 ||
1043 ios->timing == MMC_TIMING_MMC_HS200 ||
1044 ios->timing == MMC_TIMING_UHS_SDR104) ||
1045 ios->enhanced_strobe)
1051 static int sdhci_msm_restore_sdr_dll_config(struct sdhci_host *host)
1053 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1054 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1058 * SDR DLL comes into picture only for timing modes which needs
1061 if (!sdhci_msm_is_tuning_needed(host))
1064 /* Reset the tuning block */
1065 ret = msm_init_cm_dll(host);
1069 /* Restore the tuning block */
1070 ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
1075 static void sdhci_msm_set_cdr(struct sdhci_host *host, bool enable)
1077 const struct sdhci_msm_offset *msm_offset = sdhci_priv_msm_offset(host);
1078 u32 config, oldconfig = readl_relaxed(host->ioaddr +
1079 msm_offset->core_dll_config);
1083 config |= CORE_CDR_EN;
1084 config &= ~CORE_CDR_EXT_EN;
1086 config &= ~CORE_CDR_EN;
1087 config |= CORE_CDR_EXT_EN;
1090 if (config != oldconfig) {
1091 writel_relaxed(config, host->ioaddr +
1092 msm_offset->core_dll_config);
1096 static int sdhci_msm_execute_tuning(struct mmc_host *mmc, u32 opcode)
1098 struct sdhci_host *host = mmc_priv(mmc);
1099 int tuning_seq_cnt = 3;
1100 u8 phase, tuned_phases[16], tuned_phase_cnt = 0;
1102 struct mmc_ios ios = host->mmc->ios;
1103 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1104 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1106 if (!sdhci_msm_is_tuning_needed(host)) {
1107 msm_host->use_cdr = false;
1108 sdhci_msm_set_cdr(host, false);
1112 /* Clock-Data-Recovery used to dynamically adjust RX sampling point */
1113 msm_host->use_cdr = true;
1116 * Clear tuning_done flag before tuning to ensure proper
1119 msm_host->tuning_done = 0;
1122 * For HS400 tuning in HS200 timing requires:
1123 * - select MCLK/2 in VENDOR_SPEC
1124 * - program MCLK to 400MHz (or nearest supported) in GCC
1126 if (host->flags & SDHCI_HS400_TUNING) {
1127 sdhci_msm_hc_select_mode(host);
1128 msm_set_clock_rate_for_bus_mode(host, ios.clock);
1129 host->flags &= ~SDHCI_HS400_TUNING;
1133 /* First of all reset the tuning block */
1134 rc = msm_init_cm_dll(host);
1140 /* Set the phase in delay line hw block */
1141 rc = msm_config_cm_dll_phase(host, phase);
1145 rc = mmc_send_tuning(mmc, opcode, NULL);
1147 /* Tuning is successful at this tuning point */
1148 tuned_phases[tuned_phase_cnt++] = phase;
1149 dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n",
1150 mmc_hostname(mmc), phase);
1152 } while (++phase < ARRAY_SIZE(tuned_phases));
1154 if (tuned_phase_cnt) {
1155 rc = msm_find_most_appropriate_phase(host, tuned_phases,
1163 * Finally set the selected phase in delay
1166 rc = msm_config_cm_dll_phase(host, phase);
1169 msm_host->saved_tuning_phase = phase;
1170 dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n",
1171 mmc_hostname(mmc), phase);
1173 if (--tuning_seq_cnt)
1176 dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n",
1182 msm_host->tuning_done = true;
1187 * sdhci_msm_hs400 - Calibrate the DLL for HS400 bus speed mode operation.
1188 * This needs to be done for both tuning and enhanced_strobe mode.
1189 * DLL operation is only needed for clock > 100MHz. For clock <= 100MHz
1190 * fixed feedback clock is used.
1192 static void sdhci_msm_hs400(struct sdhci_host *host, struct mmc_ios *ios)
1194 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1195 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1198 if (host->clock > CORE_FREQ_100MHZ &&
1199 (msm_host->tuning_done || ios->enhanced_strobe) &&
1200 !msm_host->calibration_done) {
1201 ret = sdhci_msm_hs400_dll_calibration(host);
1203 msm_host->calibration_done = true;
1205 pr_err("%s: Failed to calibrate DLL for hs400 mode (%d)\n",
1206 mmc_hostname(host->mmc), ret);
1210 static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
1213 struct mmc_host *mmc = host->mmc;
1214 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1215 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1218 const struct sdhci_msm_offset *msm_offset =
1221 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1222 /* Select Bus Speed Mode for host */
1223 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1225 case MMC_TIMING_UHS_SDR12:
1226 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1228 case MMC_TIMING_UHS_SDR25:
1229 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1231 case MMC_TIMING_UHS_SDR50:
1232 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1234 case MMC_TIMING_MMC_HS400:
1235 case MMC_TIMING_MMC_HS200:
1236 case MMC_TIMING_UHS_SDR104:
1237 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1239 case MMC_TIMING_UHS_DDR50:
1240 case MMC_TIMING_MMC_DDR52:
1241 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1246 * When clock frequency is less than 100MHz, the feedback clock must be
1247 * provided and DLL must not be used so that tuning can be skipped. To
1248 * provide feedback clock, the mode selection can be any value less
1249 * than 3'b011 in bits [2:0] of HOST CONTROL2 register.
1251 if (host->clock <= CORE_FREQ_100MHZ) {
1252 if (uhs == MMC_TIMING_MMC_HS400 ||
1253 uhs == MMC_TIMING_MMC_HS200 ||
1254 uhs == MMC_TIMING_UHS_SDR104)
1255 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1257 * DLL is not required for clock <= 100MHz
1258 * Thus, make sure DLL it is disabled when not required
1260 config = readl_relaxed(host->ioaddr +
1261 msm_offset->core_dll_config);
1262 config |= CORE_DLL_RST;
1263 writel_relaxed(config, host->ioaddr +
1264 msm_offset->core_dll_config);
1266 config = readl_relaxed(host->ioaddr +
1267 msm_offset->core_dll_config);
1268 config |= CORE_DLL_PDN;
1269 writel_relaxed(config, host->ioaddr +
1270 msm_offset->core_dll_config);
1273 * The DLL needs to be restored and CDCLP533 recalibrated
1274 * when the clock frequency is set back to 400MHz.
1276 msm_host->calibration_done = false;
1279 dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n",
1280 mmc_hostname(host->mmc), host->clock, uhs, ctrl_2);
1281 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1283 if (mmc->ios.timing == MMC_TIMING_MMC_HS400)
1284 sdhci_msm_hs400(host, &mmc->ios);
1287 static inline void sdhci_msm_init_pwr_irq_wait(struct sdhci_msm_host *msm_host)
1289 init_waitqueue_head(&msm_host->pwr_irq_wait);
1292 static inline void sdhci_msm_complete_pwr_irq_wait(
1293 struct sdhci_msm_host *msm_host)
1295 wake_up(&msm_host->pwr_irq_wait);
1299 * sdhci_msm_check_power_status API should be called when registers writes
1300 * which can toggle sdhci IO bus ON/OFF or change IO lines HIGH/LOW happens.
1301 * To what state the register writes will change the IO lines should be passed
1302 * as the argument req_type. This API will check whether the IO line's state
1303 * is already the expected state and will wait for power irq only if
1304 * power irq is expected to be trigerred based on the current IO line state
1305 * and expected IO line state.
1307 static void sdhci_msm_check_power_status(struct sdhci_host *host, u32 req_type)
1309 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1310 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1312 u32 val = SWITCHABLE_SIGNALING_VOLTAGE;
1313 const struct sdhci_msm_offset *msm_offset =
1316 pr_debug("%s: %s: request %d curr_pwr_state %x curr_io_level %x\n",
1317 mmc_hostname(host->mmc), __func__, req_type,
1318 msm_host->curr_pwr_state, msm_host->curr_io_level);
1321 * The power interrupt will not be generated for signal voltage
1322 * switches if SWITCHABLE_SIGNALING_VOLTAGE in MCI_GENERICS is not set.
1323 * Since sdhci-msm-v5, this bit has been removed and SW must consider
1326 if (!msm_host->mci_removed)
1327 val = msm_host_readl(msm_host, host,
1328 msm_offset->core_generics);
1329 if ((req_type & REQ_IO_HIGH || req_type & REQ_IO_LOW) &&
1330 !(val & SWITCHABLE_SIGNALING_VOLTAGE)) {
1335 * The IRQ for request type IO High/LOW will be generated when -
1336 * there is a state change in 1.8V enable bit (bit 3) of
1337 * SDHCI_HOST_CONTROL2 register. The reset state of that bit is 0
1338 * which indicates 3.3V IO voltage. So, when MMC core layer tries
1339 * to set it to 3.3V before card detection happens, the
1340 * IRQ doesn't get triggered as there is no state change in this bit.
1341 * The driver already handles this case by changing the IO voltage
1342 * level to high as part of controller power up sequence. Hence, check
1343 * for host->pwr to handle a case where IO voltage high request is
1344 * issued even before controller power up.
1346 if ((req_type & REQ_IO_HIGH) && !host->pwr) {
1347 pr_debug("%s: do not wait for power IRQ that never comes, req_type: %d\n",
1348 mmc_hostname(host->mmc), req_type);
1351 if ((req_type & msm_host->curr_pwr_state) ||
1352 (req_type & msm_host->curr_io_level))
1355 * This is needed here to handle cases where register writes will
1356 * not change the current bus state or io level of the controller.
1357 * In this case, no power irq will be triggerred and we should
1361 if (!wait_event_timeout(msm_host->pwr_irq_wait,
1362 msm_host->pwr_irq_flag,
1363 msecs_to_jiffies(MSM_PWR_IRQ_TIMEOUT_MS)))
1364 dev_warn(&msm_host->pdev->dev,
1365 "%s: pwr_irq for req: (%d) timed out\n",
1366 mmc_hostname(host->mmc), req_type);
1368 pr_debug("%s: %s: request %d done\n", mmc_hostname(host->mmc),
1369 __func__, req_type);
1372 static void sdhci_msm_dump_pwr_ctrl_regs(struct sdhci_host *host)
1374 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1375 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1376 const struct sdhci_msm_offset *msm_offset =
1379 pr_err("%s: PWRCTL_STATUS: 0x%08x | PWRCTL_MASK: 0x%08x | PWRCTL_CTL: 0x%08x\n",
1380 mmc_hostname(host->mmc),
1381 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_status),
1382 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_mask),
1383 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_ctl));
1386 static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq)
1388 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1389 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1390 u32 irq_status, irq_ack = 0;
1392 u32 pwr_state = 0, io_level = 0;
1394 const struct sdhci_msm_offset *msm_offset = msm_host->offset;
1396 irq_status = msm_host_readl(msm_host, host,
1397 msm_offset->core_pwrctl_status);
1398 irq_status &= INT_MASK;
1400 msm_host_writel(msm_host, irq_status, host,
1401 msm_offset->core_pwrctl_clear);
1404 * There is a rare HW scenario where the first clear pulse could be
1405 * lost when actual reset and clear/read of status register is
1406 * happening at a time. Hence, retry for at least 10 times to make
1407 * sure status register is cleared. Otherwise, this will result in
1408 * a spurious power IRQ resulting in system instability.
1410 while (irq_status & msm_host_readl(msm_host, host,
1411 msm_offset->core_pwrctl_status)) {
1413 pr_err("%s: Timedout clearing (0x%x) pwrctl status register\n",
1414 mmc_hostname(host->mmc), irq_status);
1415 sdhci_msm_dump_pwr_ctrl_regs(host);
1419 msm_host_writel(msm_host, irq_status, host,
1420 msm_offset->core_pwrctl_clear);
1425 /* Handle BUS ON/OFF*/
1426 if (irq_status & CORE_PWRCTL_BUS_ON) {
1427 pwr_state = REQ_BUS_ON;
1428 io_level = REQ_IO_HIGH;
1429 irq_ack |= CORE_PWRCTL_BUS_SUCCESS;
1431 if (irq_status & CORE_PWRCTL_BUS_OFF) {
1432 pwr_state = REQ_BUS_OFF;
1433 io_level = REQ_IO_LOW;
1434 irq_ack |= CORE_PWRCTL_BUS_SUCCESS;
1436 /* Handle IO LOW/HIGH */
1437 if (irq_status & CORE_PWRCTL_IO_LOW) {
1438 io_level = REQ_IO_LOW;
1439 irq_ack |= CORE_PWRCTL_IO_SUCCESS;
1441 if (irq_status & CORE_PWRCTL_IO_HIGH) {
1442 io_level = REQ_IO_HIGH;
1443 irq_ack |= CORE_PWRCTL_IO_SUCCESS;
1447 * The driver has to acknowledge the interrupt, switch voltages and
1448 * report back if it succeded or not to this register. The voltage
1449 * switches are handled by the sdhci core, so just report success.
1451 msm_host_writel(msm_host, irq_ack, host,
1452 msm_offset->core_pwrctl_ctl);
1455 * If we don't have info regarding the voltage levels supported by
1456 * regulators, don't change the IO PAD PWR SWITCH.
1458 if (msm_host->caps_0 & CORE_VOLT_SUPPORT) {
1461 * We should unset IO PAD PWR switch only if the register write
1462 * can set IO lines high and the regulator also switches to 3 V.
1463 * Else, we should keep the IO PAD PWR switch set.
1464 * This is applicable to certain targets where eMMC vccq supply
1465 * is only 1.8V. In such targets, even during REQ_IO_HIGH, the
1466 * IO PAD PWR switch must be kept set to reflect actual
1467 * regulator voltage. This way, during initialization of
1468 * controllers with only 1.8V, we will set the IO PAD bit
1469 * without waiting for a REQ_IO_LOW.
1471 config = readl_relaxed(host->ioaddr +
1472 msm_offset->core_vendor_spec);
1473 new_config = config;
1475 if ((io_level & REQ_IO_HIGH) &&
1476 (msm_host->caps_0 & CORE_3_0V_SUPPORT))
1477 new_config &= ~CORE_IO_PAD_PWR_SWITCH;
1478 else if ((io_level & REQ_IO_LOW) ||
1479 (msm_host->caps_0 & CORE_1_8V_SUPPORT))
1480 new_config |= CORE_IO_PAD_PWR_SWITCH;
1482 if (config ^ new_config)
1483 writel_relaxed(new_config, host->ioaddr +
1484 msm_offset->core_vendor_spec);
1488 msm_host->curr_pwr_state = pwr_state;
1490 msm_host->curr_io_level = io_level;
1492 pr_debug("%s: %s: Handled IRQ(%d), irq_status=0x%x, ack=0x%x\n",
1493 mmc_hostname(msm_host->mmc), __func__, irq, irq_status,
1497 static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data)
1499 struct sdhci_host *host = (struct sdhci_host *)data;
1500 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1501 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1503 sdhci_msm_handle_pwr_irq(host, irq);
1504 msm_host->pwr_irq_flag = 1;
1505 sdhci_msm_complete_pwr_irq_wait(msm_host);
1511 static unsigned int sdhci_msm_get_max_clock(struct sdhci_host *host)
1513 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1514 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1515 struct clk *core_clk = msm_host->bulk_clks[0].clk;
1517 return clk_round_rate(core_clk, ULONG_MAX);
1520 static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host)
1522 return SDHCI_MSM_MIN_CLOCK;
1526 * __sdhci_msm_set_clock - sdhci_msm clock control.
1529 * MSM controller does not use internal divider and
1530 * instead directly control the GCC clock as per
1531 * HW recommendation.
1533 static void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
1537 * Keep actual_clock as zero -
1538 * - since there is no divider used so no need of having actual_clock.
1539 * - MSM controller uses SDCLK for data timeout calculation. If
1540 * actual_clock is zero, host->clock is taken for calculation.
1542 host->mmc->actual_clock = 0;
1544 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1550 * MSM controller do not use clock divider.
1551 * Thus read SDHCI_CLOCK_CONTROL and only enable
1552 * clock with no divider value programmed.
1554 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1555 sdhci_enable_clk(host, clk);
1558 /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
1559 static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
1561 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1562 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1565 msm_host->clk_rate = clock;
1569 sdhci_msm_hc_select_mode(host);
1571 msm_set_clock_rate_for_bus_mode(host, clock);
1573 __sdhci_msm_set_clock(host, clock);
1577 * Platform specific register write functions. This is so that, if any
1578 * register write needs to be followed up by platform specific actions,
1579 * they can be added here. These functions can go to sleep when writes
1580 * to certain registers are done.
1581 * These functions are relying on sdhci_set_ios not using spinlock.
1583 static int __sdhci_msm_check_write(struct sdhci_host *host, u16 val, int reg)
1585 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1586 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1590 case SDHCI_HOST_CONTROL2:
1591 req_type = (val & SDHCI_CTRL_VDD_180) ? REQ_IO_LOW :
1594 case SDHCI_SOFTWARE_RESET:
1595 if (host->pwr && (val & SDHCI_RESET_ALL))
1596 req_type = REQ_BUS_OFF;
1598 case SDHCI_POWER_CONTROL:
1599 req_type = !val ? REQ_BUS_OFF : REQ_BUS_ON;
1601 case SDHCI_TRANSFER_MODE:
1602 msm_host->transfer_mode = val;
1605 if (!msm_host->use_cdr)
1607 if ((msm_host->transfer_mode & SDHCI_TRNS_READ) &&
1608 SDHCI_GET_CMD(val) != MMC_SEND_TUNING_BLOCK_HS200 &&
1609 SDHCI_GET_CMD(val) != MMC_SEND_TUNING_BLOCK)
1610 sdhci_msm_set_cdr(host, true);
1612 sdhci_msm_set_cdr(host, false);
1617 msm_host->pwr_irq_flag = 0;
1619 * Since this register write may trigger a power irq, ensure
1620 * all previous register writes are complete by this point.
1627 /* This function may sleep*/
1628 static void sdhci_msm_writew(struct sdhci_host *host, u16 val, int reg)
1632 req_type = __sdhci_msm_check_write(host, val, reg);
1633 writew_relaxed(val, host->ioaddr + reg);
1636 sdhci_msm_check_power_status(host, req_type);
1639 /* This function may sleep*/
1640 static void sdhci_msm_writeb(struct sdhci_host *host, u8 val, int reg)
1644 req_type = __sdhci_msm_check_write(host, val, reg);
1646 writeb_relaxed(val, host->ioaddr + reg);
1649 sdhci_msm_check_power_status(host, req_type);
1652 static void sdhci_msm_set_regulator_caps(struct sdhci_msm_host *msm_host)
1654 struct mmc_host *mmc = msm_host->mmc;
1655 struct regulator *supply = mmc->supply.vqmmc;
1656 u32 caps = 0, config;
1657 struct sdhci_host *host = mmc_priv(mmc);
1658 const struct sdhci_msm_offset *msm_offset = msm_host->offset;
1660 if (!IS_ERR(mmc->supply.vqmmc)) {
1661 if (regulator_is_supported_voltage(supply, 1700000, 1950000))
1662 caps |= CORE_1_8V_SUPPORT;
1663 if (regulator_is_supported_voltage(supply, 2700000, 3600000))
1664 caps |= CORE_3_0V_SUPPORT;
1667 pr_warn("%s: 1.8/3V not supported for vqmmc\n",
1673 * Set the PAD_PWR_SWITCH_EN bit so that the PAD_PWR_SWITCH
1674 * bit can be used as required later on.
1676 u32 io_level = msm_host->curr_io_level;
1678 config = readl_relaxed(host->ioaddr +
1679 msm_offset->core_vendor_spec);
1680 config |= CORE_IO_PAD_PWR_SWITCH_EN;
1682 if ((io_level & REQ_IO_HIGH) && (caps & CORE_3_0V_SUPPORT))
1683 config &= ~CORE_IO_PAD_PWR_SWITCH;
1684 else if ((io_level & REQ_IO_LOW) || (caps & CORE_1_8V_SUPPORT))
1685 config |= CORE_IO_PAD_PWR_SWITCH;
1687 writel_relaxed(config,
1688 host->ioaddr + msm_offset->core_vendor_spec);
1690 msm_host->caps_0 |= caps;
1691 pr_debug("%s: supported caps: 0x%08x\n", mmc_hostname(mmc), caps);
1694 static const struct sdhci_msm_variant_ops mci_var_ops = {
1695 .msm_readl_relaxed = sdhci_msm_mci_variant_readl_relaxed,
1696 .msm_writel_relaxed = sdhci_msm_mci_variant_writel_relaxed,
1699 static const struct sdhci_msm_variant_ops v5_var_ops = {
1700 .msm_readl_relaxed = sdhci_msm_v5_variant_readl_relaxed,
1701 .msm_writel_relaxed = sdhci_msm_v5_variant_writel_relaxed,
1704 static const struct sdhci_msm_variant_info sdhci_msm_mci_var = {
1705 .var_ops = &mci_var_ops,
1706 .offset = &sdhci_msm_mci_offset,
1709 static const struct sdhci_msm_variant_info sdhci_msm_v5_var = {
1710 .mci_removed = true,
1711 .var_ops = &v5_var_ops,
1712 .offset = &sdhci_msm_v5_offset,
1715 static const struct sdhci_msm_variant_info sdm845_sdhci_var = {
1716 .mci_removed = true,
1717 .restore_dll_config = true,
1718 .var_ops = &v5_var_ops,
1719 .offset = &sdhci_msm_v5_offset,
1722 static const struct of_device_id sdhci_msm_dt_match[] = {
1723 {.compatible = "qcom,sdhci-msm-v4", .data = &sdhci_msm_mci_var},
1724 {.compatible = "qcom,sdhci-msm-v5", .data = &sdhci_msm_v5_var},
1725 {.compatible = "qcom,sdm845-sdhci", .data = &sdm845_sdhci_var},
1729 MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match);
1731 static const struct sdhci_ops sdhci_msm_ops = {
1732 .reset = sdhci_reset,
1733 .set_clock = sdhci_msm_set_clock,
1734 .get_min_clock = sdhci_msm_get_min_clock,
1735 .get_max_clock = sdhci_msm_get_max_clock,
1736 .set_bus_width = sdhci_set_bus_width,
1737 .set_uhs_signaling = sdhci_msm_set_uhs_signaling,
1738 .write_w = sdhci_msm_writew,
1739 .write_b = sdhci_msm_writeb,
1742 static const struct sdhci_pltfm_data sdhci_msm_pdata = {
1743 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
1744 SDHCI_QUIRK_SINGLE_POWER_WRITE |
1745 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
1746 SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
1748 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1749 .ops = &sdhci_msm_ops,
1752 static int sdhci_msm_probe(struct platform_device *pdev)
1754 struct sdhci_host *host;
1755 struct sdhci_pltfm_host *pltfm_host;
1756 struct sdhci_msm_host *msm_host;
1757 struct resource *core_memres;
1760 u16 host_version, core_minor;
1761 u32 core_version, config;
1763 const struct sdhci_msm_offset *msm_offset;
1764 const struct sdhci_msm_variant_info *var_info;
1766 host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host));
1768 return PTR_ERR(host);
1770 host->sdma_boundary = 0;
1771 pltfm_host = sdhci_priv(host);
1772 msm_host = sdhci_pltfm_priv(pltfm_host);
1773 msm_host->mmc = host->mmc;
1774 msm_host->pdev = pdev;
1776 ret = mmc_of_parse(host->mmc);
1781 * Based on the compatible string, load the required msm host info from
1782 * the data associated with the version info.
1784 var_info = of_device_get_match_data(&pdev->dev);
1786 msm_host->mci_removed = var_info->mci_removed;
1787 msm_host->restore_dll_config = var_info->restore_dll_config;
1788 msm_host->var_ops = var_info->var_ops;
1789 msm_host->offset = var_info->offset;
1791 msm_offset = msm_host->offset;
1793 sdhci_get_of_property(pdev);
1795 msm_host->saved_tuning_phase = INVALID_TUNING_PHASE;
1797 /* Setup SDCC bus voter clock. */
1798 msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");
1799 if (!IS_ERR(msm_host->bus_clk)) {
1800 /* Vote for max. clk rate for max. performance */
1801 ret = clk_set_rate(msm_host->bus_clk, INT_MAX);
1804 ret = clk_prepare_enable(msm_host->bus_clk);
1809 /* Setup main peripheral bus clock */
1810 clk = devm_clk_get(&pdev->dev, "iface");
1813 dev_err(&pdev->dev, "Peripheral clk setup failed (%d)\n", ret);
1814 goto bus_clk_disable;
1816 msm_host->bulk_clks[1].clk = clk;
1818 /* Setup SDC MMC clock */
1819 clk = devm_clk_get(&pdev->dev, "core");
1822 dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret);
1823 goto bus_clk_disable;
1825 msm_host->bulk_clks[0].clk = clk;
1827 /* Vote for maximum clock rate for maximum performance */
1828 ret = clk_set_rate(clk, INT_MAX);
1830 dev_warn(&pdev->dev, "core clock boost failed\n");
1832 clk = devm_clk_get(&pdev->dev, "cal");
1835 msm_host->bulk_clks[2].clk = clk;
1837 clk = devm_clk_get(&pdev->dev, "sleep");
1840 msm_host->bulk_clks[3].clk = clk;
1842 ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks),
1843 msm_host->bulk_clks);
1845 goto bus_clk_disable;
1848 * xo clock is needed for FLL feature of cm_dll.
1849 * In case if xo clock is not mentioned in DT, warn and proceed.
1851 msm_host->xo_clk = devm_clk_get(&pdev->dev, "xo");
1852 if (IS_ERR(msm_host->xo_clk)) {
1853 ret = PTR_ERR(msm_host->xo_clk);
1854 dev_warn(&pdev->dev, "TCXO clk not present (%d)\n", ret);
1857 if (!msm_host->mci_removed) {
1858 core_memres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1859 msm_host->core_mem = devm_ioremap_resource(&pdev->dev,
1862 if (IS_ERR(msm_host->core_mem)) {
1863 ret = PTR_ERR(msm_host->core_mem);
1868 /* Reset the vendor spec register to power on reset state */
1869 writel_relaxed(CORE_VENDOR_SPEC_POR_VAL,
1870 host->ioaddr + msm_offset->core_vendor_spec);
1872 if (!msm_host->mci_removed) {
1873 /* Set HC_MODE_EN bit in HC_MODE register */
1874 msm_host_writel(msm_host, HC_MODE_EN, host,
1875 msm_offset->core_hc_mode);
1876 config = msm_host_readl(msm_host, host,
1877 msm_offset->core_hc_mode);
1878 config |= FF_CLK_SW_RST_DIS;
1879 msm_host_writel(msm_host, config, host,
1880 msm_offset->core_hc_mode);
1883 host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
1884 dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n",
1885 host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >>
1886 SDHCI_VENDOR_VER_SHIFT));
1888 core_version = msm_host_readl(msm_host, host,
1889 msm_offset->core_mci_version);
1890 core_major = (core_version & CORE_VERSION_MAJOR_MASK) >>
1891 CORE_VERSION_MAJOR_SHIFT;
1892 core_minor = core_version & CORE_VERSION_MINOR_MASK;
1893 dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n",
1894 core_version, core_major, core_minor);
1896 if (core_major == 1 && core_minor >= 0x42)
1897 msm_host->use_14lpp_dll_reset = true;
1900 * SDCC 5 controller with major version 1, minor version 0x34 and later
1901 * with HS 400 mode support will use CM DLL instead of CDC LP 533 DLL.
1903 if (core_major == 1 && core_minor < 0x34)
1904 msm_host->use_cdclp533 = true;
1907 * Support for some capabilities is not advertised by newer
1908 * controller versions and must be explicitly enabled.
1910 if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {
1911 config = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES);
1912 config |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
1913 writel_relaxed(config, host->ioaddr +
1914 msm_offset->core_vendor_spec_capabilities0);
1917 if (core_major == 1 && core_minor >= 0x49)
1918 msm_host->updated_ddr_cfg = true;
1921 * Power on reset state may trigger power irq if previous status of
1922 * PWRCTL was either BUS_ON or IO_HIGH_V. So before enabling pwr irq
1923 * interrupt in GIC, any pending power irq interrupt should be
1924 * acknowledged. Otherwise power irq interrupt handler would be
1925 * fired prematurely.
1927 sdhci_msm_handle_pwr_irq(host, 0);
1930 * Ensure that above writes are propogated before interrupt enablement
1935 /* Setup IRQ for handling power/voltage tasks with PMIC */
1936 msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq");
1937 if (msm_host->pwr_irq < 0) {
1938 ret = msm_host->pwr_irq;
1942 sdhci_msm_init_pwr_irq_wait(msm_host);
1943 /* Enable pwr irq interrupts */
1944 msm_host_writel(msm_host, INT_MASK, host,
1945 msm_offset->core_pwrctl_mask);
1947 ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL,
1948 sdhci_msm_pwr_irq, IRQF_ONESHOT,
1949 dev_name(&pdev->dev), host);
1951 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", ret);
1955 msm_host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_NEED_RSP_BUSY;
1957 pm_runtime_get_noresume(&pdev->dev);
1958 pm_runtime_set_active(&pdev->dev);
1959 pm_runtime_enable(&pdev->dev);
1960 pm_runtime_set_autosuspend_delay(&pdev->dev,
1961 MSM_MMC_AUTOSUSPEND_DELAY_MS);
1962 pm_runtime_use_autosuspend(&pdev->dev);
1964 host->mmc_host_ops.execute_tuning = sdhci_msm_execute_tuning;
1965 ret = sdhci_add_host(host);
1967 goto pm_runtime_disable;
1968 sdhci_msm_set_regulator_caps(msm_host);
1970 pm_runtime_mark_last_busy(&pdev->dev);
1971 pm_runtime_put_autosuspend(&pdev->dev);
1976 pm_runtime_disable(&pdev->dev);
1977 pm_runtime_set_suspended(&pdev->dev);
1978 pm_runtime_put_noidle(&pdev->dev);
1980 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
1981 msm_host->bulk_clks);
1983 if (!IS_ERR(msm_host->bus_clk))
1984 clk_disable_unprepare(msm_host->bus_clk);
1986 sdhci_pltfm_free(pdev);
1990 static int sdhci_msm_remove(struct platform_device *pdev)
1992 struct sdhci_host *host = platform_get_drvdata(pdev);
1993 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1994 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1995 int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) ==
1998 sdhci_remove_host(host, dead);
2000 pm_runtime_get_sync(&pdev->dev);
2001 pm_runtime_disable(&pdev->dev);
2002 pm_runtime_put_noidle(&pdev->dev);
2004 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
2005 msm_host->bulk_clks);
2006 if (!IS_ERR(msm_host->bus_clk))
2007 clk_disable_unprepare(msm_host->bus_clk);
2008 sdhci_pltfm_free(pdev);
2012 static __maybe_unused int sdhci_msm_runtime_suspend(struct device *dev)
2014 struct sdhci_host *host = dev_get_drvdata(dev);
2015 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2016 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2018 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
2019 msm_host->bulk_clks);
2024 static __maybe_unused int sdhci_msm_runtime_resume(struct device *dev)
2026 struct sdhci_host *host = dev_get_drvdata(dev);
2027 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2028 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2031 ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks),
2032 msm_host->bulk_clks);
2036 * Whenever core-clock is gated dynamically, it's needed to
2037 * restore the SDR DLL settings when the clock is ungated.
2039 if (msm_host->restore_dll_config && msm_host->clk_rate)
2040 return sdhci_msm_restore_sdr_dll_config(host);
2045 static const struct dev_pm_ops sdhci_msm_pm_ops = {
2046 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2047 pm_runtime_force_resume)
2048 SET_RUNTIME_PM_OPS(sdhci_msm_runtime_suspend,
2049 sdhci_msm_runtime_resume,
2053 static struct platform_driver sdhci_msm_driver = {
2054 .probe = sdhci_msm_probe,
2055 .remove = sdhci_msm_remove,
2057 .name = "sdhci_msm",
2058 .of_match_table = sdhci_msm_dt_match,
2059 .pm = &sdhci_msm_pm_ops,
2063 module_platform_driver(sdhci_msm_driver);
2065 MODULE_DESCRIPTION("Qualcomm Secure Digital Host Controller Interface driver");
2066 MODULE_LICENSE("GPL v2");