drivers/mmc/host/sdhci-esdhc-imx.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Freescale eSDHC i.MX controller driver for the platform bus.
   4  *
   5  * derived from the OF-version.
   6  *
   7  * Copyright (c) 2010 Pengutronix e.K.
   8  *   Author: Wolfram Sang <kernel@pengutronix.de>
   9  */
  10
  11 #include <linux/bitfield.h>
  12 #include <linux/io.h>
  13 #include <linux/iopoll.h>
  14 #include <linux/delay.h>
  15 #include <linux/err.h>
  16 #include <linux/clk.h>
  17 #include <linux/module.h>
  18 #include <linux/slab.h>
  19 #include <linux/pm_qos.h>
  20 #include <linux/mmc/host.h>
  21 #include <linux/mmc/mmc.h>
  22 #include <linux/mmc/sdio.h>
  23 #include <linux/mmc/slot-gpio.h>
  24 #include <linux/of.h>
  25 #include <linux/of_device.h>
  26 #include <linux/pinctrl/consumer.h>
  27 #include <linux/pm_runtime.h>
  28 #include "sdhci-cqhci.h"
  29 #include "sdhci-pltfm.h"
  30 #include "sdhci-esdhc.h"
  31 #include "cqhci.h"
  32
  33 #define ESDHC_SYS_CTRL_DTOCV_MASK       0x0f
  34 #define ESDHC_CTRL_D3CD                 0x08
  35 #define ESDHC_BURST_LEN_EN_INCR         (1 << 27)
  36 /* VENDOR SPEC register */
  37 #define ESDHC_VENDOR_SPEC               0xc0
  38 #define  ESDHC_VENDOR_SPEC_SDIO_QUIRK   (1 << 1)
  39 #define  ESDHC_VENDOR_SPEC_VSELECT      (1 << 1)
  40 #define  ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
  41 #define ESDHC_DEBUG_SEL_AND_STATUS_REG          0xc2
  42 #define ESDHC_DEBUG_SEL_REG                     0xc3
  43 #define ESDHC_DEBUG_SEL_MASK                    0xf
  44 #define ESDHC_DEBUG_SEL_CMD_STATE               1
  45 #define ESDHC_DEBUG_SEL_DATA_STATE              2
  46 #define ESDHC_DEBUG_SEL_TRANS_STATE             3
  47 #define ESDHC_DEBUG_SEL_DMA_STATE               4
  48 #define ESDHC_DEBUG_SEL_ADMA_STATE              5
  49 #define ESDHC_DEBUG_SEL_FIFO_STATE              6
  50 #define ESDHC_DEBUG_SEL_ASYNC_FIFO_STATE        7
  51 #define ESDHC_WTMK_LVL                  0x44
  52 #define  ESDHC_WTMK_DEFAULT_VAL         0x10401040
  53 #define  ESDHC_WTMK_LVL_RD_WML_MASK     0x000000FF
  54 #define  ESDHC_WTMK_LVL_RD_WML_SHIFT    0
  55 #define  ESDHC_WTMK_LVL_WR_WML_MASK     0x00FF0000
  56 #define  ESDHC_WTMK_LVL_WR_WML_SHIFT    16
  57 #define  ESDHC_WTMK_LVL_WML_VAL_DEF     64
  58 #define  ESDHC_WTMK_LVL_WML_VAL_MAX     128
  59 #define ESDHC_MIX_CTRL                  0x48
  60 #define  ESDHC_MIX_CTRL_DDREN           (1 << 3)
  61 #define  ESDHC_MIX_CTRL_AC23EN          (1 << 7)
  62 #define  ESDHC_MIX_CTRL_EXE_TUNE        (1 << 22)
  63 #define  ESDHC_MIX_CTRL_SMPCLK_SEL      (1 << 23)
  64 #define  ESDHC_MIX_CTRL_AUTO_TUNE_EN    (1 << 24)
  65 #define  ESDHC_MIX_CTRL_FBCLK_SEL       (1 << 25)
  66 #define  ESDHC_MIX_CTRL_HS400_EN        (1 << 26)
  67 #define  ESDHC_MIX_CTRL_HS400_ES_EN     (1 << 27)
  68 /* Bits 3 and 6 are not SDHCI standard definitions */
  69 #define  ESDHC_MIX_CTRL_SDHCI_MASK      0xb7
  70 /* Tuning bits */
  71 #define  ESDHC_MIX_CTRL_TUNING_MASK     0x03c00000
  72
  73 /* dll control register */
  74 #define ESDHC_DLL_CTRL                  0x60
  75 #define ESDHC_DLL_OVERRIDE_VAL_SHIFT    9
  76 #define ESDHC_DLL_OVERRIDE_EN_SHIFT     8
  77
  78 /* tune control register */
  79 #define ESDHC_TUNE_CTRL_STATUS          0x68
  80 #define  ESDHC_TUNE_CTRL_STEP           1
  81 #define  ESDHC_TUNE_CTRL_MIN            0
  82 #define  ESDHC_TUNE_CTRL_MAX            ((1 << 7) - 1)
  83
  84 /* strobe dll register */
  85 #define ESDHC_STROBE_DLL_CTRL           0x70
  86 #define ESDHC_STROBE_DLL_CTRL_ENABLE    (1 << 0)
  87 #define ESDHC_STROBE_DLL_CTRL_RESET     (1 << 1)
  88 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT    0x7
  89 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT      3
  90 #define ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT    (4 << 20)
  91
  92 #define ESDHC_STROBE_DLL_STATUS         0x74
  93 #define ESDHC_STROBE_DLL_STS_REF_LOCK   (1 << 1)
  94 #define ESDHC_STROBE_DLL_STS_SLV_LOCK   0x1
  95
  96 #define ESDHC_VEND_SPEC2                0xc8
  97 #define ESDHC_VEND_SPEC2_EN_BUSY_IRQ    (1 << 8)
  98 #define ESDHC_VEND_SPEC2_AUTO_TUNE_8BIT_EN      (1 << 4)
  99 #define ESDHC_VEND_SPEC2_AUTO_TUNE_4BIT_EN      (0 << 4)
 100 #define ESDHC_VEND_SPEC2_AUTO_TUNE_1BIT_EN      (2 << 4)
 101 #define ESDHC_VEND_SPEC2_AUTO_TUNE_CMD_EN       (1 << 6)
 102 #define ESDHC_VEND_SPEC2_AUTO_TUNE_MODE_MASK    (7 << 4)
 103
 104 #define ESDHC_TUNING_CTRL               0xcc
 105 #define ESDHC_STD_TUNING_EN             (1 << 24)
 106 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
 107 #define ESDHC_TUNING_START_TAP_DEFAULT  0x1
 108 #define ESDHC_TUNING_START_TAP_MASK     0x7f
 109 #define ESDHC_TUNING_CMD_CRC_CHECK_DISABLE      (1 << 7)
 110 #define ESDHC_TUNING_STEP_DEFAULT       0x1
 111 #define ESDHC_TUNING_STEP_MASK          0x00070000
 112 #define ESDHC_TUNING_STEP_SHIFT         16
 113
 114 /* pinctrl state */
 115 #define ESDHC_PINCTRL_STATE_100MHZ      "state_100mhz"
 116 #define ESDHC_PINCTRL_STATE_200MHZ      "state_200mhz"
 117
 118 /*
 119  * Our interpretation of the SDHCI_HOST_CONTROL register
 120  */
 121 #define ESDHC_CTRL_4BITBUS              (0x1 << 1)
 122 #define ESDHC_CTRL_8BITBUS              (0x2 << 1)
 123 #define ESDHC_CTRL_BUSWIDTH_MASK        (0x3 << 1)
 124 #define USDHC_GET_BUSWIDTH(c) (c & ESDHC_CTRL_BUSWIDTH_MASK)
 125
 126 /*
 127  * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC:
 128  * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
 129  * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
 130  * Define this macro DMA error INT for fsl eSDHC
 131  */
 132 #define ESDHC_INT_VENDOR_SPEC_DMA_ERR   (1 << 28)
 133
 134 /* the address offset of CQHCI */
 135 #define ESDHC_CQHCI_ADDR_OFFSET         0x100
 136
 137 /*
 138  * The CMDTYPE of the CMD register (offset 0xE) should be set to
 139  * "11" when the STOP CMD12 is issued on imx53 to abort one
 140  * open ended multi-blk IO. Otherwise the TC INT wouldn't
 141  * be generated.
 142  * In exact block transfer, the controller doesn't complete the
 143  * operations automatically as required at the end of the
 144  * transfer and remains on hold if the abort command is not sent.
 145  * As a result, the TC flag is not asserted and SW received timeout
 146  * exception. Bit1 of Vendor Spec register is used to fix it.
 147  */
 148 #define ESDHC_FLAG_MULTIBLK_NO_INT      BIT(1)
 149 /*
 150  * The flag tells that the ESDHC controller is an USDHC block that is
 151  * integrated on the i.MX6 series.
 152  */
 153 #define ESDHC_FLAG_USDHC                BIT(3)
 154 /* The IP supports manual tuning process */
 155 #define ESDHC_FLAG_MAN_TUNING           BIT(4)
 156 /* The IP supports standard tuning process */
 157 #define ESDHC_FLAG_STD_TUNING           BIT(5)
 158 /* The IP has SDHCI_CAPABILITIES_1 register */
 159 #define ESDHC_FLAG_HAVE_CAP1            BIT(6)
 160 /*
 161  * The IP has erratum ERR004536
 162  * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
 163  * when reading data from the card
 164  * This flag is also set for i.MX25 and i.MX35 in order to get
 165  * SDHCI_QUIRK_BROKEN_ADMA, but for different reasons (ADMA capability bits).
 166  */
 167 #define ESDHC_FLAG_ERR004536            BIT(7)
 168 /* The IP supports HS200 mode */
 169 #define ESDHC_FLAG_HS200                BIT(8)
 170 /* The IP supports HS400 mode */
 171 #define ESDHC_FLAG_HS400                BIT(9)
 172 /*
 173  * The IP has errata ERR010450
 174  * uSDHC: Due to the I/O timing limit, for SDR mode, SD card clock can't
 175  * exceed 150MHz, for DDR mode, SD card clock can't exceed 45MHz.
 176  */
 177 #define ESDHC_FLAG_ERR010450            BIT(10)
 178 /* The IP supports HS400ES mode */
 179 #define ESDHC_FLAG_HS400_ES             BIT(11)
 180 /* The IP has Host Controller Interface for Command Queuing */
 181 #define ESDHC_FLAG_CQHCI                BIT(12)
 182 /* need request pmqos during low power */
 183 #define ESDHC_FLAG_PMQOS                BIT(13)
 184 /* The IP state got lost in low power mode */
 185 #define ESDHC_FLAG_STATE_LOST_IN_LPMODE         BIT(14)
 186 /* The IP lost clock rate in PM_RUNTIME */
 187 #define ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME  BIT(15)
 188 /*
 189  * The IP do not support the ACMD23 feature completely when use ADMA mode.
 190  * In ADMA mode, it only use the 16 bit block count of the register 0x4
 191  * (BLOCK_ATT) as the CMD23's argument for ACMD23 mode, which means it will
 192  * ignore the upper 16 bit of the CMD23's argument. This will block the reliable
 193  * write operation in RPMB, because RPMB reliable write need to set the bit31
 194  * of the CMD23's argument.
 195  * imx6qpdl/imx6sx/imx6sl/imx7d has this limitation only for ADMA mode, SDMA
 196  * do not has this limitation. so when these SoC use ADMA mode, it need to
 197  * disable the ACMD23 feature.
 198  */
 199 #define ESDHC_FLAG_BROKEN_AUTO_CMD23    BIT(16)
 200
 201 /* ERR004536 is not applicable for the IP  */
 202 #define ESDHC_FLAG_SKIP_ERR004536       BIT(17)
 203
 204 enum wp_types {
 205         ESDHC_WP_NONE,          /* no WP, neither controller nor gpio */
 206         ESDHC_WP_CONTROLLER,    /* mmc controller internal WP */
 207         ESDHC_WP_GPIO,          /* external gpio pin for WP */
 208 };
 209
 210 enum cd_types {
 211         ESDHC_CD_NONE,          /* no CD, neither controller nor gpio */
 212         ESDHC_CD_CONTROLLER,    /* mmc controller internal CD */
 213         ESDHC_CD_GPIO,          /* external gpio pin for CD */
 214         ESDHC_CD_PERMANENT,     /* no CD, card permanently wired to host */
 215 };
 216
 217 /*
 218  * struct esdhc_platform_data - platform data for esdhc on i.MX
 219  *
 220  * ESDHC_WP(CD)_CONTROLLER type is not available on i.MX25/35.
 221  *
 222  * @wp_type:    type of write_protect method (see wp_types enum above)
 223  * @cd_type:    type of card_detect method (see cd_types enum above)
 224  */
 225
 226 struct esdhc_platform_data {
 227         enum wp_types wp_type;
 228         enum cd_types cd_type;
 229         int max_bus_width;
 230         unsigned int delay_line;
 231         unsigned int tuning_step;       /* The delay cell steps in tuning procedure */
 232         unsigned int tuning_start_tap;  /* The start delay cell point in tuning procedure */
 233         unsigned int strobe_dll_delay_target;   /* The delay cell for strobe pad (read clock) */
 234 };
 235
 236 struct esdhc_soc_data {
 237         u32 flags;
 238 };
 239
 240 static const struct esdhc_soc_data esdhc_imx25_data = {
 241         .flags = ESDHC_FLAG_ERR004536,
 242 };
 243
 244 static const struct esdhc_soc_data esdhc_imx35_data = {
 245         .flags = ESDHC_FLAG_ERR004536,
 246 };
 247
 248 static const struct esdhc_soc_data esdhc_imx51_data = {
 249         .flags = 0,
 250 };
 251
 252 static const struct esdhc_soc_data esdhc_imx53_data = {
 253         .flags = ESDHC_FLAG_MULTIBLK_NO_INT,
 254 };
 255
 256 static const struct esdhc_soc_data usdhc_imx6q_data = {
 257         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING
 258                         | ESDHC_FLAG_BROKEN_AUTO_CMD23,
 259 };
 260
 261 static const struct esdhc_soc_data usdhc_imx6sl_data = {
 262         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 263                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536
 264                         | ESDHC_FLAG_HS200
 265                         | ESDHC_FLAG_BROKEN_AUTO_CMD23,
 266 };
 267
 268 static const struct esdhc_soc_data usdhc_imx6sll_data = {
 269         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 270                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 271                         | ESDHC_FLAG_HS400
 272                         | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
 273 };
 274
 275 static const struct esdhc_soc_data usdhc_imx6sx_data = {
 276         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 277                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 278                         | ESDHC_FLAG_STATE_LOST_IN_LPMODE
 279                         | ESDHC_FLAG_BROKEN_AUTO_CMD23,
 280 };
 281
 282 static const struct esdhc_soc_data usdhc_imx6ull_data = {
 283         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 284                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 285                         | ESDHC_FLAG_ERR010450
 286                         | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
 287 };
 288
 289 static const struct esdhc_soc_data usdhc_imx7d_data = {
 290         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 291                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 292                         | ESDHC_FLAG_HS400
 293                         | ESDHC_FLAG_STATE_LOST_IN_LPMODE
 294                         | ESDHC_FLAG_BROKEN_AUTO_CMD23,
 295 };
 296
 297 static struct esdhc_soc_data usdhc_s32g2_data = {
 298         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING
 299                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 300                         | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
 301                         | ESDHC_FLAG_SKIP_ERR004536,
 302 };
 303
 304 static struct esdhc_soc_data usdhc_imx7ulp_data = {
 305         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 306                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 307                         | ESDHC_FLAG_PMQOS | ESDHC_FLAG_HS400
 308                         | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
 309 };
 310 static struct esdhc_soc_data usdhc_imxrt1050_data = {
 311         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 312                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200,
 313 };
 314
 315 static struct esdhc_soc_data usdhc_imx8qxp_data = {
 316         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 317                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 318                         | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
 319                         | ESDHC_FLAG_STATE_LOST_IN_LPMODE
 320                         | ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME,
 321 };
 322
 323 static struct esdhc_soc_data usdhc_imx8mm_data = {
 324         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 325                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 326                         | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
 327                         | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
 328 };
 329
 330 struct pltfm_imx_data {
 331         u32 scratchpad;
 332         struct pinctrl *pinctrl;
 333         struct pinctrl_state *pins_100mhz;
 334         struct pinctrl_state *pins_200mhz;
 335         const struct esdhc_soc_data *socdata;
 336         struct esdhc_platform_data boarddata;
 337         struct clk *clk_ipg;
 338         struct clk *clk_ahb;
 339         struct clk *clk_per;
 340         unsigned int actual_clock;
 341         enum {
 342                 NO_CMD_PENDING,      /* no multiblock command pending */
 343                 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
 344                 WAIT_FOR_INT,        /* sent CMD12, waiting for response INT */
 345         } multiblock_status;
 346         u32 is_ddr;
 347         struct pm_qos_request pm_qos_req;
 348 };
 349
 350 static const struct of_device_id imx_esdhc_dt_ids[] = {
 351         { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
 352         { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
 353         { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
 354         { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
 355         { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
 356         { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
 357         { .compatible = "fsl,imx6sll-usdhc", .data = &usdhc_imx6sll_data, },
 358         { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
 359         { .compatible = "fsl,imx6ull-usdhc", .data = &usdhc_imx6ull_data, },
 360         { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
 361         { .compatible = "fsl,imx7ulp-usdhc", .data = &usdhc_imx7ulp_data, },
 362         { .compatible = "fsl,imx8qxp-usdhc", .data = &usdhc_imx8qxp_data, },
 363         { .compatible = "fsl,imx8mm-usdhc", .data = &usdhc_imx8mm_data, },
 364         { .compatible = "fsl,imxrt1050-usdhc", .data = &usdhc_imxrt1050_data, },
 365         { .compatible = "nxp,s32g2-usdhc", .data = &usdhc_s32g2_data, },
 366         { /* sentinel */ }
 367 };
 368 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
 369
 370 static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
 371 {
 372         return data->socdata == &esdhc_imx25_data;
 373 }
 374
 375 static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
 376 {
 377         return data->socdata == &esdhc_imx53_data;
 378 }
 379
 380 static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
 381 {
 382         return !!(data->socdata->flags & ESDHC_FLAG_USDHC);
 383 }
 384
 385 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
 386 {
 387         void __iomem *base = host->ioaddr + (reg & ~0x3);
 388         u32 shift = (reg & 0x3) * 8;
 389
 390         writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
 391 }
 392
 393 #define DRIVER_NAME "sdhci-esdhc-imx"
 394 #define ESDHC_IMX_DUMP(f, x...) \
 395         pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
 396 static void esdhc_dump_debug_regs(struct sdhci_host *host)
 397 {
 398         int i;
 399         char *debug_status[7] = {
 400                                  "cmd debug status",
 401                                  "data debug status",
 402                                  "trans debug status",
 403                                  "dma debug status",
 404                                  "adma debug status",
 405                                  "fifo debug status",
 406                                  "async fifo debug status"
 407         };
 408
 409         ESDHC_IMX_DUMP("========= ESDHC IMX DEBUG STATUS DUMP =========\n");
 410         for (i = 0; i < 7; i++) {
 411                 esdhc_clrset_le(host, ESDHC_DEBUG_SEL_MASK,
 412                         ESDHC_DEBUG_SEL_CMD_STATE + i, ESDHC_DEBUG_SEL_REG);
 413                 ESDHC_IMX_DUMP("%s:  0x%04x\n", debug_status[i],
 414                         readw(host->ioaddr + ESDHC_DEBUG_SEL_AND_STATUS_REG));
 415         }
 416
 417         esdhc_clrset_le(host, ESDHC_DEBUG_SEL_MASK, 0, ESDHC_DEBUG_SEL_REG);
 418
 419 }
 420
 421 static inline void esdhc_wait_for_card_clock_gate_off(struct sdhci_host *host)
 422 {
 423         u32 present_state;
 424         int ret;
 425
 426         ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, present_state,
 427                                 (present_state & ESDHC_CLOCK_GATE_OFF), 2, 100);
 428         if (ret == -ETIMEDOUT)
 429                 dev_warn(mmc_dev(host->mmc), "%s: card clock still not gate off in 100us!.\n", __func__);
 430 }
 431
 432 /* Enable the auto tuning circuit to check the CMD line and BUS line */
 433 static inline void usdhc_auto_tuning_mode_sel(struct sdhci_host *host)
 434 {
 435         u32 buswidth, auto_tune_buswidth;
 436
 437         buswidth = USDHC_GET_BUSWIDTH(readl(host->ioaddr + SDHCI_HOST_CONTROL));
 438
 439         switch (buswidth) {
 440         case ESDHC_CTRL_8BITBUS:
 441                 auto_tune_buswidth = ESDHC_VEND_SPEC2_AUTO_TUNE_8BIT_EN;
 442                 break;
 443         case ESDHC_CTRL_4BITBUS:
 444                 auto_tune_buswidth = ESDHC_VEND_SPEC2_AUTO_TUNE_4BIT_EN;
 445                 break;
 446         default:        /* 1BITBUS */
 447                 auto_tune_buswidth = ESDHC_VEND_SPEC2_AUTO_TUNE_1BIT_EN;
 448                 break;
 449         }
 450
 451         esdhc_clrset_le(host, ESDHC_VEND_SPEC2_AUTO_TUNE_MODE_MASK,
 452                         auto_tune_buswidth | ESDHC_VEND_SPEC2_AUTO_TUNE_CMD_EN,
 453                         ESDHC_VEND_SPEC2);
 454 }
 455
 456 static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
 457 {
 458         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 459         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 460         u32 val = readl(host->ioaddr + reg);
 461
 462         if (unlikely(reg == SDHCI_PRESENT_STATE)) {
 463                 u32 fsl_prss = val;
 464                 /* save the least 20 bits */
 465                 val = fsl_prss & 0x000FFFFF;
 466                 /* move dat[0-3] bits */
 467                 val |= (fsl_prss & 0x0F000000) >> 4;
 468                 /* move cmd line bit */
 469                 val |= (fsl_prss & 0x00800000) << 1;
 470         }
 471
 472         if (unlikely(reg == SDHCI_CAPABILITIES)) {
 473                 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */
 474                 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
 475                         val &= 0xffff0000;
 476
 477                 /* In FSL esdhc IC module, only bit20 is used to indicate the
 478                  * ADMA2 capability of esdhc, but this bit is messed up on
 479                  * some SOCs (e.g. on MX25, MX35 this bit is set, but they
 480                  * don't actually support ADMA2). So set the BROKEN_ADMA
 481                  * quirk on MX25/35 platforms.
 482                  */
 483
 484                 if (val & SDHCI_CAN_DO_ADMA1) {
 485                         val &= ~SDHCI_CAN_DO_ADMA1;
 486                         val |= SDHCI_CAN_DO_ADMA2;
 487                 }
 488         }
 489
 490         if (unlikely(reg == SDHCI_CAPABILITIES_1)) {
 491                 if (esdhc_is_usdhc(imx_data)) {
 492                         if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
 493                                 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;
 494                         else
 495                                 /* imx6q/dl does not have cap_1 register, fake one */
 496                                 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
 497                                         | SDHCI_SUPPORT_SDR50
 498                                         | SDHCI_USE_SDR50_TUNING
 499                                         | FIELD_PREP(SDHCI_RETUNING_MODE_MASK,
 500                                                      SDHCI_TUNING_MODE_3);
 501
 502                         /*
 503                          * Do not advertise faster UHS modes if there are no
 504                          * pinctrl states for 100MHz/200MHz.
 505                          */
 506                         if (IS_ERR_OR_NULL(imx_data->pins_100mhz))
 507                                 val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50);
 508                         if (IS_ERR_OR_NULL(imx_data->pins_200mhz))
 509                                 val &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);
 510                 }
 511         }
 512
 513         if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
 514                 val = 0;
 515                 val |= FIELD_PREP(SDHCI_MAX_CURRENT_330_MASK, 0xFF);
 516                 val |= FIELD_PREP(SDHCI_MAX_CURRENT_300_MASK, 0xFF);
 517                 val |= FIELD_PREP(SDHCI_MAX_CURRENT_180_MASK, 0xFF);
 518         }
 519
 520         if (unlikely(reg == SDHCI_INT_STATUS)) {
 521                 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
 522                         val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
 523                         val |= SDHCI_INT_ADMA_ERROR;
 524                 }
 525
 526                 /*
 527                  * mask off the interrupt we get in response to the manually
 528                  * sent CMD12
 529                  */
 530                 if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
 531                     ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
 532                         val &= ~SDHCI_INT_RESPONSE;
 533                         writel(SDHCI_INT_RESPONSE, host->ioaddr +
 534                                                    SDHCI_INT_STATUS);
 535                         imx_data->multiblock_status = NO_CMD_PENDING;
 536                 }
 537         }
 538
 539         return val;
 540 }
 541
 542 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
 543 {
 544         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 545         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 546         u32 data;
 547
 548         if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE ||
 549                         reg == SDHCI_INT_STATUS)) {
 550                 if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) {
 551                         /*
 552                          * Clear and then set D3CD bit to avoid missing the
 553                          * card interrupt. This is an eSDHC controller problem
 554                          * so we need to apply the following workaround: clear
 555                          * and set D3CD bit will make eSDHC re-sample the card
 556                          * interrupt. In case a card interrupt was lost,
 557                          * re-sample it by the following steps.
 558                          */
 559                         data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
 560                         data &= ~ESDHC_CTRL_D3CD;
 561                         writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
 562                         data |= ESDHC_CTRL_D3CD;
 563                         writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
 564                 }
 565
 566                 if (val & SDHCI_INT_ADMA_ERROR) {
 567                         val &= ~SDHCI_INT_ADMA_ERROR;
 568                         val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
 569                 }
 570         }
 571
 572         if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
 573                                 && (reg == SDHCI_INT_STATUS)
 574                                 && (val & SDHCI_INT_DATA_END))) {
 575                         u32 v;
 576                         v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 577                         v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
 578                         writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
 579
 580                         if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
 581                         {
 582                                 /* send a manual CMD12 with RESPTYP=none */
 583                                 data = MMC_STOP_TRANSMISSION << 24 |
 584                                        SDHCI_CMD_ABORTCMD << 16;
 585                                 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
 586                                 imx_data->multiblock_status = WAIT_FOR_INT;
 587                         }
 588         }
 589
 590         writel(val, host->ioaddr + reg);
 591 }
 592
 593 static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
 594 {
 595         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 596         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 597         u16 ret = 0;
 598         u32 val;
 599
 600         if (unlikely(reg == SDHCI_HOST_VERSION)) {
 601                 reg ^= 2;
 602                 if (esdhc_is_usdhc(imx_data)) {
 603                         /*
 604                          * The usdhc register returns a wrong host version.
 605                          * Correct it here.
 606                          */
 607                         return SDHCI_SPEC_300;
 608                 }
 609         }
 610
 611         if (unlikely(reg == SDHCI_HOST_CONTROL2)) {
 612                 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 613                 if (val & ESDHC_VENDOR_SPEC_VSELECT)
 614                         ret |= SDHCI_CTRL_VDD_180;
 615
 616                 if (esdhc_is_usdhc(imx_data)) {
 617                         if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
 618                                 val = readl(host->ioaddr + ESDHC_MIX_CTRL);
 619                         else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
 620                                 /* the std tuning bits is in ACMD12_ERR for imx6sl */
 621                                 val = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
 622                 }
 623
 624                 if (val & ESDHC_MIX_CTRL_EXE_TUNE)
 625                         ret |= SDHCI_CTRL_EXEC_TUNING;
 626                 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
 627                         ret |= SDHCI_CTRL_TUNED_CLK;
 628
 629                 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
 630
 631                 return ret;
 632         }
 633
 634         if (unlikely(reg == SDHCI_TRANSFER_MODE)) {
 635                 if (esdhc_is_usdhc(imx_data)) {
 636                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 637                         ret = m & ESDHC_MIX_CTRL_SDHCI_MASK;
 638                         /* Swap AC23 bit */
 639                         if (m & ESDHC_MIX_CTRL_AC23EN) {
 640                                 ret &= ~ESDHC_MIX_CTRL_AC23EN;
 641                                 ret |= SDHCI_TRNS_AUTO_CMD23;
 642                         }
 643                 } else {
 644                         ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
 645                 }
 646
 647                 return ret;
 648         }
 649
 650         return readw(host->ioaddr + reg);
 651 }
 652
 653 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
 654 {
 655         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 656         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 657         u32 new_val = 0;
 658
 659         switch (reg) {
 660         case SDHCI_CLOCK_CONTROL:
 661                 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 662                 if (val & SDHCI_CLOCK_CARD_EN)
 663                         new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
 664                 else
 665                         new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
 666                 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
 667                 if (!(new_val & ESDHC_VENDOR_SPEC_FRC_SDCLK_ON))
 668                         esdhc_wait_for_card_clock_gate_off(host);
 669                 return;
 670         case SDHCI_HOST_CONTROL2:
 671                 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 672                 if (val & SDHCI_CTRL_VDD_180)
 673                         new_val |= ESDHC_VENDOR_SPEC_VSELECT;
 674                 else
 675                         new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
 676                 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
 677                 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
 678                         u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
 679                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 680                         if (val & SDHCI_CTRL_TUNED_CLK) {
 681                                 v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
 682                         } else {
 683                                 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
 684                                 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
 685                                 m &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
 686                         }
 687
 688                         if (val & SDHCI_CTRL_EXEC_TUNING) {
 689                                 v |= ESDHC_MIX_CTRL_EXE_TUNE;
 690                                 m |= ESDHC_MIX_CTRL_FBCLK_SEL;
 691                                 m |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
 692                                 usdhc_auto_tuning_mode_sel(host);
 693                         } else {
 694                                 v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
 695                         }
 696
 697                         writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
 698                         writel(m, host->ioaddr + ESDHC_MIX_CTRL);
 699                 }
 700                 return;
 701         case SDHCI_TRANSFER_MODE:
 702                 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
 703                                 && (host->cmd->opcode == SD_IO_RW_EXTENDED)
 704                                 && (host->cmd->data->blocks > 1)
 705                                 && (host->cmd->data->flags & MMC_DATA_READ)) {
 706                         u32 v;
 707                         v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 708                         v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
 709                         writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
 710                 }
 711
 712                 if (esdhc_is_usdhc(imx_data)) {
 713                         u32 wml;
 714                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 715                         /* Swap AC23 bit */
 716                         if (val & SDHCI_TRNS_AUTO_CMD23) {
 717                                 val &= ~SDHCI_TRNS_AUTO_CMD23;
 718                                 val |= ESDHC_MIX_CTRL_AC23EN;
 719                         }
 720                         m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
 721                         writel(m, host->ioaddr + ESDHC_MIX_CTRL);
 722
 723                         /* Set watermark levels for PIO access to maximum value
 724                          * (128 words) to accommodate full 512 bytes buffer.
 725                          * For DMA access restore the levels to default value.
 726                          */
 727                         m = readl(host->ioaddr + ESDHC_WTMK_LVL);
 728                         if (val & SDHCI_TRNS_DMA) {
 729                                 wml = ESDHC_WTMK_LVL_WML_VAL_DEF;
 730                         } else {
 731                                 u8 ctrl;
 732                                 wml = ESDHC_WTMK_LVL_WML_VAL_MAX;
 733
 734                                 /*
 735                                  * Since already disable DMA mode, so also need
 736                                  * to clear the DMASEL. Otherwise, for standard
 737                                  * tuning, when send tuning command, usdhc will
 738                                  * still prefetch the ADMA script from wrong
 739                                  * DMA address, then we will see IOMMU report
 740                                  * some error which show lack of TLB mapping.
 741                                  */
 742                                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 743                                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
 744                                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 745                         }
 746                         m &= ~(ESDHC_WTMK_LVL_RD_WML_MASK |
 747                                ESDHC_WTMK_LVL_WR_WML_MASK);
 748                         m |= (wml << ESDHC_WTMK_LVL_RD_WML_SHIFT) |
 749                              (wml << ESDHC_WTMK_LVL_WR_WML_SHIFT);
 750                         writel(m, host->ioaddr + ESDHC_WTMK_LVL);
 751                 } else {
 752                         /*
 753                          * Postpone this write, we must do it together with a
 754                          * command write that is down below.
 755                          */
 756                         imx_data->scratchpad = val;
 757                 }
 758                 return;
 759         case SDHCI_COMMAND:
 760                 if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
 761                         val |= SDHCI_CMD_ABORTCMD;
 762
 763                 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
 764                     (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
 765                         imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
 766
 767                 if (esdhc_is_usdhc(imx_data))
 768                         writel(val << 16,
 769                                host->ioaddr + SDHCI_TRANSFER_MODE);
 770                 else
 771                         writel(val << 16 | imx_data->scratchpad,
 772                                host->ioaddr + SDHCI_TRANSFER_MODE);
 773                 return;
 774         case SDHCI_BLOCK_SIZE:
 775                 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
 776                 break;
 777         }
 778         esdhc_clrset_le(host, 0xffff, val, reg);
 779 }
 780
 781 static u8 esdhc_readb_le(struct sdhci_host *host, int reg)
 782 {
 783         u8 ret;
 784         u32 val;
 785
 786         switch (reg) {
 787         case SDHCI_HOST_CONTROL:
 788                 val = readl(host->ioaddr + reg);
 789
 790                 ret = val & SDHCI_CTRL_LED;
 791                 ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK;
 792                 ret |= (val & ESDHC_CTRL_4BITBUS);
 793                 ret |= (val & ESDHC_CTRL_8BITBUS) << 3;
 794                 return ret;
 795         }
 796
 797         return readb(host->ioaddr + reg);
 798 }
 799
 800 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
 801 {
 802         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 803         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 804         u32 new_val = 0;
 805         u32 mask;
 806
 807         switch (reg) {
 808         case SDHCI_POWER_CONTROL:
 809                 /*
 810                  * FSL put some DMA bits here
 811                  * If your board has a regulator, code should be here
 812                  */
 813                 return;
 814         case SDHCI_HOST_CONTROL:
 815                 /* FSL messed up here, so we need to manually compose it. */
 816                 new_val = val & SDHCI_CTRL_LED;
 817                 /* ensure the endianness */
 818                 new_val |= ESDHC_HOST_CONTROL_LE;
 819                 /* bits 8&9 are reserved on mx25 */
 820                 if (!is_imx25_esdhc(imx_data)) {
 821                         /* DMA mode bits are shifted */
 822                         new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
 823                 }
 824
 825                 /*
 826                  * Do not touch buswidth bits here. This is done in
 827                  * esdhc_pltfm_bus_width.
 828                  * Do not touch the D3CD bit either which is used for the
 829                  * SDIO interrupt erratum workaround.
 830                  */
 831                 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
 832
 833                 esdhc_clrset_le(host, mask, new_val, reg);
 834                 return;
 835         case SDHCI_SOFTWARE_RESET:
 836                 if (val & SDHCI_RESET_DATA)
 837                         new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL);
 838                 break;
 839         }
 840         esdhc_clrset_le(host, 0xff, val, reg);
 841
 842         if (reg == SDHCI_SOFTWARE_RESET) {
 843                 if (val & SDHCI_RESET_ALL) {
 844                         /*
 845                          * The esdhc has a design violation to SDHC spec which
 846                          * tells that software reset should not affect card
 847                          * detection circuit. But esdhc clears its SYSCTL
 848                          * register bits [0..2] during the software reset. This
 849                          * will stop those clocks that card detection circuit
 850                          * relies on. To work around it, we turn the clocks on
 851                          * back to keep card detection circuit functional.
 852                          */
 853                         esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
 854                         /*
 855                          * The reset on usdhc fails to clear MIX_CTRL register.
 856                          * Do it manually here.
 857                          */
 858                         if (esdhc_is_usdhc(imx_data)) {
 859                                 /*
 860                                  * the tuning bits should be kept during reset
 861                                  */
 862                                 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
 863                                 writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,
 864                                                 host->ioaddr + ESDHC_MIX_CTRL);
 865                                 imx_data->is_ddr = 0;
 866                         }
 867                 } else if (val & SDHCI_RESET_DATA) {
 868                         /*
 869                          * The eSDHC DAT line software reset clears at least the
 870                          * data transfer width on i.MX25, so make sure that the
 871                          * Host Control register is unaffected.
 872                          */
 873                         esdhc_clrset_le(host, 0xff, new_val,
 874                                         SDHCI_HOST_CONTROL);
 875                 }
 876         }
 877 }
 878
 879 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
 880 {
 881         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 882
 883         return pltfm_host->clock;
 884 }
 885
 886 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
 887 {
 888         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 889
 890         return pltfm_host->clock / 256 / 16;
 891 }
 892
 893 static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
 894                                          unsigned int clock)
 895 {
 896         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 897         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 898         unsigned int host_clock = pltfm_host->clock;
 899         int ddr_pre_div = imx_data->is_ddr ? 2 : 1;
 900         int pre_div = 1;
 901         int div = 1;
 902         int ret;
 903         u32 temp, val;
 904
 905         if (esdhc_is_usdhc(imx_data)) {
 906                 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 907                 writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
 908                         host->ioaddr + ESDHC_VENDOR_SPEC);
 909                 esdhc_wait_for_card_clock_gate_off(host);
 910         }
 911
 912         if (clock == 0) {
 913                 host->mmc->actual_clock = 0;
 914                 return;
 915         }
 916
 917         /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
 918         if (is_imx53_esdhc(imx_data)) {
 919                 /*
 920                  * According to the i.MX53 reference manual, if DLLCTRL[10] can
 921                  * be set, then the controller is eSDHCv3, else it is eSDHCv2.
 922                  */
 923                 val = readl(host->ioaddr + ESDHC_DLL_CTRL);
 924                 writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL);
 925                 temp = readl(host->ioaddr + ESDHC_DLL_CTRL);
 926                 writel(val, host->ioaddr + ESDHC_DLL_CTRL);
 927                 if (temp & BIT(10))
 928                         pre_div = 2;
 929         }
 930
 931         temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
 932         temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
 933                 | ESDHC_CLOCK_MASK);
 934         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
 935
 936         if (imx_data->socdata->flags & ESDHC_FLAG_ERR010450) {
 937                 unsigned int max_clock;
 938
 939                 max_clock = imx_data->is_ddr ? 45000000 : 150000000;
 940
 941                 clock = min(clock, max_clock);
 942         }
 943
 944         while (host_clock / (16 * pre_div * ddr_pre_div) > clock &&
 945                         pre_div < 256)
 946                 pre_div *= 2;
 947
 948         while (host_clock / (div * pre_div * ddr_pre_div) > clock && div < 16)
 949                 div++;
 950
 951         host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div);
 952         dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
 953                 clock, host->mmc->actual_clock);
 954
 955         pre_div >>= 1;
 956         div--;
 957
 958         temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
 959         temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
 960                 | (div << ESDHC_DIVIDER_SHIFT)
 961                 | (pre_div << ESDHC_PREDIV_SHIFT));
 962         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
 963
 964         /* need to wait the bit 3 of the PRSSTAT to be set, make sure card clock is stable */
 965         ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, temp,
 966                                 (temp & ESDHC_CLOCK_STABLE), 2, 100);
 967         if (ret == -ETIMEDOUT)
 968                 dev_warn(mmc_dev(host->mmc), "card clock still not stable in 100us!.\n");
 969
 970         if (esdhc_is_usdhc(imx_data)) {
 971                 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 972                 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
 973                         host->ioaddr + ESDHC_VENDOR_SPEC);
 974         }
 975
 976 }
 977
 978 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
 979 {
 980         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 981         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 982         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
 983
 984         switch (boarddata->wp_type) {
 985         case ESDHC_WP_GPIO:
 986                 return mmc_gpio_get_ro(host->mmc);
 987         case ESDHC_WP_CONTROLLER:
 988                 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
 989                                SDHCI_WRITE_PROTECT);
 990         case ESDHC_WP_NONE:
 991                 break;
 992         }
 993
 994         return -ENOSYS;
 995 }
 996
 997 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
 998 {
 999         u32 ctrl;
1000
1001         switch (width) {
1002         case MMC_BUS_WIDTH_8:
1003                 ctrl = ESDHC_CTRL_8BITBUS;
1004                 break;
1005         case MMC_BUS_WIDTH_4:
1006                 ctrl = ESDHC_CTRL_4BITBUS;
1007                 break;
1008         default:
1009                 ctrl = 0;
1010                 break;
1011         }
1012
1013         esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
1014                         SDHCI_HOST_CONTROL);
1015 }
1016
1017 static void esdhc_reset_tuning(struct sdhci_host *host)
1018 {
1019         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1020         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1021         u32 ctrl;
1022         int ret;
1023
1024         /* Reset the tuning circuit */
1025         if (esdhc_is_usdhc(imx_data)) {
1026                 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
1027                         ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL);
1028                         ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
1029                         ctrl &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
1030                         writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL);
1031                         writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1032                 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
1033                         ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1034                         ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
1035                         ctrl &= ~ESDHC_MIX_CTRL_EXE_TUNE;
1036                         writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1037                         /* Make sure ESDHC_MIX_CTRL_EXE_TUNE cleared */
1038                         ret = readl_poll_timeout(host->ioaddr + SDHCI_AUTO_CMD_STATUS,
1039                                 ctrl, !(ctrl & ESDHC_MIX_CTRL_EXE_TUNE), 1, 50);
1040                         if (ret == -ETIMEDOUT)
1041                                 dev_warn(mmc_dev(host->mmc),
1042                                  "Warning! clear execute tuning bit failed\n");
1043                         /*
1044                          * SDHCI_INT_DATA_AVAIL is W1C bit, set this bit will clear the
1045                          * usdhc IP internal logic flag execute_tuning_with_clr_buf, which
1046                          * will finally make sure the normal data transfer logic correct.
1047                          */
1048                         ctrl = readl(host->ioaddr + SDHCI_INT_STATUS);
1049                         ctrl |= SDHCI_INT_DATA_AVAIL;
1050                         writel(ctrl, host->ioaddr + SDHCI_INT_STATUS);
1051                 }
1052         }
1053 }
1054
1055 static int usdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1056 {
1057         struct sdhci_host *host = mmc_priv(mmc);
1058
1059         /*
1060          * i.MX uSDHC internally already uses a fixed optimized timing for
1061          * DDR50, normally does not require tuning for DDR50 mode.
1062          */
1063         if (host->timing == MMC_TIMING_UHS_DDR50)
1064                 return 0;
1065
1066         /*
1067          * Reset tuning circuit logic. If not, the previous tuning result
1068          * will impact current tuning, make current tuning can't set the
1069          * correct delay cell.
1070          */
1071         esdhc_reset_tuning(host);
1072         return sdhci_execute_tuning(mmc, opcode);
1073 }
1074
1075 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
1076 {
1077         u32 reg;
1078         u8 sw_rst;
1079         int ret;
1080
1081         /* FIXME: delay a bit for card to be ready for next tuning due to errors */
1082         mdelay(1);
1083
1084         /* IC suggest to reset USDHC before every tuning command */
1085         esdhc_clrset_le(host, 0xff, SDHCI_RESET_ALL, SDHCI_SOFTWARE_RESET);
1086         ret = readb_poll_timeout(host->ioaddr + SDHCI_SOFTWARE_RESET, sw_rst,
1087                                 !(sw_rst & SDHCI_RESET_ALL), 10, 100);
1088         if (ret == -ETIMEDOUT)
1089                 dev_warn(mmc_dev(host->mmc),
1090                 "warning! RESET_ALL never complete before sending tuning command\n");
1091
1092         reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
1093         reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
1094                         ESDHC_MIX_CTRL_FBCLK_SEL;
1095         writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
1096         writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1097         dev_dbg(mmc_dev(host->mmc),
1098                 "tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
1099                         val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
1100 }
1101
1102 static void esdhc_post_tuning(struct sdhci_host *host)
1103 {
1104         u32 reg;
1105
1106         usdhc_auto_tuning_mode_sel(host);
1107
1108         reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
1109         reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
1110         reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
1111         writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
1112 }
1113
1114 static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
1115 {
1116         int min, max, avg, ret;
1117
1118         /* find the mininum delay first which can pass tuning */
1119         min = ESDHC_TUNE_CTRL_MIN;
1120         while (min < ESDHC_TUNE_CTRL_MAX) {
1121                 esdhc_prepare_tuning(host, min);
1122                 if (!mmc_send_tuning(host->mmc, opcode, NULL))
1123                         break;
1124                 min += ESDHC_TUNE_CTRL_STEP;
1125         }
1126
1127         /* find the maxinum delay which can not pass tuning */
1128         max = min + ESDHC_TUNE_CTRL_STEP;
1129         while (max < ESDHC_TUNE_CTRL_MAX) {
1130                 esdhc_prepare_tuning(host, max);
1131                 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
1132                         max -= ESDHC_TUNE_CTRL_STEP;
1133                         break;
1134                 }
1135                 max += ESDHC_TUNE_CTRL_STEP;
1136         }
1137
1138         /* use average delay to get the best timing */
1139         avg = (min + max) / 2;
1140         esdhc_prepare_tuning(host, avg);
1141         ret = mmc_send_tuning(host->mmc, opcode, NULL);
1142         esdhc_post_tuning(host);
1143
1144         dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n",
1145                 ret ? "failed" : "passed", avg, ret);
1146
1147         return ret;
1148 }
1149
1150 static void esdhc_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios)
1151 {
1152         struct sdhci_host *host = mmc_priv(mmc);
1153         u32 m;
1154
1155         m = readl(host->ioaddr + ESDHC_MIX_CTRL);
1156         if (ios->enhanced_strobe)
1157                 m |= ESDHC_MIX_CTRL_HS400_ES_EN;
1158         else
1159                 m &= ~ESDHC_MIX_CTRL_HS400_ES_EN;
1160         writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1161 }
1162
1163 static int esdhc_change_pinstate(struct sdhci_host *host,
1164                                                 unsigned int uhs)
1165 {
1166         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1167         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1168         struct pinctrl_state *pinctrl;
1169
1170         dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
1171
1172         if (IS_ERR(imx_data->pinctrl) ||
1173                 IS_ERR(imx_data->pins_100mhz) ||
1174                 IS_ERR(imx_data->pins_200mhz))
1175                 return -EINVAL;
1176
1177         switch (uhs) {
1178         case MMC_TIMING_UHS_SDR50:
1179         case MMC_TIMING_UHS_DDR50:
1180                 pinctrl = imx_data->pins_100mhz;
1181                 break;
1182         case MMC_TIMING_UHS_SDR104:
1183         case MMC_TIMING_MMC_HS200:
1184         case MMC_TIMING_MMC_HS400:
1185                 pinctrl = imx_data->pins_200mhz;
1186                 break;
1187         default:
1188                 /* back to default state for other legacy timing */
1189                 return pinctrl_select_default_state(mmc_dev(host->mmc));
1190         }
1191
1192         return pinctrl_select_state(imx_data->pinctrl, pinctrl);
1193 }
1194
1195 /*
1196  * For HS400 eMMC, there is a data_strobe line. This signal is generated
1197  * by the device and used for data output and CRC status response output
1198  * in HS400 mode. The frequency of this signal follows the frequency of
1199  * CLK generated by host. The host receives the data which is aligned to the
1200  * edge of data_strobe line. Due to the time delay between CLK line and
1201  * data_strobe line, if the delay time is larger than one clock cycle,
1202  * then CLK and data_strobe line will be misaligned, read error shows up.
1203  */
1204 static void esdhc_set_strobe_dll(struct sdhci_host *host)
1205 {
1206         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1207         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1208         u32 strobe_delay;
1209         u32 v;
1210         int ret;
1211
1212         /* disable clock before enabling strobe dll */
1213         writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) &
1214                 ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
1215                 host->ioaddr + ESDHC_VENDOR_SPEC);
1216         esdhc_wait_for_card_clock_gate_off(host);
1217
1218         /* force a reset on strobe dll */
1219         writel(ESDHC_STROBE_DLL_CTRL_RESET,
1220                 host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1221         /* clear the reset bit on strobe dll before any setting */
1222         writel(0, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1223
1224         /*
1225          * enable strobe dll ctrl and adjust the delay target
1226          * for the uSDHC loopback read clock
1227          */
1228         if (imx_data->boarddata.strobe_dll_delay_target)
1229                 strobe_delay = imx_data->boarddata.strobe_dll_delay_target;
1230         else
1231                 strobe_delay = ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT;
1232         v = ESDHC_STROBE_DLL_CTRL_ENABLE |
1233                 ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT |
1234                 (strobe_delay << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
1235         writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1236
1237         /* wait max 50us to get the REF/SLV lock */
1238         ret = readl_poll_timeout(host->ioaddr + ESDHC_STROBE_DLL_STATUS, v,
1239                 ((v & ESDHC_STROBE_DLL_STS_REF_LOCK) && (v & ESDHC_STROBE_DLL_STS_SLV_LOCK)), 1, 50);
1240         if (ret == -ETIMEDOUT)
1241                 dev_warn(mmc_dev(host->mmc),
1242                 "warning! HS400 strobe DLL status REF/SLV not lock in 50us, STROBE DLL status is %x!\n", v);
1243 }
1244
1245 static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1246 {
1247         u32 m;
1248         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1249         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1250         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1251
1252         /* disable ddr mode and disable HS400 mode */
1253         m = readl(host->ioaddr + ESDHC_MIX_CTRL);
1254         m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN);
1255         imx_data->is_ddr = 0;
1256
1257         switch (timing) {
1258         case MMC_TIMING_UHS_SDR12:
1259         case MMC_TIMING_UHS_SDR25:
1260         case MMC_TIMING_UHS_SDR50:
1261         case MMC_TIMING_UHS_SDR104:
1262         case MMC_TIMING_MMC_HS:
1263         case MMC_TIMING_MMC_HS200:
1264                 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1265                 break;
1266         case MMC_TIMING_UHS_DDR50:
1267         case MMC_TIMING_MMC_DDR52:
1268                 m |= ESDHC_MIX_CTRL_DDREN;
1269                 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1270                 imx_data->is_ddr = 1;
1271                 if (boarddata->delay_line) {
1272                         u32 v;
1273                         v = boarddata->delay_line <<
1274                                 ESDHC_DLL_OVERRIDE_VAL_SHIFT |
1275                                 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT);
1276                         if (is_imx53_esdhc(imx_data))
1277                                 v <<= 1;
1278                         writel(v, host->ioaddr + ESDHC_DLL_CTRL);
1279                 }
1280                 break;
1281         case MMC_TIMING_MMC_HS400:
1282                 m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN;
1283                 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1284                 imx_data->is_ddr = 1;
1285                 /* update clock after enable DDR for strobe DLL lock */
1286                 host->ops->set_clock(host, host->clock);
1287                 esdhc_set_strobe_dll(host);
1288                 break;
1289         case MMC_TIMING_LEGACY:
1290         default:
1291                 esdhc_reset_tuning(host);
1292                 break;
1293         }
1294
1295         esdhc_change_pinstate(host, timing);
1296 }
1297
1298 static void esdhc_reset(struct sdhci_host *host, u8 mask)
1299 {
1300         sdhci_and_cqhci_reset(host, mask);
1301
1302         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1303         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1304 }
1305
1306 static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host)
1307 {
1308         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1309         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1310
1311         /* Doc Erratum: the uSDHC actual maximum timeout count is 1 << 29 */
1312         return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27;
1313 }
1314
1315 static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1316 {
1317         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1318         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1319
1320         /* use maximum timeout counter */
1321         esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK,
1322                         esdhc_is_usdhc(imx_data) ? 0xF : 0xE,
1323                         SDHCI_TIMEOUT_CONTROL);
1324 }
1325
1326 static u32 esdhc_cqhci_irq(struct sdhci_host *host, u32 intmask)
1327 {
1328         int cmd_error = 0;
1329         int data_error = 0;
1330
1331         if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
1332                 return intmask;
1333
1334         cqhci_irq(host->mmc, intmask, cmd_error, data_error);
1335
1336         return 0;
1337 }
1338
1339 static struct sdhci_ops sdhci_esdhc_ops = {
1340         .read_l = esdhc_readl_le,
1341         .read_w = esdhc_readw_le,
1342         .read_b = esdhc_readb_le,
1343         .write_l = esdhc_writel_le,
1344         .write_w = esdhc_writew_le,
1345         .write_b = esdhc_writeb_le,
1346         .set_clock = esdhc_pltfm_set_clock,
1347         .get_max_clock = esdhc_pltfm_get_max_clock,
1348         .get_min_clock = esdhc_pltfm_get_min_clock,
1349         .get_max_timeout_count = esdhc_get_max_timeout_count,
1350         .get_ro = esdhc_pltfm_get_ro,
1351         .set_timeout = esdhc_set_timeout,
1352         .set_bus_width = esdhc_pltfm_set_bus_width,
1353         .set_uhs_signaling = esdhc_set_uhs_signaling,
1354         .reset = esdhc_reset,
1355         .irq = esdhc_cqhci_irq,
1356         .dump_vendor_regs = esdhc_dump_debug_regs,
1357 };
1358
1359 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
1360         .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
1361                         | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
1362                         | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
1363                         | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
1364         .ops = &sdhci_esdhc_ops,
1365 };
1366
1367 static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host)
1368 {
1369         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1370         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1371         struct cqhci_host *cq_host = host->mmc->cqe_private;
1372         u32 tmp;
1373
1374         if (esdhc_is_usdhc(imx_data)) {
1375                 /*
1376                  * The imx6q ROM code will change the default watermark
1377                  * level setting to something insane.  Change it back here.
1378                  */
1379                 writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL);
1380
1381                 /*
1382                  * ROM code will change the bit burst_length_enable setting
1383                  * to zero if this usdhc is chosen to boot system. Change
1384                  * it back here, otherwise it will impact the performance a
1385                  * lot. This bit is used to enable/disable the burst length
1386                  * for the external AHB2AXI bridge. It's useful especially
1387                  * for INCR transfer because without burst length indicator,
1388                  * the AHB2AXI bridge does not know the burst length in
1389                  * advance. And without burst length indicator, AHB INCR
1390                  * transfer can only be converted to singles on the AXI side.
1391                  */
1392                 writel(readl(host->ioaddr + SDHCI_HOST_CONTROL)
1393                         | ESDHC_BURST_LEN_EN_INCR,
1394                         host->ioaddr + SDHCI_HOST_CONTROL);
1395
1396                 /*
1397                  * erratum ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
1398                  * TO1.1, it's harmless for MX6SL
1399                  */
1400                 if (!(imx_data->socdata->flags & ESDHC_FLAG_SKIP_ERR004536)) {
1401                         writel(readl(host->ioaddr + 0x6c) & ~BIT(7),
1402                                 host->ioaddr + 0x6c);
1403                 }
1404
1405                 /* disable DLL_CTRL delay line settings */
1406                 writel(0x0, host->ioaddr + ESDHC_DLL_CTRL);
1407
1408                 /*
1409                  * For the case of command with busy, if set the bit
1410                  * ESDHC_VEND_SPEC2_EN_BUSY_IRQ, USDHC will generate a
1411                  * transfer complete interrupt when busy is deasserted.
1412                  * When CQHCI use DCMD to send a CMD need R1b respons,
1413                  * CQHCI require to set ESDHC_VEND_SPEC2_EN_BUSY_IRQ,
1414                  * otherwise DCMD will always meet timeout waiting for
1415                  * hardware interrupt issue.
1416                  */
1417                 if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) {
1418                         tmp = readl(host->ioaddr + ESDHC_VEND_SPEC2);
1419                         tmp |= ESDHC_VEND_SPEC2_EN_BUSY_IRQ;
1420                         writel(tmp, host->ioaddr + ESDHC_VEND_SPEC2);
1421
1422                         host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
1423                 }
1424
1425                 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
1426                         tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
1427                         tmp |= ESDHC_STD_TUNING_EN;
1428
1429                         /*
1430                          * ROM code or bootloader may config the start tap
1431                          * and step, unmask them first.
1432                          */
1433                         tmp &= ~(ESDHC_TUNING_START_TAP_MASK | ESDHC_TUNING_STEP_MASK);
1434                         if (imx_data->boarddata.tuning_start_tap)
1435                                 tmp |= imx_data->boarddata.tuning_start_tap;
1436                         else
1437                                 tmp |= ESDHC_TUNING_START_TAP_DEFAULT;
1438
1439                         if (imx_data->boarddata.tuning_step) {
1440                                 tmp |= imx_data->boarddata.tuning_step
1441                                         << ESDHC_TUNING_STEP_SHIFT;
1442                         } else {
1443                                 tmp |= ESDHC_TUNING_STEP_DEFAULT
1444                                         << ESDHC_TUNING_STEP_SHIFT;
1445                         }
1446
1447                         /* Disable the CMD CRC check for tuning, if not, need to
1448                          * add some delay after every tuning command, because
1449                          * hardware standard tuning logic will directly go to next
1450                          * step once it detect the CMD CRC error, will not wait for
1451                          * the card side to finally send out the tuning data, trigger
1452                          * the buffer read ready interrupt immediately. If usdhc send
1453                          * the next tuning command some eMMC card will stuck, can't
1454                          * response, block the tuning procedure or the first command
1455                          * after the whole tuning procedure always can't get any response.
1456                          */
1457                         tmp |= ESDHC_TUNING_CMD_CRC_CHECK_DISABLE;
1458                         writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
1459                 } else if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
1460                         /*
1461                          * ESDHC_STD_TUNING_EN may be configed in bootloader
1462                          * or ROM code, so clear this bit here to make sure
1463                          * the manual tuning can work.
1464                          */
1465                         tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
1466                         tmp &= ~ESDHC_STD_TUNING_EN;
1467                         writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
1468                 }
1469
1470                 /*
1471                  * On i.MX8MM, we are running Dual Linux OS, with 1st Linux using SD Card
1472                  * as rootfs storage, 2nd Linux using eMMC as rootfs storage. We let
1473                  * the 1st linux configure power/clock for the 2nd Linux.
1474                  *
1475                  * When the 2nd Linux is booting into rootfs stage, we let the 1st Linux
1476                  * to destroy the 2nd linux, then restart the 2nd linux, we met SDHCI dump.
1477                  * After we clear the pending interrupt and halt CQCTL, issue gone.
1478                  */
1479                 if (cq_host) {
1480                         tmp = cqhci_readl(cq_host, CQHCI_IS);
1481                         cqhci_writel(cq_host, tmp, CQHCI_IS);
1482                         cqhci_writel(cq_host, CQHCI_HALT, CQHCI_CTL);
1483                 }
1484         }
1485 }
1486
1487 static void esdhc_cqe_enable(struct mmc_host *mmc)
1488 {
1489         struct sdhci_host *host = mmc_priv(mmc);
1490         struct cqhci_host *cq_host = mmc->cqe_private;
1491         u32 reg;
1492         u16 mode;
1493         int count = 10;
1494
1495         /*
1496          * CQE gets stuck if it sees Buffer Read Enable bit set, which can be
1497          * the case after tuning, so ensure the buffer is drained.
1498          */
1499         reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
1500         while (reg & SDHCI_DATA_AVAILABLE) {
1501                 sdhci_readl(host, SDHCI_BUFFER);
1502                 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
1503                 if (count-- == 0) {
1504                         dev_warn(mmc_dev(host->mmc),
1505                                 "CQE may get stuck because the Buffer Read Enable bit is set\n");
1506                         break;
1507                 }
1508                 mdelay(1);
1509         }
1510
1511         /*
1512          * Runtime resume will reset the entire host controller, which
1513          * will also clear the DMAEN/BCEN of register ESDHC_MIX_CTRL.
1514          * Here set DMAEN and BCEN when enable CMDQ.
1515          */
1516         mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
1517         if (host->flags & SDHCI_REQ_USE_DMA)
1518                 mode |= SDHCI_TRNS_DMA;
1519         if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
1520                 mode |= SDHCI_TRNS_BLK_CNT_EN;
1521         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
1522
1523         /*
1524          * Though Runtime resume reset the entire host controller,
1525          * but do not impact the CQHCI side, need to clear the
1526          * HALT bit, avoid CQHCI stuck in the first request when
1527          * system resume back.
1528          */
1529         cqhci_writel(cq_host, 0, CQHCI_CTL);
1530         if (cqhci_readl(cq_host, CQHCI_CTL) & CQHCI_HALT)
1531                 dev_err(mmc_dev(host->mmc),
1532                         "failed to exit halt state when enable CQE\n");
1533
1534
1535         sdhci_cqe_enable(mmc);
1536 }
1537
1538 static void esdhc_sdhci_dumpregs(struct mmc_host *mmc)
1539 {
1540         sdhci_dumpregs(mmc_priv(mmc));
1541 }
1542
1543 static const struct cqhci_host_ops esdhc_cqhci_ops = {
1544         .enable         = esdhc_cqe_enable,
1545         .disable        = sdhci_cqe_disable,
1546         .dumpregs       = esdhc_sdhci_dumpregs,
1547 };
1548
1549 static int
1550 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
1551                          struct sdhci_host *host,
1552                          struct pltfm_imx_data *imx_data)
1553 {
1554         struct device_node *np = pdev->dev.of_node;
1555         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1556         int ret;
1557
1558         if (of_get_property(np, "fsl,wp-controller", NULL))
1559                 boarddata->wp_type = ESDHC_WP_CONTROLLER;
1560
1561         /*
1562          * If we have this property, then activate WP check.
1563          * Retrieveing and requesting the actual WP GPIO will happen
1564          * in the call to mmc_of_parse().
1565          */
1566         if (of_property_read_bool(np, "wp-gpios"))
1567                 boarddata->wp_type = ESDHC_WP_GPIO;
1568
1569         of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step);
1570         of_property_read_u32(np, "fsl,tuning-start-tap",
1571                              &boarddata->tuning_start_tap);
1572
1573         of_property_read_u32(np, "fsl,strobe-dll-delay-target",
1574                                 &boarddata->strobe_dll_delay_target);
1575         if (of_find_property(np, "no-1-8-v", NULL))
1576                 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1577
1578         if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
1579                 boarddata->delay_line = 0;
1580
1581         mmc_of_parse_voltage(host->mmc, &host->ocr_mask);
1582
1583         if (esdhc_is_usdhc(imx_data) && !IS_ERR(imx_data->pinctrl)) {
1584                 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
1585                                                 ESDHC_PINCTRL_STATE_100MHZ);
1586                 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
1587                                                 ESDHC_PINCTRL_STATE_200MHZ);
1588         }
1589
1590         /* call to generic mmc_of_parse to support additional capabilities */
1591         ret = mmc_of_parse(host->mmc);
1592         if (ret)
1593                 return ret;
1594
1595         if (mmc_gpio_get_cd(host->mmc) >= 0)
1596                 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1597
1598         return 0;
1599 }
1600
1601 static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
1602 {
1603         struct sdhci_pltfm_host *pltfm_host;
1604         struct sdhci_host *host;
1605         struct cqhci_host *cq_host;
1606         int err;
1607         struct pltfm_imx_data *imx_data;
1608
1609         host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata,
1610                                 sizeof(*imx_data));
1611         if (IS_ERR(host))
1612                 return PTR_ERR(host);
1613
1614         pltfm_host = sdhci_priv(host);
1615
1616         imx_data = sdhci_pltfm_priv(pltfm_host);
1617
1618         imx_data->socdata = device_get_match_data(&pdev->dev);
1619
1620         if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1621                 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0);
1622
1623         imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1624         if (IS_ERR(imx_data->clk_ipg)) {
1625                 err = PTR_ERR(imx_data->clk_ipg);
1626                 goto free_sdhci;
1627         }
1628
1629         imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1630         if (IS_ERR(imx_data->clk_ahb)) {
1631                 err = PTR_ERR(imx_data->clk_ahb);
1632                 goto free_sdhci;
1633         }
1634
1635         imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
1636         if (IS_ERR(imx_data->clk_per)) {
1637                 err = PTR_ERR(imx_data->clk_per);
1638                 goto free_sdhci;
1639         }
1640
1641         pltfm_host->clk = imx_data->clk_per;
1642         pltfm_host->clock = clk_get_rate(pltfm_host->clk);
1643         err = clk_prepare_enable(imx_data->clk_per);
1644         if (err)
1645                 goto free_sdhci;
1646         err = clk_prepare_enable(imx_data->clk_ipg);
1647         if (err)
1648                 goto disable_per_clk;
1649         err = clk_prepare_enable(imx_data->clk_ahb);
1650         if (err)
1651                 goto disable_ipg_clk;
1652
1653         imx_data->pinctrl = devm_pinctrl_get(&pdev->dev);
1654         if (IS_ERR(imx_data->pinctrl))
1655                 dev_warn(mmc_dev(host->mmc), "could not get pinctrl\n");
1656
1657         if (esdhc_is_usdhc(imx_data)) {
1658                 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
1659                 host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;
1660
1661                 /* GPIO CD can be set as a wakeup source */
1662                 host->mmc->caps |= MMC_CAP_CD_WAKE;
1663
1664                 if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200))
1665                         host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
1666
1667                 /* clear tuning bits in case ROM has set it already */
1668                 writel(0x0, host->ioaddr + ESDHC_MIX_CTRL);
1669                 writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1670                 writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1671
1672                 /*
1673                  * Link usdhc specific mmc_host_ops execute_tuning function,
1674                  * to replace the standard one in sdhci_ops.
1675                  */
1676                 host->mmc_host_ops.execute_tuning = usdhc_execute_tuning;
1677         }
1678
1679         err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data);
1680         if (err)
1681                 goto disable_ahb_clk;
1682
1683         if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
1684                 sdhci_esdhc_ops.platform_execute_tuning =
1685                                         esdhc_executing_tuning;
1686
1687         if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
1688                 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1689
1690         if (host->mmc->caps & MMC_CAP_8_BIT_DATA &&
1691             imx_data->socdata->flags & ESDHC_FLAG_HS400)
1692                 host->mmc->caps2 |= MMC_CAP2_HS400;
1693
1694         if (imx_data->socdata->flags & ESDHC_FLAG_BROKEN_AUTO_CMD23)
1695                 host->quirks2 |= SDHCI_QUIRK2_ACMD23_BROKEN;
1696
1697         if (host->mmc->caps & MMC_CAP_8_BIT_DATA &&
1698             imx_data->socdata->flags & ESDHC_FLAG_HS400_ES) {
1699                 host->mmc->caps2 |= MMC_CAP2_HS400_ES;
1700                 host->mmc_host_ops.hs400_enhanced_strobe =
1701                                         esdhc_hs400_enhanced_strobe;
1702         }
1703
1704         if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) {
1705                 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
1706                 cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL);
1707                 if (!cq_host) {
1708                         err = -ENOMEM;
1709                         goto disable_ahb_clk;
1710                 }
1711
1712                 cq_host->mmio = host->ioaddr + ESDHC_CQHCI_ADDR_OFFSET;
1713                 cq_host->ops = &esdhc_cqhci_ops;
1714
1715                 err = cqhci_init(cq_host, host->mmc, false);
1716                 if (err)
1717                         goto disable_ahb_clk;
1718         }
1719
1720         sdhci_esdhc_imx_hwinit(host);
1721
1722         err = sdhci_add_host(host);
1723         if (err)
1724                 goto disable_ahb_clk;
1725
1726         /*
1727          * Setup the wakeup capability here, let user to decide
1728          * whether need to enable this wakeup through sysfs interface.
1729          */
1730         if ((host->mmc->pm_caps & MMC_PM_KEEP_POWER) &&
1731                         (host->mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ))
1732                 device_set_wakeup_capable(&pdev->dev, true);
1733
1734         pm_runtime_set_active(&pdev->dev);
1735         pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1736         pm_runtime_use_autosuspend(&pdev->dev);
1737         pm_suspend_ignore_children(&pdev->dev, 1);
1738         pm_runtime_enable(&pdev->dev);
1739
1740         return 0;
1741
1742 disable_ahb_clk:
1743         clk_disable_unprepare(imx_data->clk_ahb);
1744 disable_ipg_clk:
1745         clk_disable_unprepare(imx_data->clk_ipg);
1746 disable_per_clk:
1747         clk_disable_unprepare(imx_data->clk_per);
1748 free_sdhci:
1749         if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1750                 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1751         sdhci_pltfm_free(pdev);
1752         return err;
1753 }
1754
1755 static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
1756 {
1757         struct sdhci_host *host = platform_get_drvdata(pdev);
1758         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1759         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1760         int dead;
1761
1762         pm_runtime_get_sync(&pdev->dev);
1763         dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
1764         pm_runtime_disable(&pdev->dev);
1765         pm_runtime_put_noidle(&pdev->dev);
1766
1767         sdhci_remove_host(host, dead);
1768
1769         clk_disable_unprepare(imx_data->clk_per);
1770         clk_disable_unprepare(imx_data->clk_ipg);
1771         clk_disable_unprepare(imx_data->clk_ahb);
1772
1773         if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1774                 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1775
1776         sdhci_pltfm_free(pdev);
1777
1778         return 0;
1779 }
1780
1781 #ifdef CONFIG_PM_SLEEP
1782 static int sdhci_esdhc_suspend(struct device *dev)
1783 {
1784         struct sdhci_host *host = dev_get_drvdata(dev);
1785         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1786         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1787         int ret;
1788
1789         if (host->mmc->caps2 & MMC_CAP2_CQE) {
1790                 ret = cqhci_suspend(host->mmc);
1791                 if (ret)
1792                         return ret;
1793         }
1794
1795         if ((imx_data->socdata->flags & ESDHC_FLAG_STATE_LOST_IN_LPMODE) &&
1796                 (host->tuning_mode != SDHCI_TUNING_MODE_1)) {
1797                 mmc_retune_timer_stop(host->mmc);
1798                 mmc_retune_needed(host->mmc);
1799         }
1800
1801         if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1802                 mmc_retune_needed(host->mmc);
1803
1804         ret = sdhci_suspend_host(host);
1805         if (ret)
1806                 return ret;
1807
1808         ret = pinctrl_pm_select_sleep_state(dev);
1809         if (ret)
1810                 return ret;
1811
1812         ret = mmc_gpio_set_cd_wake(host->mmc, true);
1813
1814         return ret;
1815 }
1816
1817 static int sdhci_esdhc_resume(struct device *dev)
1818 {
1819         struct sdhci_host *host = dev_get_drvdata(dev);
1820         int ret;
1821
1822         ret = pinctrl_pm_select_default_state(dev);
1823         if (ret)
1824                 return ret;
1825
1826         /* re-initialize hw state in case it's lost in low power mode */
1827         sdhci_esdhc_imx_hwinit(host);
1828
1829         ret = sdhci_resume_host(host);
1830         if (ret)
1831                 return ret;
1832
1833         if (host->mmc->caps2 & MMC_CAP2_CQE)
1834                 ret = cqhci_resume(host->mmc);
1835
1836         if (!ret)
1837                 ret = mmc_gpio_set_cd_wake(host->mmc, false);
1838
1839         return ret;
1840 }
1841 #endif
1842
1843 #ifdef CONFIG_PM
1844 static int sdhci_esdhc_runtime_suspend(struct device *dev)
1845 {
1846         struct sdhci_host *host = dev_get_drvdata(dev);
1847         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1848         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1849         int ret;
1850
1851         if (host->mmc->caps2 & MMC_CAP2_CQE) {
1852                 ret = cqhci_suspend(host->mmc);
1853                 if (ret)
1854                         return ret;
1855         }
1856
1857         ret = sdhci_runtime_suspend_host(host);
1858         if (ret)
1859                 return ret;
1860
1861         if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1862                 mmc_retune_needed(host->mmc);
1863
1864         imx_data->actual_clock = host->mmc->actual_clock;
1865         esdhc_pltfm_set_clock(host, 0);
1866         clk_disable_unprepare(imx_data->clk_per);
1867         clk_disable_unprepare(imx_data->clk_ipg);
1868         clk_disable_unprepare(imx_data->clk_ahb);
1869
1870         if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1871                 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1872
1873         return ret;
1874 }
1875
1876 static int sdhci_esdhc_runtime_resume(struct device *dev)
1877 {
1878         struct sdhci_host *host = dev_get_drvdata(dev);
1879         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1880         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1881         int err;
1882
1883         if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1884                 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0);
1885
1886         if (imx_data->socdata->flags & ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME)
1887                 clk_set_rate(imx_data->clk_per, pltfm_host->clock);
1888
1889         err = clk_prepare_enable(imx_data->clk_ahb);
1890         if (err)
1891                 goto remove_pm_qos_request;
1892
1893         err = clk_prepare_enable(imx_data->clk_per);
1894         if (err)
1895                 goto disable_ahb_clk;
1896
1897         err = clk_prepare_enable(imx_data->clk_ipg);
1898         if (err)
1899                 goto disable_per_clk;
1900
1901         esdhc_pltfm_set_clock(host, imx_data->actual_clock);
1902
1903         err = sdhci_runtime_resume_host(host, 0);
1904         if (err)
1905                 goto disable_ipg_clk;
1906
1907         if (host->mmc->caps2 & MMC_CAP2_CQE)
1908                 err = cqhci_resume(host->mmc);
1909
1910         return err;
1911
1912 disable_ipg_clk:
1913         clk_disable_unprepare(imx_data->clk_ipg);
1914 disable_per_clk:
1915         clk_disable_unprepare(imx_data->clk_per);
1916 disable_ahb_clk:
1917         clk_disable_unprepare(imx_data->clk_ahb);
1918 remove_pm_qos_request:
1919         if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1920                 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1921         return err;
1922 }
1923 #endif
1924
1925 static const struct dev_pm_ops sdhci_esdhc_pmops = {
1926         SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume)
1927         SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend,
1928                                 sdhci_esdhc_runtime_resume, NULL)
1929 };
1930
1931 static struct platform_driver sdhci_esdhc_imx_driver = {
1932         .driver         = {
1933                 .name   = "sdhci-esdhc-imx",
1934                 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1935                 .of_match_table = imx_esdhc_dt_ids,
1936                 .pm     = &sdhci_esdhc_pmops,
1937         },
1938         .probe          = sdhci_esdhc_imx_probe,
1939         .remove         = sdhci_esdhc_imx_remove,
1940 };
1941
1942 module_platform_driver(sdhci_esdhc_imx_driver);
1943
1944 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
1945 MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
1946 MODULE_LICENSE("GPL v2");