drivers/mmc/host/sdhci-esdhc-imx.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Freescale eSDHC i.MX controller driver for the platform bus.
   4  *
   5  * derived from the OF-version.
   6  *
   7  * Copyright (c) 2010 Pengutronix e.K.
   8  *   Author: Wolfram Sang <kernel@pengutronix.de>
   9  */
  10
  11 #include <linux/io.h>
  12 #include <linux/iopoll.h>
  13 #include <linux/delay.h>
  14 #include <linux/err.h>
  15 #include <linux/clk.h>
  16 #include <linux/module.h>
  17 #include <linux/slab.h>
  18 #include <linux/pm_qos.h>
  19 #include <linux/mmc/host.h>
  20 #include <linux/mmc/mmc.h>
  21 #include <linux/mmc/sdio.h>
  22 #include <linux/mmc/slot-gpio.h>
  23 #include <linux/of.h>
  24 #include <linux/of_device.h>
  25 #include <linux/pinctrl/consumer.h>
  26 #include <linux/platform_data/mmc-esdhc-imx.h>
  27 #include <linux/pm_runtime.h>
  28 #include "sdhci-pltfm.h"
  29 #include "sdhci-esdhc.h"
  30 #include "cqhci.h"
  31
  32 #define ESDHC_SYS_CTRL_DTOCV_MASK       0x0f
  33 #define ESDHC_CTRL_D3CD                 0x08
  34 #define ESDHC_BURST_LEN_EN_INCR         (1 << 27)
  35 /* VENDOR SPEC register */
  36 #define ESDHC_VENDOR_SPEC               0xc0
  37 #define  ESDHC_VENDOR_SPEC_SDIO_QUIRK   (1 << 1)
  38 #define  ESDHC_VENDOR_SPEC_VSELECT      (1 << 1)
  39 #define  ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
  40 #define ESDHC_WTMK_LVL                  0x44
  41 #define  ESDHC_WTMK_DEFAULT_VAL         0x10401040
  42 #define  ESDHC_WTMK_LVL_RD_WML_MASK     0x000000FF
  43 #define  ESDHC_WTMK_LVL_RD_WML_SHIFT    0
  44 #define  ESDHC_WTMK_LVL_WR_WML_MASK     0x00FF0000
  45 #define  ESDHC_WTMK_LVL_WR_WML_SHIFT    16
  46 #define  ESDHC_WTMK_LVL_WML_VAL_DEF     64
  47 #define  ESDHC_WTMK_LVL_WML_VAL_MAX     128
  48 #define ESDHC_MIX_CTRL                  0x48
  49 #define  ESDHC_MIX_CTRL_DDREN           (1 << 3)
  50 #define  ESDHC_MIX_CTRL_AC23EN          (1 << 7)
  51 #define  ESDHC_MIX_CTRL_EXE_TUNE        (1 << 22)
  52 #define  ESDHC_MIX_CTRL_SMPCLK_SEL      (1 << 23)
  53 #define  ESDHC_MIX_CTRL_AUTO_TUNE_EN    (1 << 24)
  54 #define  ESDHC_MIX_CTRL_FBCLK_SEL       (1 << 25)
  55 #define  ESDHC_MIX_CTRL_HS400_EN        (1 << 26)
  56 #define  ESDHC_MIX_CTRL_HS400_ES_EN     (1 << 27)
  57 /* Bits 3 and 6 are not SDHCI standard definitions */
  58 #define  ESDHC_MIX_CTRL_SDHCI_MASK      0xb7
  59 /* Tuning bits */
  60 #define  ESDHC_MIX_CTRL_TUNING_MASK     0x03c00000
  61
  62 /* dll control register */
  63 #define ESDHC_DLL_CTRL                  0x60
  64 #define ESDHC_DLL_OVERRIDE_VAL_SHIFT    9
  65 #define ESDHC_DLL_OVERRIDE_EN_SHIFT     8
  66
  67 /* tune control register */
  68 #define ESDHC_TUNE_CTRL_STATUS          0x68
  69 #define  ESDHC_TUNE_CTRL_STEP           1
  70 #define  ESDHC_TUNE_CTRL_MIN            0
  71 #define  ESDHC_TUNE_CTRL_MAX            ((1 << 7) - 1)
  72
  73 /* strobe dll register */
  74 #define ESDHC_STROBE_DLL_CTRL           0x70
  75 #define ESDHC_STROBE_DLL_CTRL_ENABLE    (1 << 0)
  76 #define ESDHC_STROBE_DLL_CTRL_RESET     (1 << 1)
  77 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT    0x7
  78 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT      3
  79 #define ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT    (4 << 20)
  80
  81 #define ESDHC_STROBE_DLL_STATUS         0x74
  82 #define ESDHC_STROBE_DLL_STS_REF_LOCK   (1 << 1)
  83 #define ESDHC_STROBE_DLL_STS_SLV_LOCK   0x1
  84
  85 #define ESDHC_VEND_SPEC2                0xc8
  86 #define ESDHC_VEND_SPEC2_EN_BUSY_IRQ    (1 << 8)
  87
  88 #define ESDHC_TUNING_CTRL               0xcc
  89 #define ESDHC_STD_TUNING_EN             (1 << 24)
  90 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
  91 #define ESDHC_TUNING_START_TAP_DEFAULT  0x1
  92 #define ESDHC_TUNING_START_TAP_MASK     0xff
  93 #define ESDHC_TUNING_STEP_MASK          0x00070000
  94 #define ESDHC_TUNING_STEP_SHIFT         16
  95
  96 /* pinctrl state */
  97 #define ESDHC_PINCTRL_STATE_100MHZ      "state_100mhz"
  98 #define ESDHC_PINCTRL_STATE_200MHZ      "state_200mhz"
  99
 100 /*
 101  * Our interpretation of the SDHCI_HOST_CONTROL register
 102  */
 103 #define ESDHC_CTRL_4BITBUS              (0x1 << 1)
 104 #define ESDHC_CTRL_8BITBUS              (0x2 << 1)
 105 #define ESDHC_CTRL_BUSWIDTH_MASK        (0x3 << 1)
 106
 107 /*
 108  * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC:
 109  * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
 110  * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
 111  * Define this macro DMA error INT for fsl eSDHC
 112  */
 113 #define ESDHC_INT_VENDOR_SPEC_DMA_ERR   (1 << 28)
 114
 115 /* the address offset of CQHCI */
 116 #define ESDHC_CQHCI_ADDR_OFFSET         0x100
 117
 118 /*
 119  * The CMDTYPE of the CMD register (offset 0xE) should be set to
 120  * "11" when the STOP CMD12 is issued on imx53 to abort one
 121  * open ended multi-blk IO. Otherwise the TC INT wouldn't
 122  * be generated.
 123  * In exact block transfer, the controller doesn't complete the
 124  * operations automatically as required at the end of the
 125  * transfer and remains on hold if the abort command is not sent.
 126  * As a result, the TC flag is not asserted and SW received timeout
 127  * exception. Bit1 of Vendor Spec register is used to fix it.
 128  */
 129 #define ESDHC_FLAG_MULTIBLK_NO_INT      BIT(1)
 130 /*
 131  * The flag tells that the ESDHC controller is an USDHC block that is
 132  * integrated on the i.MX6 series.
 133  */
 134 #define ESDHC_FLAG_USDHC                BIT(3)
 135 /* The IP supports manual tuning process */
 136 #define ESDHC_FLAG_MAN_TUNING           BIT(4)
 137 /* The IP supports standard tuning process */
 138 #define ESDHC_FLAG_STD_TUNING           BIT(5)
 139 /* The IP has SDHCI_CAPABILITIES_1 register */
 140 #define ESDHC_FLAG_HAVE_CAP1            BIT(6)
 141 /*
 142  * The IP has erratum ERR004536
 143  * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
 144  * when reading data from the card
 145  * This flag is also set for i.MX25 and i.MX35 in order to get
 146  * SDHCI_QUIRK_BROKEN_ADMA, but for different reasons (ADMA capability bits).
 147  */
 148 #define ESDHC_FLAG_ERR004536            BIT(7)
 149 /* The IP supports HS200 mode */
 150 #define ESDHC_FLAG_HS200                BIT(8)
 151 /* The IP supports HS400 mode */
 152 #define ESDHC_FLAG_HS400                BIT(9)
 153 /*
 154  * The IP has errata ERR010450
 155  * uSDHC: Due to the I/O timing limit, for SDR mode, SD card clock can't
 156  * exceed 150MHz, for DDR mode, SD card clock can't exceed 45MHz.
 157  */
 158 #define ESDHC_FLAG_ERR010450            BIT(10)
 159 /* The IP supports HS400ES mode */
 160 #define ESDHC_FLAG_HS400_ES             BIT(11)
 161 /* The IP has Host Controller Interface for Command Queuing */
 162 #define ESDHC_FLAG_CQHCI                BIT(12)
 163 /* need request pmqos during low power */
 164 #define ESDHC_FLAG_PMQOS                BIT(13)
 165 /* The IP state got lost in low power mode */
 166 #define ESDHC_FLAG_STATE_LOST_IN_LPMODE         BIT(14)
 167 /* The IP lost clock rate in PM_RUNTIME */
 168 #define ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME  BIT(15)
 169 /*
 170  * The IP do not support the ACMD23 feature completely when use ADMA mode.
 171  * In ADMA mode, it only use the 16 bit block count of the register 0x4
 172  * (BLOCK_ATT) as the CMD23's argument for ACMD23 mode, which means it will
 173  * ignore the upper 16 bit of the CMD23's argument. This will block the reliable
 174  * write operation in RPMB, because RPMB reliable write need to set the bit31
 175  * of the CMD23's argument.
 176  * imx6qpdl/imx6sx/imx6sl/imx7d has this limitation only for ADMA mode, SDMA
 177  * do not has this limitation. so when these SoC use ADMA mode, it need to
 178  * disable the ACMD23 feature.
 179  */
 180 #define ESDHC_FLAG_BROKEN_AUTO_CMD23    BIT(16)
 181
 182 struct esdhc_soc_data {
 183         u32 flags;
 184 };
 185
 186 static const struct esdhc_soc_data esdhc_imx25_data = {
 187         .flags = ESDHC_FLAG_ERR004536,
 188 };
 189
 190 static const struct esdhc_soc_data esdhc_imx35_data = {
 191         .flags = ESDHC_FLAG_ERR004536,
 192 };
 193
 194 static const struct esdhc_soc_data esdhc_imx51_data = {
 195         .flags = 0,
 196 };
 197
 198 static const struct esdhc_soc_data esdhc_imx53_data = {
 199         .flags = ESDHC_FLAG_MULTIBLK_NO_INT,
 200 };
 201
 202 static const struct esdhc_soc_data usdhc_imx6q_data = {
 203         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING
 204                         | ESDHC_FLAG_BROKEN_AUTO_CMD23,
 205 };
 206
 207 static const struct esdhc_soc_data usdhc_imx6sl_data = {
 208         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 209                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536
 210                         | ESDHC_FLAG_HS200
 211                         | ESDHC_FLAG_BROKEN_AUTO_CMD23,
 212 };
 213
 214 static const struct esdhc_soc_data usdhc_imx6sll_data = {
 215         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 216                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 217                         | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
 218 };
 219
 220 static const struct esdhc_soc_data usdhc_imx6sx_data = {
 221         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 222                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 223                         | ESDHC_FLAG_STATE_LOST_IN_LPMODE
 224                         | ESDHC_FLAG_BROKEN_AUTO_CMD23,
 225 };
 226
 227 static const struct esdhc_soc_data usdhc_imx6ull_data = {
 228         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 229                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 230                         | ESDHC_FLAG_ERR010450
 231                         | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
 232 };
 233
 234 static const struct esdhc_soc_data usdhc_imx7d_data = {
 235         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 236                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 237                         | ESDHC_FLAG_HS400
 238                         | ESDHC_FLAG_STATE_LOST_IN_LPMODE
 239                         | ESDHC_FLAG_BROKEN_AUTO_CMD23,
 240 };
 241
 242 static struct esdhc_soc_data usdhc_imx7ulp_data = {
 243         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 244                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 245                         | ESDHC_FLAG_PMQOS | ESDHC_FLAG_HS400
 246                         | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
 247 };
 248
 249 static struct esdhc_soc_data usdhc_imx8qxp_data = {
 250         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 251                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 252                         | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
 253                         | ESDHC_FLAG_CQHCI
 254                         | ESDHC_FLAG_STATE_LOST_IN_LPMODE
 255                         | ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME,
 256 };
 257
 258 static struct esdhc_soc_data usdhc_imx8mm_data = {
 259         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 260                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 261                         | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
 262                         | ESDHC_FLAG_CQHCI
 263                         | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
 264 };
 265
 266 struct pltfm_imx_data {
 267         u32 scratchpad;
 268         struct pinctrl *pinctrl;
 269         struct pinctrl_state *pins_100mhz;
 270         struct pinctrl_state *pins_200mhz;
 271         const struct esdhc_soc_data *socdata;
 272         struct esdhc_platform_data boarddata;
 273         struct clk *clk_ipg;
 274         struct clk *clk_ahb;
 275         struct clk *clk_per;
 276         unsigned int actual_clock;
 277         enum {
 278                 NO_CMD_PENDING,      /* no multiblock command pending */
 279                 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
 280                 WAIT_FOR_INT,        /* sent CMD12, waiting for response INT */
 281         } multiblock_status;
 282         u32 is_ddr;
 283         struct pm_qos_request pm_qos_req;
 284 };
 285
 286 static const struct platform_device_id imx_esdhc_devtype[] = {
 287         {
 288                 .name = "sdhci-esdhc-imx25",
 289                 .driver_data = (kernel_ulong_t) &esdhc_imx25_data,
 290         }, {
 291                 .name = "sdhci-esdhc-imx35",
 292                 .driver_data = (kernel_ulong_t) &esdhc_imx35_data,
 293         }, {
 294                 .name = "sdhci-esdhc-imx51",
 295                 .driver_data = (kernel_ulong_t) &esdhc_imx51_data,
 296         }, {
 297                 /* sentinel */
 298         }
 299 };
 300 MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype);
 301
 302 static const struct of_device_id imx_esdhc_dt_ids[] = {
 303         { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
 304         { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
 305         { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
 306         { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
 307         { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
 308         { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
 309         { .compatible = "fsl,imx6sll-usdhc", .data = &usdhc_imx6sll_data, },
 310         { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
 311         { .compatible = "fsl,imx6ull-usdhc", .data = &usdhc_imx6ull_data, },
 312         { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
 313         { .compatible = "fsl,imx7ulp-usdhc", .data = &usdhc_imx7ulp_data, },
 314         { .compatible = "fsl,imx8qxp-usdhc", .data = &usdhc_imx8qxp_data, },
 315         { .compatible = "fsl,imx8mm-usdhc", .data = &usdhc_imx8mm_data, },
 316         { /* sentinel */ }
 317 };
 318 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
 319
 320 static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
 321 {
 322         return data->socdata == &esdhc_imx25_data;
 323 }
 324
 325 static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
 326 {
 327         return data->socdata == &esdhc_imx53_data;
 328 }
 329
 330 static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
 331 {
 332         return data->socdata == &usdhc_imx6q_data;
 333 }
 334
 335 static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
 336 {
 337         return !!(data->socdata->flags & ESDHC_FLAG_USDHC);
 338 }
 339
 340 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
 341 {
 342         void __iomem *base = host->ioaddr + (reg & ~0x3);
 343         u32 shift = (reg & 0x3) * 8;
 344
 345         writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
 346 }
 347
 348 static inline void esdhc_wait_for_card_clock_gate_off(struct sdhci_host *host)
 349 {
 350         u32 present_state;
 351         int ret;
 352
 353         ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, present_state,
 354                                 (present_state & ESDHC_CLOCK_GATE_OFF), 2, 100);
 355         if (ret == -ETIMEDOUT)
 356                 dev_warn(mmc_dev(host->mmc), "%s: card clock still not gate off in 100us!.\n", __func__);
 357 }
 358
 359 static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
 360 {
 361         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 362         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 363         u32 val = readl(host->ioaddr + reg);
 364
 365         if (unlikely(reg == SDHCI_PRESENT_STATE)) {
 366                 u32 fsl_prss = val;
 367                 /* save the least 20 bits */
 368                 val = fsl_prss & 0x000FFFFF;
 369                 /* move dat[0-3] bits */
 370                 val |= (fsl_prss & 0x0F000000) >> 4;
 371                 /* move cmd line bit */
 372                 val |= (fsl_prss & 0x00800000) << 1;
 373         }
 374
 375         if (unlikely(reg == SDHCI_CAPABILITIES)) {
 376                 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */
 377                 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
 378                         val &= 0xffff0000;
 379
 380                 /* In FSL esdhc IC module, only bit20 is used to indicate the
 381                  * ADMA2 capability of esdhc, but this bit is messed up on
 382                  * some SOCs (e.g. on MX25, MX35 this bit is set, but they
 383                  * don't actually support ADMA2). So set the BROKEN_ADMA
 384                  * quirk on MX25/35 platforms.
 385                  */
 386
 387                 if (val & SDHCI_CAN_DO_ADMA1) {
 388                         val &= ~SDHCI_CAN_DO_ADMA1;
 389                         val |= SDHCI_CAN_DO_ADMA2;
 390                 }
 391         }
 392
 393         if (unlikely(reg == SDHCI_CAPABILITIES_1)) {
 394                 if (esdhc_is_usdhc(imx_data)) {
 395                         if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
 396                                 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;
 397                         else
 398                                 /* imx6q/dl does not have cap_1 register, fake one */
 399                                 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
 400                                         | SDHCI_SUPPORT_SDR50
 401                                         | SDHCI_USE_SDR50_TUNING
 402                                         | (SDHCI_TUNING_MODE_3 << SDHCI_RETUNING_MODE_SHIFT);
 403
 404                         if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
 405                                 val |= SDHCI_SUPPORT_HS400;
 406
 407                         /*
 408                          * Do not advertise faster UHS modes if there are no
 409                          * pinctrl states for 100MHz/200MHz.
 410                          */
 411                         if (IS_ERR_OR_NULL(imx_data->pins_100mhz) ||
 412                             IS_ERR_OR_NULL(imx_data->pins_200mhz))
 413                                 val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50
 414                                          | SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);
 415                 }
 416         }
 417
 418         if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
 419                 val = 0;
 420                 val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT;
 421                 val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT;
 422                 val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT;
 423         }
 424
 425         if (unlikely(reg == SDHCI_INT_STATUS)) {
 426                 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
 427                         val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
 428                         val |= SDHCI_INT_ADMA_ERROR;
 429                 }
 430
 431                 /*
 432                  * mask off the interrupt we get in response to the manually
 433                  * sent CMD12
 434                  */
 435                 if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
 436                     ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
 437                         val &= ~SDHCI_INT_RESPONSE;
 438                         writel(SDHCI_INT_RESPONSE, host->ioaddr +
 439                                                    SDHCI_INT_STATUS);
 440                         imx_data->multiblock_status = NO_CMD_PENDING;
 441                 }
 442         }
 443
 444         return val;
 445 }
 446
 447 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
 448 {
 449         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 450         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 451         u32 data;
 452
 453         if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE ||
 454                         reg == SDHCI_INT_STATUS)) {
 455                 if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) {
 456                         /*
 457                          * Clear and then set D3CD bit to avoid missing the
 458                          * card interrupt. This is an eSDHC controller problem
 459                          * so we need to apply the following workaround: clear
 460                          * and set D3CD bit will make eSDHC re-sample the card
 461                          * interrupt. In case a card interrupt was lost,
 462                          * re-sample it by the following steps.
 463                          */
 464                         data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
 465                         data &= ~ESDHC_CTRL_D3CD;
 466                         writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
 467                         data |= ESDHC_CTRL_D3CD;
 468                         writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
 469                 }
 470
 471                 if (val & SDHCI_INT_ADMA_ERROR) {
 472                         val &= ~SDHCI_INT_ADMA_ERROR;
 473                         val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
 474                 }
 475         }
 476
 477         if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
 478                                 && (reg == SDHCI_INT_STATUS)
 479                                 && (val & SDHCI_INT_DATA_END))) {
 480                         u32 v;
 481                         v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 482                         v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
 483                         writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
 484
 485                         if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
 486                         {
 487                                 /* send a manual CMD12 with RESPTYP=none */
 488                                 data = MMC_STOP_TRANSMISSION << 24 |
 489                                        SDHCI_CMD_ABORTCMD << 16;
 490                                 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
 491                                 imx_data->multiblock_status = WAIT_FOR_INT;
 492                         }
 493         }
 494
 495         writel(val, host->ioaddr + reg);
 496 }
 497
 498 static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
 499 {
 500         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 501         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 502         u16 ret = 0;
 503         u32 val;
 504
 505         if (unlikely(reg == SDHCI_HOST_VERSION)) {
 506                 reg ^= 2;
 507                 if (esdhc_is_usdhc(imx_data)) {
 508                         /*
 509                          * The usdhc register returns a wrong host version.
 510                          * Correct it here.
 511                          */
 512                         return SDHCI_SPEC_300;
 513                 }
 514         }
 515
 516         if (unlikely(reg == SDHCI_HOST_CONTROL2)) {
 517                 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 518                 if (val & ESDHC_VENDOR_SPEC_VSELECT)
 519                         ret |= SDHCI_CTRL_VDD_180;
 520
 521                 if (esdhc_is_usdhc(imx_data)) {
 522                         if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
 523                                 val = readl(host->ioaddr + ESDHC_MIX_CTRL);
 524                         else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
 525                                 /* the std tuning bits is in ACMD12_ERR for imx6sl */
 526                                 val = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
 527                 }
 528
 529                 if (val & ESDHC_MIX_CTRL_EXE_TUNE)
 530                         ret |= SDHCI_CTRL_EXEC_TUNING;
 531                 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
 532                         ret |= SDHCI_CTRL_TUNED_CLK;
 533
 534                 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
 535
 536                 return ret;
 537         }
 538
 539         if (unlikely(reg == SDHCI_TRANSFER_MODE)) {
 540                 if (esdhc_is_usdhc(imx_data)) {
 541                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 542                         ret = m & ESDHC_MIX_CTRL_SDHCI_MASK;
 543                         /* Swap AC23 bit */
 544                         if (m & ESDHC_MIX_CTRL_AC23EN) {
 545                                 ret &= ~ESDHC_MIX_CTRL_AC23EN;
 546                                 ret |= SDHCI_TRNS_AUTO_CMD23;
 547                         }
 548                 } else {
 549                         ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
 550                 }
 551
 552                 return ret;
 553         }
 554
 555         return readw(host->ioaddr + reg);
 556 }
 557
 558 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
 559 {
 560         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 561         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 562         u32 new_val = 0;
 563
 564         switch (reg) {
 565         case SDHCI_CLOCK_CONTROL:
 566                 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 567                 if (val & SDHCI_CLOCK_CARD_EN)
 568                         new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
 569                 else
 570                         new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
 571                 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
 572                 if (!(new_val & ESDHC_VENDOR_SPEC_FRC_SDCLK_ON))
 573                         esdhc_wait_for_card_clock_gate_off(host);
 574                 return;
 575         case SDHCI_HOST_CONTROL2:
 576                 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 577                 if (val & SDHCI_CTRL_VDD_180)
 578                         new_val |= ESDHC_VENDOR_SPEC_VSELECT;
 579                 else
 580                         new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
 581                 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
 582                 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
 583                         new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
 584                         if (val & SDHCI_CTRL_TUNED_CLK) {
 585                                 new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL;
 586                                 new_val |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
 587                         } else {
 588                                 new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
 589                                 new_val &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
 590                         }
 591                         writel(new_val , host->ioaddr + ESDHC_MIX_CTRL);
 592                 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
 593                         u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
 594                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 595                         if (val & SDHCI_CTRL_TUNED_CLK) {
 596                                 v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
 597                         } else {
 598                                 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
 599                                 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
 600                                 m &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
 601                         }
 602
 603                         if (val & SDHCI_CTRL_EXEC_TUNING) {
 604                                 v |= ESDHC_MIX_CTRL_EXE_TUNE;
 605                                 m |= ESDHC_MIX_CTRL_FBCLK_SEL;
 606                                 m |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
 607                         } else {
 608                                 v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
 609                         }
 610
 611                         writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
 612                         writel(m, host->ioaddr + ESDHC_MIX_CTRL);
 613                 }
 614                 return;
 615         case SDHCI_TRANSFER_MODE:
 616                 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
 617                                 && (host->cmd->opcode == SD_IO_RW_EXTENDED)
 618                                 && (host->cmd->data->blocks > 1)
 619                                 && (host->cmd->data->flags & MMC_DATA_READ)) {
 620                         u32 v;
 621                         v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 622                         v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
 623                         writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
 624                 }
 625
 626                 if (esdhc_is_usdhc(imx_data)) {
 627                         u32 wml;
 628                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 629                         /* Swap AC23 bit */
 630                         if (val & SDHCI_TRNS_AUTO_CMD23) {
 631                                 val &= ~SDHCI_TRNS_AUTO_CMD23;
 632                                 val |= ESDHC_MIX_CTRL_AC23EN;
 633                         }
 634                         m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
 635                         writel(m, host->ioaddr + ESDHC_MIX_CTRL);
 636
 637                         /* Set watermark levels for PIO access to maximum value
 638                          * (128 words) to accommodate full 512 bytes buffer.
 639                          * For DMA access restore the levels to default value.
 640                          */
 641                         m = readl(host->ioaddr + ESDHC_WTMK_LVL);
 642                         if (val & SDHCI_TRNS_DMA) {
 643                                 wml = ESDHC_WTMK_LVL_WML_VAL_DEF;
 644                         } else {
 645                                 u8 ctrl;
 646                                 wml = ESDHC_WTMK_LVL_WML_VAL_MAX;
 647
 648                                 /*
 649                                  * Since already disable DMA mode, so also need
 650                                  * to clear the DMASEL. Otherwise, for standard
 651                                  * tuning, when send tuning command, usdhc will
 652                                  * still prefetch the ADMA script from wrong
 653                                  * DMA address, then we will see IOMMU report
 654                                  * some error which show lack of TLB mapping.
 655                                  */
 656                                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 657                                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
 658                                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 659                         }
 660                         m &= ~(ESDHC_WTMK_LVL_RD_WML_MASK |
 661                                ESDHC_WTMK_LVL_WR_WML_MASK);
 662                         m |= (wml << ESDHC_WTMK_LVL_RD_WML_SHIFT) |
 663                              (wml << ESDHC_WTMK_LVL_WR_WML_SHIFT);
 664                         writel(m, host->ioaddr + ESDHC_WTMK_LVL);
 665                 } else {
 666                         /*
 667                          * Postpone this write, we must do it together with a
 668                          * command write that is down below.
 669                          */
 670                         imx_data->scratchpad = val;
 671                 }
 672                 return;
 673         case SDHCI_COMMAND:
 674                 if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
 675                         val |= SDHCI_CMD_ABORTCMD;
 676
 677                 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
 678                     (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
 679                         imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
 680
 681                 if (esdhc_is_usdhc(imx_data))
 682                         writel(val << 16,
 683                                host->ioaddr + SDHCI_TRANSFER_MODE);
 684                 else
 685                         writel(val << 16 | imx_data->scratchpad,
 686                                host->ioaddr + SDHCI_TRANSFER_MODE);
 687                 return;
 688         case SDHCI_BLOCK_SIZE:
 689                 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
 690                 break;
 691         }
 692         esdhc_clrset_le(host, 0xffff, val, reg);
 693 }
 694
 695 static u8 esdhc_readb_le(struct sdhci_host *host, int reg)
 696 {
 697         u8 ret;
 698         u32 val;
 699
 700         switch (reg) {
 701         case SDHCI_HOST_CONTROL:
 702                 val = readl(host->ioaddr + reg);
 703
 704                 ret = val & SDHCI_CTRL_LED;
 705                 ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK;
 706                 ret |= (val & ESDHC_CTRL_4BITBUS);
 707                 ret |= (val & ESDHC_CTRL_8BITBUS) << 3;
 708                 return ret;
 709         }
 710
 711         return readb(host->ioaddr + reg);
 712 }
 713
 714 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
 715 {
 716         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 717         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 718         u32 new_val = 0;
 719         u32 mask;
 720
 721         switch (reg) {
 722         case SDHCI_POWER_CONTROL:
 723                 /*
 724                  * FSL put some DMA bits here
 725                  * If your board has a regulator, code should be here
 726                  */
 727                 return;
 728         case SDHCI_HOST_CONTROL:
 729                 /* FSL messed up here, so we need to manually compose it. */
 730                 new_val = val & SDHCI_CTRL_LED;
 731                 /* ensure the endianness */
 732                 new_val |= ESDHC_HOST_CONTROL_LE;
 733                 /* bits 8&9 are reserved on mx25 */
 734                 if (!is_imx25_esdhc(imx_data)) {
 735                         /* DMA mode bits are shifted */
 736                         new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
 737                 }
 738
 739                 /*
 740                  * Do not touch buswidth bits here. This is done in
 741                  * esdhc_pltfm_bus_width.
 742                  * Do not touch the D3CD bit either which is used for the
 743                  * SDIO interrupt erratum workaround.
 744                  */
 745                 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
 746
 747                 esdhc_clrset_le(host, mask, new_val, reg);
 748                 return;
 749         case SDHCI_SOFTWARE_RESET:
 750                 if (val & SDHCI_RESET_DATA)
 751                         new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL);
 752                 break;
 753         }
 754         esdhc_clrset_le(host, 0xff, val, reg);
 755
 756         if (reg == SDHCI_SOFTWARE_RESET) {
 757                 if (val & SDHCI_RESET_ALL) {
 758                         /*
 759                          * The esdhc has a design violation to SDHC spec which
 760                          * tells that software reset should not affect card
 761                          * detection circuit. But esdhc clears its SYSCTL
 762                          * register bits [0..2] during the software reset. This
 763                          * will stop those clocks that card detection circuit
 764                          * relies on. To work around it, we turn the clocks on
 765                          * back to keep card detection circuit functional.
 766                          */
 767                         esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
 768                         /*
 769                          * The reset on usdhc fails to clear MIX_CTRL register.
 770                          * Do it manually here.
 771                          */
 772                         if (esdhc_is_usdhc(imx_data)) {
 773                                 /*
 774                                  * the tuning bits should be kept during reset
 775                                  */
 776                                 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
 777                                 writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,
 778                                                 host->ioaddr + ESDHC_MIX_CTRL);
 779                                 imx_data->is_ddr = 0;
 780                         }
 781                 } else if (val & SDHCI_RESET_DATA) {
 782                         /*
 783                          * The eSDHC DAT line software reset clears at least the
 784                          * data transfer width on i.MX25, so make sure that the
 785                          * Host Control register is unaffected.
 786                          */
 787                         esdhc_clrset_le(host, 0xff, new_val,
 788                                         SDHCI_HOST_CONTROL);
 789                 }
 790         }
 791 }
 792
 793 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
 794 {
 795         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 796
 797         return pltfm_host->clock;
 798 }
 799
 800 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
 801 {
 802         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 803
 804         return pltfm_host->clock / 256 / 16;
 805 }
 806
 807 static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
 808                                          unsigned int clock)
 809 {
 810         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 811         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 812         unsigned int host_clock = pltfm_host->clock;
 813         int ddr_pre_div = imx_data->is_ddr ? 2 : 1;
 814         int pre_div = 1;
 815         int div = 1;
 816         int ret;
 817         u32 temp, val;
 818
 819         if (esdhc_is_usdhc(imx_data)) {
 820                 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 821                 writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
 822                         host->ioaddr + ESDHC_VENDOR_SPEC);
 823                 esdhc_wait_for_card_clock_gate_off(host);
 824         }
 825
 826         if (clock == 0) {
 827                 host->mmc->actual_clock = 0;
 828                 return;
 829         }
 830
 831         /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
 832         if (is_imx53_esdhc(imx_data)) {
 833                 /*
 834                  * According to the i.MX53 reference manual, if DLLCTRL[10] can
 835                  * be set, then the controller is eSDHCv3, else it is eSDHCv2.
 836                  */
 837                 val = readl(host->ioaddr + ESDHC_DLL_CTRL);
 838                 writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL);
 839                 temp = readl(host->ioaddr + ESDHC_DLL_CTRL);
 840                 writel(val, host->ioaddr + ESDHC_DLL_CTRL);
 841                 if (temp & BIT(10))
 842                         pre_div = 2;
 843         }
 844
 845         temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
 846         temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
 847                 | ESDHC_CLOCK_MASK);
 848         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
 849
 850         if (imx_data->socdata->flags & ESDHC_FLAG_ERR010450) {
 851                 unsigned int max_clock;
 852
 853                 max_clock = imx_data->is_ddr ? 45000000 : 150000000;
 854
 855                 clock = min(clock, max_clock);
 856         }
 857
 858         while (host_clock / (16 * pre_div * ddr_pre_div) > clock &&
 859                         pre_div < 256)
 860                 pre_div *= 2;
 861
 862         while (host_clock / (div * pre_div * ddr_pre_div) > clock && div < 16)
 863                 div++;
 864
 865         host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div);
 866         dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
 867                 clock, host->mmc->actual_clock);
 868
 869         pre_div >>= 1;
 870         div--;
 871
 872         temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
 873         temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
 874                 | (div << ESDHC_DIVIDER_SHIFT)
 875                 | (pre_div << ESDHC_PREDIV_SHIFT));
 876         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
 877
 878         /* need to wait the bit 3 of the PRSSTAT to be set, make sure card clock is stable */
 879         ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, temp,
 880                                 (temp & ESDHC_CLOCK_STABLE), 2, 100);
 881         if (ret == -ETIMEDOUT)
 882                 dev_warn(mmc_dev(host->mmc), "card clock still not stable in 100us!.\n");
 883
 884         if (esdhc_is_usdhc(imx_data)) {
 885                 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 886                 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
 887                         host->ioaddr + ESDHC_VENDOR_SPEC);
 888         }
 889
 890 }
 891
 892 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
 893 {
 894         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 895         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 896         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
 897
 898         switch (boarddata->wp_type) {
 899         case ESDHC_WP_GPIO:
 900                 return mmc_gpio_get_ro(host->mmc);
 901         case ESDHC_WP_CONTROLLER:
 902                 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
 903                                SDHCI_WRITE_PROTECT);
 904         case ESDHC_WP_NONE:
 905                 break;
 906         }
 907
 908         return -ENOSYS;
 909 }
 910
 911 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
 912 {
 913         u32 ctrl;
 914
 915         switch (width) {
 916         case MMC_BUS_WIDTH_8:
 917                 ctrl = ESDHC_CTRL_8BITBUS;
 918                 break;
 919         case MMC_BUS_WIDTH_4:
 920                 ctrl = ESDHC_CTRL_4BITBUS;
 921                 break;
 922         default:
 923                 ctrl = 0;
 924                 break;
 925         }
 926
 927         esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
 928                         SDHCI_HOST_CONTROL);
 929 }
 930
 931 static int usdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)
 932 {
 933         struct sdhci_host *host = mmc_priv(mmc);
 934
 935         /*
 936          * i.MX uSDHC internally already uses a fixed optimized timing for
 937          * DDR50, normally does not require tuning for DDR50 mode.
 938          */
 939         if (host->timing == MMC_TIMING_UHS_DDR50)
 940                 return 0;
 941
 942         return sdhci_execute_tuning(mmc, opcode);
 943 }
 944
 945 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
 946 {
 947         u32 reg;
 948
 949         /* FIXME: delay a bit for card to be ready for next tuning due to errors */
 950         mdelay(1);
 951
 952         reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
 953         reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
 954                         ESDHC_MIX_CTRL_FBCLK_SEL;
 955         writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
 956         writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
 957         dev_dbg(mmc_dev(host->mmc),
 958                 "tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
 959                         val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
 960 }
 961
 962 static void esdhc_post_tuning(struct sdhci_host *host)
 963 {
 964         u32 reg;
 965
 966         reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
 967         reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
 968         reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
 969         writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
 970 }
 971
 972 static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
 973 {
 974         int min, max, avg, ret;
 975
 976         /* find the mininum delay first which can pass tuning */
 977         min = ESDHC_TUNE_CTRL_MIN;
 978         while (min < ESDHC_TUNE_CTRL_MAX) {
 979                 esdhc_prepare_tuning(host, min);
 980                 if (!mmc_send_tuning(host->mmc, opcode, NULL))
 981                         break;
 982                 min += ESDHC_TUNE_CTRL_STEP;
 983         }
 984
 985         /* find the maxinum delay which can not pass tuning */
 986         max = min + ESDHC_TUNE_CTRL_STEP;
 987         while (max < ESDHC_TUNE_CTRL_MAX) {
 988                 esdhc_prepare_tuning(host, max);
 989                 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
 990                         max -= ESDHC_TUNE_CTRL_STEP;
 991                         break;
 992                 }
 993                 max += ESDHC_TUNE_CTRL_STEP;
 994         }
 995
 996         /* use average delay to get the best timing */
 997         avg = (min + max) / 2;
 998         esdhc_prepare_tuning(host, avg);
 999         ret = mmc_send_tuning(host->mmc, opcode, NULL);
1000         esdhc_post_tuning(host);
1001
1002         dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n",
1003                 ret ? "failed" : "passed", avg, ret);
1004
1005         return ret;
1006 }
1007
1008 static void esdhc_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios)
1009 {
1010         struct sdhci_host *host = mmc_priv(mmc);
1011         u32 m;
1012
1013         m = readl(host->ioaddr + ESDHC_MIX_CTRL);
1014         if (ios->enhanced_strobe)
1015                 m |= ESDHC_MIX_CTRL_HS400_ES_EN;
1016         else
1017                 m &= ~ESDHC_MIX_CTRL_HS400_ES_EN;
1018         writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1019 }
1020
1021 static int esdhc_change_pinstate(struct sdhci_host *host,
1022                                                 unsigned int uhs)
1023 {
1024         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1025         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1026         struct pinctrl_state *pinctrl;
1027
1028         dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
1029
1030         if (IS_ERR(imx_data->pinctrl) ||
1031                 IS_ERR(imx_data->pins_100mhz) ||
1032                 IS_ERR(imx_data->pins_200mhz))
1033                 return -EINVAL;
1034
1035         switch (uhs) {
1036         case MMC_TIMING_UHS_SDR50:
1037         case MMC_TIMING_UHS_DDR50:
1038                 pinctrl = imx_data->pins_100mhz;
1039                 break;
1040         case MMC_TIMING_UHS_SDR104:
1041         case MMC_TIMING_MMC_HS200:
1042         case MMC_TIMING_MMC_HS400:
1043                 pinctrl = imx_data->pins_200mhz;
1044                 break;
1045         default:
1046                 /* back to default state for other legacy timing */
1047                 return pinctrl_select_default_state(mmc_dev(host->mmc));
1048         }
1049
1050         return pinctrl_select_state(imx_data->pinctrl, pinctrl);
1051 }
1052
1053 /*
1054  * For HS400 eMMC, there is a data_strobe line. This signal is generated
1055  * by the device and used for data output and CRC status response output
1056  * in HS400 mode. The frequency of this signal follows the frequency of
1057  * CLK generated by host. The host receives the data which is aligned to the
1058  * edge of data_strobe line. Due to the time delay between CLK line and
1059  * data_strobe line, if the delay time is larger than one clock cycle,
1060  * then CLK and data_strobe line will be misaligned, read error shows up.
1061  */
1062 static void esdhc_set_strobe_dll(struct sdhci_host *host)
1063 {
1064         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1065         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1066         u32 strobe_delay;
1067         u32 v;
1068         int ret;
1069
1070         /* disable clock before enabling strobe dll */
1071         writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) &
1072                 ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
1073                 host->ioaddr + ESDHC_VENDOR_SPEC);
1074         esdhc_wait_for_card_clock_gate_off(host);
1075
1076         /* force a reset on strobe dll */
1077         writel(ESDHC_STROBE_DLL_CTRL_RESET,
1078                 host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1079         /* clear the reset bit on strobe dll before any setting */
1080         writel(0, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1081
1082         /*
1083          * enable strobe dll ctrl and adjust the delay target
1084          * for the uSDHC loopback read clock
1085          */
1086         if (imx_data->boarddata.strobe_dll_delay_target)
1087                 strobe_delay = imx_data->boarddata.strobe_dll_delay_target;
1088         else
1089                 strobe_delay = ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT;
1090         v = ESDHC_STROBE_DLL_CTRL_ENABLE |
1091                 ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT |
1092                 (strobe_delay << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
1093         writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1094
1095         /* wait max 50us to get the REF/SLV lock */
1096         ret = readl_poll_timeout(host->ioaddr + ESDHC_STROBE_DLL_STATUS, v,
1097                 ((v & ESDHC_STROBE_DLL_STS_REF_LOCK) && (v & ESDHC_STROBE_DLL_STS_SLV_LOCK)), 1, 50);
1098         if (ret == -ETIMEDOUT)
1099                 dev_warn(mmc_dev(host->mmc),
1100                 "warning! HS400 strobe DLL status REF/SLV not lock in 50us, STROBE DLL status is %x!\n", v);
1101 }
1102
1103 static void esdhc_reset_tuning(struct sdhci_host *host)
1104 {
1105         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1106         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1107         u32 ctrl;
1108
1109         /* Reset the tuning circuit */
1110         if (esdhc_is_usdhc(imx_data)) {
1111                 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
1112                         ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL);
1113                         ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
1114                         ctrl &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
1115                         writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL);
1116                         writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1117                 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
1118                         ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1119                         ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
1120                         writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1121                 }
1122         }
1123 }
1124
1125 static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1126 {
1127         u32 m;
1128         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1129         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1130         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1131
1132         /* disable ddr mode and disable HS400 mode */
1133         m = readl(host->ioaddr + ESDHC_MIX_CTRL);
1134         m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN);
1135         imx_data->is_ddr = 0;
1136
1137         switch (timing) {
1138         case MMC_TIMING_UHS_SDR12:
1139         case MMC_TIMING_UHS_SDR25:
1140         case MMC_TIMING_UHS_SDR50:
1141         case MMC_TIMING_UHS_SDR104:
1142         case MMC_TIMING_MMC_HS:
1143         case MMC_TIMING_MMC_HS200:
1144                 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1145                 break;
1146         case MMC_TIMING_UHS_DDR50:
1147         case MMC_TIMING_MMC_DDR52:
1148                 m |= ESDHC_MIX_CTRL_DDREN;
1149                 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1150                 imx_data->is_ddr = 1;
1151                 if (boarddata->delay_line) {
1152                         u32 v;
1153                         v = boarddata->delay_line <<
1154                                 ESDHC_DLL_OVERRIDE_VAL_SHIFT |
1155                                 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT);
1156                         if (is_imx53_esdhc(imx_data))
1157                                 v <<= 1;
1158                         writel(v, host->ioaddr + ESDHC_DLL_CTRL);
1159                 }
1160                 break;
1161         case MMC_TIMING_MMC_HS400:
1162                 m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN;
1163                 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1164                 imx_data->is_ddr = 1;
1165                 /* update clock after enable DDR for strobe DLL lock */
1166                 host->ops->set_clock(host, host->clock);
1167                 esdhc_set_strobe_dll(host);
1168                 break;
1169         case MMC_TIMING_LEGACY:
1170         default:
1171                 esdhc_reset_tuning(host);
1172                 break;
1173         }
1174
1175         esdhc_change_pinstate(host, timing);
1176 }
1177
1178 static void esdhc_reset(struct sdhci_host *host, u8 mask)
1179 {
1180         sdhci_reset(host, mask);
1181
1182         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1183         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1184 }
1185
1186 static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host)
1187 {
1188         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1189         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1190
1191         /* Doc Erratum: the uSDHC actual maximum timeout count is 1 << 29 */
1192         return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27;
1193 }
1194
1195 static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1196 {
1197         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1198         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1199
1200         /* use maximum timeout counter */
1201         esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK,
1202                         esdhc_is_usdhc(imx_data) ? 0xF : 0xE,
1203                         SDHCI_TIMEOUT_CONTROL);
1204 }
1205
1206 static u32 esdhc_cqhci_irq(struct sdhci_host *host, u32 intmask)
1207 {
1208         int cmd_error = 0;
1209         int data_error = 0;
1210
1211         if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
1212                 return intmask;
1213
1214         cqhci_irq(host->mmc, intmask, cmd_error, data_error);
1215
1216         return 0;
1217 }
1218
1219 static struct sdhci_ops sdhci_esdhc_ops = {
1220         .read_l = esdhc_readl_le,
1221         .read_w = esdhc_readw_le,
1222         .read_b = esdhc_readb_le,
1223         .write_l = esdhc_writel_le,
1224         .write_w = esdhc_writew_le,
1225         .write_b = esdhc_writeb_le,
1226         .set_clock = esdhc_pltfm_set_clock,
1227         .get_max_clock = esdhc_pltfm_get_max_clock,
1228         .get_min_clock = esdhc_pltfm_get_min_clock,
1229         .get_max_timeout_count = esdhc_get_max_timeout_count,
1230         .get_ro = esdhc_pltfm_get_ro,
1231         .set_timeout = esdhc_set_timeout,
1232         .set_bus_width = esdhc_pltfm_set_bus_width,
1233         .set_uhs_signaling = esdhc_set_uhs_signaling,
1234         .reset = esdhc_reset,
1235         .irq = esdhc_cqhci_irq,
1236 };
1237
1238 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
1239         .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
1240                         | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
1241                         | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
1242                         | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
1243         .ops = &sdhci_esdhc_ops,
1244 };
1245
1246 static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host)
1247 {
1248         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1249         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1250         struct cqhci_host *cq_host = host->mmc->cqe_private;
1251         int tmp;
1252
1253         if (esdhc_is_usdhc(imx_data)) {
1254                 /*
1255                  * The imx6q ROM code will change the default watermark
1256                  * level setting to something insane.  Change it back here.
1257                  */
1258                 writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL);
1259
1260                 /*
1261                  * ROM code will change the bit burst_length_enable setting
1262                  * to zero if this usdhc is chosen to boot system. Change
1263                  * it back here, otherwise it will impact the performance a
1264                  * lot. This bit is used to enable/disable the burst length
1265                  * for the external AHB2AXI bridge. It's useful especially
1266                  * for INCR transfer because without burst length indicator,
1267                  * the AHB2AXI bridge does not know the burst length in
1268                  * advance. And without burst length indicator, AHB INCR
1269                  * transfer can only be converted to singles on the AXI side.
1270                  */
1271                 writel(readl(host->ioaddr + SDHCI_HOST_CONTROL)
1272                         | ESDHC_BURST_LEN_EN_INCR,
1273                         host->ioaddr + SDHCI_HOST_CONTROL);
1274
1275                 /*
1276                  * erratum ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
1277                  * TO1.1, it's harmless for MX6SL
1278                  */
1279                 writel(readl(host->ioaddr + 0x6c) & ~BIT(7),
1280                         host->ioaddr + 0x6c);
1281
1282                 /* disable DLL_CTRL delay line settings */
1283                 writel(0x0, host->ioaddr + ESDHC_DLL_CTRL);
1284
1285                 /*
1286                  * For the case of command with busy, if set the bit
1287                  * ESDHC_VEND_SPEC2_EN_BUSY_IRQ, USDHC will generate a
1288                  * transfer complete interrupt when busy is deasserted.
1289                  * When CQHCI use DCMD to send a CMD need R1b respons,
1290                  * CQHCI require to set ESDHC_VEND_SPEC2_EN_BUSY_IRQ,
1291                  * otherwise DCMD will always meet timeout waiting for
1292                  * hardware interrupt issue.
1293                  */
1294                 if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) {
1295                         tmp = readl(host->ioaddr + ESDHC_VEND_SPEC2);
1296                         tmp |= ESDHC_VEND_SPEC2_EN_BUSY_IRQ;
1297                         writel(tmp, host->ioaddr + ESDHC_VEND_SPEC2);
1298
1299                         host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
1300                 }
1301
1302                 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
1303                         tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
1304                         tmp |= ESDHC_STD_TUNING_EN |
1305                                 ESDHC_TUNING_START_TAP_DEFAULT;
1306                         if (imx_data->boarddata.tuning_start_tap) {
1307                                 tmp &= ~ESDHC_TUNING_START_TAP_MASK;
1308                                 tmp |= imx_data->boarddata.tuning_start_tap;
1309                         }
1310
1311                         if (imx_data->boarddata.tuning_step) {
1312                                 tmp &= ~ESDHC_TUNING_STEP_MASK;
1313                                 tmp |= imx_data->boarddata.tuning_step
1314                                         << ESDHC_TUNING_STEP_SHIFT;
1315                         }
1316                         writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
1317                 } else if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
1318                         /*
1319                          * ESDHC_STD_TUNING_EN may be configed in bootloader
1320                          * or ROM code, so clear this bit here to make sure
1321                          * the manual tuning can work.
1322                          */
1323                         tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
1324                         tmp &= ~ESDHC_STD_TUNING_EN;
1325                         writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
1326                 }
1327
1328                 /*
1329                  * On i.MX8MM, we are running Dual Linux OS, with 1st Linux using SD Card
1330                  * as rootfs storage, 2nd Linux using eMMC as rootfs storage. We let the
1331                  * the 1st linux configure power/clock for the 2nd Linux.
1332                  *
1333                  * When the 2nd Linux is booting into rootfs stage, we let the 1st Linux
1334                  * to destroy the 2nd linux, then restart the 2nd linux, we met SDHCI dump.
1335                  * After we clear the pending interrupt and halt CQCTL, issue gone.
1336                  */
1337                 if (cq_host) {
1338                         tmp = cqhci_readl(cq_host, CQHCI_IS);
1339                         cqhci_writel(cq_host, tmp, CQHCI_IS);
1340                         cqhci_writel(cq_host, CQHCI_HALT, CQHCI_CTL);
1341                 }
1342         }
1343 }
1344
1345 static void esdhc_cqe_enable(struct mmc_host *mmc)
1346 {
1347         struct sdhci_host *host = mmc_priv(mmc);
1348         struct cqhci_host *cq_host = mmc->cqe_private;
1349         u32 reg;
1350         u16 mode;
1351         int count = 10;
1352
1353         /*
1354          * CQE gets stuck if it sees Buffer Read Enable bit set, which can be
1355          * the case after tuning, so ensure the buffer is drained.
1356          */
1357         reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
1358         while (reg & SDHCI_DATA_AVAILABLE) {
1359                 sdhci_readl(host, SDHCI_BUFFER);
1360                 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
1361                 if (count-- == 0) {
1362                         dev_warn(mmc_dev(host->mmc),
1363                                 "CQE may get stuck because the Buffer Read Enable bit is set\n");
1364                         break;
1365                 }
1366                 mdelay(1);
1367         }
1368
1369         /*
1370          * Runtime resume will reset the entire host controller, which
1371          * will also clear the DMAEN/BCEN of register ESDHC_MIX_CTRL.
1372          * Here set DMAEN and BCEN when enable CMDQ.
1373          */
1374         mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
1375         if (host->flags & SDHCI_REQ_USE_DMA)
1376                 mode |= SDHCI_TRNS_DMA;
1377         if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
1378                 mode |= SDHCI_TRNS_BLK_CNT_EN;
1379         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
1380
1381         /*
1382          * Though Runtime resume reset the entire host controller,
1383          * but do not impact the CQHCI side, need to clear the
1384          * HALT bit, avoid CQHCI stuck in the first request when
1385          * system resume back.
1386          */
1387         cqhci_writel(cq_host, 0, CQHCI_CTL);
1388         if (cqhci_readl(cq_host, CQHCI_CTL) && CQHCI_HALT)
1389                 dev_err(mmc_dev(host->mmc),
1390                         "failed to exit halt state when enable CQE\n");
1391
1392
1393         sdhci_cqe_enable(mmc);
1394 }
1395
1396 static void esdhc_sdhci_dumpregs(struct mmc_host *mmc)
1397 {
1398         sdhci_dumpregs(mmc_priv(mmc));
1399 }
1400
1401 static const struct cqhci_host_ops esdhc_cqhci_ops = {
1402         .enable         = esdhc_cqe_enable,
1403         .disable        = sdhci_cqe_disable,
1404         .dumpregs       = esdhc_sdhci_dumpregs,
1405 };
1406
1407 #ifdef CONFIG_OF
1408 static int
1409 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
1410                          struct sdhci_host *host,
1411                          struct pltfm_imx_data *imx_data)
1412 {
1413         struct device_node *np = pdev->dev.of_node;
1414         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1415         int ret;
1416
1417         if (of_get_property(np, "fsl,wp-controller", NULL))
1418                 boarddata->wp_type = ESDHC_WP_CONTROLLER;
1419
1420         /*
1421          * If we have this property, then activate WP check.
1422          * Retrieveing and requesting the actual WP GPIO will happen
1423          * in the call to mmc_of_parse().
1424          */
1425         if (of_property_read_bool(np, "wp-gpios"))
1426                 boarddata->wp_type = ESDHC_WP_GPIO;
1427
1428         of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step);
1429         of_property_read_u32(np, "fsl,tuning-start-tap",
1430                              &boarddata->tuning_start_tap);
1431
1432         of_property_read_u32(np, "fsl,strobe-dll-delay-target",
1433                                 &boarddata->strobe_dll_delay_target);
1434         if (of_find_property(np, "no-1-8-v", NULL))
1435                 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1436
1437         if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
1438                 boarddata->delay_line = 0;
1439
1440         mmc_of_parse_voltage(np, &host->ocr_mask);
1441
1442         if (esdhc_is_usdhc(imx_data)) {
1443                 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
1444                                                 ESDHC_PINCTRL_STATE_100MHZ);
1445                 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
1446                                                 ESDHC_PINCTRL_STATE_200MHZ);
1447         }
1448
1449         /* call to generic mmc_of_parse to support additional capabilities */
1450         ret = mmc_of_parse(host->mmc);
1451         if (ret)
1452                 return ret;
1453
1454         if (mmc_gpio_get_cd(host->mmc) >= 0)
1455                 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1456
1457         return 0;
1458 }
1459 #else
1460 static inline int
1461 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
1462                          struct sdhci_host *host,
1463                          struct pltfm_imx_data *imx_data)
1464 {
1465         return -ENODEV;
1466 }
1467 #endif
1468
1469 static int sdhci_esdhc_imx_probe_nondt(struct platform_device *pdev,
1470                          struct sdhci_host *host,
1471                          struct pltfm_imx_data *imx_data)
1472 {
1473         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1474         int err;
1475
1476         if (!host->mmc->parent->platform_data) {
1477                 dev_err(mmc_dev(host->mmc), "no board data!\n");
1478                 return -EINVAL;
1479         }
1480
1481         imx_data->boarddata = *((struct esdhc_platform_data *)
1482                                 host->mmc->parent->platform_data);
1483         /* write_protect */
1484         if (boarddata->wp_type == ESDHC_WP_GPIO) {
1485                 host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
1486
1487                 err = mmc_gpiod_request_ro(host->mmc, "wp", 0, 0);
1488                 if (err) {
1489                         dev_err(mmc_dev(host->mmc),
1490                                 "failed to request write-protect gpio!\n");
1491                         return err;
1492                 }
1493         }
1494
1495         /* card_detect */
1496         switch (boarddata->cd_type) {
1497         case ESDHC_CD_GPIO:
1498                 err = mmc_gpiod_request_cd(host->mmc, "cd", 0, false, 0);
1499                 if (err) {
1500                         dev_err(mmc_dev(host->mmc),
1501                                 "failed to request card-detect gpio!\n");
1502                         return err;
1503                 }
1504                 /* fall through */
1505
1506         case ESDHC_CD_CONTROLLER:
1507                 /* we have a working card_detect back */
1508                 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1509                 break;
1510
1511         case ESDHC_CD_PERMANENT:
1512                 host->mmc->caps |= MMC_CAP_NONREMOVABLE;
1513                 break;
1514
1515         case ESDHC_CD_NONE:
1516                 break;
1517         }
1518
1519         switch (boarddata->max_bus_width) {
1520         case 8:
1521                 host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA;
1522                 break;
1523         case 4:
1524                 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
1525                 break;
1526         case 1:
1527         default:
1528                 host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
1529                 break;
1530         }
1531
1532         return 0;
1533 }
1534
1535 static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
1536 {
1537         const struct of_device_id *of_id =
1538                         of_match_device(imx_esdhc_dt_ids, &pdev->dev);
1539         struct sdhci_pltfm_host *pltfm_host;
1540         struct sdhci_host *host;
1541         struct cqhci_host *cq_host;
1542         int err;
1543         struct pltfm_imx_data *imx_data;
1544
1545         host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata,
1546                                 sizeof(*imx_data));
1547         if (IS_ERR(host))
1548                 return PTR_ERR(host);
1549
1550         pltfm_host = sdhci_priv(host);
1551
1552         imx_data = sdhci_pltfm_priv(pltfm_host);
1553
1554         imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *)
1555                                                   pdev->id_entry->driver_data;
1556
1557         if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1558                 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0);
1559
1560         imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1561         if (IS_ERR(imx_data->clk_ipg)) {
1562                 err = PTR_ERR(imx_data->clk_ipg);
1563                 goto free_sdhci;
1564         }
1565
1566         imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1567         if (IS_ERR(imx_data->clk_ahb)) {
1568                 err = PTR_ERR(imx_data->clk_ahb);
1569                 goto free_sdhci;
1570         }
1571
1572         imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
1573         if (IS_ERR(imx_data->clk_per)) {
1574                 err = PTR_ERR(imx_data->clk_per);
1575                 goto free_sdhci;
1576         }
1577
1578         pltfm_host->clk = imx_data->clk_per;
1579         pltfm_host->clock = clk_get_rate(pltfm_host->clk);
1580         err = clk_prepare_enable(imx_data->clk_per);
1581         if (err)
1582                 goto free_sdhci;
1583         err = clk_prepare_enable(imx_data->clk_ipg);
1584         if (err)
1585                 goto disable_per_clk;
1586         err = clk_prepare_enable(imx_data->clk_ahb);
1587         if (err)
1588                 goto disable_ipg_clk;
1589
1590         imx_data->pinctrl = devm_pinctrl_get(&pdev->dev);
1591         if (IS_ERR(imx_data->pinctrl)) {
1592                 err = PTR_ERR(imx_data->pinctrl);
1593                 dev_warn(mmc_dev(host->mmc), "could not get pinctrl\n");
1594         }
1595
1596         if (esdhc_is_usdhc(imx_data)) {
1597                 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
1598                 host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;
1599                 if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200))
1600                         host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
1601
1602                 /* clear tuning bits in case ROM has set it already */
1603                 writel(0x0, host->ioaddr + ESDHC_MIX_CTRL);
1604                 writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1605                 writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1606
1607                 /*
1608                  * Link usdhc specific mmc_host_ops execute_tuning function,
1609                  * to replace the standard one in sdhci_ops.
1610                  */
1611                 host->mmc_host_ops.execute_tuning = usdhc_execute_tuning;
1612         }
1613
1614         if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
1615                 sdhci_esdhc_ops.platform_execute_tuning =
1616                                         esdhc_executing_tuning;
1617
1618         if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
1619                 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1620
1621         if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
1622                 host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400;
1623
1624         if (imx_data->socdata->flags & ESDHC_FLAG_BROKEN_AUTO_CMD23)
1625                 host->quirks2 |= SDHCI_QUIRK2_ACMD23_BROKEN;
1626
1627         if (imx_data->socdata->flags & ESDHC_FLAG_HS400_ES) {
1628                 host->mmc->caps2 |= MMC_CAP2_HS400_ES;
1629                 host->mmc_host_ops.hs400_enhanced_strobe =
1630                                         esdhc_hs400_enhanced_strobe;
1631         }
1632
1633         if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) {
1634                 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
1635                 cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL);
1636                 if (!cq_host) {
1637                         err = -ENOMEM;
1638                         goto disable_ahb_clk;
1639                 }
1640
1641                 cq_host->mmio = host->ioaddr + ESDHC_CQHCI_ADDR_OFFSET;
1642                 cq_host->ops = &esdhc_cqhci_ops;
1643
1644                 err = cqhci_init(cq_host, host->mmc, false);
1645                 if (err)
1646                         goto disable_ahb_clk;
1647         }
1648
1649         if (of_id)
1650                 err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data);
1651         else
1652                 err = sdhci_esdhc_imx_probe_nondt(pdev, host, imx_data);
1653         if (err)
1654                 goto disable_ahb_clk;
1655
1656         host->tuning_delay = 1;
1657
1658         sdhci_esdhc_imx_hwinit(host);
1659
1660         err = sdhci_add_host(host);
1661         if (err)
1662                 goto disable_ahb_clk;
1663
1664         pm_runtime_set_active(&pdev->dev);
1665         pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1666         pm_runtime_use_autosuspend(&pdev->dev);
1667         pm_suspend_ignore_children(&pdev->dev, 1);
1668         pm_runtime_enable(&pdev->dev);
1669
1670         return 0;
1671
1672 disable_ahb_clk:
1673         clk_disable_unprepare(imx_data->clk_ahb);
1674 disable_ipg_clk:
1675         clk_disable_unprepare(imx_data->clk_ipg);
1676 disable_per_clk:
1677         clk_disable_unprepare(imx_data->clk_per);
1678 free_sdhci:
1679         if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1680                 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1681         sdhci_pltfm_free(pdev);
1682         return err;
1683 }
1684
1685 static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
1686 {
1687         struct sdhci_host *host = platform_get_drvdata(pdev);
1688         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1689         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1690         int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
1691
1692         pm_runtime_get_sync(&pdev->dev);
1693         pm_runtime_disable(&pdev->dev);
1694         pm_runtime_put_noidle(&pdev->dev);
1695
1696         sdhci_remove_host(host, dead);
1697
1698         clk_disable_unprepare(imx_data->clk_per);
1699         clk_disable_unprepare(imx_data->clk_ipg);
1700         clk_disable_unprepare(imx_data->clk_ahb);
1701
1702         if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1703                 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1704
1705         sdhci_pltfm_free(pdev);
1706
1707         return 0;
1708 }
1709
1710 #ifdef CONFIG_PM_SLEEP
1711 static int sdhci_esdhc_suspend(struct device *dev)
1712 {
1713         struct sdhci_host *host = dev_get_drvdata(dev);
1714         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1715         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1716         int ret;
1717
1718         if (host->mmc->caps2 & MMC_CAP2_CQE) {
1719                 ret = cqhci_suspend(host->mmc);
1720                 if (ret)
1721                         return ret;
1722         }
1723
1724         if ((imx_data->socdata->flags & ESDHC_FLAG_STATE_LOST_IN_LPMODE) &&
1725                 (host->tuning_mode != SDHCI_TUNING_MODE_1)) {
1726                 mmc_retune_timer_stop(host->mmc);
1727                 mmc_retune_needed(host->mmc);
1728         }
1729
1730         if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1731                 mmc_retune_needed(host->mmc);
1732
1733         ret = sdhci_suspend_host(host);
1734         if (!ret)
1735                 return pinctrl_pm_select_sleep_state(dev);
1736
1737         return ret;
1738 }
1739
1740 static int sdhci_esdhc_resume(struct device *dev)
1741 {
1742         struct sdhci_host *host = dev_get_drvdata(dev);
1743         int ret;
1744
1745         ret = pinctrl_pm_select_default_state(dev);
1746         if (ret)
1747                 return ret;
1748
1749         /* re-initialize hw state in case it's lost in low power mode */
1750         sdhci_esdhc_imx_hwinit(host);
1751
1752         ret = sdhci_resume_host(host);
1753         if (ret)
1754                 return ret;
1755
1756         if (host->mmc->caps2 & MMC_CAP2_CQE)
1757                 ret = cqhci_resume(host->mmc);
1758
1759         return ret;
1760 }
1761 #endif
1762
1763 #ifdef CONFIG_PM
1764 static int sdhci_esdhc_runtime_suspend(struct device *dev)
1765 {
1766         struct sdhci_host *host = dev_get_drvdata(dev);
1767         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1768         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1769         int ret;
1770
1771         if (host->mmc->caps2 & MMC_CAP2_CQE) {
1772                 ret = cqhci_suspend(host->mmc);
1773                 if (ret)
1774                         return ret;
1775         }
1776
1777         ret = sdhci_runtime_suspend_host(host);
1778         if (ret)
1779                 return ret;
1780
1781         if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1782                 mmc_retune_needed(host->mmc);
1783
1784         imx_data->actual_clock = host->mmc->actual_clock;
1785         esdhc_pltfm_set_clock(host, 0);
1786         clk_disable_unprepare(imx_data->clk_per);
1787         clk_disable_unprepare(imx_data->clk_ipg);
1788         clk_disable_unprepare(imx_data->clk_ahb);
1789
1790         if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1791                 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1792
1793         return ret;
1794 }
1795
1796 static int sdhci_esdhc_runtime_resume(struct device *dev)
1797 {
1798         struct sdhci_host *host = dev_get_drvdata(dev);
1799         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1800         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1801         int err;
1802
1803         if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1804                 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0);
1805
1806         if (imx_data->socdata->flags & ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME)
1807                 clk_set_rate(imx_data->clk_per, pltfm_host->clock);
1808
1809         err = clk_prepare_enable(imx_data->clk_ahb);
1810         if (err)
1811                 goto remove_pm_qos_request;
1812
1813         err = clk_prepare_enable(imx_data->clk_per);
1814         if (err)
1815                 goto disable_ahb_clk;
1816
1817         err = clk_prepare_enable(imx_data->clk_ipg);
1818         if (err)
1819                 goto disable_per_clk;
1820
1821         esdhc_pltfm_set_clock(host, imx_data->actual_clock);
1822
1823         err = sdhci_runtime_resume_host(host, 0);
1824         if (err)
1825                 goto disable_ipg_clk;
1826
1827         if (host->mmc->caps2 & MMC_CAP2_CQE)
1828                 err = cqhci_resume(host->mmc);
1829
1830         return err;
1831
1832 disable_ipg_clk:
1833         clk_disable_unprepare(imx_data->clk_ipg);
1834 disable_per_clk:
1835         clk_disable_unprepare(imx_data->clk_per);
1836 disable_ahb_clk:
1837         clk_disable_unprepare(imx_data->clk_ahb);
1838 remove_pm_qos_request:
1839         if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1840                 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1841         return err;
1842 }
1843 #endif
1844
1845 static const struct dev_pm_ops sdhci_esdhc_pmops = {
1846         SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume)
1847         SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend,
1848                                 sdhci_esdhc_runtime_resume, NULL)
1849 };
1850
1851 static struct platform_driver sdhci_esdhc_imx_driver = {
1852         .driver         = {
1853                 .name   = "sdhci-esdhc-imx",
1854                 .of_match_table = imx_esdhc_dt_ids,
1855                 .pm     = &sdhci_esdhc_pmops,
1856         },
1857         .id_table       = imx_esdhc_devtype,
1858         .probe          = sdhci_esdhc_imx_probe,
1859         .remove         = sdhci_esdhc_imx_remove,
1860 };
1861
1862 module_platform_driver(sdhci_esdhc_imx_driver);
1863
1864 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
1865 MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
1866 MODULE_LICENSE("GPL v2");