drivers/mmc/host/sdhci-esdhc-imx.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Freescale eSDHC i.MX controller driver for the platform bus.
   4  *
   5  * derived from the OF-version.
   6  *
   7  * Copyright (c) 2010 Pengutronix e.K.
   8  *   Author: Wolfram Sang <kernel@pengutronix.de>
   9  */
  10
  11 #include <linux/bitfield.h>
  12 #include <linux/io.h>
  13 #include <linux/iopoll.h>
  14 #include <linux/delay.h>
  15 #include <linux/err.h>
  16 #include <linux/clk.h>
  17 #include <linux/module.h>
  18 #include <linux/slab.h>
  19 #include <linux/pm_qos.h>
  20 #include <linux/mmc/host.h>
  21 #include <linux/mmc/mmc.h>
  22 #include <linux/mmc/sdio.h>
  23 #include <linux/mmc/slot-gpio.h>
  24 #include <linux/of.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/pinctrl/consumer.h>
  27 #include <linux/pm_runtime.h>
  28 #include "sdhci-cqhci.h"
  29 #include "sdhci-pltfm.h"
  30 #include "sdhci-esdhc.h"
  31 #include "cqhci.h"
  32
  33 #define ESDHC_SYS_CTRL_DTOCV_MASK       0x0f
  34 #define ESDHC_CTRL_D3CD                 0x08
  35 #define ESDHC_BURST_LEN_EN_INCR         (1 << 27)
  36 /* VENDOR SPEC register */
  37 #define ESDHC_VENDOR_SPEC               0xc0
  38 #define  ESDHC_VENDOR_SPEC_SDIO_QUIRK   (1 << 1)
  39 #define  ESDHC_VENDOR_SPEC_VSELECT      (1 << 1)
  40 #define  ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
  41 #define ESDHC_DEBUG_SEL_AND_STATUS_REG          0xc2
  42 #define ESDHC_DEBUG_SEL_REG                     0xc3
  43 #define ESDHC_DEBUG_SEL_MASK                    0xf
  44 #define ESDHC_DEBUG_SEL_CMD_STATE               1
  45 #define ESDHC_DEBUG_SEL_DATA_STATE              2
  46 #define ESDHC_DEBUG_SEL_TRANS_STATE             3
  47 #define ESDHC_DEBUG_SEL_DMA_STATE               4
  48 #define ESDHC_DEBUG_SEL_ADMA_STATE              5
  49 #define ESDHC_DEBUG_SEL_FIFO_STATE              6
  50 #define ESDHC_DEBUG_SEL_ASYNC_FIFO_STATE        7
  51 #define ESDHC_WTMK_LVL                  0x44
  52 #define  ESDHC_WTMK_DEFAULT_VAL         0x10401040
  53 #define  ESDHC_WTMK_LVL_RD_WML_MASK     0x000000FF
  54 #define  ESDHC_WTMK_LVL_RD_WML_SHIFT    0
  55 #define  ESDHC_WTMK_LVL_WR_WML_MASK     0x00FF0000
  56 #define  ESDHC_WTMK_LVL_WR_WML_SHIFT    16
  57 #define  ESDHC_WTMK_LVL_WML_VAL_DEF     64
  58 #define  ESDHC_WTMK_LVL_WML_VAL_MAX     128
  59 #define ESDHC_MIX_CTRL                  0x48
  60 #define  ESDHC_MIX_CTRL_DDREN           (1 << 3)
  61 #define  ESDHC_MIX_CTRL_AC23EN          (1 << 7)
  62 #define  ESDHC_MIX_CTRL_EXE_TUNE        (1 << 22)
  63 #define  ESDHC_MIX_CTRL_SMPCLK_SEL      (1 << 23)
  64 #define  ESDHC_MIX_CTRL_AUTO_TUNE_EN    (1 << 24)
  65 #define  ESDHC_MIX_CTRL_FBCLK_SEL       (1 << 25)
  66 #define  ESDHC_MIX_CTRL_HS400_EN        (1 << 26)
  67 #define  ESDHC_MIX_CTRL_HS400_ES_EN     (1 << 27)
  68 /* Bits 3 and 6 are not SDHCI standard definitions */
  69 #define  ESDHC_MIX_CTRL_SDHCI_MASK      0xb7
  70 /* Tuning bits */
  71 #define  ESDHC_MIX_CTRL_TUNING_MASK     0x03c00000
  72
  73 /* dll control register */
  74 #define ESDHC_DLL_CTRL                  0x60
  75 #define ESDHC_DLL_OVERRIDE_VAL_SHIFT    9
  76 #define ESDHC_DLL_OVERRIDE_EN_SHIFT     8
  77
  78 /* tune control register */
  79 #define ESDHC_TUNE_CTRL_STATUS          0x68
  80 #define  ESDHC_TUNE_CTRL_STEP           1
  81 #define  ESDHC_TUNE_CTRL_MIN            0
  82 #define  ESDHC_TUNE_CTRL_MAX            ((1 << 7) - 1)
  83
  84 /* strobe dll register */
  85 #define ESDHC_STROBE_DLL_CTRL           0x70
  86 #define ESDHC_STROBE_DLL_CTRL_ENABLE    (1 << 0)
  87 #define ESDHC_STROBE_DLL_CTRL_RESET     (1 << 1)
  88 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT    0x7
  89 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT      3
  90 #define ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT    (4 << 20)
  91
  92 #define ESDHC_STROBE_DLL_STATUS         0x74
  93 #define ESDHC_STROBE_DLL_STS_REF_LOCK   (1 << 1)
  94 #define ESDHC_STROBE_DLL_STS_SLV_LOCK   0x1
  95
  96 #define ESDHC_VEND_SPEC2                0xc8
  97 #define ESDHC_VEND_SPEC2_EN_BUSY_IRQ    (1 << 8)
  98 #define ESDHC_VEND_SPEC2_AUTO_TUNE_8BIT_EN      (1 << 4)
  99 #define ESDHC_VEND_SPEC2_AUTO_TUNE_4BIT_EN      (0 << 4)
 100 #define ESDHC_VEND_SPEC2_AUTO_TUNE_1BIT_EN      (2 << 4)
 101 #define ESDHC_VEND_SPEC2_AUTO_TUNE_CMD_EN       (1 << 6)
 102 #define ESDHC_VEND_SPEC2_AUTO_TUNE_MODE_MASK    (7 << 4)
 103
 104 #define ESDHC_TUNING_CTRL               0xcc
 105 #define ESDHC_STD_TUNING_EN             (1 << 24)
 106 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
 107 #define ESDHC_TUNING_START_TAP_DEFAULT  0x1
 108 #define ESDHC_TUNING_START_TAP_MASK     0x7f
 109 #define ESDHC_TUNING_CMD_CRC_CHECK_DISABLE      (1 << 7)
 110 #define ESDHC_TUNING_STEP_DEFAULT       0x1
 111 #define ESDHC_TUNING_STEP_MASK          0x00070000
 112 #define ESDHC_TUNING_STEP_SHIFT         16
 113
 114 /* pinctrl state */
 115 #define ESDHC_PINCTRL_STATE_100MHZ      "state_100mhz"
 116 #define ESDHC_PINCTRL_STATE_200MHZ      "state_200mhz"
 117
 118 /*
 119  * Our interpretation of the SDHCI_HOST_CONTROL register
 120  */
 121 #define ESDHC_CTRL_4BITBUS              (0x1 << 1)
 122 #define ESDHC_CTRL_8BITBUS              (0x2 << 1)
 123 #define ESDHC_CTRL_BUSWIDTH_MASK        (0x3 << 1)
 124 #define USDHC_GET_BUSWIDTH(c) (c & ESDHC_CTRL_BUSWIDTH_MASK)
 125
 126 /*
 127  * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC:
 128  * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
 129  * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
 130  * Define this macro DMA error INT for fsl eSDHC
 131  */
 132 #define ESDHC_INT_VENDOR_SPEC_DMA_ERR   (1 << 28)
 133
 134 /* the address offset of CQHCI */
 135 #define ESDHC_CQHCI_ADDR_OFFSET         0x100
 136
 137 /*
 138  * The CMDTYPE of the CMD register (offset 0xE) should be set to
 139  * "11" when the STOP CMD12 is issued on imx53 to abort one
 140  * open ended multi-blk IO. Otherwise the TC INT wouldn't
 141  * be generated.
 142  * In exact block transfer, the controller doesn't complete the
 143  * operations automatically as required at the end of the
 144  * transfer and remains on hold if the abort command is not sent.
 145  * As a result, the TC flag is not asserted and SW received timeout
 146  * exception. Bit1 of Vendor Spec register is used to fix it.
 147  */
 148 #define ESDHC_FLAG_MULTIBLK_NO_INT      BIT(1)
 149 /*
 150  * The flag tells that the ESDHC controller is an USDHC block that is
 151  * integrated on the i.MX6 series.
 152  */
 153 #define ESDHC_FLAG_USDHC                BIT(3)
 154 /* The IP supports manual tuning process */
 155 #define ESDHC_FLAG_MAN_TUNING           BIT(4)
 156 /* The IP supports standard tuning process */
 157 #define ESDHC_FLAG_STD_TUNING           BIT(5)
 158 /* The IP has SDHCI_CAPABILITIES_1 register */
 159 #define ESDHC_FLAG_HAVE_CAP1            BIT(6)
 160 /*
 161  * The IP has erratum ERR004536
 162  * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
 163  * when reading data from the card
 164  * This flag is also set for i.MX25 and i.MX35 in order to get
 165  * SDHCI_QUIRK_BROKEN_ADMA, but for different reasons (ADMA capability bits).
 166  */
 167 #define ESDHC_FLAG_ERR004536            BIT(7)
 168 /* The IP supports HS200 mode */
 169 #define ESDHC_FLAG_HS200                BIT(8)
 170 /* The IP supports HS400 mode */
 171 #define ESDHC_FLAG_HS400                BIT(9)
 172 /*
 173  * The IP has errata ERR010450
 174  * uSDHC: At 1.8V due to the I/O timing limit, for SDR mode, SD card
 175  * clock can't exceed 150MHz, for DDR mode, SD card clock can't exceed 45MHz.
 176  */
 177 #define ESDHC_FLAG_ERR010450            BIT(10)
 178 /* The IP supports HS400ES mode */
 179 #define ESDHC_FLAG_HS400_ES             BIT(11)
 180 /* The IP has Host Controller Interface for Command Queuing */
 181 #define ESDHC_FLAG_CQHCI                BIT(12)
 182 /* need request pmqos during low power */
 183 #define ESDHC_FLAG_PMQOS                BIT(13)
 184 /* The IP state got lost in low power mode */
 185 #define ESDHC_FLAG_STATE_LOST_IN_LPMODE         BIT(14)
 186 /* The IP lost clock rate in PM_RUNTIME */
 187 #define ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME  BIT(15)
 188 /*
 189  * The IP do not support the ACMD23 feature completely when use ADMA mode.
 190  * In ADMA mode, it only use the 16 bit block count of the register 0x4
 191  * (BLOCK_ATT) as the CMD23's argument for ACMD23 mode, which means it will
 192  * ignore the upper 16 bit of the CMD23's argument. This will block the reliable
 193  * write operation in RPMB, because RPMB reliable write need to set the bit31
 194  * of the CMD23's argument.
 195  * imx6qpdl/imx6sx/imx6sl/imx7d has this limitation only for ADMA mode, SDMA
 196  * do not has this limitation. so when these SoC use ADMA mode, it need to
 197  * disable the ACMD23 feature.
 198  */
 199 #define ESDHC_FLAG_BROKEN_AUTO_CMD23    BIT(16)
 200
 201 /* ERR004536 is not applicable for the IP  */
 202 #define ESDHC_FLAG_SKIP_ERR004536       BIT(17)
 203
 204 enum wp_types {
 205         ESDHC_WP_NONE,          /* no WP, neither controller nor gpio */
 206         ESDHC_WP_CONTROLLER,    /* mmc controller internal WP */
 207         ESDHC_WP_GPIO,          /* external gpio pin for WP */
 208 };
 209
 210 enum cd_types {
 211         ESDHC_CD_NONE,          /* no CD, neither controller nor gpio */
 212         ESDHC_CD_CONTROLLER,    /* mmc controller internal CD */
 213         ESDHC_CD_GPIO,          /* external gpio pin for CD */
 214         ESDHC_CD_PERMANENT,     /* no CD, card permanently wired to host */
 215 };
 216
 217 /*
 218  * struct esdhc_platform_data - platform data for esdhc on i.MX
 219  *
 220  * ESDHC_WP(CD)_CONTROLLER type is not available on i.MX25/35.
 221  *
 222  * @wp_type:    type of write_protect method (see wp_types enum above)
 223  * @cd_type:    type of card_detect method (see cd_types enum above)
 224  */
 225
 226 struct esdhc_platform_data {
 227         enum wp_types wp_type;
 228         enum cd_types cd_type;
 229         int max_bus_width;
 230         unsigned int delay_line;
 231         unsigned int tuning_step;       /* The delay cell steps in tuning procedure */
 232         unsigned int tuning_start_tap;  /* The start delay cell point in tuning procedure */
 233         unsigned int strobe_dll_delay_target;   /* The delay cell for strobe pad (read clock) */
 234 };
 235
 236 struct esdhc_soc_data {
 237         u32 flags;
 238 };
 239
 240 static const struct esdhc_soc_data esdhc_imx25_data = {
 241         .flags = ESDHC_FLAG_ERR004536,
 242 };
 243
 244 static const struct esdhc_soc_data esdhc_imx35_data = {
 245         .flags = ESDHC_FLAG_ERR004536,
 246 };
 247
 248 static const struct esdhc_soc_data esdhc_imx51_data = {
 249         .flags = 0,
 250 };
 251
 252 static const struct esdhc_soc_data esdhc_imx53_data = {
 253         .flags = ESDHC_FLAG_MULTIBLK_NO_INT,
 254 };
 255
 256 static const struct esdhc_soc_data usdhc_imx6q_data = {
 257         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING
 258                         | ESDHC_FLAG_BROKEN_AUTO_CMD23,
 259 };
 260
 261 static const struct esdhc_soc_data usdhc_imx6sl_data = {
 262         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 263                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536
 264                         | ESDHC_FLAG_HS200
 265                         | ESDHC_FLAG_BROKEN_AUTO_CMD23,
 266 };
 267
 268 static const struct esdhc_soc_data usdhc_imx6sll_data = {
 269         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 270                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 271                         | ESDHC_FLAG_HS400
 272                         | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
 273 };
 274
 275 static const struct esdhc_soc_data usdhc_imx6sx_data = {
 276         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 277                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 278                         | ESDHC_FLAG_STATE_LOST_IN_LPMODE
 279                         | ESDHC_FLAG_BROKEN_AUTO_CMD23,
 280 };
 281
 282 static const struct esdhc_soc_data usdhc_imx6ull_data = {
 283         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 284                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 285                         | ESDHC_FLAG_ERR010450
 286                         | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
 287 };
 288
 289 static const struct esdhc_soc_data usdhc_imx7d_data = {
 290         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 291                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 292                         | ESDHC_FLAG_HS400
 293                         | ESDHC_FLAG_STATE_LOST_IN_LPMODE
 294                         | ESDHC_FLAG_BROKEN_AUTO_CMD23,
 295 };
 296
 297 static struct esdhc_soc_data usdhc_s32g2_data = {
 298         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING
 299                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 300                         | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
 301                         | ESDHC_FLAG_SKIP_ERR004536,
 302 };
 303
 304 static struct esdhc_soc_data usdhc_imx7ulp_data = {
 305         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 306                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 307                         | ESDHC_FLAG_PMQOS | ESDHC_FLAG_HS400
 308                         | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
 309 };
 310 static struct esdhc_soc_data usdhc_imxrt1050_data = {
 311         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 312                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200,
 313 };
 314
 315 static struct esdhc_soc_data usdhc_imx8qxp_data = {
 316         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 317                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 318                         | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
 319                         | ESDHC_FLAG_STATE_LOST_IN_LPMODE
 320                         | ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME,
 321 };
 322
 323 static struct esdhc_soc_data usdhc_imx8mm_data = {
 324         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 325                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
 326                         | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
 327                         | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
 328 };
 329
 330 struct pltfm_imx_data {
 331         u32 scratchpad;
 332         struct pinctrl *pinctrl;
 333         struct pinctrl_state *pins_100mhz;
 334         struct pinctrl_state *pins_200mhz;
 335         const struct esdhc_soc_data *socdata;
 336         struct esdhc_platform_data boarddata;
 337         struct clk *clk_ipg;
 338         struct clk *clk_ahb;
 339         struct clk *clk_per;
 340         unsigned int actual_clock;
 341
 342         /*
 343          * USDHC has one limition, require the SDIO device a different
 344          * register setting. Driver has to recognize card type during
 345          * the card init, but at this stage, mmc_host->card is not
 346          * available. So involve this field to save the card type
 347          * during card init through usdhc_init_card().
 348          */
 349         unsigned int init_card_type;
 350
 351         enum {
 352                 NO_CMD_PENDING,      /* no multiblock command pending */
 353                 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
 354                 WAIT_FOR_INT,        /* sent CMD12, waiting for response INT */
 355         } multiblock_status;
 356         u32 is_ddr;
 357         struct pm_qos_request pm_qos_req;
 358 };
 359
 360 static const struct of_device_id imx_esdhc_dt_ids[] = {
 361         { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
 362         { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
 363         { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
 364         { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
 365         { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
 366         { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
 367         { .compatible = "fsl,imx6sll-usdhc", .data = &usdhc_imx6sll_data, },
 368         { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
 369         { .compatible = "fsl,imx6ull-usdhc", .data = &usdhc_imx6ull_data, },
 370         { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
 371         { .compatible = "fsl,imx7ulp-usdhc", .data = &usdhc_imx7ulp_data, },
 372         { .compatible = "fsl,imx8qxp-usdhc", .data = &usdhc_imx8qxp_data, },
 373         { .compatible = "fsl,imx8mm-usdhc", .data = &usdhc_imx8mm_data, },
 374         { .compatible = "fsl,imxrt1050-usdhc", .data = &usdhc_imxrt1050_data, },
 375         { .compatible = "nxp,s32g2-usdhc", .data = &usdhc_s32g2_data, },
 376         { /* sentinel */ }
 377 };
 378 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
 379
 380 static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
 381 {
 382         return data->socdata == &esdhc_imx25_data;
 383 }
 384
 385 static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
 386 {
 387         return data->socdata == &esdhc_imx53_data;
 388 }
 389
 390 static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
 391 {
 392         return !!(data->socdata->flags & ESDHC_FLAG_USDHC);
 393 }
 394
 395 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
 396 {
 397         void __iomem *base = host->ioaddr + (reg & ~0x3);
 398         u32 shift = (reg & 0x3) * 8;
 399
 400         writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
 401 }
 402
 403 #define DRIVER_NAME "sdhci-esdhc-imx"
 404 #define ESDHC_IMX_DUMP(f, x...) \
 405         pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
 406 static void esdhc_dump_debug_regs(struct sdhci_host *host)
 407 {
 408         int i;
 409         char *debug_status[7] = {
 410                                  "cmd debug status",
 411                                  "data debug status",
 412                                  "trans debug status",
 413                                  "dma debug status",
 414                                  "adma debug status",
 415                                  "fifo debug status",
 416                                  "async fifo debug status"
 417         };
 418
 419         ESDHC_IMX_DUMP("========= ESDHC IMX DEBUG STATUS DUMP =========\n");
 420         for (i = 0; i < 7; i++) {
 421                 esdhc_clrset_le(host, ESDHC_DEBUG_SEL_MASK,
 422                         ESDHC_DEBUG_SEL_CMD_STATE + i, ESDHC_DEBUG_SEL_REG);
 423                 ESDHC_IMX_DUMP("%s:  0x%04x\n", debug_status[i],
 424                         readw(host->ioaddr + ESDHC_DEBUG_SEL_AND_STATUS_REG));
 425         }
 426
 427         esdhc_clrset_le(host, ESDHC_DEBUG_SEL_MASK, 0, ESDHC_DEBUG_SEL_REG);
 428
 429 }
 430
 431 static inline void esdhc_wait_for_card_clock_gate_off(struct sdhci_host *host)
 432 {
 433         u32 present_state;
 434         int ret;
 435
 436         ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, present_state,
 437                                 (present_state & ESDHC_CLOCK_GATE_OFF), 2, 100);
 438         if (ret == -ETIMEDOUT)
 439                 dev_warn(mmc_dev(host->mmc), "%s: card clock still not gate off in 100us!.\n", __func__);
 440 }
 441
 442 /* Enable the auto tuning circuit to check the CMD line and BUS line */
 443 static inline void usdhc_auto_tuning_mode_sel_and_en(struct sdhci_host *host)
 444 {
 445         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 446         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 447         u32 buswidth, auto_tune_buswidth;
 448         u32 reg;
 449
 450         buswidth = USDHC_GET_BUSWIDTH(readl(host->ioaddr + SDHCI_HOST_CONTROL));
 451
 452         switch (buswidth) {
 453         case ESDHC_CTRL_8BITBUS:
 454                 auto_tune_buswidth = ESDHC_VEND_SPEC2_AUTO_TUNE_8BIT_EN;
 455                 break;
 456         case ESDHC_CTRL_4BITBUS:
 457                 auto_tune_buswidth = ESDHC_VEND_SPEC2_AUTO_TUNE_4BIT_EN;
 458                 break;
 459         default:        /* 1BITBUS */
 460                 auto_tune_buswidth = ESDHC_VEND_SPEC2_AUTO_TUNE_1BIT_EN;
 461                 break;
 462         }
 463
 464         /*
 465          * For USDHC, auto tuning circuit can not handle the async sdio
 466          * device interrupt correctly. When sdio device use 4 data lines,
 467          * async sdio interrupt will use the shared DAT[1], if enable auto
 468          * tuning circuit check these 4 data lines, include the DAT[1],
 469          * this circuit will detect this interrupt, take this as a data on
 470          * DAT[1], and adjust the delay cell wrongly.
 471          * This is the hardware design limitation, to avoid this, for sdio
 472          * device, config the auto tuning circuit only check DAT[0] and CMD
 473          * line.
 474          */
 475         if (imx_data->init_card_type == MMC_TYPE_SDIO)
 476                 auto_tune_buswidth = ESDHC_VEND_SPEC2_AUTO_TUNE_1BIT_EN;
 477
 478         esdhc_clrset_le(host, ESDHC_VEND_SPEC2_AUTO_TUNE_MODE_MASK,
 479                         auto_tune_buswidth | ESDHC_VEND_SPEC2_AUTO_TUNE_CMD_EN,
 480                         ESDHC_VEND_SPEC2);
 481
 482         reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
 483         reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
 484         writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
 485 }
 486
 487 static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
 488 {
 489         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 490         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 491         u32 val = readl(host->ioaddr + reg);
 492
 493         if (unlikely(reg == SDHCI_PRESENT_STATE)) {
 494                 u32 fsl_prss = val;
 495                 /* save the least 20 bits */
 496                 val = fsl_prss & 0x000FFFFF;
 497                 /* move dat[0-3] bits */
 498                 val |= (fsl_prss & 0x0F000000) >> 4;
 499                 /* move cmd line bit */
 500                 val |= (fsl_prss & 0x00800000) << 1;
 501         }
 502
 503         if (unlikely(reg == SDHCI_CAPABILITIES)) {
 504                 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */
 505                 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
 506                         val &= 0xffff0000;
 507
 508                 /* In FSL esdhc IC module, only bit20 is used to indicate the
 509                  * ADMA2 capability of esdhc, but this bit is messed up on
 510                  * some SOCs (e.g. on MX25, MX35 this bit is set, but they
 511                  * don't actually support ADMA2). So set the BROKEN_ADMA
 512                  * quirk on MX25/35 platforms.
 513                  */
 514
 515                 if (val & SDHCI_CAN_DO_ADMA1) {
 516                         val &= ~SDHCI_CAN_DO_ADMA1;
 517                         val |= SDHCI_CAN_DO_ADMA2;
 518                 }
 519         }
 520
 521         if (unlikely(reg == SDHCI_CAPABILITIES_1)) {
 522                 if (esdhc_is_usdhc(imx_data)) {
 523                         if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
 524                                 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;
 525                         else
 526                                 /* imx6q/dl does not have cap_1 register, fake one */
 527                                 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
 528                                         | SDHCI_SUPPORT_SDR50
 529                                         | SDHCI_USE_SDR50_TUNING
 530                                         | FIELD_PREP(SDHCI_RETUNING_MODE_MASK,
 531                                                      SDHCI_TUNING_MODE_3);
 532
 533                         /*
 534                          * Do not advertise faster UHS modes if there are no
 535                          * pinctrl states for 100MHz/200MHz.
 536                          */
 537                         if (IS_ERR_OR_NULL(imx_data->pins_100mhz))
 538                                 val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50);
 539                         if (IS_ERR_OR_NULL(imx_data->pins_200mhz))
 540                                 val &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);
 541                 }
 542         }
 543
 544         if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
 545                 val = 0;
 546                 val |= FIELD_PREP(SDHCI_MAX_CURRENT_330_MASK, 0xFF);
 547                 val |= FIELD_PREP(SDHCI_MAX_CURRENT_300_MASK, 0xFF);
 548                 val |= FIELD_PREP(SDHCI_MAX_CURRENT_180_MASK, 0xFF);
 549         }
 550
 551         if (unlikely(reg == SDHCI_INT_STATUS)) {
 552                 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
 553                         val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
 554                         val |= SDHCI_INT_ADMA_ERROR;
 555                 }
 556
 557                 /*
 558                  * mask off the interrupt we get in response to the manually
 559                  * sent CMD12
 560                  */
 561                 if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
 562                     ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
 563                         val &= ~SDHCI_INT_RESPONSE;
 564                         writel(SDHCI_INT_RESPONSE, host->ioaddr +
 565                                                    SDHCI_INT_STATUS);
 566                         imx_data->multiblock_status = NO_CMD_PENDING;
 567                 }
 568         }
 569
 570         return val;
 571 }
 572
 573 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
 574 {
 575         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 576         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 577         u32 data;
 578
 579         if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE ||
 580                         reg == SDHCI_INT_STATUS)) {
 581                 if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) {
 582                         /*
 583                          * Clear and then set D3CD bit to avoid missing the
 584                          * card interrupt. This is an eSDHC controller problem
 585                          * so we need to apply the following workaround: clear
 586                          * and set D3CD bit will make eSDHC re-sample the card
 587                          * interrupt. In case a card interrupt was lost,
 588                          * re-sample it by the following steps.
 589                          */
 590                         data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
 591                         data &= ~ESDHC_CTRL_D3CD;
 592                         writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
 593                         data |= ESDHC_CTRL_D3CD;
 594                         writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
 595                 }
 596
 597                 if (val & SDHCI_INT_ADMA_ERROR) {
 598                         val &= ~SDHCI_INT_ADMA_ERROR;
 599                         val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
 600                 }
 601         }
 602
 603         if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
 604                                 && (reg == SDHCI_INT_STATUS)
 605                                 && (val & SDHCI_INT_DATA_END))) {
 606                         u32 v;
 607                         v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 608                         v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
 609                         writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
 610
 611                         if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
 612                         {
 613                                 /* send a manual CMD12 with RESPTYP=none */
 614                                 data = MMC_STOP_TRANSMISSION << 24 |
 615                                        SDHCI_CMD_ABORTCMD << 16;
 616                                 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
 617                                 imx_data->multiblock_status = WAIT_FOR_INT;
 618                         }
 619         }
 620
 621         writel(val, host->ioaddr + reg);
 622 }
 623
 624 static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
 625 {
 626         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 627         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 628         u16 ret = 0;
 629         u32 val;
 630
 631         if (unlikely(reg == SDHCI_HOST_VERSION)) {
 632                 reg ^= 2;
 633                 if (esdhc_is_usdhc(imx_data)) {
 634                         /*
 635                          * The usdhc register returns a wrong host version.
 636                          * Correct it here.
 637                          */
 638                         return SDHCI_SPEC_300;
 639                 }
 640         }
 641
 642         if (unlikely(reg == SDHCI_HOST_CONTROL2)) {
 643                 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 644                 if (val & ESDHC_VENDOR_SPEC_VSELECT)
 645                         ret |= SDHCI_CTRL_VDD_180;
 646
 647                 if (esdhc_is_usdhc(imx_data)) {
 648                         if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
 649                                 val = readl(host->ioaddr + ESDHC_MIX_CTRL);
 650                         else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
 651                                 /* the std tuning bits is in ACMD12_ERR for imx6sl */
 652                                 val = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
 653                 }
 654
 655                 if (val & ESDHC_MIX_CTRL_EXE_TUNE)
 656                         ret |= SDHCI_CTRL_EXEC_TUNING;
 657                 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
 658                         ret |= SDHCI_CTRL_TUNED_CLK;
 659
 660                 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
 661
 662                 return ret;
 663         }
 664
 665         if (unlikely(reg == SDHCI_TRANSFER_MODE)) {
 666                 if (esdhc_is_usdhc(imx_data)) {
 667                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 668                         ret = m & ESDHC_MIX_CTRL_SDHCI_MASK;
 669                         /* Swap AC23 bit */
 670                         if (m & ESDHC_MIX_CTRL_AC23EN) {
 671                                 ret &= ~ESDHC_MIX_CTRL_AC23EN;
 672                                 ret |= SDHCI_TRNS_AUTO_CMD23;
 673                         }
 674                 } else {
 675                         ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
 676                 }
 677
 678                 return ret;
 679         }
 680
 681         return readw(host->ioaddr + reg);
 682 }
 683
 684 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
 685 {
 686         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 687         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 688         u32 new_val = 0;
 689
 690         switch (reg) {
 691         case SDHCI_CLOCK_CONTROL:
 692                 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 693                 if (val & SDHCI_CLOCK_CARD_EN)
 694                         new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
 695                 else
 696                         new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
 697                 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
 698                 if (!(new_val & ESDHC_VENDOR_SPEC_FRC_SDCLK_ON))
 699                         esdhc_wait_for_card_clock_gate_off(host);
 700                 return;
 701         case SDHCI_HOST_CONTROL2:
 702                 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 703                 if (val & SDHCI_CTRL_VDD_180)
 704                         new_val |= ESDHC_VENDOR_SPEC_VSELECT;
 705                 else
 706                         new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
 707                 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
 708                 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
 709                         u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
 710                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 711                         if (val & SDHCI_CTRL_TUNED_CLK) {
 712                                 v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
 713                         } else {
 714                                 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
 715                                 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
 716                         }
 717
 718                         if (val & SDHCI_CTRL_EXEC_TUNING) {
 719                                 v |= ESDHC_MIX_CTRL_EXE_TUNE;
 720                                 m |= ESDHC_MIX_CTRL_FBCLK_SEL;
 721                         } else {
 722                                 v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
 723                         }
 724
 725                         writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
 726                         writel(m, host->ioaddr + ESDHC_MIX_CTRL);
 727                 }
 728                 return;
 729         case SDHCI_TRANSFER_MODE:
 730                 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
 731                                 && (host->cmd->opcode == SD_IO_RW_EXTENDED)
 732                                 && (host->cmd->data->blocks > 1)
 733                                 && (host->cmd->data->flags & MMC_DATA_READ)) {
 734                         u32 v;
 735                         v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 736                         v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
 737                         writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
 738                 }
 739
 740                 if (esdhc_is_usdhc(imx_data)) {
 741                         u32 wml;
 742                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 743                         /* Swap AC23 bit */
 744                         if (val & SDHCI_TRNS_AUTO_CMD23) {
 745                                 val &= ~SDHCI_TRNS_AUTO_CMD23;
 746                                 val |= ESDHC_MIX_CTRL_AC23EN;
 747                         }
 748                         m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
 749                         writel(m, host->ioaddr + ESDHC_MIX_CTRL);
 750
 751                         /* Set watermark levels for PIO access to maximum value
 752                          * (128 words) to accommodate full 512 bytes buffer.
 753                          * For DMA access restore the levels to default value.
 754                          */
 755                         m = readl(host->ioaddr + ESDHC_WTMK_LVL);
 756                         if (val & SDHCI_TRNS_DMA) {
 757                                 wml = ESDHC_WTMK_LVL_WML_VAL_DEF;
 758                         } else {
 759                                 u8 ctrl;
 760                                 wml = ESDHC_WTMK_LVL_WML_VAL_MAX;
 761
 762                                 /*
 763                                  * Since already disable DMA mode, so also need
 764                                  * to clear the DMASEL. Otherwise, for standard
 765                                  * tuning, when send tuning command, usdhc will
 766                                  * still prefetch the ADMA script from wrong
 767                                  * DMA address, then we will see IOMMU report
 768                                  * some error which show lack of TLB mapping.
 769                                  */
 770                                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 771                                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
 772                                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 773                         }
 774                         m &= ~(ESDHC_WTMK_LVL_RD_WML_MASK |
 775                                ESDHC_WTMK_LVL_WR_WML_MASK);
 776                         m |= (wml << ESDHC_WTMK_LVL_RD_WML_SHIFT) |
 777                              (wml << ESDHC_WTMK_LVL_WR_WML_SHIFT);
 778                         writel(m, host->ioaddr + ESDHC_WTMK_LVL);
 779                 } else {
 780                         /*
 781                          * Postpone this write, we must do it together with a
 782                          * command write that is down below.
 783                          */
 784                         imx_data->scratchpad = val;
 785                 }
 786                 return;
 787         case SDHCI_COMMAND:
 788                 if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
 789                         val |= SDHCI_CMD_ABORTCMD;
 790
 791                 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
 792                     (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
 793                         imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
 794
 795                 if (esdhc_is_usdhc(imx_data))
 796                         writel(val << 16,
 797                                host->ioaddr + SDHCI_TRANSFER_MODE);
 798                 else
 799                         writel(val << 16 | imx_data->scratchpad,
 800                                host->ioaddr + SDHCI_TRANSFER_MODE);
 801                 return;
 802         case SDHCI_BLOCK_SIZE:
 803                 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
 804                 break;
 805         }
 806         esdhc_clrset_le(host, 0xffff, val, reg);
 807 }
 808
 809 static u8 esdhc_readb_le(struct sdhci_host *host, int reg)
 810 {
 811         u8 ret;
 812         u32 val;
 813
 814         switch (reg) {
 815         case SDHCI_HOST_CONTROL:
 816                 val = readl(host->ioaddr + reg);
 817
 818                 ret = val & SDHCI_CTRL_LED;
 819                 ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK;
 820                 ret |= (val & ESDHC_CTRL_4BITBUS);
 821                 ret |= (val & ESDHC_CTRL_8BITBUS) << 3;
 822                 return ret;
 823         }
 824
 825         return readb(host->ioaddr + reg);
 826 }
 827
 828 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
 829 {
 830         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 831         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 832         u32 new_val = 0;
 833         u32 mask;
 834
 835         switch (reg) {
 836         case SDHCI_POWER_CONTROL:
 837                 /*
 838                  * FSL put some DMA bits here
 839                  * If your board has a regulator, code should be here
 840                  */
 841                 return;
 842         case SDHCI_HOST_CONTROL:
 843                 /* FSL messed up here, so we need to manually compose it. */
 844                 new_val = val & SDHCI_CTRL_LED;
 845                 /* ensure the endianness */
 846                 new_val |= ESDHC_HOST_CONTROL_LE;
 847                 /* bits 8&9 are reserved on mx25 */
 848                 if (!is_imx25_esdhc(imx_data)) {
 849                         /* DMA mode bits are shifted */
 850                         new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
 851                 }
 852
 853                 /*
 854                  * Do not touch buswidth bits here. This is done in
 855                  * esdhc_pltfm_bus_width.
 856                  * Do not touch the D3CD bit either which is used for the
 857                  * SDIO interrupt erratum workaround.
 858                  */
 859                 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
 860
 861                 esdhc_clrset_le(host, mask, new_val, reg);
 862                 return;
 863         case SDHCI_SOFTWARE_RESET:
 864                 if (val & SDHCI_RESET_DATA)
 865                         new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL);
 866                 break;
 867         }
 868         esdhc_clrset_le(host, 0xff, val, reg);
 869
 870         if (reg == SDHCI_SOFTWARE_RESET) {
 871                 if (val & SDHCI_RESET_ALL) {
 872                         /*
 873                          * The esdhc has a design violation to SDHC spec which
 874                          * tells that software reset should not affect card
 875                          * detection circuit. But esdhc clears its SYSCTL
 876                          * register bits [0..2] during the software reset. This
 877                          * will stop those clocks that card detection circuit
 878                          * relies on. To work around it, we turn the clocks on
 879                          * back to keep card detection circuit functional.
 880                          */
 881                         esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
 882                         /*
 883                          * The reset on usdhc fails to clear MIX_CTRL register.
 884                          * Do it manually here.
 885                          */
 886                         if (esdhc_is_usdhc(imx_data)) {
 887                                 /*
 888                                  * the tuning bits should be kept during reset
 889                                  */
 890                                 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
 891                                 writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,
 892                                                 host->ioaddr + ESDHC_MIX_CTRL);
 893                                 imx_data->is_ddr = 0;
 894                         }
 895                 } else if (val & SDHCI_RESET_DATA) {
 896                         /*
 897                          * The eSDHC DAT line software reset clears at least the
 898                          * data transfer width on i.MX25, so make sure that the
 899                          * Host Control register is unaffected.
 900                          */
 901                         esdhc_clrset_le(host, 0xff, new_val,
 902                                         SDHCI_HOST_CONTROL);
 903                 }
 904         }
 905 }
 906
 907 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
 908 {
 909         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 910
 911         return pltfm_host->clock;
 912 }
 913
 914 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
 915 {
 916         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 917
 918         return pltfm_host->clock / 256 / 16;
 919 }
 920
 921 static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
 922                                          unsigned int clock)
 923 {
 924         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 925         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
 926         unsigned int host_clock = pltfm_host->clock;
 927         int ddr_pre_div = imx_data->is_ddr ? 2 : 1;
 928         int pre_div = 1;
 929         int div = 1;
 930         int ret;
 931         u32 temp, val;
 932
 933         if (esdhc_is_usdhc(imx_data)) {
 934                 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 935                 writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
 936                         host->ioaddr + ESDHC_VENDOR_SPEC);
 937                 esdhc_wait_for_card_clock_gate_off(host);
 938         }
 939
 940         if (clock == 0) {
 941                 host->mmc->actual_clock = 0;
 942                 return;
 943         }
 944
 945         /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
 946         if (is_imx53_esdhc(imx_data)) {
 947                 /*
 948                  * According to the i.MX53 reference manual, if DLLCTRL[10] can
 949                  * be set, then the controller is eSDHCv3, else it is eSDHCv2.
 950                  */
 951                 val = readl(host->ioaddr + ESDHC_DLL_CTRL);
 952                 writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL);
 953                 temp = readl(host->ioaddr + ESDHC_DLL_CTRL);
 954                 writel(val, host->ioaddr + ESDHC_DLL_CTRL);
 955                 if (temp & BIT(10))
 956                         pre_div = 2;
 957         }
 958
 959         temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
 960         temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
 961                 | ESDHC_CLOCK_MASK);
 962         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
 963
 964         if ((imx_data->socdata->flags & ESDHC_FLAG_ERR010450) &&
 965             (!(host->quirks2 & SDHCI_QUIRK2_NO_1_8_V))) {
 966                 unsigned int max_clock;
 967
 968                 max_clock = imx_data->is_ddr ? 45000000 : 150000000;
 969
 970                 clock = min(clock, max_clock);
 971         }
 972
 973         while (host_clock / (16 * pre_div * ddr_pre_div) > clock &&
 974                         pre_div < 256)
 975                 pre_div *= 2;
 976
 977         while (host_clock / (div * pre_div * ddr_pre_div) > clock && div < 16)
 978                 div++;
 979
 980         host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div);
 981         dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
 982                 clock, host->mmc->actual_clock);
 983
 984         pre_div >>= 1;
 985         div--;
 986
 987         temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
 988         temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
 989                 | (div << ESDHC_DIVIDER_SHIFT)
 990                 | (pre_div << ESDHC_PREDIV_SHIFT));
 991         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
 992
 993         /* need to wait the bit 3 of the PRSSTAT to be set, make sure card clock is stable */
 994         ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, temp,
 995                                 (temp & ESDHC_CLOCK_STABLE), 2, 100);
 996         if (ret == -ETIMEDOUT)
 997                 dev_warn(mmc_dev(host->mmc), "card clock still not stable in 100us!.\n");
 998
 999         if (esdhc_is_usdhc(imx_data)) {
1000                 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
1001                 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
1002                         host->ioaddr + ESDHC_VENDOR_SPEC);
1003         }
1004
1005 }
1006
1007 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
1008 {
1009         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1010         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1011         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1012
1013         switch (boarddata->wp_type) {
1014         case ESDHC_WP_GPIO:
1015                 return mmc_gpio_get_ro(host->mmc);
1016         case ESDHC_WP_CONTROLLER:
1017                 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
1018                                SDHCI_WRITE_PROTECT);
1019         case ESDHC_WP_NONE:
1020                 break;
1021         }
1022
1023         return -ENOSYS;
1024 }
1025
1026 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
1027 {
1028         u32 ctrl;
1029
1030         switch (width) {
1031         case MMC_BUS_WIDTH_8:
1032                 ctrl = ESDHC_CTRL_8BITBUS;
1033                 break;
1034         case MMC_BUS_WIDTH_4:
1035                 ctrl = ESDHC_CTRL_4BITBUS;
1036                 break;
1037         default:
1038                 ctrl = 0;
1039                 break;
1040         }
1041
1042         esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
1043                         SDHCI_HOST_CONTROL);
1044 }
1045
1046 static void esdhc_reset_tuning(struct sdhci_host *host)
1047 {
1048         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1049         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1050         u32 ctrl;
1051         int ret;
1052
1053         /* Reset the tuning circuit */
1054         if (esdhc_is_usdhc(imx_data)) {
1055                 ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL);
1056                 ctrl &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
1057                 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
1058                         ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
1059                         ctrl &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
1060                         writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL);
1061                         writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1062                 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
1063                         writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL);
1064                         ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1065                         ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
1066                         ctrl &= ~ESDHC_MIX_CTRL_EXE_TUNE;
1067                         writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1068                         /* Make sure ESDHC_MIX_CTRL_EXE_TUNE cleared */
1069                         ret = readl_poll_timeout(host->ioaddr + SDHCI_AUTO_CMD_STATUS,
1070                                 ctrl, !(ctrl & ESDHC_MIX_CTRL_EXE_TUNE), 1, 50);
1071                         if (ret == -ETIMEDOUT)
1072                                 dev_warn(mmc_dev(host->mmc),
1073                                  "Warning! clear execute tuning bit failed\n");
1074                         /*
1075                          * SDHCI_INT_DATA_AVAIL is W1C bit, set this bit will clear the
1076                          * usdhc IP internal logic flag execute_tuning_with_clr_buf, which
1077                          * will finally make sure the normal data transfer logic correct.
1078                          */
1079                         ctrl = readl(host->ioaddr + SDHCI_INT_STATUS);
1080                         ctrl |= SDHCI_INT_DATA_AVAIL;
1081                         writel(ctrl, host->ioaddr + SDHCI_INT_STATUS);
1082                 }
1083         }
1084 }
1085
1086 static void usdhc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1087 {
1088         struct sdhci_host *host = mmc_priv(mmc);
1089         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1090         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1091
1092         imx_data->init_card_type = card->type;
1093 }
1094
1095 static int usdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1096 {
1097         struct sdhci_host *host = mmc_priv(mmc);
1098         int err;
1099
1100         /*
1101          * i.MX uSDHC internally already uses a fixed optimized timing for
1102          * DDR50, normally does not require tuning for DDR50 mode.
1103          */
1104         if (host->timing == MMC_TIMING_UHS_DDR50)
1105                 return 0;
1106
1107         /*
1108          * Reset tuning circuit logic. If not, the previous tuning result
1109          * will impact current tuning, make current tuning can't set the
1110          * correct delay cell.
1111          */
1112         esdhc_reset_tuning(host);
1113         err = sdhci_execute_tuning(mmc, opcode);
1114         /* If tuning done, enable auto tuning */
1115         if (!err && !host->tuning_err)
1116                 usdhc_auto_tuning_mode_sel_and_en(host);
1117
1118         return err;
1119 }
1120
1121 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
1122 {
1123         u32 reg;
1124         u8 sw_rst;
1125         int ret;
1126
1127         /* FIXME: delay a bit for card to be ready for next tuning due to errors */
1128         mdelay(1);
1129
1130         /* IC suggest to reset USDHC before every tuning command */
1131         esdhc_clrset_le(host, 0xff, SDHCI_RESET_ALL, SDHCI_SOFTWARE_RESET);
1132         ret = readb_poll_timeout(host->ioaddr + SDHCI_SOFTWARE_RESET, sw_rst,
1133                                 !(sw_rst & SDHCI_RESET_ALL), 10, 100);
1134         if (ret == -ETIMEDOUT)
1135                 dev_warn(mmc_dev(host->mmc),
1136                 "warning! RESET_ALL never complete before sending tuning command\n");
1137
1138         reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
1139         reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
1140                         ESDHC_MIX_CTRL_FBCLK_SEL;
1141         writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
1142         writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1143         dev_dbg(mmc_dev(host->mmc),
1144                 "tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
1145                         val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
1146 }
1147
1148 static void esdhc_post_tuning(struct sdhci_host *host)
1149 {
1150         u32 reg;
1151
1152         reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
1153         reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
1154         writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
1155 }
1156
1157 static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
1158 {
1159         int min, max, avg, ret;
1160
1161         /* find the mininum delay first which can pass tuning */
1162         min = ESDHC_TUNE_CTRL_MIN;
1163         while (min < ESDHC_TUNE_CTRL_MAX) {
1164                 esdhc_prepare_tuning(host, min);
1165                 if (!mmc_send_tuning(host->mmc, opcode, NULL))
1166                         break;
1167                 min += ESDHC_TUNE_CTRL_STEP;
1168         }
1169
1170         /* find the maxinum delay which can not pass tuning */
1171         max = min + ESDHC_TUNE_CTRL_STEP;
1172         while (max < ESDHC_TUNE_CTRL_MAX) {
1173                 esdhc_prepare_tuning(host, max);
1174                 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
1175                         max -= ESDHC_TUNE_CTRL_STEP;
1176                         break;
1177                 }
1178                 max += ESDHC_TUNE_CTRL_STEP;
1179         }
1180
1181         /* use average delay to get the best timing */
1182         avg = (min + max) / 2;
1183         esdhc_prepare_tuning(host, avg);
1184         ret = mmc_send_tuning(host->mmc, opcode, NULL);
1185         esdhc_post_tuning(host);
1186
1187         dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n",
1188                 ret ? "failed" : "passed", avg, ret);
1189
1190         return ret;
1191 }
1192
1193 static void esdhc_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios)
1194 {
1195         struct sdhci_host *host = mmc_priv(mmc);
1196         u32 m;
1197
1198         m = readl(host->ioaddr + ESDHC_MIX_CTRL);
1199         if (ios->enhanced_strobe)
1200                 m |= ESDHC_MIX_CTRL_HS400_ES_EN;
1201         else
1202                 m &= ~ESDHC_MIX_CTRL_HS400_ES_EN;
1203         writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1204 }
1205
1206 static int esdhc_change_pinstate(struct sdhci_host *host,
1207                                                 unsigned int uhs)
1208 {
1209         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1210         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1211         struct pinctrl_state *pinctrl;
1212
1213         dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
1214
1215         if (IS_ERR(imx_data->pinctrl) ||
1216                 IS_ERR(imx_data->pins_100mhz) ||
1217                 IS_ERR(imx_data->pins_200mhz))
1218                 return -EINVAL;
1219
1220         switch (uhs) {
1221         case MMC_TIMING_UHS_SDR50:
1222         case MMC_TIMING_UHS_DDR50:
1223                 pinctrl = imx_data->pins_100mhz;
1224                 break;
1225         case MMC_TIMING_UHS_SDR104:
1226         case MMC_TIMING_MMC_HS200:
1227         case MMC_TIMING_MMC_HS400:
1228                 pinctrl = imx_data->pins_200mhz;
1229                 break;
1230         default:
1231                 /* back to default state for other legacy timing */
1232                 return pinctrl_select_default_state(mmc_dev(host->mmc));
1233         }
1234
1235         return pinctrl_select_state(imx_data->pinctrl, pinctrl);
1236 }
1237
1238 /*
1239  * For HS400 eMMC, there is a data_strobe line. This signal is generated
1240  * by the device and used for data output and CRC status response output
1241  * in HS400 mode. The frequency of this signal follows the frequency of
1242  * CLK generated by host. The host receives the data which is aligned to the
1243  * edge of data_strobe line. Due to the time delay between CLK line and
1244  * data_strobe line, if the delay time is larger than one clock cycle,
1245  * then CLK and data_strobe line will be misaligned, read error shows up.
1246  */
1247 static void esdhc_set_strobe_dll(struct sdhci_host *host)
1248 {
1249         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1250         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1251         u32 strobe_delay;
1252         u32 v;
1253         int ret;
1254
1255         /* disable clock before enabling strobe dll */
1256         writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) &
1257                 ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
1258                 host->ioaddr + ESDHC_VENDOR_SPEC);
1259         esdhc_wait_for_card_clock_gate_off(host);
1260
1261         /* force a reset on strobe dll */
1262         writel(ESDHC_STROBE_DLL_CTRL_RESET,
1263                 host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1264         /* clear the reset bit on strobe dll before any setting */
1265         writel(0, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1266
1267         /*
1268          * enable strobe dll ctrl and adjust the delay target
1269          * for the uSDHC loopback read clock
1270          */
1271         if (imx_data->boarddata.strobe_dll_delay_target)
1272                 strobe_delay = imx_data->boarddata.strobe_dll_delay_target;
1273         else
1274                 strobe_delay = ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT;
1275         v = ESDHC_STROBE_DLL_CTRL_ENABLE |
1276                 ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT |
1277                 (strobe_delay << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
1278         writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1279
1280         /* wait max 50us to get the REF/SLV lock */
1281         ret = readl_poll_timeout(host->ioaddr + ESDHC_STROBE_DLL_STATUS, v,
1282                 ((v & ESDHC_STROBE_DLL_STS_REF_LOCK) && (v & ESDHC_STROBE_DLL_STS_SLV_LOCK)), 1, 50);
1283         if (ret == -ETIMEDOUT)
1284                 dev_warn(mmc_dev(host->mmc),
1285                 "warning! HS400 strobe DLL status REF/SLV not lock in 50us, STROBE DLL status is %x!\n", v);
1286 }
1287
1288 static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1289 {
1290         u32 m;
1291         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1292         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1293         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1294
1295         /* disable ddr mode and disable HS400 mode */
1296         m = readl(host->ioaddr + ESDHC_MIX_CTRL);
1297         m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN);
1298         imx_data->is_ddr = 0;
1299
1300         switch (timing) {
1301         case MMC_TIMING_UHS_SDR12:
1302         case MMC_TIMING_UHS_SDR25:
1303         case MMC_TIMING_UHS_SDR50:
1304         case MMC_TIMING_UHS_SDR104:
1305         case MMC_TIMING_MMC_HS:
1306         case MMC_TIMING_MMC_HS200:
1307                 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1308                 break;
1309         case MMC_TIMING_UHS_DDR50:
1310         case MMC_TIMING_MMC_DDR52:
1311                 m |= ESDHC_MIX_CTRL_DDREN;
1312                 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1313                 imx_data->is_ddr = 1;
1314                 if (boarddata->delay_line) {
1315                         u32 v;
1316                         v = boarddata->delay_line <<
1317                                 ESDHC_DLL_OVERRIDE_VAL_SHIFT |
1318                                 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT);
1319                         if (is_imx53_esdhc(imx_data))
1320                                 v <<= 1;
1321                         writel(v, host->ioaddr + ESDHC_DLL_CTRL);
1322                 }
1323                 break;
1324         case MMC_TIMING_MMC_HS400:
1325                 m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN;
1326                 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1327                 imx_data->is_ddr = 1;
1328                 /* update clock after enable DDR for strobe DLL lock */
1329                 host->ops->set_clock(host, host->clock);
1330                 esdhc_set_strobe_dll(host);
1331                 break;
1332         case MMC_TIMING_LEGACY:
1333         default:
1334                 esdhc_reset_tuning(host);
1335                 break;
1336         }
1337
1338         esdhc_change_pinstate(host, timing);
1339 }
1340
1341 static void esdhc_reset(struct sdhci_host *host, u8 mask)
1342 {
1343         sdhci_and_cqhci_reset(host, mask);
1344
1345         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1346         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1347 }
1348
1349 static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host)
1350 {
1351         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1352         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1353
1354         /* Doc Erratum: the uSDHC actual maximum timeout count is 1 << 29 */
1355         return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27;
1356 }
1357
1358 static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1359 {
1360         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1361         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1362
1363         /* use maximum timeout counter */
1364         esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK,
1365                         esdhc_is_usdhc(imx_data) ? 0xF : 0xE,
1366                         SDHCI_TIMEOUT_CONTROL);
1367 }
1368
1369 static u32 esdhc_cqhci_irq(struct sdhci_host *host, u32 intmask)
1370 {
1371         int cmd_error = 0;
1372         int data_error = 0;
1373
1374         if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
1375                 return intmask;
1376
1377         cqhci_irq(host->mmc, intmask, cmd_error, data_error);
1378
1379         return 0;
1380 }
1381
1382 static struct sdhci_ops sdhci_esdhc_ops = {
1383         .read_l = esdhc_readl_le,
1384         .read_w = esdhc_readw_le,
1385         .read_b = esdhc_readb_le,
1386         .write_l = esdhc_writel_le,
1387         .write_w = esdhc_writew_le,
1388         .write_b = esdhc_writeb_le,
1389         .set_clock = esdhc_pltfm_set_clock,
1390         .get_max_clock = esdhc_pltfm_get_max_clock,
1391         .get_min_clock = esdhc_pltfm_get_min_clock,
1392         .get_max_timeout_count = esdhc_get_max_timeout_count,
1393         .get_ro = esdhc_pltfm_get_ro,
1394         .set_timeout = esdhc_set_timeout,
1395         .set_bus_width = esdhc_pltfm_set_bus_width,
1396         .set_uhs_signaling = esdhc_set_uhs_signaling,
1397         .reset = esdhc_reset,
1398         .irq = esdhc_cqhci_irq,
1399         .dump_vendor_regs = esdhc_dump_debug_regs,
1400 };
1401
1402 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
1403         .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
1404                         | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
1405                         | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
1406                         | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
1407         .ops = &sdhci_esdhc_ops,
1408 };
1409
1410 static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host)
1411 {
1412         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1413         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1414         struct cqhci_host *cq_host = host->mmc->cqe_private;
1415         u32 tmp;
1416
1417         if (esdhc_is_usdhc(imx_data)) {
1418                 /*
1419                  * The imx6q ROM code will change the default watermark
1420                  * level setting to something insane.  Change it back here.
1421                  */
1422                 writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL);
1423
1424                 /*
1425                  * ROM code will change the bit burst_length_enable setting
1426                  * to zero if this usdhc is chosen to boot system. Change
1427                  * it back here, otherwise it will impact the performance a
1428                  * lot. This bit is used to enable/disable the burst length
1429                  * for the external AHB2AXI bridge. It's useful especially
1430                  * for INCR transfer because without burst length indicator,
1431                  * the AHB2AXI bridge does not know the burst length in
1432                  * advance. And without burst length indicator, AHB INCR
1433                  * transfer can only be converted to singles on the AXI side.
1434                  */
1435                 writel(readl(host->ioaddr + SDHCI_HOST_CONTROL)
1436                         | ESDHC_BURST_LEN_EN_INCR,
1437                         host->ioaddr + SDHCI_HOST_CONTROL);
1438
1439                 /*
1440                  * erratum ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
1441                  * TO1.1, it's harmless for MX6SL
1442                  */
1443                 if (!(imx_data->socdata->flags & ESDHC_FLAG_SKIP_ERR004536)) {
1444                         writel(readl(host->ioaddr + 0x6c) & ~BIT(7),
1445                                 host->ioaddr + 0x6c);
1446                 }
1447
1448                 /* disable DLL_CTRL delay line settings */
1449                 writel(0x0, host->ioaddr + ESDHC_DLL_CTRL);
1450
1451                 /*
1452                  * For the case of command with busy, if set the bit
1453                  * ESDHC_VEND_SPEC2_EN_BUSY_IRQ, USDHC will generate a
1454                  * transfer complete interrupt when busy is deasserted.
1455                  * When CQHCI use DCMD to send a CMD need R1b respons,
1456                  * CQHCI require to set ESDHC_VEND_SPEC2_EN_BUSY_IRQ,
1457                  * otherwise DCMD will always meet timeout waiting for
1458                  * hardware interrupt issue.
1459                  */
1460                 if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) {
1461                         tmp = readl(host->ioaddr + ESDHC_VEND_SPEC2);
1462                         tmp |= ESDHC_VEND_SPEC2_EN_BUSY_IRQ;
1463                         writel(tmp, host->ioaddr + ESDHC_VEND_SPEC2);
1464
1465                         host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
1466                 }
1467
1468                 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
1469                         tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
1470                         tmp |= ESDHC_STD_TUNING_EN;
1471
1472                         /*
1473                          * ROM code or bootloader may config the start tap
1474                          * and step, unmask them first.
1475                          */
1476                         tmp &= ~(ESDHC_TUNING_START_TAP_MASK | ESDHC_TUNING_STEP_MASK);
1477                         if (imx_data->boarddata.tuning_start_tap)
1478                                 tmp |= imx_data->boarddata.tuning_start_tap;
1479                         else
1480                                 tmp |= ESDHC_TUNING_START_TAP_DEFAULT;
1481
1482                         if (imx_data->boarddata.tuning_step) {
1483                                 tmp |= imx_data->boarddata.tuning_step
1484                                         << ESDHC_TUNING_STEP_SHIFT;
1485                         } else {
1486                                 tmp |= ESDHC_TUNING_STEP_DEFAULT
1487                                         << ESDHC_TUNING_STEP_SHIFT;
1488                         }
1489
1490                         /* Disable the CMD CRC check for tuning, if not, need to
1491                          * add some delay after every tuning command, because
1492                          * hardware standard tuning logic will directly go to next
1493                          * step once it detect the CMD CRC error, will not wait for
1494                          * the card side to finally send out the tuning data, trigger
1495                          * the buffer read ready interrupt immediately. If usdhc send
1496                          * the next tuning command some eMMC card will stuck, can't
1497                          * response, block the tuning procedure or the first command
1498                          * after the whole tuning procedure always can't get any response.
1499                          */
1500                         tmp |= ESDHC_TUNING_CMD_CRC_CHECK_DISABLE;
1501                         writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
1502                 } else if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
1503                         /*
1504                          * ESDHC_STD_TUNING_EN may be configed in bootloader
1505                          * or ROM code, so clear this bit here to make sure
1506                          * the manual tuning can work.
1507                          */
1508                         tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
1509                         tmp &= ~ESDHC_STD_TUNING_EN;
1510                         writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
1511                 }
1512
1513                 /*
1514                  * On i.MX8MM, we are running Dual Linux OS, with 1st Linux using SD Card
1515                  * as rootfs storage, 2nd Linux using eMMC as rootfs storage. We let
1516                  * the 1st linux configure power/clock for the 2nd Linux.
1517                  *
1518                  * When the 2nd Linux is booting into rootfs stage, we let the 1st Linux
1519                  * to destroy the 2nd linux, then restart the 2nd linux, we met SDHCI dump.
1520                  * After we clear the pending interrupt and halt CQCTL, issue gone.
1521                  */
1522                 if (cq_host) {
1523                         tmp = cqhci_readl(cq_host, CQHCI_IS);
1524                         cqhci_writel(cq_host, tmp, CQHCI_IS);
1525                         cqhci_writel(cq_host, CQHCI_HALT, CQHCI_CTL);
1526                 }
1527         }
1528 }
1529
1530 static void esdhc_cqe_enable(struct mmc_host *mmc)
1531 {
1532         struct sdhci_host *host = mmc_priv(mmc);
1533         struct cqhci_host *cq_host = mmc->cqe_private;
1534         u32 reg;
1535         u16 mode;
1536         int count = 10;
1537
1538         /*
1539          * CQE gets stuck if it sees Buffer Read Enable bit set, which can be
1540          * the case after tuning, so ensure the buffer is drained.
1541          */
1542         reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
1543         while (reg & SDHCI_DATA_AVAILABLE) {
1544                 sdhci_readl(host, SDHCI_BUFFER);
1545                 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
1546                 if (count-- == 0) {
1547                         dev_warn(mmc_dev(host->mmc),
1548                                 "CQE may get stuck because the Buffer Read Enable bit is set\n");
1549                         break;
1550                 }
1551                 mdelay(1);
1552         }
1553
1554         /*
1555          * Runtime resume will reset the entire host controller, which
1556          * will also clear the DMAEN/BCEN of register ESDHC_MIX_CTRL.
1557          * Here set DMAEN and BCEN when enable CMDQ.
1558          */
1559         mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
1560         if (host->flags & SDHCI_REQ_USE_DMA)
1561                 mode |= SDHCI_TRNS_DMA;
1562         if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
1563                 mode |= SDHCI_TRNS_BLK_CNT_EN;
1564         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
1565
1566         /*
1567          * Though Runtime resume reset the entire host controller,
1568          * but do not impact the CQHCI side, need to clear the
1569          * HALT bit, avoid CQHCI stuck in the first request when
1570          * system resume back.
1571          */
1572         cqhci_writel(cq_host, 0, CQHCI_CTL);
1573         if (cqhci_readl(cq_host, CQHCI_CTL) & CQHCI_HALT)
1574                 dev_err(mmc_dev(host->mmc),
1575                         "failed to exit halt state when enable CQE\n");
1576
1577
1578         sdhci_cqe_enable(mmc);
1579 }
1580
1581 static void esdhc_sdhci_dumpregs(struct mmc_host *mmc)
1582 {
1583         sdhci_dumpregs(mmc_priv(mmc));
1584 }
1585
1586 static const struct cqhci_host_ops esdhc_cqhci_ops = {
1587         .enable         = esdhc_cqe_enable,
1588         .disable        = sdhci_cqe_disable,
1589         .dumpregs       = esdhc_sdhci_dumpregs,
1590 };
1591
1592 static int
1593 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
1594                          struct sdhci_host *host,
1595                          struct pltfm_imx_data *imx_data)
1596 {
1597         struct device_node *np = pdev->dev.of_node;
1598         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1599         int ret;
1600
1601         if (of_property_read_bool(np, "fsl,wp-controller"))
1602                 boarddata->wp_type = ESDHC_WP_CONTROLLER;
1603
1604         /*
1605          * If we have this property, then activate WP check.
1606          * Retrieveing and requesting the actual WP GPIO will happen
1607          * in the call to mmc_of_parse().
1608          */
1609         if (of_property_read_bool(np, "wp-gpios"))
1610                 boarddata->wp_type = ESDHC_WP_GPIO;
1611
1612         of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step);
1613         of_property_read_u32(np, "fsl,tuning-start-tap",
1614                              &boarddata->tuning_start_tap);
1615
1616         of_property_read_u32(np, "fsl,strobe-dll-delay-target",
1617                                 &boarddata->strobe_dll_delay_target);
1618         if (of_property_read_bool(np, "no-1-8-v"))
1619                 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1620
1621         if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
1622                 boarddata->delay_line = 0;
1623
1624         mmc_of_parse_voltage(host->mmc, &host->ocr_mask);
1625
1626         if (esdhc_is_usdhc(imx_data) && !IS_ERR(imx_data->pinctrl)) {
1627                 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
1628                                                 ESDHC_PINCTRL_STATE_100MHZ);
1629                 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
1630                                                 ESDHC_PINCTRL_STATE_200MHZ);
1631         }
1632
1633         /* call to generic mmc_of_parse to support additional capabilities */
1634         ret = mmc_of_parse(host->mmc);
1635         if (ret)
1636                 return ret;
1637
1638         /* HS400/HS400ES require 8 bit bus */
1639         if (!(host->mmc->caps & MMC_CAP_8_BIT_DATA))
1640                 host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES);
1641
1642         if (mmc_gpio_get_cd(host->mmc) >= 0)
1643                 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1644
1645         return 0;
1646 }
1647
1648 static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
1649 {
1650         struct sdhci_pltfm_host *pltfm_host;
1651         struct sdhci_host *host;
1652         struct cqhci_host *cq_host;
1653         int err;
1654         struct pltfm_imx_data *imx_data;
1655
1656         host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata,
1657                                 sizeof(*imx_data));
1658         if (IS_ERR(host))
1659                 return PTR_ERR(host);
1660
1661         pltfm_host = sdhci_priv(host);
1662
1663         imx_data = sdhci_pltfm_priv(pltfm_host);
1664
1665         imx_data->socdata = device_get_match_data(&pdev->dev);
1666
1667         if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1668                 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0);
1669
1670         imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1671         if (IS_ERR(imx_data->clk_ipg)) {
1672                 err = PTR_ERR(imx_data->clk_ipg);
1673                 goto free_sdhci;
1674         }
1675
1676         imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1677         if (IS_ERR(imx_data->clk_ahb)) {
1678                 err = PTR_ERR(imx_data->clk_ahb);
1679                 goto free_sdhci;
1680         }
1681
1682         imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
1683         if (IS_ERR(imx_data->clk_per)) {
1684                 err = PTR_ERR(imx_data->clk_per);
1685                 goto free_sdhci;
1686         }
1687
1688         pltfm_host->clk = imx_data->clk_per;
1689         pltfm_host->clock = clk_get_rate(pltfm_host->clk);
1690         err = clk_prepare_enable(imx_data->clk_per);
1691         if (err)
1692                 goto free_sdhci;
1693         err = clk_prepare_enable(imx_data->clk_ipg);
1694         if (err)
1695                 goto disable_per_clk;
1696         err = clk_prepare_enable(imx_data->clk_ahb);
1697         if (err)
1698                 goto disable_ipg_clk;
1699
1700         imx_data->pinctrl = devm_pinctrl_get(&pdev->dev);
1701         if (IS_ERR(imx_data->pinctrl))
1702                 dev_warn(mmc_dev(host->mmc), "could not get pinctrl\n");
1703
1704         if (esdhc_is_usdhc(imx_data)) {
1705                 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
1706                 host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;
1707
1708                 /* GPIO CD can be set as a wakeup source */
1709                 host->mmc->caps |= MMC_CAP_CD_WAKE;
1710
1711                 if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200))
1712                         host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
1713
1714                 /* clear tuning bits in case ROM has set it already */
1715                 writel(0x0, host->ioaddr + ESDHC_MIX_CTRL);
1716                 writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1717                 writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1718
1719                 /*
1720                  * Link usdhc specific mmc_host_ops execute_tuning function,
1721                  * to replace the standard one in sdhci_ops.
1722                  */
1723                 host->mmc_host_ops.execute_tuning = usdhc_execute_tuning;
1724
1725                 /*
1726                  * Link usdhc specific mmc_host_ops init card function,
1727                  * to distinguish the card type.
1728                  */
1729                 host->mmc_host_ops.init_card = usdhc_init_card;
1730         }
1731
1732         if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
1733                 sdhci_esdhc_ops.platform_execute_tuning =
1734                                         esdhc_executing_tuning;
1735
1736         if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
1737                 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1738
1739         if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
1740                 host->mmc->caps2 |= MMC_CAP2_HS400;
1741
1742         if (imx_data->socdata->flags & ESDHC_FLAG_BROKEN_AUTO_CMD23)
1743                 host->quirks2 |= SDHCI_QUIRK2_ACMD23_BROKEN;
1744
1745         if (imx_data->socdata->flags & ESDHC_FLAG_HS400_ES) {
1746                 host->mmc->caps2 |= MMC_CAP2_HS400_ES;
1747                 host->mmc_host_ops.hs400_enhanced_strobe =
1748                                         esdhc_hs400_enhanced_strobe;
1749         }
1750
1751         if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) {
1752                 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
1753                 cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL);
1754                 if (!cq_host) {
1755                         err = -ENOMEM;
1756                         goto disable_ahb_clk;
1757                 }
1758
1759                 cq_host->mmio = host->ioaddr + ESDHC_CQHCI_ADDR_OFFSET;
1760                 cq_host->ops = &esdhc_cqhci_ops;
1761
1762                 err = cqhci_init(cq_host, host->mmc, false);
1763                 if (err)
1764                         goto disable_ahb_clk;
1765         }
1766
1767         err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data);
1768         if (err)
1769                 goto disable_ahb_clk;
1770
1771         sdhci_esdhc_imx_hwinit(host);
1772
1773         err = sdhci_add_host(host);
1774         if (err)
1775                 goto disable_ahb_clk;
1776
1777         /*
1778          * Setup the wakeup capability here, let user to decide
1779          * whether need to enable this wakeup through sysfs interface.
1780          */
1781         if ((host->mmc->pm_caps & MMC_PM_KEEP_POWER) &&
1782                         (host->mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ))
1783                 device_set_wakeup_capable(&pdev->dev, true);
1784
1785         pm_runtime_set_active(&pdev->dev);
1786         pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1787         pm_runtime_use_autosuspend(&pdev->dev);
1788         pm_suspend_ignore_children(&pdev->dev, 1);
1789         pm_runtime_enable(&pdev->dev);
1790
1791         return 0;
1792
1793 disable_ahb_clk:
1794         clk_disable_unprepare(imx_data->clk_ahb);
1795 disable_ipg_clk:
1796         clk_disable_unprepare(imx_data->clk_ipg);
1797 disable_per_clk:
1798         clk_disable_unprepare(imx_data->clk_per);
1799 free_sdhci:
1800         if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1801                 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1802         sdhci_pltfm_free(pdev);
1803         return err;
1804 }
1805
1806 static void sdhci_esdhc_imx_remove(struct platform_device *pdev)
1807 {
1808         struct sdhci_host *host = platform_get_drvdata(pdev);
1809         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1810         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1811         int dead;
1812
1813         pm_runtime_get_sync(&pdev->dev);
1814         dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
1815         pm_runtime_disable(&pdev->dev);
1816         pm_runtime_put_noidle(&pdev->dev);
1817
1818         sdhci_remove_host(host, dead);
1819
1820         clk_disable_unprepare(imx_data->clk_per);
1821         clk_disable_unprepare(imx_data->clk_ipg);
1822         clk_disable_unprepare(imx_data->clk_ahb);
1823
1824         if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1825                 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1826
1827         sdhci_pltfm_free(pdev);
1828 }
1829
1830 #ifdef CONFIG_PM_SLEEP
1831 static int sdhci_esdhc_suspend(struct device *dev)
1832 {
1833         struct sdhci_host *host = dev_get_drvdata(dev);
1834         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1835         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1836         int ret;
1837
1838         if (host->mmc->caps2 & MMC_CAP2_CQE) {
1839                 ret = cqhci_suspend(host->mmc);
1840                 if (ret)
1841                         return ret;
1842         }
1843
1844         if ((imx_data->socdata->flags & ESDHC_FLAG_STATE_LOST_IN_LPMODE) &&
1845                 (host->tuning_mode != SDHCI_TUNING_MODE_1)) {
1846                 mmc_retune_timer_stop(host->mmc);
1847                 mmc_retune_needed(host->mmc);
1848         }
1849
1850         if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1851                 mmc_retune_needed(host->mmc);
1852
1853         ret = sdhci_suspend_host(host);
1854         if (ret)
1855                 return ret;
1856
1857         ret = pinctrl_pm_select_sleep_state(dev);
1858         if (ret)
1859                 return ret;
1860
1861         ret = mmc_gpio_set_cd_wake(host->mmc, true);
1862
1863         return ret;
1864 }
1865
1866 static int sdhci_esdhc_resume(struct device *dev)
1867 {
1868         struct sdhci_host *host = dev_get_drvdata(dev);
1869         int ret;
1870
1871         ret = pinctrl_pm_select_default_state(dev);
1872         if (ret)
1873                 return ret;
1874
1875         /* re-initialize hw state in case it's lost in low power mode */
1876         sdhci_esdhc_imx_hwinit(host);
1877
1878         ret = sdhci_resume_host(host);
1879         if (ret)
1880                 return ret;
1881
1882         if (host->mmc->caps2 & MMC_CAP2_CQE)
1883                 ret = cqhci_resume(host->mmc);
1884
1885         if (!ret)
1886                 ret = mmc_gpio_set_cd_wake(host->mmc, false);
1887
1888         return ret;
1889 }
1890 #endif
1891
1892 #ifdef CONFIG_PM
1893 static int sdhci_esdhc_runtime_suspend(struct device *dev)
1894 {
1895         struct sdhci_host *host = dev_get_drvdata(dev);
1896         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1897         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1898         int ret;
1899
1900         if (host->mmc->caps2 & MMC_CAP2_CQE) {
1901                 ret = cqhci_suspend(host->mmc);
1902                 if (ret)
1903                         return ret;
1904         }
1905
1906         ret = sdhci_runtime_suspend_host(host);
1907         if (ret)
1908                 return ret;
1909
1910         if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1911                 mmc_retune_needed(host->mmc);
1912
1913         imx_data->actual_clock = host->mmc->actual_clock;
1914         esdhc_pltfm_set_clock(host, 0);
1915         clk_disable_unprepare(imx_data->clk_per);
1916         clk_disable_unprepare(imx_data->clk_ipg);
1917         clk_disable_unprepare(imx_data->clk_ahb);
1918
1919         if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1920                 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1921
1922         return ret;
1923 }
1924
1925 static int sdhci_esdhc_runtime_resume(struct device *dev)
1926 {
1927         struct sdhci_host *host = dev_get_drvdata(dev);
1928         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1929         struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1930         int err;
1931
1932         if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1933                 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0);
1934
1935         if (imx_data->socdata->flags & ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME)
1936                 clk_set_rate(imx_data->clk_per, pltfm_host->clock);
1937
1938         err = clk_prepare_enable(imx_data->clk_ahb);
1939         if (err)
1940                 goto remove_pm_qos_request;
1941
1942         err = clk_prepare_enable(imx_data->clk_per);
1943         if (err)
1944                 goto disable_ahb_clk;
1945
1946         err = clk_prepare_enable(imx_data->clk_ipg);
1947         if (err)
1948                 goto disable_per_clk;
1949
1950         esdhc_pltfm_set_clock(host, imx_data->actual_clock);
1951
1952         err = sdhci_runtime_resume_host(host, 0);
1953         if (err)
1954                 goto disable_ipg_clk;
1955
1956         if (host->mmc->caps2 & MMC_CAP2_CQE)
1957                 err = cqhci_resume(host->mmc);
1958
1959         return err;
1960
1961 disable_ipg_clk:
1962         clk_disable_unprepare(imx_data->clk_ipg);
1963 disable_per_clk:
1964         clk_disable_unprepare(imx_data->clk_per);
1965 disable_ahb_clk:
1966         clk_disable_unprepare(imx_data->clk_ahb);
1967 remove_pm_qos_request:
1968         if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1969                 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1970         return err;
1971 }
1972 #endif
1973
1974 static const struct dev_pm_ops sdhci_esdhc_pmops = {
1975         SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume)
1976         SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend,
1977                                 sdhci_esdhc_runtime_resume, NULL)
1978 };
1979
1980 static struct platform_driver sdhci_esdhc_imx_driver = {
1981         .driver         = {
1982                 .name   = "sdhci-esdhc-imx",
1983                 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1984                 .of_match_table = imx_esdhc_dt_ids,
1985                 .pm     = &sdhci_esdhc_pmops,
1986         },
1987         .probe          = sdhci_esdhc_imx_probe,
1988         .remove_new     = sdhci_esdhc_imx_remove,
1989 };
1990
1991 module_platform_driver(sdhci_esdhc_imx_driver);
1992
1993 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
1994 MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
1995 MODULE_LICENSE("GPL v2");