drivers/mmc/host/renesas_sdhi_core.c

   1 /*
   2  * Renesas SDHI
   3  *
   4  * Copyright (C) 2015-17 Renesas Electronics Corporation
   5  * Copyright (C) 2016-17 Sang Engineering, Wolfram Sang
   6  * Copyright (C) 2016-17 Horms Solutions, Simon Horman
   7  * Copyright (C) 2009 Magnus Damm
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * Based on "Compaq ASIC3 support":
  14  *
  15  * Copyright 2001 Compaq Computer Corporation.
  16  * Copyright 2004-2005 Phil Blundell
  17  * Copyright 2007-2008 OpenedHand Ltd.
  18  *
  19  * Authors: Phil Blundell <pb@handhelds.org>,
  20  *          Samuel Ortiz <sameo@openedhand.com>
  21  *
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/clk.h>
  26 #include <linux/slab.h>
  27 #include <linux/of_device.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/mmc/host.h>
  30 #include <linux/mfd/tmio.h>
  31 #include <linux/sh_dma.h>
  32 #include <linux/delay.h>
  33 #include <linux/pinctrl/consumer.h>
  34 #include <linux/pinctrl/pinctrl-state.h>
  35 #include <linux/regulator/consumer.h>
  36
  37 #include "renesas_sdhi.h"
  38 #include "tmio_mmc.h"
  39
  40 #define EXT_ACC           0xe4
  41
  42 #define SDHI_VER_GEN2_SDR50     0x490c
  43 /* very old datasheets said 0x490c for SDR104, too. They are wrong! */
  44 #define SDHI_VER_GEN2_SDR104    0xcb0d
  45 #define SDHI_VER_GEN3_SD        0xcc10
  46 #define SDHI_VER_GEN3_SDMMC     0xcd10
  47
  48 #define host_to_priv(host) container_of((host)->pdata, struct renesas_sdhi, mmc_data)
  49
  50 struct renesas_sdhi {
  51         struct clk *clk;
  52         struct clk *clk_cd;
  53         struct tmio_mmc_data mmc_data;
  54         struct tmio_mmc_dma dma_priv;
  55         struct pinctrl *pinctrl;
  56         struct pinctrl_state *pins_default, *pins_uhs;
  57         void __iomem *scc_ctl;
  58 };
  59
  60 static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width)
  61 {
  62         u32 val;
  63
  64         /*
  65          * see also
  66          *      renesas_sdhi_of_data :: dma_buswidth
  67          */
  68         switch (sd_ctrl_read16(host, CTL_VERSION)) {
  69         case SDHI_VER_GEN2_SDR50:
  70                 val = (width == 32) ? 0x0001 : 0x0000;
  71                 break;
  72         case SDHI_VER_GEN2_SDR104:
  73                 val = (width == 32) ? 0x0000 : 0x0001;
  74                 break;
  75         case SDHI_VER_GEN3_SD:
  76         case SDHI_VER_GEN3_SDMMC:
  77                 if (width == 64)
  78                         val = 0x0000;
  79                 else if (width == 32)
  80                         val = 0x0101;
  81                 else
  82                         val = 0x0001;
  83                 break;
  84         default:
  85                 /* nothing to do */
  86                 return;
  87         }
  88
  89         sd_ctrl_write16(host, EXT_ACC, val);
  90 }
  91
  92 static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host)
  93 {
  94         struct mmc_host *mmc = host->mmc;
  95         struct renesas_sdhi *priv = host_to_priv(host);
  96         int ret = clk_prepare_enable(priv->clk);
  97         if (ret < 0)
  98                 return ret;
  99
 100         ret = clk_prepare_enable(priv->clk_cd);
 101         if (ret < 0) {
 102                 clk_disable_unprepare(priv->clk);
 103                 return ret;
 104         }
 105
 106         /*
 107          * The clock driver may not know what maximum frequency
 108          * actually works, so it should be set with the max-frequency
 109          * property which will already have been read to f_max.  If it
 110          * was missing, assume the current frequency is the maximum.
 111          */
 112         if (!mmc->f_max)
 113                 mmc->f_max = clk_get_rate(priv->clk);
 114
 115         /*
 116          * Minimum frequency is the minimum input clock frequency
 117          * divided by our maximum divider.
 118          */
 119         mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L);
 120
 121         /* enable 16bit data access on SDBUF as default */
 122         renesas_sdhi_sdbuf_width(host, 16);
 123
 124         return 0;
 125 }
 126
 127 static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host,
 128                                               unsigned int new_clock)
 129 {
 130         struct renesas_sdhi *priv = host_to_priv(host);
 131         unsigned int freq, diff, best_freq = 0, diff_min = ~0;
 132         int i, ret;
 133
 134         /* tested only on R-Car Gen2+ currently; may work for others */
 135         if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
 136                 return clk_get_rate(priv->clk);
 137
 138         /*
 139          * We want the bus clock to be as close as possible to, but no
 140          * greater than, new_clock.  As we can divide by 1 << i for
 141          * any i in [0, 9] we want the input clock to be as close as
 142          * possible, but no greater than, new_clock << i.
 143          */
 144         for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) {
 145                 freq = clk_round_rate(priv->clk, new_clock << i);
 146                 if (freq > (new_clock << i)) {
 147                         /* Too fast; look for a slightly slower option */
 148                         freq = clk_round_rate(priv->clk,
 149                                               (new_clock << i) / 4 * 3);
 150                         if (freq > (new_clock << i))
 151                                 continue;
 152                 }
 153
 154                 diff = new_clock - (freq >> i);
 155                 if (diff <= diff_min) {
 156                         best_freq = freq;
 157                         diff_min = diff;
 158                 }
 159         }
 160
 161         ret = clk_set_rate(priv->clk, best_freq);
 162
 163         return ret == 0 ? best_freq : clk_get_rate(priv->clk);
 164 }
 165
 166 static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host)
 167 {
 168         struct renesas_sdhi *priv = host_to_priv(host);
 169
 170         clk_disable_unprepare(priv->clk);
 171         clk_disable_unprepare(priv->clk_cd);
 172 }
 173
 174 static int renesas_sdhi_card_busy(struct mmc_host *mmc)
 175 {
 176         struct tmio_mmc_host *host = mmc_priv(mmc);
 177
 178         return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) & TMIO_STAT_DAT0);
 179 }
 180
 181 static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc,
 182                                                       struct mmc_ios *ios)
 183 {
 184         struct tmio_mmc_host *host = mmc_priv(mmc);
 185         struct renesas_sdhi *priv = host_to_priv(host);
 186         struct pinctrl_state *pin_state;
 187         int ret;
 188
 189         switch (ios->signal_voltage) {
 190         case MMC_SIGNAL_VOLTAGE_330:
 191                 pin_state = priv->pins_default;
 192                 break;
 193         case MMC_SIGNAL_VOLTAGE_180:
 194                 pin_state = priv->pins_uhs;
 195                 break;
 196         default:
 197                 return -EINVAL;
 198         }
 199
 200         /*
 201          * If anything is missing, assume signal voltage is fixed at
 202          * 3.3V and succeed/fail accordingly.
 203          */
 204         if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state))
 205                 return ios->signal_voltage ==
 206                         MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL;
 207
 208         ret = mmc_regulator_set_vqmmc(host->mmc, ios);
 209         if (ret)
 210                 return ret;
 211
 212         return pinctrl_select_state(priv->pinctrl, pin_state);
 213 }
 214
 215 /* SCC registers */
 216 #define SH_MOBILE_SDHI_SCC_DTCNTL       0x000
 217 #define SH_MOBILE_SDHI_SCC_TAPSET       0x002
 218 #define SH_MOBILE_SDHI_SCC_DT2FF        0x004
 219 #define SH_MOBILE_SDHI_SCC_CKSEL        0x006
 220 #define SH_MOBILE_SDHI_SCC_RVSCNTL      0x008
 221 #define SH_MOBILE_SDHI_SCC_RVSREQ       0x00A
 222
 223 /* Definitions for values the SH_MOBILE_SDHI_SCC_DTCNTL register */
 224 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN         BIT(0)
 225 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT  16
 226 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK   0xff
 227
 228 /* Definitions for values the SH_MOBILE_SDHI_SCC_CKSEL register */
 229 #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL          BIT(0)
 230 /* Definitions for values the SH_MOBILE_SDHI_SCC_RVSCNTL register */
 231 #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN        BIT(0)
 232 /* Definitions for values the SH_MOBILE_SDHI_SCC_RVSREQ register */
 233 #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR        BIT(2)
 234
 235 static inline u32 sd_scc_read32(struct tmio_mmc_host *host,
 236                                 struct renesas_sdhi *priv, int addr)
 237 {
 238         return readl(priv->scc_ctl + (addr << host->bus_shift));
 239 }
 240
 241 static inline void sd_scc_write32(struct tmio_mmc_host *host,
 242                                   struct renesas_sdhi *priv,
 243                                   int addr, u32 val)
 244 {
 245         writel(val, priv->scc_ctl + (addr << host->bus_shift));
 246 }
 247
 248 static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host)
 249 {
 250         struct renesas_sdhi *priv;
 251
 252         priv = host_to_priv(host);
 253
 254         /* set sampling clock selection range */
 255         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
 256                        0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
 257
 258         /* Initialize SCC */
 259         sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0);
 260
 261         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
 262                        SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
 263                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL));
 264
 265         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
 266                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 267
 268         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
 269                        SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
 270                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
 271
 272         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 273                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 274
 275         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
 276                        ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
 277                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
 278
 279         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, host->scc_tappos);
 280
 281         /* Read TAPNUM */
 282         return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >>
 283                 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
 284                 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK;
 285 }
 286
 287 static void renesas_sdhi_prepare_tuning(struct tmio_mmc_host *host,
 288                                          unsigned long tap)
 289 {
 290         struct renesas_sdhi *priv = host_to_priv(host);
 291
 292         /* Set sampling clock position */
 293         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, tap);
 294 }
 295
 296 #define SH_MOBILE_SDHI_MAX_TAP 3
 297
 298 static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host)
 299 {
 300         struct renesas_sdhi *priv = host_to_priv(host);
 301         unsigned long tap_cnt;  /* counter of tuning success */
 302         unsigned long tap_set;  /* tap position */
 303         unsigned long tap_start;/* start position of tuning success */
 304         unsigned long tap_end;  /* end position of tuning success */
 305         unsigned long ntap;     /* temporary counter of tuning success */
 306         unsigned long i;
 307
 308         /* Clear SCC_RVSREQ */
 309         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
 310
 311         /*
 312          * Find the longest consecutive run of successful probes.  If that
 313          * is more than SH_MOBILE_SDHI_MAX_TAP probes long then use the
 314          * center index as the tap.
 315          */
 316         tap_cnt = 0;
 317         ntap = 0;
 318         tap_start = 0;
 319         tap_end = 0;
 320         for (i = 0; i < host->tap_num * 2; i++) {
 321                 if (test_bit(i, host->taps))
 322                         ntap++;
 323                 else {
 324                         if (ntap > tap_cnt) {
 325                                 tap_start = i - ntap;
 326                                 tap_end = i - 1;
 327                                 tap_cnt = ntap;
 328                         }
 329                         ntap = 0;
 330                 }
 331         }
 332
 333         if (ntap > tap_cnt) {
 334                 tap_start = i - ntap;
 335                 tap_end = i - 1;
 336                 tap_cnt = ntap;
 337         }
 338
 339         if (tap_cnt >= SH_MOBILE_SDHI_MAX_TAP)
 340                 tap_set = (tap_start + tap_end) / 2 % host->tap_num;
 341         else
 342                 return -EIO;
 343
 344         /* Set SCC */
 345         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, tap_set);
 346
 347         /* Enable auto re-tuning */
 348         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
 349                        SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN |
 350                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
 351
 352         return 0;
 353 }
 354
 355
 356 static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host)
 357 {
 358         struct renesas_sdhi *priv = host_to_priv(host);
 359
 360         /* Check SCC error */
 361         if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) &
 362             SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &&
 363             sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) &
 364             SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) {
 365                 /* Clear SCC error */
 366                 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
 367                 return true;
 368         }
 369
 370         return false;
 371 }
 372
 373 static void renesas_sdhi_hw_reset(struct tmio_mmc_host *host)
 374 {
 375         struct renesas_sdhi *priv;
 376
 377         priv = host_to_priv(host);
 378
 379         /* Reset SCC */
 380         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
 381                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 382
 383         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
 384                        ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL &
 385                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
 386
 387         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 388                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 389
 390         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
 391                        ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
 392                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
 393
 394         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
 395                        ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
 396                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
 397 }
 398
 399 static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host)
 400 {
 401         int timeout = 1000;
 402
 403         while (--timeout && !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS)
 404                               & TMIO_STAT_SCLKDIVEN))
 405                 udelay(1);
 406
 407         if (!timeout) {
 408                 dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n");
 409                 return -EBUSY;
 410         }
 411
 412         return 0;
 413 }
 414
 415 static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr)
 416 {
 417         switch (addr)
 418         {
 419         case CTL_SD_CMD:
 420         case CTL_STOP_INTERNAL_ACTION:
 421         case CTL_XFER_BLK_COUNT:
 422         case CTL_SD_CARD_CLK_CTL:
 423         case CTL_SD_XFER_LEN:
 424         case CTL_SD_MEM_CARD_OPT:
 425         case CTL_TRANSACTION_CTL:
 426         case CTL_DMA_ENABLE:
 427         case EXT_ACC:
 428                 return renesas_sdhi_wait_idle(host);
 429         }
 430
 431         return 0;
 432 }
 433
 434 static int renesas_sdhi_multi_io_quirk(struct mmc_card *card,
 435                                          unsigned int direction, int blk_size)
 436 {
 437         /*
 438          * In Renesas controllers, when performing a
 439          * multiple block read of one or two blocks,
 440          * depending on the timing with which the
 441          * response register is read, the response
 442          * value may not be read properly.
 443          * Use single block read for this HW bug
 444          */
 445         if ((direction == MMC_DATA_READ) &&
 446             blk_size == 2)
 447                 return 1;
 448
 449         return blk_size;
 450 }
 451
 452 static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable)
 453 {
 454         sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? 2 : 0);
 455
 456         /* enable 32bit access if DMA mode if possibile */
 457         renesas_sdhi_sdbuf_width(host, enable ? 32 : 16);
 458 }
 459
 460 int renesas_sdhi_probe(struct platform_device *pdev,
 461                        const struct tmio_mmc_dma_ops *dma_ops)
 462 {
 463         const struct renesas_sdhi_of_data *of_data = of_device_get_match_data( &pdev->dev);
 464         struct renesas_sdhi *priv;
 465         struct tmio_mmc_data *mmc_data;
 466         struct tmio_mmc_data *mmd = pdev->dev.platform_data;
 467         struct tmio_mmc_host *host;
 468         struct resource *res;
 469         int irq, ret, i;
 470         struct tmio_mmc_dma *dma_priv;
 471
 472         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 473         if (!res)
 474                 return -EINVAL;
 475
 476         priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi), GFP_KERNEL);
 477         if (!priv)
 478                 return -ENOMEM;
 479
 480         mmc_data = &priv->mmc_data;
 481         dma_priv = &priv->dma_priv;
 482
 483         priv->clk = devm_clk_get(&pdev->dev, NULL);
 484         if (IS_ERR(priv->clk)) {
 485                 ret = PTR_ERR(priv->clk);
 486                 dev_err(&pdev->dev, "cannot get clock: %d\n", ret);
 487                 goto eprobe;
 488         }
 489
 490         /*
 491          * Some controllers provide a 2nd clock just to run the internal card
 492          * detection logic. Unfortunately, the existing driver architecture does
 493          * not support a separation of clocks for runtime PM usage. When
 494          * native hotplug is used, the tmio driver assumes that the core
 495          * must continue to run for card detect to stay active, so we cannot
 496          * disable it.
 497          * Additionally, it is prohibited to supply a clock to the core but not
 498          * to the card detect circuit. That leaves us with if separate clocks
 499          * are presented, we must treat them both as virtually 1 clock.
 500          */
 501         priv->clk_cd = devm_clk_get(&pdev->dev, "cd");
 502         if (IS_ERR(priv->clk_cd))
 503                 priv->clk_cd = NULL;
 504
 505         priv->pinctrl = devm_pinctrl_get(&pdev->dev);
 506         if (!IS_ERR(priv->pinctrl)) {
 507                 priv->pins_default = pinctrl_lookup_state(priv->pinctrl,
 508                                                 PINCTRL_STATE_DEFAULT);
 509                 priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl,
 510                                                 "state_uhs");
 511         }
 512
 513         host = tmio_mmc_host_alloc(pdev);
 514         if (!host) {
 515                 ret = -ENOMEM;
 516                 goto eprobe;
 517         }
 518
 519
 520         if (of_data) {
 521                 mmc_data->flags |= of_data->tmio_flags;
 522                 mmc_data->ocr_mask = of_data->tmio_ocr_mask;
 523                 mmc_data->capabilities |= of_data->capabilities;
 524                 mmc_data->capabilities2 |= of_data->capabilities2;
 525                 mmc_data->dma_rx_offset = of_data->dma_rx_offset;
 526                 dma_priv->dma_buswidth = of_data->dma_buswidth;
 527                 host->bus_shift = of_data->bus_shift;
 528         }
 529
 530         host->dma               = dma_priv;
 531         host->write16_hook      = renesas_sdhi_write16_hook;
 532         host->clk_enable        = renesas_sdhi_clk_enable;
 533         host->clk_update        = renesas_sdhi_clk_update;
 534         host->clk_disable       = renesas_sdhi_clk_disable;
 535         host->multi_io_quirk    = renesas_sdhi_multi_io_quirk;
 536
 537         /* SDR speeds are only available on Gen2+ */
 538         if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) {
 539                 /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */
 540                 host->card_busy = renesas_sdhi_card_busy;
 541                 host->start_signal_voltage_switch =
 542                         renesas_sdhi_start_signal_voltage_switch;
 543         }
 544
 545         /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */
 546         if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */
 547                 host->bus_shift = 1;
 548
 549         if (mmd)
 550                 *mmc_data = *mmd;
 551
 552         dma_priv->filter = shdma_chan_filter;
 553         dma_priv->enable = renesas_sdhi_enable_dma;
 554
 555         mmc_data->alignment_shift = 1; /* 2-byte alignment */
 556         mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED;
 557
 558         /*
 559          * All SDHI blocks support 2-byte and larger block sizes in 4-bit
 560          * bus width mode.
 561          */
 562         mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES;
 563
 564         /*
 565          * All SDHI blocks support SDIO IRQ signalling.
 566          */
 567         mmc_data->flags |= TMIO_MMC_SDIO_IRQ;
 568
 569         /*
 570          * All SDHI have CMD12 controll bit
 571          */
 572         mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL;
 573
 574         /* All SDHI have SDIO status bits which must be 1 */
 575         mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS;
 576
 577         ret = tmio_mmc_host_probe(host, mmc_data, dma_ops);
 578         if (ret < 0)
 579                 goto efree;
 580
 581         /* Enable tuning iff we have an SCC and a supported mode */
 582         if (of_data && of_data->scc_offset &&
 583             (host->mmc->caps & MMC_CAP_UHS_SDR104 ||
 584              host->mmc->caps2 & MMC_CAP2_HS200_1_8V_SDR)) {
 585                 const struct renesas_sdhi_scc *taps = of_data->taps;
 586                 bool hit = false;
 587
 588                 host->mmc->caps |= MMC_CAP_HW_RESET;
 589
 590                 for (i = 0; i < of_data->taps_num; i++) {
 591                         if (taps[i].clk_rate == 0 ||
 592                             taps[i].clk_rate == host->mmc->f_max) {
 593                                 host->scc_tappos = taps->tap;
 594                                 hit = true;
 595                                 break;
 596                         }
 597                 }
 598
 599                 if (!hit)
 600                         dev_warn(&host->pdev->dev, "Unknown clock rate for SDR104\n");
 601
 602                 priv->scc_ctl = host->ctl + of_data->scc_offset;
 603                 host->init_tuning = renesas_sdhi_init_tuning;
 604                 host->prepare_tuning = renesas_sdhi_prepare_tuning;
 605                 host->select_tuning = renesas_sdhi_select_tuning;
 606                 host->check_scc_error = renesas_sdhi_check_scc_error;
 607                 host->hw_reset = renesas_sdhi_hw_reset;
 608         }
 609
 610         i = 0;
 611         while (1) {
 612                 irq = platform_get_irq(pdev, i);
 613                 if (irq < 0)
 614                         break;
 615                 i++;
 616                 ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0,
 617                                   dev_name(&pdev->dev), host);
 618                 if (ret)
 619                         goto eirq;
 620         }
 621
 622         /* There must be at least one IRQ source */
 623         if (!i) {
 624                 ret = irq;
 625                 goto eirq;
 626         }
 627
 628         dev_info(&pdev->dev, "%s base at 0x%08lx max clock rate %u MHz\n",
 629                  mmc_hostname(host->mmc), (unsigned long)
 630                  (platform_get_resource(pdev, IORESOURCE_MEM, 0)->start),
 631                  host->mmc->f_max / 1000000);
 632
 633         return ret;
 634
 635 eirq:
 636         tmio_mmc_host_remove(host);
 637 efree:
 638         tmio_mmc_host_free(host);
 639 eprobe:
 640         return ret;
 641 }
 642 EXPORT_SYMBOL_GPL(renesas_sdhi_probe);
 643
 644 int renesas_sdhi_remove(struct platform_device *pdev)
 645 {
 646         struct mmc_host *mmc = platform_get_drvdata(pdev);
 647         struct tmio_mmc_host *host = mmc_priv(mmc);
 648
 649         tmio_mmc_host_remove(host);
 650
 651         return 0;
 652 }
 653 EXPORT_SYMBOL_GPL(renesas_sdhi_remove);