2 * drivers/mmc/host/omap_hsmmc.c
4 * Driver for OMAP2430/3430 MMC controller.
6 * Copyright (C) 2007 Texas Instruments.
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/kernel.h>
21 #include <linux/debugfs.h>
22 #include <linux/seq_file.h>
23 #include <linux/interrupt.h>
24 #include <linux/delay.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/platform_device.h>
27 #include <linux/timer.h>
28 #include <linux/clk.h>
30 #include <linux/of_gpio.h>
31 #include <linux/of_device.h>
32 #include <linux/mmc/host.h>
33 #include <linux/mmc/core.h>
34 #include <linux/mmc/mmc.h>
36 #include <linux/semaphore.h>
37 #include <linux/gpio.h>
38 #include <linux/regulator/consumer.h>
39 #include <linux/pm_runtime.h>
41 #include <mach/hardware.h>
42 #include <plat/board.h>
46 /* OMAP HSMMC Host Controller Registers */
47 #define OMAP_HSMMC_SYSCONFIG 0x0010
48 #define OMAP_HSMMC_SYSSTATUS 0x0014
49 #define OMAP_HSMMC_CON 0x002C
50 #define OMAP_HSMMC_BLK 0x0104
51 #define OMAP_HSMMC_ARG 0x0108
52 #define OMAP_HSMMC_CMD 0x010C
53 #define OMAP_HSMMC_RSP10 0x0110
54 #define OMAP_HSMMC_RSP32 0x0114
55 #define OMAP_HSMMC_RSP54 0x0118
56 #define OMAP_HSMMC_RSP76 0x011C
57 #define OMAP_HSMMC_DATA 0x0120
58 #define OMAP_HSMMC_HCTL 0x0128
59 #define OMAP_HSMMC_SYSCTL 0x012C
60 #define OMAP_HSMMC_STAT 0x0130
61 #define OMAP_HSMMC_IE 0x0134
62 #define OMAP_HSMMC_ISE 0x0138
63 #define OMAP_HSMMC_CAPA 0x0140
65 #define VS18 (1 << 26)
66 #define VS30 (1 << 25)
67 #define SDVS18 (0x5 << 9)
68 #define SDVS30 (0x6 << 9)
69 #define SDVS33 (0x7 << 9)
70 #define SDVS_MASK 0x00000E00
71 #define SDVSCLR 0xFFFFF1FF
72 #define SDVSDET 0x00000400
79 #define CLKD_MASK 0x0000FFC0
81 #define DTO_MASK 0x000F0000
83 #define INT_EN_MASK 0x307F0033
84 #define BWR_ENABLE (1 << 4)
85 #define BRR_ENABLE (1 << 5)
86 #define DTO_ENABLE (1 << 20)
87 #define INIT_STREAM (1 << 1)
88 #define ACEN_ACMD12 (1 << 2)
89 #define DP_SELECT (1 << 21)
94 #define FOUR_BIT (1 << 1)
100 #define CMD_TIMEOUT (1 << 16)
101 #define DATA_TIMEOUT (1 << 20)
102 #define CMD_CRC (1 << 17)
103 #define DATA_CRC (1 << 21)
104 #define CARD_ERR (1 << 28)
105 #define STAT_CLEAR 0xFFFFFFFF
106 #define INIT_STREAM_CMD 0x00000000
107 #define DUAL_VOLT_OCR_BIT 7
108 #define SRC (1 << 25)
109 #define SRD (1 << 26)
110 #define SOFTRESET (1 << 1)
111 #define RESETDONE (1 << 0)
113 #define MMC_AUTOSUSPEND_DELAY 100
114 #define MMC_TIMEOUT_MS 20
115 #define OMAP_MMC_MIN_CLOCK 400000
116 #define OMAP_MMC_MAX_CLOCK 52000000
117 #define DRIVER_NAME "omap_hsmmc"
119 #define AUTO_CMD12 (1 << 0) /* Auto CMD12 support */
121 * One controller can have multiple slots, like on some omap boards using
122 * omap.c controller driver. Luckily this is not currently done on any known
123 * omap_hsmmc.c device.
125 #define mmc_slot(host) (host->pdata->slots[host->slot_id])
128 * MMC Host controller read/write API's
130 #define OMAP_HSMMC_READ(base, reg) \
131 __raw_readl((base) + OMAP_HSMMC_##reg)
133 #define OMAP_HSMMC_WRITE(base, reg, val) \
134 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
136 struct omap_hsmmc_next {
137 unsigned int dma_len;
141 struct omap_hsmmc_host {
143 struct mmc_host *mmc;
144 struct mmc_request *mrq;
145 struct mmc_command *cmd;
146 struct mmc_data *data;
150 * vcc == configured supply
151 * vcc_aux == optional
152 * - MMC1, supply for DAT4..DAT7
153 * - MMC2/MMC2, external level shifter voltage supply, for
154 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
156 struct regulator *vcc;
157 struct regulator *vcc_aux;
159 resource_size_t mapbase;
160 spinlock_t irq_lock; /* Prevent races with irq handler */
161 unsigned int dma_len;
162 unsigned int dma_sg_idx;
163 unsigned char bus_mode;
164 unsigned char power_mode;
170 int dma_line_tx, dma_line_rx;
181 struct omap_hsmmc_next next_data;
183 struct omap_mmc_platform_data *pdata;
186 static int omap_hsmmc_card_detect(struct device *dev, int slot)
188 struct omap_mmc_platform_data *mmc = dev->platform_data;
190 /* NOTE: assumes card detect signal is active-low */
191 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
194 static int omap_hsmmc_get_wp(struct device *dev, int slot)
196 struct omap_mmc_platform_data *mmc = dev->platform_data;
198 /* NOTE: assumes write protect signal is active-high */
199 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
202 static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
204 struct omap_mmc_platform_data *mmc = dev->platform_data;
206 /* NOTE: assumes card detect signal is active-low */
207 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
212 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
214 struct omap_mmc_platform_data *mmc = dev->platform_data;
216 disable_irq(mmc->slots[0].card_detect_irq);
220 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
222 struct omap_mmc_platform_data *mmc = dev->platform_data;
224 enable_irq(mmc->slots[0].card_detect_irq);
230 #define omap_hsmmc_suspend_cdirq NULL
231 #define omap_hsmmc_resume_cdirq NULL
235 #ifdef CONFIG_REGULATOR
237 static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on,
240 struct omap_hsmmc_host *host =
241 platform_get_drvdata(to_platform_device(dev));
245 * If we don't see a Vcc regulator, assume it's a fixed
246 * voltage always-on regulator.
251 * With DT, never turn OFF the regulator. This is because
252 * the pbias cell programming support is still missing when
253 * booting with Device tree
255 if (dev->of_node && !vdd)
258 if (mmc_slot(host).before_set_reg)
259 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
262 * Assume Vcc regulator is used only to power the card ... OMAP
263 * VDDS is used to power the pins, optionally with a transceiver to
264 * support cards using voltages other than VDDS (1.8V nominal). When a
265 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
267 * In some cases this regulator won't support enable/disable;
268 * e.g. it's a fixed rail for a WLAN chip.
270 * In other cases vcc_aux switches interface power. Example, for
271 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
272 * chips/cards need an interface voltage rail too.
275 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
276 /* Enable interface voltage rail, if needed */
277 if (ret == 0 && host->vcc_aux) {
278 ret = regulator_enable(host->vcc_aux);
280 ret = mmc_regulator_set_ocr(host->mmc,
284 /* Shut down the rail */
286 ret = regulator_disable(host->vcc_aux);
288 /* Then proceed to shut down the local regulator */
289 ret = mmc_regulator_set_ocr(host->mmc,
294 if (mmc_slot(host).after_set_reg)
295 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
300 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
302 struct regulator *reg;
305 mmc_slot(host).set_power = omap_hsmmc_set_power;
307 reg = regulator_get(host->dev, "vmmc");
309 dev_dbg(host->dev, "vmmc regulator missing\n");
312 ocr_value = mmc_regulator_get_ocrmask(reg);
313 if (!mmc_slot(host).ocr_mask) {
314 mmc_slot(host).ocr_mask = ocr_value;
316 if (!(mmc_slot(host).ocr_mask & ocr_value)) {
317 dev_err(host->dev, "ocrmask %x is not supported\n",
318 mmc_slot(host).ocr_mask);
319 mmc_slot(host).ocr_mask = 0;
324 /* Allow an aux regulator */
325 reg = regulator_get(host->dev, "vmmc_aux");
326 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
328 /* For eMMC do not power off when not in sleep state */
329 if (mmc_slot(host).no_regulator_off_init)
332 * UGLY HACK: workaround regulator framework bugs.
333 * When the bootloader leaves a supply active, it's
334 * initialized with zero usecount ... and we can't
335 * disable it without first enabling it. Until the
336 * framework is fixed, we need a workaround like this
337 * (which is safe for MMC, but not in general).
339 if (regulator_is_enabled(host->vcc) > 0 ||
340 (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
341 int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
343 mmc_slot(host).set_power(host->dev, host->slot_id,
345 mmc_slot(host).set_power(host->dev, host->slot_id,
353 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
355 regulator_put(host->vcc);
356 regulator_put(host->vcc_aux);
357 mmc_slot(host).set_power = NULL;
360 static inline int omap_hsmmc_have_reg(void)
367 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
372 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
376 static inline int omap_hsmmc_have_reg(void)
383 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
387 if (gpio_is_valid(pdata->slots[0].switch_pin)) {
388 if (pdata->slots[0].cover)
389 pdata->slots[0].get_cover_state =
390 omap_hsmmc_get_cover_state;
392 pdata->slots[0].card_detect = omap_hsmmc_card_detect;
393 pdata->slots[0].card_detect_irq =
394 gpio_to_irq(pdata->slots[0].switch_pin);
395 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
398 ret = gpio_direction_input(pdata->slots[0].switch_pin);
402 pdata->slots[0].switch_pin = -EINVAL;
404 if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
405 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
406 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
409 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
413 pdata->slots[0].gpio_wp = -EINVAL;
418 gpio_free(pdata->slots[0].gpio_wp);
420 if (gpio_is_valid(pdata->slots[0].switch_pin))
422 gpio_free(pdata->slots[0].switch_pin);
426 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
428 if (gpio_is_valid(pdata->slots[0].gpio_wp))
429 gpio_free(pdata->slots[0].gpio_wp);
430 if (gpio_is_valid(pdata->slots[0].switch_pin))
431 gpio_free(pdata->slots[0].switch_pin);
435 * Start clock to the card
437 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
439 OMAP_HSMMC_WRITE(host->base, SYSCTL,
440 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
444 * Stop clock to the card
446 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
448 OMAP_HSMMC_WRITE(host->base, SYSCTL,
449 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
450 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
451 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
454 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
455 struct mmc_command *cmd)
457 unsigned int irq_mask;
460 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
462 irq_mask = INT_EN_MASK;
464 /* Disable timeout for erases */
465 if (cmd->opcode == MMC_ERASE)
466 irq_mask &= ~DTO_ENABLE;
468 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
469 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
470 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
473 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
475 OMAP_HSMMC_WRITE(host->base, ISE, 0);
476 OMAP_HSMMC_WRITE(host->base, IE, 0);
477 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
480 /* Calculate divisor for the given clock frequency */
481 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
486 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
494 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
496 struct mmc_ios *ios = &host->mmc->ios;
497 unsigned long regval;
498 unsigned long timeout;
500 dev_dbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
502 omap_hsmmc_stop_clock(host);
504 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
505 regval = regval & ~(CLKD_MASK | DTO_MASK);
506 regval = regval | (calc_divisor(host, ios) << 6) | (DTO << 16);
507 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
508 OMAP_HSMMC_WRITE(host->base, SYSCTL,
509 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
511 /* Wait till the ICS bit is set */
512 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
513 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
514 && time_before(jiffies, timeout))
517 omap_hsmmc_start_clock(host);
520 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
522 struct mmc_ios *ios = &host->mmc->ios;
525 con = OMAP_HSMMC_READ(host->base, CON);
526 switch (ios->bus_width) {
527 case MMC_BUS_WIDTH_8:
528 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
530 case MMC_BUS_WIDTH_4:
531 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
532 OMAP_HSMMC_WRITE(host->base, HCTL,
533 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
535 case MMC_BUS_WIDTH_1:
536 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
537 OMAP_HSMMC_WRITE(host->base, HCTL,
538 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
543 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
545 struct mmc_ios *ios = &host->mmc->ios;
548 con = OMAP_HSMMC_READ(host->base, CON);
549 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
550 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
552 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
558 * Restore the MMC host context, if it was lost as result of a
559 * power state change.
561 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
563 struct mmc_ios *ios = &host->mmc->ios;
564 struct omap_mmc_platform_data *pdata = host->pdata;
565 int context_loss = 0;
567 unsigned long timeout;
569 if (pdata->get_context_loss_count) {
570 context_loss = pdata->get_context_loss_count(host->dev);
571 if (context_loss < 0)
575 dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
576 context_loss == host->context_loss ? "not " : "");
577 if (host->context_loss == context_loss)
580 /* Wait for hardware reset */
581 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
582 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
583 && time_before(jiffies, timeout))
586 /* Do software reset */
587 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
588 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
589 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
590 && time_before(jiffies, timeout))
593 OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
594 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
596 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
597 if (host->power_mode != MMC_POWER_OFF &&
598 (1 << ios->vdd) <= MMC_VDD_23_24)
608 OMAP_HSMMC_WRITE(host->base, HCTL,
609 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
611 OMAP_HSMMC_WRITE(host->base, CAPA,
612 OMAP_HSMMC_READ(host->base, CAPA) | capa);
614 OMAP_HSMMC_WRITE(host->base, HCTL,
615 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
617 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
618 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
619 && time_before(jiffies, timeout))
622 omap_hsmmc_disable_irq(host);
624 /* Do not initialize card-specific things if the power is off */
625 if (host->power_mode == MMC_POWER_OFF)
628 omap_hsmmc_set_bus_width(host);
630 omap_hsmmc_set_clock(host);
632 omap_hsmmc_set_bus_mode(host);
635 host->context_loss = context_loss;
637 dev_dbg(mmc_dev(host->mmc), "context is restored\n");
642 * Save the MMC host context (store the number of power state changes so far).
644 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
646 struct omap_mmc_platform_data *pdata = host->pdata;
649 if (pdata->get_context_loss_count) {
650 context_loss = pdata->get_context_loss_count(host->dev);
651 if (context_loss < 0)
653 host->context_loss = context_loss;
659 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
664 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
671 * Send init stream sequence to card
672 * before sending IDLE command
674 static void send_init_stream(struct omap_hsmmc_host *host)
677 unsigned long timeout;
679 if (host->protect_card)
682 disable_irq(host->irq);
684 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
685 OMAP_HSMMC_WRITE(host->base, CON,
686 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
687 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
689 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
690 while ((reg != CC) && time_before(jiffies, timeout))
691 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
693 OMAP_HSMMC_WRITE(host->base, CON,
694 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
696 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
697 OMAP_HSMMC_READ(host->base, STAT);
699 enable_irq(host->irq);
703 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
707 if (mmc_slot(host).get_cover_state)
708 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
713 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
716 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
717 struct omap_hsmmc_host *host = mmc_priv(mmc);
719 return sprintf(buf, "%s\n",
720 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
723 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
726 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
729 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
730 struct omap_hsmmc_host *host = mmc_priv(mmc);
732 return sprintf(buf, "%s\n", mmc_slot(host).name);
735 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
738 * Configure the response type and send the cmd.
741 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
742 struct mmc_data *data)
744 int cmdreg = 0, resptype = 0, cmdtype = 0;
746 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
747 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
750 omap_hsmmc_enable_irq(host, cmd);
752 host->response_busy = 0;
753 if (cmd->flags & MMC_RSP_PRESENT) {
754 if (cmd->flags & MMC_RSP_136)
756 else if (cmd->flags & MMC_RSP_BUSY) {
758 host->response_busy = 1;
764 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
765 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
766 * a val of 0x3, rest 0x0.
768 if (cmd == host->mrq->stop)
771 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
772 if ((host->flags & AUTO_CMD12) && mmc_op_multi(cmd->opcode))
773 cmdreg |= ACEN_ACMD12;
776 cmdreg |= DP_SELECT | MSBS | BCE;
777 if (data->flags & MMC_DATA_READ)
786 host->req_in_progress = 1;
788 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
789 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
793 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
795 if (data->flags & MMC_DATA_WRITE)
796 return DMA_TO_DEVICE;
798 return DMA_FROM_DEVICE;
801 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
805 spin_lock(&host->irq_lock);
806 host->req_in_progress = 0;
807 dma_ch = host->dma_ch;
808 spin_unlock(&host->irq_lock);
810 omap_hsmmc_disable_irq(host);
811 /* Do not complete the request if DMA is still in progress */
812 if (mrq->data && host->use_dma && dma_ch != -1)
815 mmc_request_done(host->mmc, mrq);
819 * Notify the transfer complete to MMC core
822 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
825 struct mmc_request *mrq = host->mrq;
827 /* TC before CC from CMD6 - don't know why, but it happens */
828 if (host->cmd && host->cmd->opcode == 6 &&
829 host->response_busy) {
830 host->response_busy = 0;
834 omap_hsmmc_request_done(host, mrq);
841 data->bytes_xfered += data->blocks * (data->blksz);
843 data->bytes_xfered = 0;
845 if (data->stop && ((!(host->flags & AUTO_CMD12)) || data->error)) {
846 omap_hsmmc_start_command(host, data->stop, NULL);
849 data->stop->resp[0] = OMAP_HSMMC_READ(host->base,
851 omap_hsmmc_request_done(host, data->mrq);
856 * Notify the core about command completion
859 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
863 if (cmd->flags & MMC_RSP_PRESENT) {
864 if (cmd->flags & MMC_RSP_136) {
865 /* response type 2 */
866 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
867 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
868 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
869 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
871 /* response types 1, 1b, 3, 4, 5, 6 */
872 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
875 if ((host->data == NULL && !host->response_busy) || cmd->error)
876 omap_hsmmc_request_done(host, cmd->mrq);
880 * DMA clean up for command errors
882 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
886 host->data->error = errno;
888 spin_lock(&host->irq_lock);
889 dma_ch = host->dma_ch;
891 spin_unlock(&host->irq_lock);
893 if (host->use_dma && dma_ch != -1) {
894 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg,
896 omap_hsmmc_get_dma_dir(host, host->data));
897 omap_free_dma(dma_ch);
898 host->data->host_cookie = 0;
904 * Readable error output
906 #ifdef CONFIG_MMC_DEBUG
907 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
909 /* --- means reserved bit without definition at documentation */
910 static const char *omap_hsmmc_status_bits[] = {
911 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
912 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
913 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
914 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
920 len = sprintf(buf, "MMC IRQ 0x%x :", status);
923 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
924 if (status & (1 << i)) {
925 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
929 dev_dbg(mmc_dev(host->mmc), "%s\n", res);
932 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
936 #endif /* CONFIG_MMC_DEBUG */
939 * MMC controller internal state machines reset
941 * Used to reset command or data internal state machines, using respectively
942 * SRC or SRD bit of SYSCTL register
943 * Can be called from interrupt context
945 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
949 unsigned long limit = (loops_per_jiffy *
950 msecs_to_jiffies(MMC_TIMEOUT_MS));
952 OMAP_HSMMC_WRITE(host->base, SYSCTL,
953 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
956 * OMAP4 ES2 and greater has an updated reset logic.
957 * Monitor a 0->1 transition first
959 if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
960 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
966 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
970 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
971 dev_err(mmc_dev(host->mmc),
972 "Timeout waiting on controller reset in %s\n",
976 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
978 struct mmc_data *data;
979 int end_cmd = 0, end_trans = 0;
981 if (!host->req_in_progress) {
983 OMAP_HSMMC_WRITE(host->base, STAT, status);
984 /* Flush posted write */
985 status = OMAP_HSMMC_READ(host->base, STAT);
986 } while (status & INT_EN_MASK);
991 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
994 omap_hsmmc_dbg_report_irq(host, status);
995 if ((status & CMD_TIMEOUT) ||
996 (status & CMD_CRC)) {
998 if (status & CMD_TIMEOUT) {
999 omap_hsmmc_reset_controller_fsm(host,
1001 host->cmd->error = -ETIMEDOUT;
1003 host->cmd->error = -EILSEQ;
1007 if (host->data || host->response_busy) {
1009 omap_hsmmc_dma_cleanup(host,
1011 host->response_busy = 0;
1012 omap_hsmmc_reset_controller_fsm(host, SRD);
1015 if ((status & DATA_TIMEOUT) ||
1016 (status & DATA_CRC)) {
1017 if (host->data || host->response_busy) {
1018 int err = (status & DATA_TIMEOUT) ?
1019 -ETIMEDOUT : -EILSEQ;
1022 omap_hsmmc_dma_cleanup(host, err);
1024 host->mrq->cmd->error = err;
1025 host->response_busy = 0;
1026 omap_hsmmc_reset_controller_fsm(host, SRD);
1030 if (status & CARD_ERR) {
1031 dev_dbg(mmc_dev(host->mmc),
1032 "Ignoring card err CMD%d\n", host->cmd->opcode);
1040 OMAP_HSMMC_WRITE(host->base, STAT, status);
1042 if (end_cmd || ((status & CC) && host->cmd))
1043 omap_hsmmc_cmd_done(host, host->cmd);
1044 if ((end_trans || (status & TC)) && host->mrq)
1045 omap_hsmmc_xfer_done(host, data);
1049 * MMC controller IRQ handler
1051 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1053 struct omap_hsmmc_host *host = dev_id;
1056 status = OMAP_HSMMC_READ(host->base, STAT);
1058 omap_hsmmc_do_irq(host, status);
1059 /* Flush posted write */
1060 status = OMAP_HSMMC_READ(host->base, STAT);
1061 } while (status & INT_EN_MASK);
1066 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1070 OMAP_HSMMC_WRITE(host->base, HCTL,
1071 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1072 for (i = 0; i < loops_per_jiffy; i++) {
1073 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1080 * Switch MMC interface voltage ... only relevant for MMC1.
1082 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1083 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1084 * Some chips, like eMMC ones, use internal transceivers.
1086 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1091 /* Disable the clocks */
1092 pm_runtime_put_sync(host->dev);
1093 if (host->got_dbclk)
1094 clk_disable(host->dbclk);
1096 /* Turn the power off */
1097 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1099 /* Turn the power ON with given VDD 1.8 or 3.0v */
1101 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1103 pm_runtime_get_sync(host->dev);
1104 if (host->got_dbclk)
1105 clk_enable(host->dbclk);
1110 OMAP_HSMMC_WRITE(host->base, HCTL,
1111 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1112 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1115 * If a MMC dual voltage card is detected, the set_ios fn calls
1116 * this fn with VDD bit set for 1.8V. Upon card removal from the
1117 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1119 * Cope with a bit of slop in the range ... per data sheets:
1120 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1121 * but recommended values are 1.71V to 1.89V
1122 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1123 * but recommended values are 2.7V to 3.3V
1125 * Board setup code shouldn't permit anything very out-of-range.
1126 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1127 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1129 if ((1 << vdd) <= MMC_VDD_23_24)
1134 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1135 set_sd_bus_power(host);
1139 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1143 /* Protect the card while the cover is open */
1144 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1146 if (!mmc_slot(host).get_cover_state)
1149 host->reqs_blocked = 0;
1150 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1151 if (host->protect_card) {
1152 dev_info(host->dev, "%s: cover is closed, "
1153 "card is now accessible\n",
1154 mmc_hostname(host->mmc));
1155 host->protect_card = 0;
1158 if (!host->protect_card) {
1159 dev_info(host->dev, "%s: cover is open, "
1160 "card is now inaccessible\n",
1161 mmc_hostname(host->mmc));
1162 host->protect_card = 1;
1168 * irq handler to notify the core about card insertion/removal
1170 static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
1172 struct omap_hsmmc_host *host = dev_id;
1173 struct omap_mmc_slot_data *slot = &mmc_slot(host);
1176 if (host->suspended)
1179 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1181 if (slot->card_detect)
1182 carddetect = slot->card_detect(host->dev, host->slot_id);
1184 omap_hsmmc_protect_card(host);
1185 carddetect = -ENOSYS;
1189 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1191 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1195 static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
1196 struct mmc_data *data)
1200 if (data->flags & MMC_DATA_WRITE)
1201 sync_dev = host->dma_line_tx;
1203 sync_dev = host->dma_line_rx;
1207 static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
1208 struct mmc_data *data,
1209 struct scatterlist *sgl)
1211 int blksz, nblk, dma_ch;
1213 dma_ch = host->dma_ch;
1214 if (data->flags & MMC_DATA_WRITE) {
1215 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1216 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1217 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1218 sg_dma_address(sgl), 0, 0);
1220 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1221 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1222 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1223 sg_dma_address(sgl), 0, 0);
1226 blksz = host->data->blksz;
1227 nblk = sg_dma_len(sgl) / blksz;
1229 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1230 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
1231 omap_hsmmc_get_dma_sync_dev(host, data),
1232 !(data->flags & MMC_DATA_WRITE));
1234 omap_start_dma(dma_ch);
1238 * DMA call back function
1240 static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data)
1242 struct omap_hsmmc_host *host = cb_data;
1243 struct mmc_data *data;
1244 int dma_ch, req_in_progress;
1246 if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
1247 dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
1252 spin_lock(&host->irq_lock);
1253 if (host->dma_ch < 0) {
1254 spin_unlock(&host->irq_lock);
1258 data = host->mrq->data;
1260 if (host->dma_sg_idx < host->dma_len) {
1261 /* Fire up the next transfer. */
1262 omap_hsmmc_config_dma_params(host, data,
1263 data->sg + host->dma_sg_idx);
1264 spin_unlock(&host->irq_lock);
1268 if (!data->host_cookie)
1269 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1270 omap_hsmmc_get_dma_dir(host, data));
1272 req_in_progress = host->req_in_progress;
1273 dma_ch = host->dma_ch;
1275 spin_unlock(&host->irq_lock);
1277 omap_free_dma(dma_ch);
1279 /* If DMA has finished after TC, complete the request */
1280 if (!req_in_progress) {
1281 struct mmc_request *mrq = host->mrq;
1284 mmc_request_done(host->mmc, mrq);
1288 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1289 struct mmc_data *data,
1290 struct omap_hsmmc_next *next)
1294 if (!next && data->host_cookie &&
1295 data->host_cookie != host->next_data.cookie) {
1296 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
1297 " host->next_data.cookie %d\n",
1298 __func__, data->host_cookie, host->next_data.cookie);
1299 data->host_cookie = 0;
1302 /* Check if next job is already prepared */
1304 (!next && data->host_cookie != host->next_data.cookie)) {
1305 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1307 omap_hsmmc_get_dma_dir(host, data));
1310 dma_len = host->next_data.dma_len;
1311 host->next_data.dma_len = 0;
1319 next->dma_len = dma_len;
1320 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1322 host->dma_len = dma_len;
1328 * Routine to configure and start DMA for the MMC card
1330 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1331 struct mmc_request *req)
1333 int dma_ch = 0, ret = 0, i;
1334 struct mmc_data *data = req->data;
1336 /* Sanity check: all the SG entries must be aligned by block size. */
1337 for (i = 0; i < data->sg_len; i++) {
1338 struct scatterlist *sgl;
1341 if (sgl->length % data->blksz)
1344 if ((data->blksz % 4) != 0)
1345 /* REVISIT: The MMC buffer increments only when MSB is written.
1346 * Return error for blksz which is non multiple of four.
1350 BUG_ON(host->dma_ch != -1);
1352 ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1353 "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
1355 dev_err(mmc_dev(host->mmc),
1356 "%s: omap_request_dma() failed with %d\n",
1357 mmc_hostname(host->mmc), ret);
1360 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL);
1364 host->dma_ch = dma_ch;
1365 host->dma_sg_idx = 0;
1367 omap_hsmmc_config_dma_params(host, data, data->sg);
1372 static void set_data_timeout(struct omap_hsmmc_host *host,
1373 unsigned int timeout_ns,
1374 unsigned int timeout_clks)
1376 unsigned int timeout, cycle_ns;
1377 uint32_t reg, clkd, dto = 0;
1379 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1380 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1384 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
1385 timeout = timeout_ns / cycle_ns;
1386 timeout += timeout_clks;
1388 while ((timeout & 0x80000000) == 0) {
1405 reg |= dto << DTO_SHIFT;
1406 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1410 * Configure block length for MMC/SD cards and initiate the transfer.
1413 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1416 host->data = req->data;
1418 if (req->data == NULL) {
1419 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1421 * Set an arbitrary 100ms data timeout for commands with
1424 if (req->cmd->flags & MMC_RSP_BUSY)
1425 set_data_timeout(host, 100000000U, 0);
1429 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1430 | (req->data->blocks << 16));
1431 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
1433 if (host->use_dma) {
1434 ret = omap_hsmmc_start_dma_transfer(host, req);
1436 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1443 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1446 struct omap_hsmmc_host *host = mmc_priv(mmc);
1447 struct mmc_data *data = mrq->data;
1449 if (host->use_dma) {
1450 if (data->host_cookie)
1451 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
1453 omap_hsmmc_get_dma_dir(host, data));
1454 data->host_cookie = 0;
1458 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1461 struct omap_hsmmc_host *host = mmc_priv(mmc);
1463 if (mrq->data->host_cookie) {
1464 mrq->data->host_cookie = 0;
1469 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1471 mrq->data->host_cookie = 0;
1475 * Request function. for read/write operation
1477 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1479 struct omap_hsmmc_host *host = mmc_priv(mmc);
1482 BUG_ON(host->req_in_progress);
1483 BUG_ON(host->dma_ch != -1);
1484 if (host->protect_card) {
1485 if (host->reqs_blocked < 3) {
1487 * Ensure the controller is left in a consistent
1488 * state by resetting the command and data state
1491 omap_hsmmc_reset_controller_fsm(host, SRD);
1492 omap_hsmmc_reset_controller_fsm(host, SRC);
1493 host->reqs_blocked += 1;
1495 req->cmd->error = -EBADF;
1497 req->data->error = -EBADF;
1498 req->cmd->retries = 0;
1499 mmc_request_done(mmc, req);
1501 } else if (host->reqs_blocked)
1502 host->reqs_blocked = 0;
1503 WARN_ON(host->mrq != NULL);
1505 err = omap_hsmmc_prepare_data(host, req);
1507 req->cmd->error = err;
1509 req->data->error = err;
1511 mmc_request_done(mmc, req);
1515 omap_hsmmc_start_command(host, req->cmd, req->data);
1518 /* Routine to configure clock values. Exposed API to core */
1519 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1521 struct omap_hsmmc_host *host = mmc_priv(mmc);
1522 int do_send_init_stream = 0;
1524 pm_runtime_get_sync(host->dev);
1526 if (ios->power_mode != host->power_mode) {
1527 switch (ios->power_mode) {
1529 mmc_slot(host).set_power(host->dev, host->slot_id,
1534 mmc_slot(host).set_power(host->dev, host->slot_id,
1536 host->vdd = ios->vdd;
1539 do_send_init_stream = 1;
1542 host->power_mode = ios->power_mode;
1545 /* FIXME: set registers based only on changes to ios */
1547 omap_hsmmc_set_bus_width(host);
1549 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1550 /* Only MMC1 can interface at 3V without some flavor
1551 * of external transceiver; but they all handle 1.8V.
1553 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1554 (ios->vdd == DUAL_VOLT_OCR_BIT) &&
1556 * With pbias cell programming missing, this
1557 * can't be allowed when booting with device
1560 !host->dev->of_node) {
1562 * The mmc_select_voltage fn of the core does
1563 * not seem to set the power_mode to
1564 * MMC_POWER_UP upon recalculating the voltage.
1567 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1568 dev_dbg(mmc_dev(host->mmc),
1569 "Switch operation failed\n");
1573 omap_hsmmc_set_clock(host);
1575 if (do_send_init_stream)
1576 send_init_stream(host);
1578 omap_hsmmc_set_bus_mode(host);
1580 pm_runtime_put_autosuspend(host->dev);
1583 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1585 struct omap_hsmmc_host *host = mmc_priv(mmc);
1587 if (!mmc_slot(host).card_detect)
1589 return mmc_slot(host).card_detect(host->dev, host->slot_id);
1592 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1594 struct omap_hsmmc_host *host = mmc_priv(mmc);
1596 if (!mmc_slot(host).get_ro)
1598 return mmc_slot(host).get_ro(host->dev, 0);
1601 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1603 struct omap_hsmmc_host *host = mmc_priv(mmc);
1605 if (mmc_slot(host).init_card)
1606 mmc_slot(host).init_card(card);
1609 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1611 u32 hctl, capa, value;
1613 /* Only MMC1 supports 3.0V */
1614 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1622 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1623 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1625 value = OMAP_HSMMC_READ(host->base, CAPA);
1626 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1628 /* Set the controller to AUTO IDLE mode */
1629 value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1630 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1632 /* Set SD bus power bit */
1633 set_sd_bus_power(host);
1636 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1638 struct omap_hsmmc_host *host = mmc_priv(mmc);
1640 pm_runtime_get_sync(host->dev);
1645 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc)
1647 struct omap_hsmmc_host *host = mmc_priv(mmc);
1649 pm_runtime_mark_last_busy(host->dev);
1650 pm_runtime_put_autosuspend(host->dev);
1655 static const struct mmc_host_ops omap_hsmmc_ops = {
1656 .enable = omap_hsmmc_enable_fclk,
1657 .disable = omap_hsmmc_disable_fclk,
1658 .post_req = omap_hsmmc_post_req,
1659 .pre_req = omap_hsmmc_pre_req,
1660 .request = omap_hsmmc_request,
1661 .set_ios = omap_hsmmc_set_ios,
1662 .get_cd = omap_hsmmc_get_cd,
1663 .get_ro = omap_hsmmc_get_ro,
1664 .init_card = omap_hsmmc_init_card,
1665 /* NYET -- enable_sdio_irq */
1668 #ifdef CONFIG_DEBUG_FS
1670 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1672 struct mmc_host *mmc = s->private;
1673 struct omap_hsmmc_host *host = mmc_priv(mmc);
1674 int context_loss = 0;
1676 if (host->pdata->get_context_loss_count)
1677 context_loss = host->pdata->get_context_loss_count(host->dev);
1679 seq_printf(s, "mmc%d:\n ctx_loss:\t%d:%d\n\nregs:\n",
1680 mmc->index, host->context_loss, context_loss);
1682 if (host->suspended) {
1683 seq_printf(s, "host suspended, can't read registers\n");
1687 pm_runtime_get_sync(host->dev);
1689 seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1690 OMAP_HSMMC_READ(host->base, SYSCONFIG));
1691 seq_printf(s, "CON:\t\t0x%08x\n",
1692 OMAP_HSMMC_READ(host->base, CON));
1693 seq_printf(s, "HCTL:\t\t0x%08x\n",
1694 OMAP_HSMMC_READ(host->base, HCTL));
1695 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1696 OMAP_HSMMC_READ(host->base, SYSCTL));
1697 seq_printf(s, "IE:\t\t0x%08x\n",
1698 OMAP_HSMMC_READ(host->base, IE));
1699 seq_printf(s, "ISE:\t\t0x%08x\n",
1700 OMAP_HSMMC_READ(host->base, ISE));
1701 seq_printf(s, "CAPA:\t\t0x%08x\n",
1702 OMAP_HSMMC_READ(host->base, CAPA));
1704 pm_runtime_mark_last_busy(host->dev);
1705 pm_runtime_put_autosuspend(host->dev);
1710 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1712 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1715 static const struct file_operations mmc_regs_fops = {
1716 .open = omap_hsmmc_regs_open,
1718 .llseek = seq_lseek,
1719 .release = single_release,
1722 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1724 if (mmc->debugfs_root)
1725 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1726 mmc, &mmc_regs_fops);
1731 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1738 static u16 omap4_reg_offset = 0x100;
1740 static const struct of_device_id omap_mmc_of_match[] = {
1742 .compatible = "ti,omap2-hsmmc",
1745 .compatible = "ti,omap3-hsmmc",
1748 .compatible = "ti,omap4-hsmmc",
1749 .data = &omap4_reg_offset,
1753 MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1755 static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1757 struct omap_mmc_platform_data *pdata;
1758 struct device_node *np = dev->of_node;
1761 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1763 return NULL; /* out of memory */
1765 if (of_find_property(np, "ti,dual-volt", NULL))
1766 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1768 /* This driver only supports 1 slot */
1769 pdata->nr_slots = 1;
1770 pdata->slots[0].switch_pin = of_get_named_gpio(np, "cd-gpios", 0);
1771 pdata->slots[0].gpio_wp = of_get_named_gpio(np, "wp-gpios", 0);
1773 if (of_find_property(np, "ti,non-removable", NULL)) {
1774 pdata->slots[0].nonremovable = true;
1775 pdata->slots[0].no_regulator_off_init = true;
1777 of_property_read_u32(np, "ti,bus-width", &bus_width);
1779 pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA;
1780 else if (bus_width == 8)
1781 pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA;
1783 if (of_find_property(np, "ti,needs-special-reset", NULL))
1784 pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
1789 static inline struct omap_mmc_platform_data
1790 *of_get_hsmmc_pdata(struct device *dev)
1796 static int __devinit omap_hsmmc_probe(struct platform_device *pdev)
1798 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1799 struct mmc_host *mmc;
1800 struct omap_hsmmc_host *host = NULL;
1801 struct resource *res;
1803 const struct of_device_id *match;
1805 match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
1807 pdata = of_get_hsmmc_pdata(&pdev->dev);
1809 u16 *offsetp = match->data;
1810 pdata->reg_offset = *offsetp;
1814 if (pdata == NULL) {
1815 dev_err(&pdev->dev, "Platform Data is missing\n");
1819 if (pdata->nr_slots == 0) {
1820 dev_err(&pdev->dev, "No Slots\n");
1824 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1825 irq = platform_get_irq(pdev, 0);
1826 if (res == NULL || irq < 0)
1829 res = request_mem_region(res->start, resource_size(res), pdev->name);
1833 ret = omap_hsmmc_gpio_init(pdata);
1837 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1843 host = mmc_priv(mmc);
1845 host->pdata = pdata;
1846 host->dev = &pdev->dev;
1848 host->dev->dma_mask = &pdata->dma_mask;
1852 host->mapbase = res->start + pdata->reg_offset;
1853 host->base = ioremap(host->mapbase, SZ_4K);
1854 host->power_mode = MMC_POWER_OFF;
1855 host->flags = AUTO_CMD12;
1856 host->next_data.cookie = 1;
1858 platform_set_drvdata(pdev, host);
1860 mmc->ops = &omap_hsmmc_ops;
1863 * If regulator_disable can only put vcc_aux to sleep then there is
1866 if (mmc_slot(host).vcc_aux_disable_is_sleep)
1867 mmc_slot(host).no_off = 1;
1869 mmc->f_min = OMAP_MMC_MIN_CLOCK;
1871 if (pdata->max_freq > 0)
1872 mmc->f_max = pdata->max_freq;
1874 mmc->f_max = OMAP_MMC_MAX_CLOCK;
1876 spin_lock_init(&host->irq_lock);
1878 host->fclk = clk_get(&pdev->dev, "fck");
1879 if (IS_ERR(host->fclk)) {
1880 ret = PTR_ERR(host->fclk);
1885 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
1886 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
1887 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
1890 pm_runtime_enable(host->dev);
1891 pm_runtime_get_sync(host->dev);
1892 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1893 pm_runtime_use_autosuspend(host->dev);
1895 omap_hsmmc_context_save(host);
1897 if (cpu_is_omap2430()) {
1898 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1900 * MMC can still work without debounce clock.
1902 if (IS_ERR(host->dbclk))
1903 dev_warn(mmc_dev(host->mmc),
1904 "Failed to get debounce clock\n");
1906 host->got_dbclk = 1;
1908 if (host->got_dbclk)
1909 if (clk_enable(host->dbclk) != 0)
1910 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1914 /* Since we do only SG emulation, we can have as many segs
1916 mmc->max_segs = 1024;
1918 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1919 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1920 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1921 mmc->max_seg_size = mmc->max_req_size;
1923 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1924 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
1926 mmc->caps |= mmc_slot(host).caps;
1927 if (mmc->caps & MMC_CAP_8_BIT_DATA)
1928 mmc->caps |= MMC_CAP_4_BIT_DATA;
1930 if (mmc_slot(host).nonremovable)
1931 mmc->caps |= MMC_CAP_NONREMOVABLE;
1933 mmc->pm_caps = mmc_slot(host).pm_caps;
1935 omap_hsmmc_conf_bus_power(host);
1937 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1939 dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
1942 host->dma_line_tx = res->start;
1944 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1946 dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
1949 host->dma_line_rx = res->start;
1951 /* Request IRQ for MMC operations */
1952 ret = request_irq(host->irq, omap_hsmmc_irq, 0,
1953 mmc_hostname(mmc), host);
1955 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1959 if (pdata->init != NULL) {
1960 if (pdata->init(&pdev->dev) != 0) {
1961 dev_dbg(mmc_dev(host->mmc),
1962 "Unable to configure MMC IRQs\n");
1963 goto err_irq_cd_init;
1967 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
1968 ret = omap_hsmmc_reg_get(host);
1974 mmc->ocr_avail = mmc_slot(host).ocr_mask;
1976 /* Request IRQ for card detect */
1977 if ((mmc_slot(host).card_detect_irq)) {
1978 ret = request_threaded_irq(mmc_slot(host).card_detect_irq,
1981 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
1982 mmc_hostname(mmc), host);
1984 dev_dbg(mmc_dev(host->mmc),
1985 "Unable to grab MMC CD IRQ\n");
1988 pdata->suspend = omap_hsmmc_suspend_cdirq;
1989 pdata->resume = omap_hsmmc_resume_cdirq;
1992 omap_hsmmc_disable_irq(host);
1994 omap_hsmmc_protect_card(host);
1998 if (mmc_slot(host).name != NULL) {
1999 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2003 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
2004 ret = device_create_file(&mmc->class_dev,
2005 &dev_attr_cover_switch);
2010 omap_hsmmc_debugfs(mmc);
2011 pm_runtime_mark_last_busy(host->dev);
2012 pm_runtime_put_autosuspend(host->dev);
2017 mmc_remove_host(mmc);
2018 free_irq(mmc_slot(host).card_detect_irq, host);
2021 omap_hsmmc_reg_put(host);
2023 if (host->pdata->cleanup)
2024 host->pdata->cleanup(&pdev->dev);
2026 free_irq(host->irq, host);
2028 pm_runtime_put_sync(host->dev);
2029 pm_runtime_disable(host->dev);
2030 clk_put(host->fclk);
2031 if (host->got_dbclk) {
2032 clk_disable(host->dbclk);
2033 clk_put(host->dbclk);
2036 iounmap(host->base);
2037 platform_set_drvdata(pdev, NULL);
2040 omap_hsmmc_gpio_free(pdata);
2042 release_mem_region(res->start, resource_size(res));
2046 static int __devexit omap_hsmmc_remove(struct platform_device *pdev)
2048 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2049 struct resource *res;
2051 pm_runtime_get_sync(host->dev);
2052 mmc_remove_host(host->mmc);
2054 omap_hsmmc_reg_put(host);
2055 if (host->pdata->cleanup)
2056 host->pdata->cleanup(&pdev->dev);
2057 free_irq(host->irq, host);
2058 if (mmc_slot(host).card_detect_irq)
2059 free_irq(mmc_slot(host).card_detect_irq, host);
2061 pm_runtime_put_sync(host->dev);
2062 pm_runtime_disable(host->dev);
2063 clk_put(host->fclk);
2064 if (host->got_dbclk) {
2065 clk_disable(host->dbclk);
2066 clk_put(host->dbclk);
2069 mmc_free_host(host->mmc);
2070 iounmap(host->base);
2071 omap_hsmmc_gpio_free(pdev->dev.platform_data);
2073 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2075 release_mem_region(res->start, resource_size(res));
2076 platform_set_drvdata(pdev, NULL);
2082 static int omap_hsmmc_suspend(struct device *dev)
2085 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2090 if (host && host->suspended)
2093 pm_runtime_get_sync(host->dev);
2094 host->suspended = 1;
2095 if (host->pdata->suspend) {
2096 ret = host->pdata->suspend(dev, host->slot_id);
2098 dev_dbg(dev, "Unable to handle MMC board"
2099 " level suspend\n");
2100 host->suspended = 0;
2104 ret = mmc_suspend_host(host->mmc);
2107 host->suspended = 0;
2108 if (host->pdata->resume) {
2109 ret = host->pdata->resume(dev, host->slot_id);
2111 dev_dbg(dev, "Unmask interrupt failed\n");
2116 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2117 omap_hsmmc_disable_irq(host);
2118 OMAP_HSMMC_WRITE(host->base, HCTL,
2119 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2122 if (host->got_dbclk)
2123 clk_disable(host->dbclk);
2125 pm_runtime_put_sync(host->dev);
2129 /* Routine to resume the MMC device */
2130 static int omap_hsmmc_resume(struct device *dev)
2133 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2138 if (host && !host->suspended)
2141 pm_runtime_get_sync(host->dev);
2143 if (host->got_dbclk)
2144 clk_enable(host->dbclk);
2146 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2147 omap_hsmmc_conf_bus_power(host);
2149 if (host->pdata->resume) {
2150 ret = host->pdata->resume(dev, host->slot_id);
2152 dev_dbg(dev, "Unmask interrupt failed\n");
2155 omap_hsmmc_protect_card(host);
2157 /* Notify the core to resume the host */
2158 ret = mmc_resume_host(host->mmc);
2160 host->suspended = 0;
2162 pm_runtime_mark_last_busy(host->dev);
2163 pm_runtime_put_autosuspend(host->dev);
2170 #define omap_hsmmc_suspend NULL
2171 #define omap_hsmmc_resume NULL
2174 static int omap_hsmmc_runtime_suspend(struct device *dev)
2176 struct omap_hsmmc_host *host;
2178 host = platform_get_drvdata(to_platform_device(dev));
2179 omap_hsmmc_context_save(host);
2180 dev_dbg(dev, "disabled\n");
2185 static int omap_hsmmc_runtime_resume(struct device *dev)
2187 struct omap_hsmmc_host *host;
2189 host = platform_get_drvdata(to_platform_device(dev));
2190 omap_hsmmc_context_restore(host);
2191 dev_dbg(dev, "enabled\n");
2196 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2197 .suspend = omap_hsmmc_suspend,
2198 .resume = omap_hsmmc_resume,
2199 .runtime_suspend = omap_hsmmc_runtime_suspend,
2200 .runtime_resume = omap_hsmmc_runtime_resume,
2203 static struct platform_driver omap_hsmmc_driver = {
2204 .probe = omap_hsmmc_probe,
2205 .remove = __devexit_p(omap_hsmmc_remove),
2207 .name = DRIVER_NAME,
2208 .owner = THIS_MODULE,
2209 .pm = &omap_hsmmc_dev_pm_ops,
2210 .of_match_table = of_match_ptr(omap_mmc_of_match),
2214 module_platform_driver(omap_hsmmc_driver);
2215 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2216 MODULE_LICENSE("GPL");
2217 MODULE_ALIAS("platform:" DRIVER_NAME);
2218 MODULE_AUTHOR("Texas Instruments Inc");