2 * drivers/mmc/host/omap_hsmmc.c
4 * Driver for OMAP2430/3430 MMC controller.
6 * Copyright (C) 2007 Texas Instruments.
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/debugfs.h>
21 #include <linux/seq_file.h>
22 #include <linux/interrupt.h>
23 #include <linux/delay.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/platform_device.h>
26 #include <linux/workqueue.h>
27 #include <linux/timer.h>
28 #include <linux/clk.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/core.h>
32 #include <linux/semaphore.h>
33 #include <linux/gpio.h>
34 #include <linux/regulator/consumer.h>
36 #include <mach/hardware.h>
37 #include <plat/board.h>
41 /* OMAP HSMMC Host Controller Registers */
42 #define OMAP_HSMMC_SYSCONFIG 0x0010
43 #define OMAP_HSMMC_SYSSTATUS 0x0014
44 #define OMAP_HSMMC_CON 0x002C
45 #define OMAP_HSMMC_BLK 0x0104
46 #define OMAP_HSMMC_ARG 0x0108
47 #define OMAP_HSMMC_CMD 0x010C
48 #define OMAP_HSMMC_RSP10 0x0110
49 #define OMAP_HSMMC_RSP32 0x0114
50 #define OMAP_HSMMC_RSP54 0x0118
51 #define OMAP_HSMMC_RSP76 0x011C
52 #define OMAP_HSMMC_DATA 0x0120
53 #define OMAP_HSMMC_HCTL 0x0128
54 #define OMAP_HSMMC_SYSCTL 0x012C
55 #define OMAP_HSMMC_STAT 0x0130
56 #define OMAP_HSMMC_IE 0x0134
57 #define OMAP_HSMMC_ISE 0x0138
58 #define OMAP_HSMMC_CAPA 0x0140
60 #define VS18 (1 << 26)
61 #define VS30 (1 << 25)
62 #define SDVS18 (0x5 << 9)
63 #define SDVS30 (0x6 << 9)
64 #define SDVS33 (0x7 << 9)
65 #define SDVS_MASK 0x00000E00
66 #define SDVSCLR 0xFFFFF1FF
67 #define SDVSDET 0x00000400
74 #define CLKD_MASK 0x0000FFC0
76 #define DTO_MASK 0x000F0000
78 #define INT_EN_MASK 0x307F0033
79 #define BWR_ENABLE (1 << 4)
80 #define BRR_ENABLE (1 << 5)
81 #define INIT_STREAM (1 << 1)
82 #define DP_SELECT (1 << 21)
87 #define FOUR_BIT (1 << 1)
93 #define CMD_TIMEOUT (1 << 16)
94 #define DATA_TIMEOUT (1 << 20)
95 #define CMD_CRC (1 << 17)
96 #define DATA_CRC (1 << 21)
97 #define CARD_ERR (1 << 28)
98 #define STAT_CLEAR 0xFFFFFFFF
99 #define INIT_STREAM_CMD 0x00000000
100 #define DUAL_VOLT_OCR_BIT 7
101 #define SRC (1 << 25)
102 #define SRD (1 << 26)
103 #define SOFTRESET (1 << 1)
104 #define RESETDONE (1 << 0)
107 * FIXME: Most likely all the data using these _DEVID defines should come
108 * from the platform_data, or implemented in controller and slot specific
111 #define OMAP_MMC1_DEVID 0
112 #define OMAP_MMC2_DEVID 1
113 #define OMAP_MMC3_DEVID 2
114 #define OMAP_MMC4_DEVID 3
115 #define OMAP_MMC5_DEVID 4
117 #define MMC_TIMEOUT_MS 20
118 #define OMAP_MMC_MASTER_CLOCK 96000000
119 #define DRIVER_NAME "mmci-omap-hs"
121 /* Timeouts for entering power saving states on inactivity, msec */
122 #define OMAP_MMC_DISABLED_TIMEOUT 100
123 #define OMAP_MMC_SLEEP_TIMEOUT 1000
124 #define OMAP_MMC_OFF_TIMEOUT 8000
127 * One controller can have multiple slots, like on some omap boards using
128 * omap.c controller driver. Luckily this is not currently done on any known
129 * omap_hsmmc.c device.
131 #define mmc_slot(host) (host->pdata->slots[host->slot_id])
134 * MMC Host controller read/write API's
136 #define OMAP_HSMMC_READ(base, reg) \
137 __raw_readl((base) + OMAP_HSMMC_##reg)
139 #define OMAP_HSMMC_WRITE(base, reg, val) \
140 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
142 struct omap_hsmmc_host {
144 struct mmc_host *mmc;
145 struct mmc_request *mrq;
146 struct mmc_command *cmd;
147 struct mmc_data *data;
152 * vcc == configured supply
153 * vcc_aux == optional
154 * - MMC1, supply for DAT4..DAT7
155 * - MMC2/MMC2, external level shifter voltage supply, for
156 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
158 struct regulator *vcc;
159 struct regulator *vcc_aux;
160 struct semaphore sem;
161 struct work_struct mmc_carddetect_work;
163 resource_size_t mapbase;
164 spinlock_t irq_lock; /* Prevent races with irq handler */
167 unsigned int dma_len;
168 unsigned int dma_sg_idx;
169 unsigned char bus_mode;
170 unsigned char power_mode;
176 int dma_line_tx, dma_line_rx;
187 struct omap_mmc_platform_data *pdata;
190 static int omap_hsmmc_card_detect(struct device *dev, int slot)
192 struct omap_mmc_platform_data *mmc = dev->platform_data;
194 /* NOTE: assumes card detect signal is active-low */
195 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
198 static int omap_hsmmc_get_wp(struct device *dev, int slot)
200 struct omap_mmc_platform_data *mmc = dev->platform_data;
202 /* NOTE: assumes write protect signal is active-high */
203 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
206 static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
208 struct omap_mmc_platform_data *mmc = dev->platform_data;
210 /* NOTE: assumes card detect signal is active-low */
211 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
216 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
218 struct omap_mmc_platform_data *mmc = dev->platform_data;
220 disable_irq(mmc->slots[0].card_detect_irq);
224 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
226 struct omap_mmc_platform_data *mmc = dev->platform_data;
228 enable_irq(mmc->slots[0].card_detect_irq);
234 #define omap_hsmmc_suspend_cdirq NULL
235 #define omap_hsmmc_resume_cdirq NULL
239 static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on,
242 struct omap_hsmmc_host *host =
243 platform_get_drvdata(to_platform_device(dev));
246 if (mmc_slot(host).before_set_reg)
247 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
250 ret = mmc_regulator_set_ocr(host->vcc, vdd);
252 ret = mmc_regulator_set_ocr(host->vcc, 0);
254 if (mmc_slot(host).after_set_reg)
255 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
260 static int omap_hsmmc_23_set_power(struct device *dev, int slot, int power_on,
263 struct omap_hsmmc_host *host =
264 platform_get_drvdata(to_platform_device(dev));
268 * If we don't see a Vcc regulator, assume it's a fixed
269 * voltage always-on regulator.
274 if (mmc_slot(host).before_set_reg)
275 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
278 * Assume Vcc regulator is used only to power the card ... OMAP
279 * VDDS is used to power the pins, optionally with a transceiver to
280 * support cards using voltages other than VDDS (1.8V nominal). When a
281 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
283 * In some cases this regulator won't support enable/disable;
284 * e.g. it's a fixed rail for a WLAN chip.
286 * In other cases vcc_aux switches interface power. Example, for
287 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
288 * chips/cards need an interface voltage rail too.
291 ret = mmc_regulator_set_ocr(host->vcc, vdd);
292 /* Enable interface voltage rail, if needed */
293 if (ret == 0 && host->vcc_aux) {
294 ret = regulator_enable(host->vcc_aux);
296 ret = mmc_regulator_set_ocr(host->vcc, 0);
300 ret = regulator_is_enabled(host->vcc_aux);
302 ret = regulator_disable(host->vcc_aux);
305 ret = mmc_regulator_set_ocr(host->vcc, 0);
308 if (mmc_slot(host).after_set_reg)
309 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
314 static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep,
315 int vdd, int cardsleep)
317 struct omap_hsmmc_host *host =
318 platform_get_drvdata(to_platform_device(dev));
319 int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
321 return regulator_set_mode(host->vcc, mode);
324 static int omap_hsmmc_23_set_sleep(struct device *dev, int slot, int sleep,
325 int vdd, int cardsleep)
327 struct omap_hsmmc_host *host =
328 platform_get_drvdata(to_platform_device(dev));
332 * If we don't see a Vcc regulator, assume it's a fixed
333 * voltage always-on regulator.
338 mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
341 return regulator_set_mode(host->vcc, mode);
344 /* VCC can be turned off if card is asleep */
346 err = mmc_regulator_set_ocr(host->vcc, 0);
348 err = mmc_regulator_set_ocr(host->vcc, vdd);
350 err = regulator_set_mode(host->vcc, mode);
353 return regulator_set_mode(host->vcc_aux, mode);
356 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
360 if (gpio_is_valid(pdata->slots[0].switch_pin)) {
361 pdata->suspend = omap_hsmmc_suspend_cdirq;
362 pdata->resume = omap_hsmmc_resume_cdirq;
363 if (pdata->slots[0].cover)
364 pdata->slots[0].get_cover_state =
365 omap_hsmmc_get_cover_state;
367 pdata->slots[0].card_detect = omap_hsmmc_card_detect;
368 pdata->slots[0].card_detect_irq =
369 gpio_to_irq(pdata->slots[0].switch_pin);
370 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
373 ret = gpio_direction_input(pdata->slots[0].switch_pin);
377 pdata->slots[0].switch_pin = -EINVAL;
379 if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
380 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
381 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
384 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
388 pdata->slots[0].gpio_wp = -EINVAL;
393 gpio_free(pdata->slots[0].gpio_wp);
395 if (gpio_is_valid(pdata->slots[0].switch_pin))
397 gpio_free(pdata->slots[0].switch_pin);
401 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
403 if (gpio_is_valid(pdata->slots[0].gpio_wp))
404 gpio_free(pdata->slots[0].gpio_wp);
405 if (gpio_is_valid(pdata->slots[0].switch_pin))
406 gpio_free(pdata->slots[0].switch_pin);
409 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
411 struct regulator *reg;
415 case OMAP_MMC1_DEVID:
416 /* On-chip level shifting via PBIAS0/PBIAS1 */
417 mmc_slot(host).set_power = omap_hsmmc_1_set_power;
418 mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep;
420 case OMAP_MMC2_DEVID:
421 case OMAP_MMC3_DEVID:
422 /* Off-chip level shifting, or none */
423 mmc_slot(host).set_power = omap_hsmmc_23_set_power;
424 mmc_slot(host).set_sleep = omap_hsmmc_23_set_sleep;
427 pr_err("MMC%d configuration not supported!\n", host->id);
431 reg = regulator_get(host->dev, "vmmc");
433 dev_dbg(host->dev, "vmmc regulator missing\n");
435 * HACK: until fixed.c regulator is usable,
436 * we don't require a main regulator
439 if (host->id == OMAP_MMC1_DEVID) {
445 mmc_slot(host).ocr_mask = mmc_regulator_get_ocrmask(reg);
447 /* Allow an aux regulator */
448 reg = regulator_get(host->dev, "vmmc_aux");
449 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
452 * UGLY HACK: workaround regulator framework bugs.
453 * When the bootloader leaves a supply active, it's
454 * initialized with zero usecount ... and we can't
455 * disable it without first enabling it. Until the
456 * framework is fixed, we need a workaround like this
457 * (which is safe for MMC, but not in general).
459 if (regulator_is_enabled(host->vcc) > 0) {
460 regulator_enable(host->vcc);
461 regulator_disable(host->vcc);
464 if (regulator_is_enabled(reg) > 0) {
465 regulator_enable(reg);
466 regulator_disable(reg);
474 mmc_slot(host).set_power = NULL;
475 mmc_slot(host).set_sleep = NULL;
479 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
481 regulator_put(host->vcc);
482 regulator_put(host->vcc_aux);
483 mmc_slot(host).set_power = NULL;
484 mmc_slot(host).set_sleep = NULL;
488 * Stop clock to the card
490 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
492 OMAP_HSMMC_WRITE(host->base, SYSCTL,
493 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
494 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
495 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
501 * Restore the MMC host context, if it was lost as result of a
502 * power state change.
504 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
506 struct mmc_ios *ios = &host->mmc->ios;
507 struct omap_mmc_platform_data *pdata = host->pdata;
508 int context_loss = 0;
511 unsigned long timeout;
513 if (pdata->get_context_loss_count) {
514 context_loss = pdata->get_context_loss_count(host->dev);
515 if (context_loss < 0)
519 dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
520 context_loss == host->context_loss ? "not " : "");
521 if (host->context_loss == context_loss)
524 /* Wait for hardware reset */
525 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
526 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
527 && time_before(jiffies, timeout))
530 /* Do software reset */
531 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
532 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
533 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
534 && time_before(jiffies, timeout))
537 OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
538 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
540 if (host->id == OMAP_MMC1_DEVID) {
541 if (host->power_mode != MMC_POWER_OFF &&
542 (1 << ios->vdd) <= MMC_VDD_23_24)
552 OMAP_HSMMC_WRITE(host->base, HCTL,
553 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
555 OMAP_HSMMC_WRITE(host->base, CAPA,
556 OMAP_HSMMC_READ(host->base, CAPA) | capa);
558 OMAP_HSMMC_WRITE(host->base, HCTL,
559 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
561 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
562 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
563 && time_before(jiffies, timeout))
566 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
567 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
568 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
570 /* Do not initialize card-specific things if the power is off */
571 if (host->power_mode == MMC_POWER_OFF)
574 con = OMAP_HSMMC_READ(host->base, CON);
575 switch (ios->bus_width) {
576 case MMC_BUS_WIDTH_8:
577 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
579 case MMC_BUS_WIDTH_4:
580 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
581 OMAP_HSMMC_WRITE(host->base, HCTL,
582 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
584 case MMC_BUS_WIDTH_1:
585 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
586 OMAP_HSMMC_WRITE(host->base, HCTL,
587 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
592 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
596 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
603 OMAP_HSMMC_WRITE(host->base, SYSCTL,
604 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
605 OMAP_HSMMC_WRITE(host->base, SYSCTL, (dsor << 6) | (DTO << 16));
606 OMAP_HSMMC_WRITE(host->base, SYSCTL,
607 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
609 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
610 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
611 && time_before(jiffies, timeout))
614 OMAP_HSMMC_WRITE(host->base, SYSCTL,
615 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
617 con = OMAP_HSMMC_READ(host->base, CON);
618 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
619 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
621 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
623 host->context_loss = context_loss;
625 dev_dbg(mmc_dev(host->mmc), "context is restored\n");
630 * Save the MMC host context (store the number of power state changes so far).
632 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
634 struct omap_mmc_platform_data *pdata = host->pdata;
637 if (pdata->get_context_loss_count) {
638 context_loss = pdata->get_context_loss_count(host->dev);
639 if (context_loss < 0)
641 host->context_loss = context_loss;
647 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
652 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
659 * Send init stream sequence to card
660 * before sending IDLE command
662 static void send_init_stream(struct omap_hsmmc_host *host)
665 unsigned long timeout;
667 if (host->protect_card)
670 disable_irq(host->irq);
671 OMAP_HSMMC_WRITE(host->base, CON,
672 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
673 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
675 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
676 while ((reg != CC) && time_before(jiffies, timeout))
677 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
679 OMAP_HSMMC_WRITE(host->base, CON,
680 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
682 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
683 OMAP_HSMMC_READ(host->base, STAT);
685 enable_irq(host->irq);
689 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
693 if (mmc_slot(host).get_cover_state)
694 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
699 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
702 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
703 struct omap_hsmmc_host *host = mmc_priv(mmc);
705 return sprintf(buf, "%s\n",
706 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
709 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
712 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
715 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
716 struct omap_hsmmc_host *host = mmc_priv(mmc);
718 return sprintf(buf, "%s\n", mmc_slot(host).name);
721 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
724 * Configure the response type and send the cmd.
727 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
728 struct mmc_data *data)
730 int cmdreg = 0, resptype = 0, cmdtype = 0;
732 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
733 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
737 * Clear status bits and enable interrupts
739 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
740 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
743 OMAP_HSMMC_WRITE(host->base, IE,
744 INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE));
746 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
748 host->response_busy = 0;
749 if (cmd->flags & MMC_RSP_PRESENT) {
750 if (cmd->flags & MMC_RSP_136)
752 else if (cmd->flags & MMC_RSP_BUSY) {
754 host->response_busy = 1;
760 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
761 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
762 * a val of 0x3, rest 0x0.
764 if (cmd == host->mrq->stop)
767 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
770 cmdreg |= DP_SELECT | MSBS | BCE;
771 if (data->flags & MMC_DATA_READ)
781 * In an interrupt context (i.e. STOP command), the spinlock is unlocked
782 * by the interrupt handler, otherwise (i.e. for a new request) it is
786 spin_unlock_irqrestore(&host->irq_lock, host->flags);
788 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
789 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
793 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
795 if (data->flags & MMC_DATA_WRITE)
796 return DMA_TO_DEVICE;
798 return DMA_FROM_DEVICE;
802 * Notify the transfer complete to MMC core
805 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
808 struct mmc_request *mrq = host->mrq;
810 /* TC before CC from CMD6 - don't know why, but it happens */
811 if (host->cmd && host->cmd->opcode == 6 &&
812 host->response_busy) {
813 host->response_busy = 0;
818 mmc_request_done(host->mmc, mrq);
824 if (host->use_dma && host->dma_ch != -1)
825 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
826 omap_hsmmc_get_dma_dir(host, data));
829 data->bytes_xfered += data->blocks * (data->blksz);
831 data->bytes_xfered = 0;
835 mmc_request_done(host->mmc, data->mrq);
838 omap_hsmmc_start_command(host, data->stop, NULL);
842 * Notify the core about command completion
845 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
849 if (cmd->flags & MMC_RSP_PRESENT) {
850 if (cmd->flags & MMC_RSP_136) {
851 /* response type 2 */
852 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
853 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
854 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
855 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
857 /* response types 1, 1b, 3, 4, 5, 6 */
858 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
861 if ((host->data == NULL && !host->response_busy) || cmd->error) {
863 mmc_request_done(host->mmc, cmd->mrq);
868 * DMA clean up for command errors
870 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
872 host->data->error = errno;
874 if (host->use_dma && host->dma_ch != -1) {
875 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
876 omap_hsmmc_get_dma_dir(host, host->data));
877 omap_free_dma(host->dma_ch);
885 * Readable error output
887 #ifdef CONFIG_MMC_DEBUG
888 static void omap_hsmmc_report_irq(struct omap_hsmmc_host *host, u32 status)
890 /* --- means reserved bit without definition at documentation */
891 static const char *omap_hsmmc_status_bits[] = {
892 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
893 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
894 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
895 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
901 len = sprintf(buf, "MMC IRQ 0x%x :", status);
904 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
905 if (status & (1 << i)) {
906 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
910 dev_dbg(mmc_dev(host->mmc), "%s\n", res);
912 #endif /* CONFIG_MMC_DEBUG */
915 * MMC controller internal state machines reset
917 * Used to reset command or data internal state machines, using respectively
918 * SRC or SRD bit of SYSCTL register
919 * Can be called from interrupt context
921 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
925 unsigned long limit = (loops_per_jiffy *
926 msecs_to_jiffies(MMC_TIMEOUT_MS));
928 OMAP_HSMMC_WRITE(host->base, SYSCTL,
929 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
931 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
935 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
936 dev_err(mmc_dev(host->mmc),
937 "Timeout waiting on controller reset in %s\n",
942 * MMC controller IRQ handler
944 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
946 struct omap_hsmmc_host *host = dev_id;
947 struct mmc_data *data;
948 int end_cmd = 0, end_trans = 0, status;
950 spin_lock(&host->irq_lock);
952 if (host->mrq == NULL) {
953 OMAP_HSMMC_WRITE(host->base, STAT,
954 OMAP_HSMMC_READ(host->base, STAT));
955 /* Flush posted write */
956 OMAP_HSMMC_READ(host->base, STAT);
957 spin_unlock(&host->irq_lock);
962 status = OMAP_HSMMC_READ(host->base, STAT);
963 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
966 #ifdef CONFIG_MMC_DEBUG
967 omap_hsmmc_report_irq(host, status);
969 if ((status & CMD_TIMEOUT) ||
970 (status & CMD_CRC)) {
972 if (status & CMD_TIMEOUT) {
973 omap_hsmmc_reset_controller_fsm(host,
975 host->cmd->error = -ETIMEDOUT;
977 host->cmd->error = -EILSEQ;
981 if (host->data || host->response_busy) {
983 omap_hsmmc_dma_cleanup(host,
985 host->response_busy = 0;
986 omap_hsmmc_reset_controller_fsm(host, SRD);
989 if ((status & DATA_TIMEOUT) ||
990 (status & DATA_CRC)) {
991 if (host->data || host->response_busy) {
992 int err = (status & DATA_TIMEOUT) ?
993 -ETIMEDOUT : -EILSEQ;
996 omap_hsmmc_dma_cleanup(host, err);
998 host->mrq->cmd->error = err;
999 host->response_busy = 0;
1000 omap_hsmmc_reset_controller_fsm(host, SRD);
1004 if (status & CARD_ERR) {
1005 dev_dbg(mmc_dev(host->mmc),
1006 "Ignoring card err CMD%d\n", host->cmd->opcode);
1014 OMAP_HSMMC_WRITE(host->base, STAT, status);
1015 /* Flush posted write */
1016 OMAP_HSMMC_READ(host->base, STAT);
1018 if (end_cmd || ((status & CC) && host->cmd))
1019 omap_hsmmc_cmd_done(host, host->cmd);
1020 if ((end_trans || (status & TC)) && host->mrq)
1021 omap_hsmmc_xfer_done(host, data);
1023 spin_unlock(&host->irq_lock);
1028 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1032 OMAP_HSMMC_WRITE(host->base, HCTL,
1033 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1034 for (i = 0; i < loops_per_jiffy; i++) {
1035 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1042 * Switch MMC interface voltage ... only relevant for MMC1.
1044 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1045 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1046 * Some chips, like eMMC ones, use internal transceivers.
1048 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1053 /* Disable the clocks */
1054 clk_disable(host->fclk);
1055 clk_disable(host->iclk);
1056 if (host->got_dbclk)
1057 clk_disable(host->dbclk);
1059 /* Turn the power off */
1060 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1062 /* Turn the power ON with given VDD 1.8 or 3.0v */
1064 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1066 clk_enable(host->iclk);
1067 clk_enable(host->fclk);
1068 if (host->got_dbclk)
1069 clk_enable(host->dbclk);
1074 OMAP_HSMMC_WRITE(host->base, HCTL,
1075 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1076 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1079 * If a MMC dual voltage card is detected, the set_ios fn calls
1080 * this fn with VDD bit set for 1.8V. Upon card removal from the
1081 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1083 * Cope with a bit of slop in the range ... per data sheets:
1084 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1085 * but recommended values are 1.71V to 1.89V
1086 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1087 * but recommended values are 2.7V to 3.3V
1089 * Board setup code shouldn't permit anything very out-of-range.
1090 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1091 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1093 if ((1 << vdd) <= MMC_VDD_23_24)
1098 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1099 set_sd_bus_power(host);
1103 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1107 /* Protect the card while the cover is open */
1108 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1110 if (!mmc_slot(host).get_cover_state)
1113 host->reqs_blocked = 0;
1114 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1115 if (host->protect_card) {
1116 printk(KERN_INFO "%s: cover is closed, "
1117 "card is now accessible\n",
1118 mmc_hostname(host->mmc));
1119 host->protect_card = 0;
1122 if (!host->protect_card) {
1123 printk(KERN_INFO "%s: cover is open, "
1124 "card is now inaccessible\n",
1125 mmc_hostname(host->mmc));
1126 host->protect_card = 1;
1132 * Work Item to notify the core about card insertion/removal
1134 static void omap_hsmmc_detect(struct work_struct *work)
1136 struct omap_hsmmc_host *host =
1137 container_of(work, struct omap_hsmmc_host, mmc_carddetect_work);
1138 struct omap_mmc_slot_data *slot = &mmc_slot(host);
1141 if (host->suspended)
1144 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1146 if (slot->card_detect)
1147 carddetect = slot->card_detect(host->dev, host->slot_id);
1149 omap_hsmmc_protect_card(host);
1150 carddetect = -ENOSYS;
1154 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1156 mmc_host_enable(host->mmc);
1157 omap_hsmmc_reset_controller_fsm(host, SRD);
1158 mmc_host_lazy_disable(host->mmc);
1160 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1165 * ISR for handling card insertion and removal
1167 static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id)
1169 struct omap_hsmmc_host *host = (struct omap_hsmmc_host *)dev_id;
1171 if (host->suspended)
1173 schedule_work(&host->mmc_carddetect_work);
1178 static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
1179 struct mmc_data *data)
1183 if (data->flags & MMC_DATA_WRITE)
1184 sync_dev = host->dma_line_tx;
1186 sync_dev = host->dma_line_rx;
1190 static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
1191 struct mmc_data *data,
1192 struct scatterlist *sgl)
1194 int blksz, nblk, dma_ch;
1196 dma_ch = host->dma_ch;
1197 if (data->flags & MMC_DATA_WRITE) {
1198 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1199 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1200 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1201 sg_dma_address(sgl), 0, 0);
1203 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1204 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1205 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1206 sg_dma_address(sgl), 0, 0);
1209 blksz = host->data->blksz;
1210 nblk = sg_dma_len(sgl) / blksz;
1212 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1213 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
1214 omap_hsmmc_get_dma_sync_dev(host, data),
1215 !(data->flags & MMC_DATA_WRITE));
1217 omap_start_dma(dma_ch);
1221 * DMA call back function
1223 static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *data)
1225 struct omap_hsmmc_host *host = data;
1227 if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
1228 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
1230 if (host->dma_ch < 0)
1234 if (host->dma_sg_idx < host->dma_len) {
1235 /* Fire up the next transfer. */
1236 omap_hsmmc_config_dma_params(host, host->data,
1237 host->data->sg + host->dma_sg_idx);
1241 omap_free_dma(host->dma_ch);
1244 * DMA Callback: run in interrupt context.
1245 * mutex_unlock will throw a kernel warning if used.
1251 * Routine to configure and start DMA for the MMC card
1253 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1254 struct mmc_request *req)
1256 int dma_ch = 0, ret = 0, err = 1, i;
1257 struct mmc_data *data = req->data;
1259 /* Sanity check: all the SG entries must be aligned by block size. */
1260 for (i = 0; i < data->sg_len; i++) {
1261 struct scatterlist *sgl;
1264 if (sgl->length % data->blksz)
1267 if ((data->blksz % 4) != 0)
1268 /* REVISIT: The MMC buffer increments only when MSB is written.
1269 * Return error for blksz which is non multiple of four.
1274 * If for some reason the DMA transfer is still active,
1275 * we wait for timeout period and free the dma
1277 if (host->dma_ch != -1) {
1278 set_current_state(TASK_UNINTERRUPTIBLE);
1279 schedule_timeout(100);
1280 if (down_trylock(&host->sem)) {
1281 omap_free_dma(host->dma_ch);
1287 if (down_trylock(&host->sem))
1291 ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1292 "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
1294 dev_err(mmc_dev(host->mmc),
1295 "%s: omap_request_dma() failed with %d\n",
1296 mmc_hostname(host->mmc), ret);
1300 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1301 data->sg_len, omap_hsmmc_get_dma_dir(host, data));
1302 host->dma_ch = dma_ch;
1303 host->dma_sg_idx = 0;
1305 omap_hsmmc_config_dma_params(host, data, data->sg);
1310 static void set_data_timeout(struct omap_hsmmc_host *host,
1311 unsigned int timeout_ns,
1312 unsigned int timeout_clks)
1314 unsigned int timeout, cycle_ns;
1315 uint32_t reg, clkd, dto = 0;
1317 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1318 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1322 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
1323 timeout = timeout_ns / cycle_ns;
1324 timeout += timeout_clks;
1326 while ((timeout & 0x80000000) == 0) {
1343 reg |= dto << DTO_SHIFT;
1344 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1348 * Configure block length for MMC/SD cards and initiate the transfer.
1351 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1354 host->data = req->data;
1356 if (req->data == NULL) {
1357 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1359 * Set an arbitrary 100ms data timeout for commands with
1362 if (req->cmd->flags & MMC_RSP_BUSY)
1363 set_data_timeout(host, 100000000U, 0);
1367 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1368 | (req->data->blocks << 16));
1369 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
1371 if (host->use_dma) {
1372 ret = omap_hsmmc_start_dma_transfer(host, req);
1374 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1382 * Request function. for read/write operation
1384 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1386 struct omap_hsmmc_host *host = mmc_priv(mmc);
1390 * Prevent races with the interrupt handler because of unexpected
1391 * interrupts, but not if we are already in interrupt context i.e.
1394 if (!in_interrupt()) {
1395 spin_lock_irqsave(&host->irq_lock, host->flags);
1397 * Protect the card from I/O if there is a possibility
1398 * it can be removed.
1400 if (host->protect_card) {
1401 if (host->reqs_blocked < 3) {
1403 * Ensure the controller is left in a consistent
1404 * state by resetting the command and data state
1407 omap_hsmmc_reset_controller_fsm(host, SRD);
1408 omap_hsmmc_reset_controller_fsm(host, SRC);
1409 host->reqs_blocked += 1;
1411 req->cmd->error = -EBADF;
1413 req->data->error = -EBADF;
1414 spin_unlock_irqrestore(&host->irq_lock, host->flags);
1415 mmc_request_done(mmc, req);
1417 } else if (host->reqs_blocked)
1418 host->reqs_blocked = 0;
1420 WARN_ON(host->mrq != NULL);
1422 err = omap_hsmmc_prepare_data(host, req);
1424 req->cmd->error = err;
1426 req->data->error = err;
1428 if (!in_interrupt())
1429 spin_unlock_irqrestore(&host->irq_lock, host->flags);
1430 mmc_request_done(mmc, req);
1434 omap_hsmmc_start_command(host, req->cmd, req->data);
1437 /* Routine to configure clock values. Exposed API to core */
1438 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1440 struct omap_hsmmc_host *host = mmc_priv(mmc);
1442 unsigned long regval;
1443 unsigned long timeout;
1445 int do_send_init_stream = 0;
1447 mmc_host_enable(host->mmc);
1449 if (ios->power_mode != host->power_mode) {
1450 switch (ios->power_mode) {
1452 mmc_slot(host).set_power(host->dev, host->slot_id,
1457 mmc_slot(host).set_power(host->dev, host->slot_id,
1459 host->vdd = ios->vdd;
1462 do_send_init_stream = 1;
1465 host->power_mode = ios->power_mode;
1468 /* FIXME: set registers based only on changes to ios */
1470 con = OMAP_HSMMC_READ(host->base, CON);
1471 switch (mmc->ios.bus_width) {
1472 case MMC_BUS_WIDTH_8:
1473 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
1475 case MMC_BUS_WIDTH_4:
1476 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
1477 OMAP_HSMMC_WRITE(host->base, HCTL,
1478 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
1480 case MMC_BUS_WIDTH_1:
1481 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
1482 OMAP_HSMMC_WRITE(host->base, HCTL,
1483 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
1487 if (host->id == OMAP_MMC1_DEVID) {
1488 /* Only MMC1 can interface at 3V without some flavor
1489 * of external transceiver; but they all handle 1.8V.
1491 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1492 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1494 * The mmc_select_voltage fn of the core does
1495 * not seem to set the power_mode to
1496 * MMC_POWER_UP upon recalculating the voltage.
1499 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1500 dev_dbg(mmc_dev(host->mmc),
1501 "Switch operation failed\n");
1506 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
1510 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
1516 omap_hsmmc_stop_clock(host);
1517 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
1518 regval = regval & ~(CLKD_MASK);
1519 regval = regval | (dsor << 6) | (DTO << 16);
1520 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
1521 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1522 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
1524 /* Wait till the ICS bit is set */
1525 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
1526 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
1527 && time_before(jiffies, timeout))
1530 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1531 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
1533 if (do_send_init_stream)
1534 send_init_stream(host);
1536 con = OMAP_HSMMC_READ(host->base, CON);
1537 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
1538 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
1540 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
1542 if (host->power_mode == MMC_POWER_OFF)
1543 mmc_host_disable(host->mmc);
1545 mmc_host_lazy_disable(host->mmc);
1548 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1550 struct omap_hsmmc_host *host = mmc_priv(mmc);
1552 if (!mmc_slot(host).card_detect)
1554 return mmc_slot(host).card_detect(host->dev, host->slot_id);
1557 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1559 struct omap_hsmmc_host *host = mmc_priv(mmc);
1561 if (!mmc_slot(host).get_ro)
1563 return mmc_slot(host).get_ro(host->dev, 0);
1566 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1568 u32 hctl, capa, value;
1570 /* Only MMC1 supports 3.0V */
1571 if (host->id == OMAP_MMC1_DEVID) {
1579 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1580 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1582 value = OMAP_HSMMC_READ(host->base, CAPA);
1583 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1585 /* Set the controller to AUTO IDLE mode */
1586 value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1587 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1589 /* Set SD bus power bit */
1590 set_sd_bus_power(host);
1594 * Dynamic power saving handling, FSM:
1595 * ENABLED -> DISABLED -> CARDSLEEP / REGSLEEP -> OFF
1597 * |______________________|______________________|
1599 * ENABLED: mmc host is fully functional
1600 * DISABLED: fclk is off
1601 * CARDSLEEP: fclk is off, card is asleep, voltage regulator is asleep
1602 * REGSLEEP: fclk is off, voltage regulator is asleep
1603 * OFF: fclk is off, voltage regulator is off
1605 * Transition handlers return the timeout for the next state transition
1606 * or negative error.
1609 enum {ENABLED = 0, DISABLED, CARDSLEEP, REGSLEEP, OFF};
1611 /* Handler for [ENABLED -> DISABLED] transition */
1612 static int omap_hsmmc_enabled_to_disabled(struct omap_hsmmc_host *host)
1614 omap_hsmmc_context_save(host);
1615 clk_disable(host->fclk);
1616 host->dpm_state = DISABLED;
1618 dev_dbg(mmc_dev(host->mmc), "ENABLED -> DISABLED\n");
1620 if (host->power_mode == MMC_POWER_OFF)
1623 return msecs_to_jiffies(OMAP_MMC_SLEEP_TIMEOUT);
1626 /* Handler for [DISABLED -> REGSLEEP / CARDSLEEP] transition */
1627 static int omap_hsmmc_disabled_to_sleep(struct omap_hsmmc_host *host)
1631 if (!mmc_try_claim_host(host->mmc))
1634 clk_enable(host->fclk);
1635 omap_hsmmc_context_restore(host);
1636 if (mmc_card_can_sleep(host->mmc)) {
1637 err = mmc_card_sleep(host->mmc);
1639 clk_disable(host->fclk);
1640 mmc_release_host(host->mmc);
1643 new_state = CARDSLEEP;
1645 new_state = REGSLEEP;
1647 if (mmc_slot(host).set_sleep)
1648 mmc_slot(host).set_sleep(host->dev, host->slot_id, 1, 0,
1649 new_state == CARDSLEEP);
1650 /* FIXME: turn off bus power and perhaps interrupts too */
1651 clk_disable(host->fclk);
1652 host->dpm_state = new_state;
1654 mmc_release_host(host->mmc);
1656 dev_dbg(mmc_dev(host->mmc), "DISABLED -> %s\n",
1657 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
1659 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
1660 mmc_slot(host).card_detect ||
1661 (mmc_slot(host).get_cover_state &&
1662 mmc_slot(host).get_cover_state(host->dev, host->slot_id)))
1663 return msecs_to_jiffies(OMAP_MMC_OFF_TIMEOUT);
1668 /* Handler for [REGSLEEP / CARDSLEEP -> OFF] transition */
1669 static int omap_hsmmc_sleep_to_off(struct omap_hsmmc_host *host)
1671 if (!mmc_try_claim_host(host->mmc))
1674 if (!((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
1675 mmc_slot(host).card_detect ||
1676 (mmc_slot(host).get_cover_state &&
1677 mmc_slot(host).get_cover_state(host->dev, host->slot_id)))) {
1678 mmc_release_host(host->mmc);
1682 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1684 host->power_mode = MMC_POWER_OFF;
1686 dev_dbg(mmc_dev(host->mmc), "%s -> OFF\n",
1687 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
1689 host->dpm_state = OFF;
1691 mmc_release_host(host->mmc);
1696 /* Handler for [DISABLED -> ENABLED] transition */
1697 static int omap_hsmmc_disabled_to_enabled(struct omap_hsmmc_host *host)
1701 err = clk_enable(host->fclk);
1705 omap_hsmmc_context_restore(host);
1706 host->dpm_state = ENABLED;
1708 dev_dbg(mmc_dev(host->mmc), "DISABLED -> ENABLED\n");
1713 /* Handler for [SLEEP -> ENABLED] transition */
1714 static int omap_hsmmc_sleep_to_enabled(struct omap_hsmmc_host *host)
1716 if (!mmc_try_claim_host(host->mmc))
1719 clk_enable(host->fclk);
1720 omap_hsmmc_context_restore(host);
1721 if (mmc_slot(host).set_sleep)
1722 mmc_slot(host).set_sleep(host->dev, host->slot_id, 0,
1723 host->vdd, host->dpm_state == CARDSLEEP);
1724 if (mmc_card_can_sleep(host->mmc))
1725 mmc_card_awake(host->mmc);
1727 dev_dbg(mmc_dev(host->mmc), "%s -> ENABLED\n",
1728 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
1730 host->dpm_state = ENABLED;
1732 mmc_release_host(host->mmc);
1737 /* Handler for [OFF -> ENABLED] transition */
1738 static int omap_hsmmc_off_to_enabled(struct omap_hsmmc_host *host)
1740 clk_enable(host->fclk);
1742 omap_hsmmc_context_restore(host);
1743 omap_hsmmc_conf_bus_power(host);
1744 mmc_power_restore_host(host->mmc);
1746 host->dpm_state = ENABLED;
1748 dev_dbg(mmc_dev(host->mmc), "OFF -> ENABLED\n");
1754 * Bring MMC host to ENABLED from any other PM state.
1756 static int omap_hsmmc_enable(struct mmc_host *mmc)
1758 struct omap_hsmmc_host *host = mmc_priv(mmc);
1760 switch (host->dpm_state) {
1762 return omap_hsmmc_disabled_to_enabled(host);
1765 return omap_hsmmc_sleep_to_enabled(host);
1767 return omap_hsmmc_off_to_enabled(host);
1769 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1775 * Bring MMC host in PM state (one level deeper).
1777 static int omap_hsmmc_disable(struct mmc_host *mmc, int lazy)
1779 struct omap_hsmmc_host *host = mmc_priv(mmc);
1781 switch (host->dpm_state) {
1785 delay = omap_hsmmc_enabled_to_disabled(host);
1786 if (lazy || delay < 0)
1791 return omap_hsmmc_disabled_to_sleep(host);
1794 return omap_hsmmc_sleep_to_off(host);
1796 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1801 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1803 struct omap_hsmmc_host *host = mmc_priv(mmc);
1806 err = clk_enable(host->fclk);
1809 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: enabled\n");
1810 omap_hsmmc_context_restore(host);
1814 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
1816 struct omap_hsmmc_host *host = mmc_priv(mmc);
1818 omap_hsmmc_context_save(host);
1819 clk_disable(host->fclk);
1820 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n");
1824 static const struct mmc_host_ops omap_hsmmc_ops = {
1825 .enable = omap_hsmmc_enable_fclk,
1826 .disable = omap_hsmmc_disable_fclk,
1827 .request = omap_hsmmc_request,
1828 .set_ios = omap_hsmmc_set_ios,
1829 .get_cd = omap_hsmmc_get_cd,
1830 .get_ro = omap_hsmmc_get_ro,
1831 /* NYET -- enable_sdio_irq */
1834 static const struct mmc_host_ops omap_hsmmc_ps_ops = {
1835 .enable = omap_hsmmc_enable,
1836 .disable = omap_hsmmc_disable,
1837 .request = omap_hsmmc_request,
1838 .set_ios = omap_hsmmc_set_ios,
1839 .get_cd = omap_hsmmc_get_cd,
1840 .get_ro = omap_hsmmc_get_ro,
1841 /* NYET -- enable_sdio_irq */
1844 #ifdef CONFIG_DEBUG_FS
1846 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1848 struct mmc_host *mmc = s->private;
1849 struct omap_hsmmc_host *host = mmc_priv(mmc);
1850 int context_loss = 0;
1852 if (host->pdata->get_context_loss_count)
1853 context_loss = host->pdata->get_context_loss_count(host->dev);
1855 seq_printf(s, "mmc%d:\n"
1858 " nesting_cnt:\t%d\n"
1859 " ctx_loss:\t%d:%d\n"
1861 mmc->index, mmc->enabled ? 1 : 0,
1862 host->dpm_state, mmc->nesting_cnt,
1863 host->context_loss, context_loss);
1865 if (host->suspended || host->dpm_state == OFF) {
1866 seq_printf(s, "host suspended, can't read registers\n");
1870 if (clk_enable(host->fclk) != 0) {
1871 seq_printf(s, "can't read the regs\n");
1875 seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1876 OMAP_HSMMC_READ(host->base, SYSCONFIG));
1877 seq_printf(s, "CON:\t\t0x%08x\n",
1878 OMAP_HSMMC_READ(host->base, CON));
1879 seq_printf(s, "HCTL:\t\t0x%08x\n",
1880 OMAP_HSMMC_READ(host->base, HCTL));
1881 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1882 OMAP_HSMMC_READ(host->base, SYSCTL));
1883 seq_printf(s, "IE:\t\t0x%08x\n",
1884 OMAP_HSMMC_READ(host->base, IE));
1885 seq_printf(s, "ISE:\t\t0x%08x\n",
1886 OMAP_HSMMC_READ(host->base, ISE));
1887 seq_printf(s, "CAPA:\t\t0x%08x\n",
1888 OMAP_HSMMC_READ(host->base, CAPA));
1890 clk_disable(host->fclk);
1895 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1897 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1900 static const struct file_operations mmc_regs_fops = {
1901 .open = omap_hsmmc_regs_open,
1903 .llseek = seq_lseek,
1904 .release = single_release,
1907 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1909 if (mmc->debugfs_root)
1910 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1911 mmc, &mmc_regs_fops);
1916 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1922 static int __init omap_hsmmc_probe(struct platform_device *pdev)
1924 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1925 struct mmc_host *mmc;
1926 struct omap_hsmmc_host *host = NULL;
1927 struct resource *res;
1930 if (pdata == NULL) {
1931 dev_err(&pdev->dev, "Platform Data is missing\n");
1935 if (pdata->nr_slots == 0) {
1936 dev_err(&pdev->dev, "No Slots\n");
1940 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1941 irq = platform_get_irq(pdev, 0);
1942 if (res == NULL || irq < 0)
1945 res = request_mem_region(res->start, res->end - res->start + 1,
1950 ret = omap_hsmmc_gpio_init(pdata);
1954 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1960 host = mmc_priv(mmc);
1962 host->pdata = pdata;
1963 host->dev = &pdev->dev;
1965 host->dev->dma_mask = &pdata->dma_mask;
1968 host->id = pdev->id;
1970 host->mapbase = res->start;
1971 host->base = ioremap(host->mapbase, SZ_4K);
1972 host->power_mode = -1;
1974 platform_set_drvdata(pdev, host);
1975 INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect);
1977 if (mmc_slot(host).power_saving)
1978 mmc->ops = &omap_hsmmc_ps_ops;
1980 mmc->ops = &omap_hsmmc_ops;
1982 mmc->f_min = 400000;
1983 mmc->f_max = 52000000;
1985 sema_init(&host->sem, 1);
1986 spin_lock_init(&host->irq_lock);
1988 host->iclk = clk_get(&pdev->dev, "ick");
1989 if (IS_ERR(host->iclk)) {
1990 ret = PTR_ERR(host->iclk);
1994 host->fclk = clk_get(&pdev->dev, "fck");
1995 if (IS_ERR(host->fclk)) {
1996 ret = PTR_ERR(host->fclk);
1998 clk_put(host->iclk);
2002 omap_hsmmc_context_save(host);
2004 mmc->caps |= MMC_CAP_DISABLE;
2005 mmc_set_disable_delay(mmc, OMAP_MMC_DISABLED_TIMEOUT);
2006 /* we start off in DISABLED state */
2007 host->dpm_state = DISABLED;
2009 if (mmc_host_enable(host->mmc) != 0) {
2010 clk_put(host->iclk);
2011 clk_put(host->fclk);
2015 if (clk_enable(host->iclk) != 0) {
2016 mmc_host_disable(host->mmc);
2017 clk_put(host->iclk);
2018 clk_put(host->fclk);
2022 if (cpu_is_omap2430()) {
2023 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
2025 * MMC can still work without debounce clock.
2027 if (IS_ERR(host->dbclk))
2028 dev_warn(mmc_dev(host->mmc),
2029 "Failed to get debounce clock\n");
2031 host->got_dbclk = 1;
2033 if (host->got_dbclk)
2034 if (clk_enable(host->dbclk) != 0)
2035 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
2039 /* Since we do only SG emulation, we can have as many segs
2041 mmc->max_phys_segs = 1024;
2042 mmc->max_hw_segs = 1024;
2044 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
2045 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
2046 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2047 mmc->max_seg_size = mmc->max_req_size;
2049 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
2050 MMC_CAP_WAIT_WHILE_BUSY;
2052 if (mmc_slot(host).wires >= 8)
2053 mmc->caps |= MMC_CAP_8_BIT_DATA;
2054 else if (mmc_slot(host).wires >= 4)
2055 mmc->caps |= MMC_CAP_4_BIT_DATA;
2057 if (mmc_slot(host).nonremovable)
2058 mmc->caps |= MMC_CAP_NONREMOVABLE;
2060 omap_hsmmc_conf_bus_power(host);
2062 /* Select DMA lines */
2064 case OMAP_MMC1_DEVID:
2065 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
2066 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
2068 case OMAP_MMC2_DEVID:
2069 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
2070 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
2072 case OMAP_MMC3_DEVID:
2073 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
2074 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
2076 case OMAP_MMC4_DEVID:
2077 host->dma_line_tx = OMAP44XX_DMA_MMC4_TX;
2078 host->dma_line_rx = OMAP44XX_DMA_MMC4_RX;
2080 case OMAP_MMC5_DEVID:
2081 host->dma_line_tx = OMAP44XX_DMA_MMC5_TX;
2082 host->dma_line_rx = OMAP44XX_DMA_MMC5_RX;
2085 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
2089 /* Request IRQ for MMC operations */
2090 ret = request_irq(host->irq, omap_hsmmc_irq, IRQF_DISABLED,
2091 mmc_hostname(mmc), host);
2093 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2097 if (pdata->init != NULL) {
2098 if (pdata->init(&pdev->dev) != 0) {
2099 dev_dbg(mmc_dev(host->mmc),
2100 "Unable to configure MMC IRQs\n");
2101 goto err_irq_cd_init;
2105 if (!mmc_slot(host).set_power) {
2106 ret = omap_hsmmc_reg_get(host);
2112 mmc->ocr_avail = mmc_slot(host).ocr_mask;
2114 /* Request IRQ for card detect */
2115 if ((mmc_slot(host).card_detect_irq)) {
2116 ret = request_irq(mmc_slot(host).card_detect_irq,
2117 omap_hsmmc_cd_handler,
2118 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
2120 mmc_hostname(mmc), host);
2122 dev_dbg(mmc_dev(host->mmc),
2123 "Unable to grab MMC CD IRQ\n");
2128 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
2129 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
2131 mmc_host_lazy_disable(host->mmc);
2133 omap_hsmmc_protect_card(host);
2137 if (mmc_slot(host).name != NULL) {
2138 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2142 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
2143 ret = device_create_file(&mmc->class_dev,
2144 &dev_attr_cover_switch);
2149 omap_hsmmc_debugfs(mmc);
2154 mmc_remove_host(mmc);
2155 free_irq(mmc_slot(host).card_detect_irq, host);
2158 omap_hsmmc_reg_put(host);
2160 if (host->pdata->cleanup)
2161 host->pdata->cleanup(&pdev->dev);
2163 free_irq(host->irq, host);
2165 mmc_host_disable(host->mmc);
2166 clk_disable(host->iclk);
2167 clk_put(host->fclk);
2168 clk_put(host->iclk);
2169 if (host->got_dbclk) {
2170 clk_disable(host->dbclk);
2171 clk_put(host->dbclk);
2174 iounmap(host->base);
2175 platform_set_drvdata(pdev, NULL);
2178 omap_hsmmc_gpio_free(pdata);
2180 release_mem_region(res->start, res->end - res->start + 1);
2184 static int omap_hsmmc_remove(struct platform_device *pdev)
2186 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2187 struct resource *res;
2190 mmc_host_enable(host->mmc);
2191 mmc_remove_host(host->mmc);
2193 omap_hsmmc_reg_put(host);
2194 if (host->pdata->cleanup)
2195 host->pdata->cleanup(&pdev->dev);
2196 free_irq(host->irq, host);
2197 if (mmc_slot(host).card_detect_irq)
2198 free_irq(mmc_slot(host).card_detect_irq, host);
2199 flush_scheduled_work();
2201 mmc_host_disable(host->mmc);
2202 clk_disable(host->iclk);
2203 clk_put(host->fclk);
2204 clk_put(host->iclk);
2205 if (host->got_dbclk) {
2206 clk_disable(host->dbclk);
2207 clk_put(host->dbclk);
2210 mmc_free_host(host->mmc);
2211 iounmap(host->base);
2212 omap_hsmmc_gpio_free(pdev->dev.platform_data);
2215 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2217 release_mem_region(res->start, res->end - res->start + 1);
2218 platform_set_drvdata(pdev, NULL);
2224 static int omap_hsmmc_suspend(struct platform_device *pdev, pm_message_t state)
2227 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2229 if (host && host->suspended)
2233 host->suspended = 1;
2234 if (host->pdata->suspend) {
2235 ret = host->pdata->suspend(&pdev->dev,
2238 dev_dbg(mmc_dev(host->mmc),
2239 "Unable to handle MMC board"
2240 " level suspend\n");
2241 host->suspended = 0;
2245 cancel_work_sync(&host->mmc_carddetect_work);
2246 mmc_host_enable(host->mmc);
2247 ret = mmc_suspend_host(host->mmc, state);
2249 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2250 OMAP_HSMMC_WRITE(host->base, IE, 0);
2253 OMAP_HSMMC_WRITE(host->base, HCTL,
2254 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2255 mmc_host_disable(host->mmc);
2256 clk_disable(host->iclk);
2257 if (host->got_dbclk)
2258 clk_disable(host->dbclk);
2260 host->suspended = 0;
2261 if (host->pdata->resume) {
2262 ret = host->pdata->resume(&pdev->dev,
2265 dev_dbg(mmc_dev(host->mmc),
2266 "Unmask interrupt failed\n");
2268 mmc_host_disable(host->mmc);
2275 /* Routine to resume the MMC device */
2276 static int omap_hsmmc_resume(struct platform_device *pdev)
2279 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2281 if (host && !host->suspended)
2285 ret = clk_enable(host->iclk);
2289 if (mmc_host_enable(host->mmc) != 0) {
2290 clk_disable(host->iclk);
2294 if (host->got_dbclk)
2295 clk_enable(host->dbclk);
2297 omap_hsmmc_conf_bus_power(host);
2299 if (host->pdata->resume) {
2300 ret = host->pdata->resume(&pdev->dev, host->slot_id);
2302 dev_dbg(mmc_dev(host->mmc),
2303 "Unmask interrupt failed\n");
2306 omap_hsmmc_protect_card(host);
2308 /* Notify the core to resume the host */
2309 ret = mmc_resume_host(host->mmc);
2311 host->suspended = 0;
2313 mmc_host_lazy_disable(host->mmc);
2319 dev_dbg(mmc_dev(host->mmc),
2320 "Failed to enable MMC clocks during resume\n");
2325 #define omap_hsmmc_suspend NULL
2326 #define omap_hsmmc_resume NULL
2329 static struct platform_driver omap_hsmmc_driver = {
2330 .remove = omap_hsmmc_remove,
2331 .suspend = omap_hsmmc_suspend,
2332 .resume = omap_hsmmc_resume,
2334 .name = DRIVER_NAME,
2335 .owner = THIS_MODULE,
2339 static int __init omap_hsmmc_init(void)
2341 /* Register the MMC driver */
2342 return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe);
2345 static void __exit omap_hsmmc_cleanup(void)
2347 /* Unregister MMC driver */
2348 platform_driver_unregister(&omap_hsmmc_driver);
2351 module_init(omap_hsmmc_init);
2352 module_exit(omap_hsmmc_cleanup);
2354 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2355 MODULE_LICENSE("GPL");
2356 MODULE_ALIAS("platform:" DRIVER_NAME);
2357 MODULE_AUTHOR("Texas Instruments Inc");