drivers/mmc/host/omap_hsmmc.c

   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/debugfs.h>
  21 #include <linux/seq_file.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/delay.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/workqueue.h>
  27 #include <linux/timer.h>
  28 #include <linux/clk.h>
  29 #include <linux/mmc/host.h>
  30 #include <linux/mmc/core.h>
  31 #include <linux/mmc/mmc.h>
  32 #include <linux/io.h>
  33 #include <linux/semaphore.h>
  34 #include <linux/gpio.h>
  35 #include <linux/regulator/consumer.h>
  36 #include <linux/pm_runtime.h>
  37 #include <plat/dma.h>
  38 #include <mach/hardware.h>
  39 #include <plat/board.h>
  40 #include <plat/mmc.h>
  41 #include <plat/cpu.h>
  42
  43 /* OMAP HSMMC Host Controller Registers */
  44 #define OMAP_HSMMC_SYSCONFIG    0x0010
  45 #define OMAP_HSMMC_SYSSTATUS    0x0014
  46 #define OMAP_HSMMC_CON          0x002C
  47 #define OMAP_HSMMC_BLK          0x0104
  48 #define OMAP_HSMMC_ARG          0x0108
  49 #define OMAP_HSMMC_CMD          0x010C
  50 #define OMAP_HSMMC_RSP10        0x0110
  51 #define OMAP_HSMMC_RSP32        0x0114
  52 #define OMAP_HSMMC_RSP54        0x0118
  53 #define OMAP_HSMMC_RSP76        0x011C
  54 #define OMAP_HSMMC_DATA         0x0120
  55 #define OMAP_HSMMC_HCTL         0x0128
  56 #define OMAP_HSMMC_SYSCTL       0x012C
  57 #define OMAP_HSMMC_STAT         0x0130
  58 #define OMAP_HSMMC_IE           0x0134
  59 #define OMAP_HSMMC_ISE          0x0138
  60 #define OMAP_HSMMC_CAPA         0x0140
  61
  62 #define VS18                    (1 << 26)
  63 #define VS30                    (1 << 25)
  64 #define SDVS18                  (0x5 << 9)
  65 #define SDVS30                  (0x6 << 9)
  66 #define SDVS33                  (0x7 << 9)
  67 #define SDVS_MASK               0x00000E00
  68 #define SDVSCLR                 0xFFFFF1FF
  69 #define SDVSDET                 0x00000400
  70 #define AUTOIDLE                0x1
  71 #define SDBP                    (1 << 8)
  72 #define DTO                     0xe
  73 #define ICE                     0x1
  74 #define ICS                     0x2
  75 #define CEN                     (1 << 2)
  76 #define CLKD_MASK               0x0000FFC0
  77 #define CLKD_SHIFT              6
  78 #define DTO_MASK                0x000F0000
  79 #define DTO_SHIFT               16
  80 #define INT_EN_MASK             0x307F0033
  81 #define BWR_ENABLE              (1 << 4)
  82 #define BRR_ENABLE              (1 << 5)
  83 #define DTO_ENABLE              (1 << 20)
  84 #define INIT_STREAM             (1 << 1)
  85 #define DP_SELECT               (1 << 21)
  86 #define DDIR                    (1 << 4)
  87 #define DMA_EN                  0x1
  88 #define MSBS                    (1 << 5)
  89 #define BCE                     (1 << 1)
  90 #define FOUR_BIT                (1 << 1)
  91 #define DW8                     (1 << 5)
  92 #define CC                      0x1
  93 #define TC                      0x02
  94 #define OD                      0x1
  95 #define ERR                     (1 << 15)
  96 #define CMD_TIMEOUT             (1 << 16)
  97 #define DATA_TIMEOUT            (1 << 20)
  98 #define CMD_CRC                 (1 << 17)
  99 #define DATA_CRC                (1 << 21)
 100 #define CARD_ERR                (1 << 28)
 101 #define STAT_CLEAR              0xFFFFFFFF
 102 #define INIT_STREAM_CMD         0x00000000
 103 #define DUAL_VOLT_OCR_BIT       7
 104 #define SRC                     (1 << 25)
 105 #define SRD                     (1 << 26)
 106 #define SOFTRESET               (1 << 1)
 107 #define RESETDONE               (1 << 0)
 108
 109 /*
 110  * FIXME: Most likely all the data using these _DEVID defines should come
 111  * from the platform_data, or implemented in controller and slot specific
 112  * functions.
 113  */
 114 #define OMAP_MMC1_DEVID         0
 115 #define OMAP_MMC2_DEVID         1
 116 #define OMAP_MMC3_DEVID         2
 117 #define OMAP_MMC4_DEVID         3
 118 #define OMAP_MMC5_DEVID         4
 119
 120 #define MMC_AUTOSUSPEND_DELAY   100
 121 #define MMC_TIMEOUT_MS          20
 122 #define OMAP_MMC_MASTER_CLOCK   96000000
 123 #define DRIVER_NAME             "omap_hsmmc"
 124
 125 /*
 126  * One controller can have multiple slots, like on some omap boards using
 127  * omap.c controller driver. Luckily this is not currently done on any known
 128  * omap_hsmmc.c device.
 129  */
 130 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
 131
 132 /*
 133  * MMC Host controller read/write API's
 134  */
 135 #define OMAP_HSMMC_READ(base, reg)      \
 136         __raw_readl((base) + OMAP_HSMMC_##reg)
 137
 138 #define OMAP_HSMMC_WRITE(base, reg, val) \
 139         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 140
 141 struct omap_hsmmc_next {
 142         unsigned int    dma_len;
 143         s32             cookie;
 144 };
 145
 146 struct omap_hsmmc_host {
 147         struct  device          *dev;
 148         struct  mmc_host        *mmc;
 149         struct  mmc_request     *mrq;
 150         struct  mmc_command     *cmd;
 151         struct  mmc_data        *data;
 152         struct  clk             *fclk;
 153         struct  clk             *iclk;
 154         struct  clk             *dbclk;
 155         /*
 156          * vcc == configured supply
 157          * vcc_aux == optional
 158          *   -  MMC1, supply for DAT4..DAT7
 159          *   -  MMC2/MMC2, external level shifter voltage supply, for
 160          *      chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
 161          */
 162         struct  regulator       *vcc;
 163         struct  regulator       *vcc_aux;
 164         struct  work_struct     mmc_carddetect_work;
 165         void    __iomem         *base;
 166         resource_size_t         mapbase;
 167         spinlock_t              irq_lock; /* Prevent races with irq handler */
 168         unsigned int            id;
 169         unsigned int            dma_len;
 170         unsigned int            dma_sg_idx;
 171         unsigned char           bus_mode;
 172         unsigned char           power_mode;
 173         u32                     *buffer;
 174         u32                     bytesleft;
 175         int                     suspended;
 176         int                     irq;
 177         int                     use_dma, dma_ch;
 178         int                     dma_line_tx, dma_line_rx;
 179         int                     slot_id;
 180         int                     got_dbclk;
 181         int                     response_busy;
 182         int                     context_loss;
 183         int                     dpm_state;
 184         int                     vdd;
 185         int                     protect_card;
 186         int                     reqs_blocked;
 187         int                     use_reg;
 188         int                     req_in_progress;
 189         struct omap_hsmmc_next  next_data;
 190
 191         struct  omap_mmc_platform_data  *pdata;
 192 };
 193
 194 static int omap_hsmmc_card_detect(struct device *dev, int slot)
 195 {
 196         struct omap_mmc_platform_data *mmc = dev->platform_data;
 197
 198         /* NOTE: assumes card detect signal is active-low */
 199         return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
 200 }
 201
 202 static int omap_hsmmc_get_wp(struct device *dev, int slot)
 203 {
 204         struct omap_mmc_platform_data *mmc = dev->platform_data;
 205
 206         /* NOTE: assumes write protect signal is active-high */
 207         return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
 208 }
 209
 210 static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
 211 {
 212         struct omap_mmc_platform_data *mmc = dev->platform_data;
 213
 214         /* NOTE: assumes card detect signal is active-low */
 215         return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
 216 }
 217
 218 #ifdef CONFIG_PM
 219
 220 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
 221 {
 222         struct omap_mmc_platform_data *mmc = dev->platform_data;
 223
 224         disable_irq(mmc->slots[0].card_detect_irq);
 225         return 0;
 226 }
 227
 228 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
 229 {
 230         struct omap_mmc_platform_data *mmc = dev->platform_data;
 231
 232         enable_irq(mmc->slots[0].card_detect_irq);
 233         return 0;
 234 }
 235
 236 #else
 237
 238 #define omap_hsmmc_suspend_cdirq        NULL
 239 #define omap_hsmmc_resume_cdirq         NULL
 240
 241 #endif
 242
 243 #ifdef CONFIG_REGULATOR
 244
 245 static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on,
 246                                   int vdd)
 247 {
 248         struct omap_hsmmc_host *host =
 249                 platform_get_drvdata(to_platform_device(dev));
 250         int ret;
 251
 252         if (mmc_slot(host).before_set_reg)
 253                 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
 254
 255         if (power_on)
 256                 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
 257         else
 258                 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
 259
 260         if (mmc_slot(host).after_set_reg)
 261                 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
 262
 263         return ret;
 264 }
 265
 266 static int omap_hsmmc_235_set_power(struct device *dev, int slot, int power_on,
 267                                    int vdd)
 268 {
 269         struct omap_hsmmc_host *host =
 270                 platform_get_drvdata(to_platform_device(dev));
 271         int ret = 0;
 272
 273         /*
 274          * If we don't see a Vcc regulator, assume it's a fixed
 275          * voltage always-on regulator.
 276          */
 277         if (!host->vcc)
 278                 return 0;
 279
 280         if (mmc_slot(host).before_set_reg)
 281                 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
 282
 283         /*
 284          * Assume Vcc regulator is used only to power the card ... OMAP
 285          * VDDS is used to power the pins, optionally with a transceiver to
 286          * support cards using voltages other than VDDS (1.8V nominal).  When a
 287          * transceiver is used, DAT3..7 are muxed as transceiver control pins.
 288          *
 289          * In some cases this regulator won't support enable/disable;
 290          * e.g. it's a fixed rail for a WLAN chip.
 291          *
 292          * In other cases vcc_aux switches interface power.  Example, for
 293          * eMMC cards it represents VccQ.  Sometimes transceivers or SDIO
 294          * chips/cards need an interface voltage rail too.
 295          */
 296         if (power_on) {
 297                 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
 298                 /* Enable interface voltage rail, if needed */
 299                 if (ret == 0 && host->vcc_aux) {
 300                         ret = regulator_enable(host->vcc_aux);
 301                         if (ret < 0)
 302                                 ret = mmc_regulator_set_ocr(host->mmc,
 303                                                         host->vcc, 0);
 304                 }
 305         } else {
 306                 /* Shut down the rail */
 307                 if (host->vcc_aux)
 308                         ret = regulator_disable(host->vcc_aux);
 309                 if (!ret) {
 310                         /* Then proceed to shut down the local regulator */
 311                         ret = mmc_regulator_set_ocr(host->mmc,
 312                                                 host->vcc, 0);
 313                 }
 314         }
 315
 316         if (mmc_slot(host).after_set_reg)
 317                 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
 318
 319         return ret;
 320 }
 321
 322 static int omap_hsmmc_4_set_power(struct device *dev, int slot, int power_on,
 323                                         int vdd)
 324 {
 325         return 0;
 326 }
 327
 328 static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep,
 329                                   int vdd, int cardsleep)
 330 {
 331         struct omap_hsmmc_host *host =
 332                 platform_get_drvdata(to_platform_device(dev));
 333         int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
 334
 335         return regulator_set_mode(host->vcc, mode);
 336 }
 337
 338 static int omap_hsmmc_235_set_sleep(struct device *dev, int slot, int sleep,
 339                                    int vdd, int cardsleep)
 340 {
 341         struct omap_hsmmc_host *host =
 342                 platform_get_drvdata(to_platform_device(dev));
 343         int err, mode;
 344
 345         /*
 346          * If we don't see a Vcc regulator, assume it's a fixed
 347          * voltage always-on regulator.
 348          */
 349         if (!host->vcc)
 350                 return 0;
 351
 352         mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
 353
 354         if (!host->vcc_aux)
 355                 return regulator_set_mode(host->vcc, mode);
 356
 357         if (cardsleep) {
 358                 /* VCC can be turned off if card is asleep */
 359                 if (sleep)
 360                         err = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
 361                 else
 362                         err = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
 363         } else
 364                 err = regulator_set_mode(host->vcc, mode);
 365         if (err)
 366                 return err;
 367
 368         if (!mmc_slot(host).vcc_aux_disable_is_sleep)
 369                 return regulator_set_mode(host->vcc_aux, mode);
 370
 371         if (sleep)
 372                 return regulator_disable(host->vcc_aux);
 373         else
 374                 return regulator_enable(host->vcc_aux);
 375 }
 376
 377 static int omap_hsmmc_4_set_sleep(struct device *dev, int slot, int sleep,
 378                                         int vdd, int cardsleep)
 379 {
 380         return 0;
 381 }
 382
 383 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
 384 {
 385         struct regulator *reg;
 386         int ret = 0;
 387         int ocr_value = 0;
 388
 389         switch (host->id) {
 390         case OMAP_MMC1_DEVID:
 391                 /* On-chip level shifting via PBIAS0/PBIAS1 */
 392                 mmc_slot(host).set_power = omap_hsmmc_1_set_power;
 393                 mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep;
 394                 break;
 395         case OMAP_MMC2_DEVID:
 396         case OMAP_MMC3_DEVID:
 397         case OMAP_MMC5_DEVID:
 398                 /* Off-chip level shifting, or none */
 399                 mmc_slot(host).set_power = omap_hsmmc_235_set_power;
 400                 mmc_slot(host).set_sleep = omap_hsmmc_235_set_sleep;
 401                 break;
 402         case OMAP_MMC4_DEVID:
 403                 mmc_slot(host).set_power = omap_hsmmc_4_set_power;
 404                 mmc_slot(host).set_sleep = omap_hsmmc_4_set_sleep;
 405         default:
 406                 pr_err("MMC%d configuration not supported!\n", host->id);
 407                 return -EINVAL;
 408         }
 409
 410         reg = regulator_get(host->dev, "vmmc");
 411         if (IS_ERR(reg)) {
 412                 dev_dbg(host->dev, "vmmc regulator missing\n");
 413                 /*
 414                 * HACK: until fixed.c regulator is usable,
 415                 * we don't require a main regulator
 416                 * for MMC2 or MMC3
 417                 */
 418                 if (host->id == OMAP_MMC1_DEVID) {
 419                         ret = PTR_ERR(reg);
 420                         goto err;
 421                 }
 422         } else {
 423                 host->vcc = reg;
 424                 ocr_value = mmc_regulator_get_ocrmask(reg);
 425                 if (!mmc_slot(host).ocr_mask) {
 426                         mmc_slot(host).ocr_mask = ocr_value;
 427                 } else {
 428                         if (!(mmc_slot(host).ocr_mask & ocr_value)) {
 429                                 pr_err("MMC%d ocrmask %x is not supported\n",
 430                                         host->id, mmc_slot(host).ocr_mask);
 431                                 mmc_slot(host).ocr_mask = 0;
 432                                 return -EINVAL;
 433                         }
 434                 }
 435
 436                 /* Allow an aux regulator */
 437                 reg = regulator_get(host->dev, "vmmc_aux");
 438                 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
 439
 440                 /* For eMMC do not power off when not in sleep state */
 441                 if (mmc_slot(host).no_regulator_off_init)
 442                         return 0;
 443                 /*
 444                 * UGLY HACK:  workaround regulator framework bugs.
 445                 * When the bootloader leaves a supply active, it's
 446                 * initialized with zero usecount ... and we can't
 447                 * disable it without first enabling it.  Until the
 448                 * framework is fixed, we need a workaround like this
 449                 * (which is safe for MMC, but not in general).
 450                 */
 451                 if (regulator_is_enabled(host->vcc) > 0) {
 452                         regulator_enable(host->vcc);
 453                         regulator_disable(host->vcc);
 454                 }
 455                 if (host->vcc_aux) {
 456                         if (regulator_is_enabled(reg) > 0) {
 457                                 regulator_enable(reg);
 458                                 regulator_disable(reg);
 459                         }
 460                 }
 461         }
 462
 463         return 0;
 464
 465 err:
 466         mmc_slot(host).set_power = NULL;
 467         mmc_slot(host).set_sleep = NULL;
 468         return ret;
 469 }
 470
 471 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
 472 {
 473         regulator_put(host->vcc);
 474         regulator_put(host->vcc_aux);
 475         mmc_slot(host).set_power = NULL;
 476         mmc_slot(host).set_sleep = NULL;
 477 }
 478
 479 static inline int omap_hsmmc_have_reg(void)
 480 {
 481         return 1;
 482 }
 483
 484 #else
 485
 486 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
 487 {
 488         return -EINVAL;
 489 }
 490
 491 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
 492 {
 493 }
 494
 495 static inline int omap_hsmmc_have_reg(void)
 496 {
 497         return 0;
 498 }
 499
 500 #endif
 501
 502 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
 503 {
 504         int ret;
 505
 506         if (gpio_is_valid(pdata->slots[0].switch_pin)) {
 507                 if (pdata->slots[0].cover)
 508                         pdata->slots[0].get_cover_state =
 509                                         omap_hsmmc_get_cover_state;
 510                 else
 511                         pdata->slots[0].card_detect = omap_hsmmc_card_detect;
 512                 pdata->slots[0].card_detect_irq =
 513                                 gpio_to_irq(pdata->slots[0].switch_pin);
 514                 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
 515                 if (ret)
 516                         return ret;
 517                 ret = gpio_direction_input(pdata->slots[0].switch_pin);
 518                 if (ret)
 519                         goto err_free_sp;
 520         } else
 521                 pdata->slots[0].switch_pin = -EINVAL;
 522
 523         if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
 524                 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
 525                 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
 526                 if (ret)
 527                         goto err_free_cd;
 528                 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
 529                 if (ret)
 530                         goto err_free_wp;
 531         } else
 532                 pdata->slots[0].gpio_wp = -EINVAL;
 533
 534         return 0;
 535
 536 err_free_wp:
 537         gpio_free(pdata->slots[0].gpio_wp);
 538 err_free_cd:
 539         if (gpio_is_valid(pdata->slots[0].switch_pin))
 540 err_free_sp:
 541                 gpio_free(pdata->slots[0].switch_pin);
 542         return ret;
 543 }
 544
 545 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
 546 {
 547         if (gpio_is_valid(pdata->slots[0].gpio_wp))
 548                 gpio_free(pdata->slots[0].gpio_wp);
 549         if (gpio_is_valid(pdata->slots[0].switch_pin))
 550                 gpio_free(pdata->slots[0].switch_pin);
 551 }
 552
 553 /*
 554  * Stop clock to the card
 555  */
 556 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
 557 {
 558         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 559                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 560         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 561                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
 562 }
 563
 564 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
 565                                   struct mmc_command *cmd)
 566 {
 567         unsigned int irq_mask;
 568
 569         if (host->use_dma)
 570                 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
 571         else
 572                 irq_mask = INT_EN_MASK;
 573
 574         /* Disable timeout for erases */
 575         if (cmd->opcode == MMC_ERASE)
 576                 irq_mask &= ~DTO_ENABLE;
 577
 578         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 579         OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
 580         OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
 581 }
 582
 583 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
 584 {
 585         OMAP_HSMMC_WRITE(host->base, ISE, 0);
 586         OMAP_HSMMC_WRITE(host->base, IE, 0);
 587         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 588 }
 589
 590 #ifdef CONFIG_PM
 591
 592 /*
 593  * Restore the MMC host context, if it was lost as result of a
 594  * power state change.
 595  */
 596 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 597 {
 598         struct mmc_ios *ios = &host->mmc->ios;
 599         struct omap_mmc_platform_data *pdata = host->pdata;
 600         int context_loss = 0;
 601         u32 hctl, capa, con;
 602         u16 dsor = 0;
 603         unsigned long timeout;
 604
 605         if (pdata->get_context_loss_count) {
 606                 context_loss = pdata->get_context_loss_count(host->dev);
 607                 if (context_loss < 0)
 608                         return 1;
 609         }
 610
 611         dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
 612                 context_loss == host->context_loss ? "not " : "");
 613         if (host->context_loss == context_loss)
 614                 return 1;
 615
 616         /* Wait for hardware reset */
 617         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 618         while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
 619                 && time_before(jiffies, timeout))
 620                 ;
 621
 622         /* Do software reset */
 623         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
 624         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 625         while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
 626                 && time_before(jiffies, timeout))
 627                 ;
 628
 629         OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
 630                         OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
 631
 632         if (host->id == OMAP_MMC1_DEVID) {
 633                 if (host->power_mode != MMC_POWER_OFF &&
 634                     (1 << ios->vdd) <= MMC_VDD_23_24)
 635                         hctl = SDVS18;
 636                 else
 637                         hctl = SDVS30;
 638                 capa = VS30 | VS18;
 639         } else {
 640                 hctl = SDVS18;
 641                 capa = VS18;
 642         }
 643
 644         OMAP_HSMMC_WRITE(host->base, HCTL,
 645                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
 646
 647         OMAP_HSMMC_WRITE(host->base, CAPA,
 648                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
 649
 650         OMAP_HSMMC_WRITE(host->base, HCTL,
 651                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 652
 653         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 654         while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
 655                 && time_before(jiffies, timeout))
 656                 ;
 657
 658         omap_hsmmc_disable_irq(host);
 659
 660         /* Do not initialize card-specific things if the power is off */
 661         if (host->power_mode == MMC_POWER_OFF)
 662                 goto out;
 663
 664         con = OMAP_HSMMC_READ(host->base, CON);
 665         switch (ios->bus_width) {
 666         case MMC_BUS_WIDTH_8:
 667                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
 668                 break;
 669         case MMC_BUS_WIDTH_4:
 670                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 671                 OMAP_HSMMC_WRITE(host->base, HCTL,
 672                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 673                 break;
 674         case MMC_BUS_WIDTH_1:
 675                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 676                 OMAP_HSMMC_WRITE(host->base, HCTL,
 677                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 678                 break;
 679         }
 680
 681         if (ios->clock) {
 682                 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
 683                 if (dsor < 1)
 684                         dsor = 1;
 685
 686                 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
 687                         dsor++;
 688
 689                 if (dsor > 250)
 690                         dsor = 250;
 691         }
 692
 693         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 694                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 695         OMAP_HSMMC_WRITE(host->base, SYSCTL, (dsor << 6) | (DTO << 16));
 696         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 697                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 698
 699         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 700         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
 701                 && time_before(jiffies, timeout))
 702                 ;
 703
 704         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 705                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 706
 707         con = OMAP_HSMMC_READ(host->base, CON);
 708         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 709                 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
 710         else
 711                 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
 712 out:
 713         host->context_loss = context_loss;
 714
 715         dev_dbg(mmc_dev(host->mmc), "context is restored\n");
 716         return 0;
 717 }
 718
 719 /*
 720  * Save the MMC host context (store the number of power state changes so far).
 721  */
 722 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 723 {
 724         struct omap_mmc_platform_data *pdata = host->pdata;
 725         int context_loss;
 726
 727         if (pdata->get_context_loss_count) {
 728                 context_loss = pdata->get_context_loss_count(host->dev);
 729                 if (context_loss < 0)
 730                         return;
 731                 host->context_loss = context_loss;
 732         }
 733 }
 734
 735 #else
 736
 737 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 738 {
 739         return 0;
 740 }
 741
 742 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 743 {
 744 }
 745
 746 #endif
 747
 748 /*
 749  * Send init stream sequence to card
 750  * before sending IDLE command
 751  */
 752 static void send_init_stream(struct omap_hsmmc_host *host)
 753 {
 754         int reg = 0;
 755         unsigned long timeout;
 756
 757         if (host->protect_card)
 758                 return;
 759
 760         disable_irq(host->irq);
 761
 762         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 763         OMAP_HSMMC_WRITE(host->base, CON,
 764                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 765         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 766
 767         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 768         while ((reg != CC) && time_before(jiffies, timeout))
 769                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
 770
 771         OMAP_HSMMC_WRITE(host->base, CON,
 772                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 773
 774         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 775         OMAP_HSMMC_READ(host->base, STAT);
 776
 777         enable_irq(host->irq);
 778 }
 779
 780 static inline
 781 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
 782 {
 783         int r = 1;
 784
 785         if (mmc_slot(host).get_cover_state)
 786                 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
 787         return r;
 788 }
 789
 790 static ssize_t
 791 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
 792                            char *buf)
 793 {
 794         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 795         struct omap_hsmmc_host *host = mmc_priv(mmc);
 796
 797         return sprintf(buf, "%s\n",
 798                         omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
 799 }
 800
 801 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
 802
 803 static ssize_t
 804 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
 805                         char *buf)
 806 {
 807         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 808         struct omap_hsmmc_host *host = mmc_priv(mmc);
 809
 810         return sprintf(buf, "%s\n", mmc_slot(host).name);
 811 }
 812
 813 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
 814
 815 /*
 816  * Configure the response type and send the cmd.
 817  */
 818 static void
 819 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
 820         struct mmc_data *data)
 821 {
 822         int cmdreg = 0, resptype = 0, cmdtype = 0;
 823
 824         dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 825                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 826         host->cmd = cmd;
 827
 828         omap_hsmmc_enable_irq(host, cmd);
 829
 830         host->response_busy = 0;
 831         if (cmd->flags & MMC_RSP_PRESENT) {
 832                 if (cmd->flags & MMC_RSP_136)
 833                         resptype = 1;
 834                 else if (cmd->flags & MMC_RSP_BUSY) {
 835                         resptype = 3;
 836                         host->response_busy = 1;
 837                 } else
 838                         resptype = 2;
 839         }
 840
 841         /*
 842          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 843          * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
 844          * a val of 0x3, rest 0x0.
 845          */
 846         if (cmd == host->mrq->stop)
 847                 cmdtype = 0x3;
 848
 849         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 850
 851         if (data) {
 852                 cmdreg |= DP_SELECT | MSBS | BCE;
 853                 if (data->flags & MMC_DATA_READ)
 854                         cmdreg |= DDIR;
 855                 else
 856                         cmdreg &= ~(DDIR);
 857         }
 858
 859         if (host->use_dma)
 860                 cmdreg |= DMA_EN;
 861
 862         host->req_in_progress = 1;
 863
 864         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 865         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 866 }
 867
 868 static int
 869 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
 870 {
 871         if (data->flags & MMC_DATA_WRITE)
 872                 return DMA_TO_DEVICE;
 873         else
 874                 return DMA_FROM_DEVICE;
 875 }
 876
 877 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
 878 {
 879         int dma_ch;
 880
 881         spin_lock(&host->irq_lock);
 882         host->req_in_progress = 0;
 883         dma_ch = host->dma_ch;
 884         spin_unlock(&host->irq_lock);
 885
 886         omap_hsmmc_disable_irq(host);
 887         /* Do not complete the request if DMA is still in progress */
 888         if (mrq->data && host->use_dma && dma_ch != -1)
 889                 return;
 890         host->mrq = NULL;
 891         mmc_request_done(host->mmc, mrq);
 892 }
 893
 894 /*
 895  * Notify the transfer complete to MMC core
 896  */
 897 static void
 898 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
 899 {
 900         if (!data) {
 901                 struct mmc_request *mrq = host->mrq;
 902
 903                 /* TC before CC from CMD6 - don't know why, but it happens */
 904                 if (host->cmd && host->cmd->opcode == 6 &&
 905                     host->response_busy) {
 906                         host->response_busy = 0;
 907                         return;
 908                 }
 909
 910                 omap_hsmmc_request_done(host, mrq);
 911                 return;
 912         }
 913
 914         host->data = NULL;
 915
 916         if (!data->error)
 917                 data->bytes_xfered += data->blocks * (data->blksz);
 918         else
 919                 data->bytes_xfered = 0;
 920
 921         if (!data->stop) {
 922                 omap_hsmmc_request_done(host, data->mrq);
 923                 return;
 924         }
 925         omap_hsmmc_start_command(host, data->stop, NULL);
 926 }
 927
 928 /*
 929  * Notify the core about command completion
 930  */
 931 static void
 932 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
 933 {
 934         host->cmd = NULL;
 935
 936         if (cmd->flags & MMC_RSP_PRESENT) {
 937                 if (cmd->flags & MMC_RSP_136) {
 938                         /* response type 2 */
 939                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
 940                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
 941                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
 942                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
 943                 } else {
 944                         /* response types 1, 1b, 3, 4, 5, 6 */
 945                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
 946                 }
 947         }
 948         if ((host->data == NULL && !host->response_busy) || cmd->error)
 949                 omap_hsmmc_request_done(host, cmd->mrq);
 950 }
 951
 952 /*
 953  * DMA clean up for command errors
 954  */
 955 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
 956 {
 957         int dma_ch;
 958
 959         host->data->error = errno;
 960
 961         spin_lock(&host->irq_lock);
 962         dma_ch = host->dma_ch;
 963         host->dma_ch = -1;
 964         spin_unlock(&host->irq_lock);
 965
 966         if (host->use_dma && dma_ch != -1) {
 967                 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg,
 968                         host->data->sg_len,
 969                         omap_hsmmc_get_dma_dir(host, host->data));
 970                 omap_free_dma(dma_ch);
 971         }
 972         host->data = NULL;
 973 }
 974
 975 /*
 976  * Readable error output
 977  */
 978 #ifdef CONFIG_MMC_DEBUG
 979 static void omap_hsmmc_report_irq(struct omap_hsmmc_host *host, u32 status)
 980 {
 981         /* --- means reserved bit without definition at documentation */
 982         static const char *omap_hsmmc_status_bits[] = {
 983                 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
 984                 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
 985                 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
 986                 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
 987         };
 988         char res[256];
 989         char *buf = res;
 990         int len, i;
 991
 992         len = sprintf(buf, "MMC IRQ 0x%x :", status);
 993         buf += len;
 994
 995         for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
 996                 if (status & (1 << i)) {
 997                         len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
 998                         buf += len;
 999                 }
1000
1001         dev_dbg(mmc_dev(host->mmc), "%s\n", res);
1002 }
1003 #endif  /* CONFIG_MMC_DEBUG */
1004
1005 /*
1006  * MMC controller internal state machines reset
1007  *
1008  * Used to reset command or data internal state machines, using respectively
1009  *  SRC or SRD bit of SYSCTL register
1010  * Can be called from interrupt context
1011  */
1012 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
1013                                                    unsigned long bit)
1014 {
1015         unsigned long i = 0;
1016         unsigned long limit = (loops_per_jiffy *
1017                                 msecs_to_jiffies(MMC_TIMEOUT_MS));
1018
1019         OMAP_HSMMC_WRITE(host->base, SYSCTL,
1020                          OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1021
1022         /*
1023          * OMAP4 ES2 and greater has an updated reset logic.
1024          * Monitor a 0->1 transition first
1025          */
1026         if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
1027                 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
1028                                         && (i++ < limit))
1029                         cpu_relax();
1030         }
1031         i = 0;
1032
1033         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1034                 (i++ < limit))
1035                 cpu_relax();
1036
1037         if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1038                 dev_err(mmc_dev(host->mmc),
1039                         "Timeout waiting on controller reset in %s\n",
1040                         __func__);
1041 }
1042
1043 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1044 {
1045         struct mmc_data *data;
1046         int end_cmd = 0, end_trans = 0;
1047
1048         if (!host->req_in_progress) {
1049                 do {
1050                         OMAP_HSMMC_WRITE(host->base, STAT, status);
1051                         /* Flush posted write */
1052                         status = OMAP_HSMMC_READ(host->base, STAT);
1053                 } while (status & INT_EN_MASK);
1054                 return;
1055         }
1056
1057         data = host->data;
1058         dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1059
1060         if (status & ERR) {
1061 #ifdef CONFIG_MMC_DEBUG
1062                 omap_hsmmc_report_irq(host, status);
1063 #endif
1064                 if ((status & CMD_TIMEOUT) ||
1065                         (status & CMD_CRC)) {
1066                         if (host->cmd) {
1067                                 if (status & CMD_TIMEOUT) {
1068                                         omap_hsmmc_reset_controller_fsm(host,
1069                                                                         SRC);
1070                                         host->cmd->error = -ETIMEDOUT;
1071                                 } else {
1072                                         host->cmd->error = -EILSEQ;
1073                                 }
1074                                 end_cmd = 1;
1075                         }
1076                         if (host->data || host->response_busy) {
1077                                 if (host->data)
1078                                         omap_hsmmc_dma_cleanup(host,
1079                                                                 -ETIMEDOUT);
1080                                 host->response_busy = 0;
1081                                 omap_hsmmc_reset_controller_fsm(host, SRD);
1082                         }
1083                 }
1084                 if ((status & DATA_TIMEOUT) ||
1085                         (status & DATA_CRC)) {
1086                         if (host->data || host->response_busy) {
1087                                 int err = (status & DATA_TIMEOUT) ?
1088                                                 -ETIMEDOUT : -EILSEQ;
1089
1090                                 if (host->data)
1091                                         omap_hsmmc_dma_cleanup(host, err);
1092                                 else
1093                                         host->mrq->cmd->error = err;
1094                                 host->response_busy = 0;
1095                                 omap_hsmmc_reset_controller_fsm(host, SRD);
1096                                 end_trans = 1;
1097                         }
1098                 }
1099                 if (status & CARD_ERR) {
1100                         dev_dbg(mmc_dev(host->mmc),
1101                                 "Ignoring card err CMD%d\n", host->cmd->opcode);
1102                         if (host->cmd)
1103                                 end_cmd = 1;
1104                         if (host->data)
1105                                 end_trans = 1;
1106                 }
1107         }
1108
1109         OMAP_HSMMC_WRITE(host->base, STAT, status);
1110
1111         if (end_cmd || ((status & CC) && host->cmd))
1112                 omap_hsmmc_cmd_done(host, host->cmd);
1113         if ((end_trans || (status & TC)) && host->mrq)
1114                 omap_hsmmc_xfer_done(host, data);
1115 }
1116
1117 /*
1118  * MMC controller IRQ handler
1119  */
1120 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1121 {
1122         struct omap_hsmmc_host *host = dev_id;
1123         int status;
1124
1125         status = OMAP_HSMMC_READ(host->base, STAT);
1126         do {
1127                 omap_hsmmc_do_irq(host, status);
1128                 /* Flush posted write */
1129                 status = OMAP_HSMMC_READ(host->base, STAT);
1130         } while (status & INT_EN_MASK);
1131
1132         return IRQ_HANDLED;
1133 }
1134
1135 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1136 {
1137         unsigned long i;
1138
1139         OMAP_HSMMC_WRITE(host->base, HCTL,
1140                          OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1141         for (i = 0; i < loops_per_jiffy; i++) {
1142                 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1143                         break;
1144                 cpu_relax();
1145         }
1146 }
1147
1148 /*
1149  * Switch MMC interface voltage ... only relevant for MMC1.
1150  *
1151  * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1152  * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1153  * Some chips, like eMMC ones, use internal transceivers.
1154  */
1155 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1156 {
1157         u32 reg_val = 0;
1158         int ret;
1159
1160         /* Disable the clocks */
1161         pm_runtime_put_sync(host->dev);
1162         if (host->got_dbclk)
1163                 clk_disable(host->dbclk);
1164
1165         /* Turn the power off */
1166         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1167
1168         /* Turn the power ON with given VDD 1.8 or 3.0v */
1169         if (!ret)
1170                 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1171                                                vdd);
1172         pm_runtime_get_sync(host->dev);
1173         if (host->got_dbclk)
1174                 clk_enable(host->dbclk);
1175
1176         if (ret != 0)
1177                 goto err;
1178
1179         OMAP_HSMMC_WRITE(host->base, HCTL,
1180                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1181         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1182
1183         /*
1184          * If a MMC dual voltage card is detected, the set_ios fn calls
1185          * this fn with VDD bit set for 1.8V. Upon card removal from the
1186          * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1187          *
1188          * Cope with a bit of slop in the range ... per data sheets:
1189          *  - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1190          *    but recommended values are 1.71V to 1.89V
1191          *  - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1192          *    but recommended values are 2.7V to 3.3V
1193          *
1194          * Board setup code shouldn't permit anything very out-of-range.
1195          * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1196          * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1197          */
1198         if ((1 << vdd) <= MMC_VDD_23_24)
1199                 reg_val |= SDVS18;
1200         else
1201                 reg_val |= SDVS30;
1202
1203         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1204         set_sd_bus_power(host);
1205
1206         return 0;
1207 err:
1208         dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1209         return ret;
1210 }
1211
1212 /* Protect the card while the cover is open */
1213 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1214 {
1215         if (!mmc_slot(host).get_cover_state)
1216                 return;
1217
1218         host->reqs_blocked = 0;
1219         if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1220                 if (host->protect_card) {
1221                         printk(KERN_INFO "%s: cover is closed, "
1222                                          "card is now accessible\n",
1223                                          mmc_hostname(host->mmc));
1224                         host->protect_card = 0;
1225                 }
1226         } else {
1227                 if (!host->protect_card) {
1228                         printk(KERN_INFO "%s: cover is open, "
1229                                          "card is now inaccessible\n",
1230                                          mmc_hostname(host->mmc));
1231                         host->protect_card = 1;
1232                 }
1233         }
1234 }
1235
1236 /*
1237  * Work Item to notify the core about card insertion/removal
1238  */
1239 static void omap_hsmmc_detect(struct work_struct *work)
1240 {
1241         struct omap_hsmmc_host *host =
1242                 container_of(work, struct omap_hsmmc_host, mmc_carddetect_work);
1243         struct omap_mmc_slot_data *slot = &mmc_slot(host);
1244         int carddetect;
1245
1246         if (host->suspended)
1247                 return;
1248
1249         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1250
1251         if (slot->card_detect)
1252                 carddetect = slot->card_detect(host->dev, host->slot_id);
1253         else {
1254                 omap_hsmmc_protect_card(host);
1255                 carddetect = -ENOSYS;
1256         }
1257
1258         if (carddetect)
1259                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1260         else
1261                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1262 }
1263
1264 /*
1265  * ISR for handling card insertion and removal
1266  */
1267 static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id)
1268 {
1269         struct omap_hsmmc_host *host = (struct omap_hsmmc_host *)dev_id;
1270
1271         if (host->suspended)
1272                 return IRQ_HANDLED;
1273         schedule_work(&host->mmc_carddetect_work);
1274
1275         return IRQ_HANDLED;
1276 }
1277
1278 static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
1279                                      struct mmc_data *data)
1280 {
1281         int sync_dev;
1282
1283         if (data->flags & MMC_DATA_WRITE)
1284                 sync_dev = host->dma_line_tx;
1285         else
1286                 sync_dev = host->dma_line_rx;
1287         return sync_dev;
1288 }
1289
1290 static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
1291                                        struct mmc_data *data,
1292                                        struct scatterlist *sgl)
1293 {
1294         int blksz, nblk, dma_ch;
1295
1296         dma_ch = host->dma_ch;
1297         if (data->flags & MMC_DATA_WRITE) {
1298                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1299                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1300                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1301                         sg_dma_address(sgl), 0, 0);
1302         } else {
1303                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1304                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1305                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1306                         sg_dma_address(sgl), 0, 0);
1307         }
1308
1309         blksz = host->data->blksz;
1310         nblk = sg_dma_len(sgl) / blksz;
1311
1312         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1313                         blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
1314                         omap_hsmmc_get_dma_sync_dev(host, data),
1315                         !(data->flags & MMC_DATA_WRITE));
1316
1317         omap_start_dma(dma_ch);
1318 }
1319
1320 /*
1321  * DMA call back function
1322  */
1323 static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data)
1324 {
1325         struct omap_hsmmc_host *host = cb_data;
1326         struct mmc_data *data = host->mrq->data;
1327         int dma_ch, req_in_progress;
1328
1329         if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
1330                 dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
1331                         ch_status);
1332                 return;
1333         }
1334
1335         spin_lock(&host->irq_lock);
1336         if (host->dma_ch < 0) {
1337                 spin_unlock(&host->irq_lock);
1338                 return;
1339         }
1340
1341         host->dma_sg_idx++;
1342         if (host->dma_sg_idx < host->dma_len) {
1343                 /* Fire up the next transfer. */
1344                 omap_hsmmc_config_dma_params(host, data,
1345                                            data->sg + host->dma_sg_idx);
1346                 spin_unlock(&host->irq_lock);
1347                 return;
1348         }
1349
1350         if (!data->host_cookie)
1351                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1352                              omap_hsmmc_get_dma_dir(host, data));
1353
1354         req_in_progress = host->req_in_progress;
1355         dma_ch = host->dma_ch;
1356         host->dma_ch = -1;
1357         spin_unlock(&host->irq_lock);
1358
1359         omap_free_dma(dma_ch);
1360
1361         /* If DMA has finished after TC, complete the request */
1362         if (!req_in_progress) {
1363                 struct mmc_request *mrq = host->mrq;
1364
1365                 host->mrq = NULL;
1366                 mmc_request_done(host->mmc, mrq);
1367         }
1368 }
1369
1370 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1371                                        struct mmc_data *data,
1372                                        struct omap_hsmmc_next *next)
1373 {
1374         int dma_len;
1375
1376         if (!next && data->host_cookie &&
1377             data->host_cookie != host->next_data.cookie) {
1378                 printk(KERN_WARNING "[%s] invalid cookie: data->host_cookie %d"
1379                        " host->next_data.cookie %d\n",
1380                        __func__, data->host_cookie, host->next_data.cookie);
1381                 data->host_cookie = 0;
1382         }
1383
1384         /* Check if next job is already prepared */
1385         if (next ||
1386             (!next && data->host_cookie != host->next_data.cookie)) {
1387                 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1388                                      data->sg_len,
1389                                      omap_hsmmc_get_dma_dir(host, data));
1390
1391         } else {
1392                 dma_len = host->next_data.dma_len;
1393                 host->next_data.dma_len = 0;
1394         }
1395
1396
1397         if (dma_len == 0)
1398                 return -EINVAL;
1399
1400         if (next) {
1401                 next->dma_len = dma_len;
1402                 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1403         } else
1404                 host->dma_len = dma_len;
1405
1406         return 0;
1407 }
1408
1409 /*
1410  * Routine to configure and start DMA for the MMC card
1411  */
1412 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1413                                         struct mmc_request *req)
1414 {
1415         int dma_ch = 0, ret = 0, i;
1416         struct mmc_data *data = req->data;
1417
1418         /* Sanity check: all the SG entries must be aligned by block size. */
1419         for (i = 0; i < data->sg_len; i++) {
1420                 struct scatterlist *sgl;
1421
1422                 sgl = data->sg + i;
1423                 if (sgl->length % data->blksz)
1424                         return -EINVAL;
1425         }
1426         if ((data->blksz % 4) != 0)
1427                 /* REVISIT: The MMC buffer increments only when MSB is written.
1428                  * Return error for blksz which is non multiple of four.
1429                  */
1430                 return -EINVAL;
1431
1432         BUG_ON(host->dma_ch != -1);
1433
1434         ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1435                                "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
1436         if (ret != 0) {
1437                 dev_err(mmc_dev(host->mmc),
1438                         "%s: omap_request_dma() failed with %d\n",
1439                         mmc_hostname(host->mmc), ret);
1440                 return ret;
1441         }
1442         ret = omap_hsmmc_pre_dma_transfer(host, data, NULL);
1443         if (ret)
1444                 return ret;
1445
1446         host->dma_ch = dma_ch;
1447         host->dma_sg_idx = 0;
1448
1449         omap_hsmmc_config_dma_params(host, data, data->sg);
1450
1451         return 0;
1452 }
1453
1454 static void set_data_timeout(struct omap_hsmmc_host *host,
1455                              unsigned int timeout_ns,
1456                              unsigned int timeout_clks)
1457 {
1458         unsigned int timeout, cycle_ns;
1459         uint32_t reg, clkd, dto = 0;
1460
1461         reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1462         clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1463         if (clkd == 0)
1464                 clkd = 1;
1465
1466         cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
1467         timeout = timeout_ns / cycle_ns;
1468         timeout += timeout_clks;
1469         if (timeout) {
1470                 while ((timeout & 0x80000000) == 0) {
1471                         dto += 1;
1472                         timeout <<= 1;
1473                 }
1474                 dto = 31 - dto;
1475                 timeout <<= 1;
1476                 if (timeout && dto)
1477                         dto += 1;
1478                 if (dto >= 13)
1479                         dto -= 13;
1480                 else
1481                         dto = 0;
1482                 if (dto > 14)
1483                         dto = 14;
1484         }
1485
1486         reg &= ~DTO_MASK;
1487         reg |= dto << DTO_SHIFT;
1488         OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1489 }
1490
1491 /*
1492  * Configure block length for MMC/SD cards and initiate the transfer.
1493  */
1494 static int
1495 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1496 {
1497         int ret;
1498         host->data = req->data;
1499
1500         if (req->data == NULL) {
1501                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1502                 /*
1503                  * Set an arbitrary 100ms data timeout for commands with
1504                  * busy signal.
1505                  */
1506                 if (req->cmd->flags & MMC_RSP_BUSY)
1507                         set_data_timeout(host, 100000000U, 0);
1508                 return 0;
1509         }
1510
1511         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1512                                         | (req->data->blocks << 16));
1513         set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
1514
1515         if (host->use_dma) {
1516                 ret = omap_hsmmc_start_dma_transfer(host, req);
1517                 if (ret != 0) {
1518                         dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1519                         return ret;
1520                 }
1521         }
1522         return 0;
1523 }
1524
1525 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1526                                 int err)
1527 {
1528         struct omap_hsmmc_host *host = mmc_priv(mmc);
1529         struct mmc_data *data = mrq->data;
1530
1531         if (host->use_dma) {
1532                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1533                              omap_hsmmc_get_dma_dir(host, data));
1534                 data->host_cookie = 0;
1535         }
1536 }
1537
1538 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1539                                bool is_first_req)
1540 {
1541         struct omap_hsmmc_host *host = mmc_priv(mmc);
1542
1543         if (mrq->data->host_cookie) {
1544                 mrq->data->host_cookie = 0;
1545                 return ;
1546         }
1547
1548         if (host->use_dma)
1549                 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1550                                                 &host->next_data))
1551                         mrq->data->host_cookie = 0;
1552 }
1553
1554 /*
1555  * Request function. for read/write operation
1556  */
1557 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1558 {
1559         struct omap_hsmmc_host *host = mmc_priv(mmc);
1560         int err;
1561
1562         BUG_ON(host->req_in_progress);
1563         BUG_ON(host->dma_ch != -1);
1564         if (host->protect_card) {
1565                 if (host->reqs_blocked < 3) {
1566                         /*
1567                          * Ensure the controller is left in a consistent
1568                          * state by resetting the command and data state
1569                          * machines.
1570                          */
1571                         omap_hsmmc_reset_controller_fsm(host, SRD);
1572                         omap_hsmmc_reset_controller_fsm(host, SRC);
1573                         host->reqs_blocked += 1;
1574                 }
1575                 req->cmd->error = -EBADF;
1576                 if (req->data)
1577                         req->data->error = -EBADF;
1578                 req->cmd->retries = 0;
1579                 mmc_request_done(mmc, req);
1580                 return;
1581         } else if (host->reqs_blocked)
1582                 host->reqs_blocked = 0;
1583         WARN_ON(host->mrq != NULL);
1584         host->mrq = req;
1585         err = omap_hsmmc_prepare_data(host, req);
1586         if (err) {
1587                 req->cmd->error = err;
1588                 if (req->data)
1589                         req->data->error = err;
1590                 host->mrq = NULL;
1591                 mmc_request_done(mmc, req);
1592                 return;
1593         }
1594
1595         omap_hsmmc_start_command(host, req->cmd, req->data);
1596 }
1597
1598 /* Routine to configure clock values. Exposed API to core */
1599 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1600 {
1601         struct omap_hsmmc_host *host = mmc_priv(mmc);
1602         u16 dsor = 0;
1603         unsigned long regval;
1604         unsigned long timeout;
1605         u32 con;
1606         int do_send_init_stream = 0;
1607
1608         pm_runtime_get_sync(host->dev);
1609
1610         if (ios->power_mode != host->power_mode) {
1611                 switch (ios->power_mode) {
1612                 case MMC_POWER_OFF:
1613                         mmc_slot(host).set_power(host->dev, host->slot_id,
1614                                                  0, 0);
1615                         host->vdd = 0;
1616                         break;
1617                 case MMC_POWER_UP:
1618                         mmc_slot(host).set_power(host->dev, host->slot_id,
1619                                                  1, ios->vdd);
1620                         host->vdd = ios->vdd;
1621                         break;
1622                 case MMC_POWER_ON:
1623                         do_send_init_stream = 1;
1624                         break;
1625                 }
1626                 host->power_mode = ios->power_mode;
1627         }
1628
1629         /* FIXME: set registers based only on changes to ios */
1630
1631         con = OMAP_HSMMC_READ(host->base, CON);
1632         switch (mmc->ios.bus_width) {
1633         case MMC_BUS_WIDTH_8:
1634                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
1635                 break;
1636         case MMC_BUS_WIDTH_4:
1637                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
1638                 OMAP_HSMMC_WRITE(host->base, HCTL,
1639                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
1640                 break;
1641         case MMC_BUS_WIDTH_1:
1642                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
1643                 OMAP_HSMMC_WRITE(host->base, HCTL,
1644                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
1645                 break;
1646         }
1647
1648         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1649                 /* Only MMC1 can interface at 3V without some flavor
1650                  * of external transceiver; but they all handle 1.8V.
1651                  */
1652                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1653                         (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1654                                 /*
1655                                  * The mmc_select_voltage fn of the core does
1656                                  * not seem to set the power_mode to
1657                                  * MMC_POWER_UP upon recalculating the voltage.
1658                                  * vdd 1.8v.
1659                                  */
1660                         if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1661                                 dev_dbg(mmc_dev(host->mmc),
1662                                                 "Switch operation failed\n");
1663                 }
1664         }
1665
1666         if (ios->clock) {
1667                 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
1668                 if (dsor < 1)
1669                         dsor = 1;
1670
1671                 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
1672                         dsor++;
1673
1674                 if (dsor > 250)
1675                         dsor = 250;
1676         }
1677         omap_hsmmc_stop_clock(host);
1678         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
1679         regval = regval & ~(CLKD_MASK);
1680         regval = regval | (dsor << 6) | (DTO << 16);
1681         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
1682         OMAP_HSMMC_WRITE(host->base, SYSCTL,
1683                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
1684
1685         /* Wait till the ICS bit is set */
1686         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
1687         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
1688                 && time_before(jiffies, timeout))
1689                 msleep(1);
1690
1691         OMAP_HSMMC_WRITE(host->base, SYSCTL,
1692                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
1693
1694         if (do_send_init_stream)
1695                 send_init_stream(host);
1696
1697         con = OMAP_HSMMC_READ(host->base, CON);
1698         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
1699                 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
1700         else
1701                 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
1702
1703         pm_runtime_put_autosuspend(host->dev);
1704 }
1705
1706 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1707 {
1708         struct omap_hsmmc_host *host = mmc_priv(mmc);
1709
1710         if (!mmc_slot(host).card_detect)
1711                 return -ENOSYS;
1712         return mmc_slot(host).card_detect(host->dev, host->slot_id);
1713 }
1714
1715 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1716 {
1717         struct omap_hsmmc_host *host = mmc_priv(mmc);
1718
1719         if (!mmc_slot(host).get_ro)
1720                 return -ENOSYS;
1721         return mmc_slot(host).get_ro(host->dev, 0);
1722 }
1723
1724 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1725 {
1726         struct omap_hsmmc_host *host = mmc_priv(mmc);
1727
1728         if (mmc_slot(host).init_card)
1729                 mmc_slot(host).init_card(card);
1730 }
1731
1732 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1733 {
1734         u32 hctl, capa, value;
1735
1736         /* Only MMC1 supports 3.0V */
1737         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1738                 hctl = SDVS30;
1739                 capa = VS30 | VS18;
1740         } else {
1741                 hctl = SDVS18;
1742                 capa = VS18;
1743         }
1744
1745         value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1746         OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1747
1748         value = OMAP_HSMMC_READ(host->base, CAPA);
1749         OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1750
1751         /* Set the controller to AUTO IDLE mode */
1752         value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1753         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1754
1755         /* Set SD bus power bit */
1756         set_sd_bus_power(host);
1757 }
1758
1759 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1760 {
1761         struct omap_hsmmc_host *host = mmc_priv(mmc);
1762
1763         pm_runtime_get_sync(host->dev);
1764
1765         return 0;
1766 }
1767
1768 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
1769 {
1770         struct omap_hsmmc_host *host = mmc_priv(mmc);
1771
1772         pm_runtime_mark_last_busy(host->dev);
1773         pm_runtime_put_autosuspend(host->dev);
1774
1775         return 0;
1776 }
1777
1778 static const struct mmc_host_ops omap_hsmmc_ops = {
1779         .enable = omap_hsmmc_enable_fclk,
1780         .disable = omap_hsmmc_disable_fclk,
1781         .post_req = omap_hsmmc_post_req,
1782         .pre_req = omap_hsmmc_pre_req,
1783         .request = omap_hsmmc_request,
1784         .set_ios = omap_hsmmc_set_ios,
1785         .get_cd = omap_hsmmc_get_cd,
1786         .get_ro = omap_hsmmc_get_ro,
1787         .init_card = omap_hsmmc_init_card,
1788         /* NYET -- enable_sdio_irq */
1789 };
1790
1791 #ifdef CONFIG_DEBUG_FS
1792
1793 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1794 {
1795         struct mmc_host *mmc = s->private;
1796         struct omap_hsmmc_host *host = mmc_priv(mmc);
1797         int context_loss = 0;
1798
1799         if (host->pdata->get_context_loss_count)
1800                 context_loss = host->pdata->get_context_loss_count(host->dev);
1801
1802         seq_printf(s, "mmc%d:\n"
1803                         " enabled:\t%d\n"
1804                         " dpm_state:\t%d\n"
1805                         " nesting_cnt:\t%d\n"
1806                         " ctx_loss:\t%d:%d\n"
1807                         "\nregs:\n",
1808                         mmc->index, mmc->enabled ? 1 : 0,
1809                         host->dpm_state, mmc->nesting_cnt,
1810                         host->context_loss, context_loss);
1811
1812         if (host->suspended) {
1813                 seq_printf(s, "host suspended, can't read registers\n");
1814                 return 0;
1815         }
1816
1817         pm_runtime_get_sync(host->dev);
1818
1819         seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1820                         OMAP_HSMMC_READ(host->base, SYSCONFIG));
1821         seq_printf(s, "CON:\t\t0x%08x\n",
1822                         OMAP_HSMMC_READ(host->base, CON));
1823         seq_printf(s, "HCTL:\t\t0x%08x\n",
1824                         OMAP_HSMMC_READ(host->base, HCTL));
1825         seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1826                         OMAP_HSMMC_READ(host->base, SYSCTL));
1827         seq_printf(s, "IE:\t\t0x%08x\n",
1828                         OMAP_HSMMC_READ(host->base, IE));
1829         seq_printf(s, "ISE:\t\t0x%08x\n",
1830                         OMAP_HSMMC_READ(host->base, ISE));
1831         seq_printf(s, "CAPA:\t\t0x%08x\n",
1832                         OMAP_HSMMC_READ(host->base, CAPA));
1833
1834         pm_runtime_mark_last_busy(host->dev);
1835         pm_runtime_put_autosuspend(host->dev);
1836
1837         return 0;
1838 }
1839
1840 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1841 {
1842         return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1843 }
1844
1845 static const struct file_operations mmc_regs_fops = {
1846         .open           = omap_hsmmc_regs_open,
1847         .read           = seq_read,
1848         .llseek         = seq_lseek,
1849         .release        = single_release,
1850 };
1851
1852 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1853 {
1854         if (mmc->debugfs_root)
1855                 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1856                         mmc, &mmc_regs_fops);
1857 }
1858
1859 #else
1860
1861 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1862 {
1863 }
1864
1865 #endif
1866
1867 static int __init omap_hsmmc_probe(struct platform_device *pdev)
1868 {
1869         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1870         struct mmc_host *mmc;
1871         struct omap_hsmmc_host *host = NULL;
1872         struct resource *res;
1873         int ret, irq;
1874
1875         if (pdata == NULL) {
1876                 dev_err(&pdev->dev, "Platform Data is missing\n");
1877                 return -ENXIO;
1878         }
1879
1880         if (pdata->nr_slots == 0) {
1881                 dev_err(&pdev->dev, "No Slots\n");
1882                 return -ENXIO;
1883         }
1884
1885         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1886         irq = platform_get_irq(pdev, 0);
1887         if (res == NULL || irq < 0)
1888                 return -ENXIO;
1889
1890         res->start += pdata->reg_offset;
1891         res->end += pdata->reg_offset;
1892         res = request_mem_region(res->start, resource_size(res), pdev->name);
1893         if (res == NULL)
1894                 return -EBUSY;
1895
1896         ret = omap_hsmmc_gpio_init(pdata);
1897         if (ret)
1898                 goto err;
1899
1900         mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1901         if (!mmc) {
1902                 ret = -ENOMEM;
1903                 goto err_alloc;
1904         }
1905
1906         host            = mmc_priv(mmc);
1907         host->mmc       = mmc;
1908         host->pdata     = pdata;
1909         host->dev       = &pdev->dev;
1910         host->use_dma   = 1;
1911         host->dev->dma_mask = &pdata->dma_mask;
1912         host->dma_ch    = -1;
1913         host->irq       = irq;
1914         host->id        = pdev->id;
1915         host->slot_id   = 0;
1916         host->mapbase   = res->start;
1917         host->base      = ioremap(host->mapbase, SZ_4K);
1918         host->power_mode = MMC_POWER_OFF;
1919         host->next_data.cookie = 1;
1920
1921         platform_set_drvdata(pdev, host);
1922         INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect);
1923
1924         mmc->ops        = &omap_hsmmc_ops;
1925
1926         /*
1927          * If regulator_disable can only put vcc_aux to sleep then there is
1928          * no off state.
1929          */
1930         if (mmc_slot(host).vcc_aux_disable_is_sleep)
1931                 mmc_slot(host).no_off = 1;
1932
1933         mmc->f_min      = 400000;
1934         mmc->f_max      = 52000000;
1935
1936         spin_lock_init(&host->irq_lock);
1937
1938         host->iclk = clk_get(&pdev->dev, "ick");
1939         if (IS_ERR(host->iclk)) {
1940                 ret = PTR_ERR(host->iclk);
1941                 host->iclk = NULL;
1942                 goto err1;
1943         }
1944         host->fclk = clk_get(&pdev->dev, "fck");
1945         if (IS_ERR(host->fclk)) {
1946                 ret = PTR_ERR(host->fclk);
1947                 host->fclk = NULL;
1948                 clk_put(host->iclk);
1949                 goto err1;
1950         }
1951
1952         omap_hsmmc_context_save(host);
1953
1954         mmc->caps |= MMC_CAP_DISABLE;
1955
1956         pm_runtime_enable(host->dev);
1957         pm_runtime_get_sync(host->dev);
1958         pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1959         pm_runtime_use_autosuspend(host->dev);
1960
1961         if (cpu_is_omap2430()) {
1962                 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1963                 /*
1964                  * MMC can still work without debounce clock.
1965                  */
1966                 if (IS_ERR(host->dbclk))
1967                         dev_warn(mmc_dev(host->mmc),
1968                                 "Failed to get debounce clock\n");
1969                 else
1970                         host->got_dbclk = 1;
1971
1972                 if (host->got_dbclk)
1973                         if (clk_enable(host->dbclk) != 0)
1974                                 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1975                                                         " clk failed\n");
1976         }
1977
1978         /* Since we do only SG emulation, we can have as many segs
1979          * as we want. */
1980         mmc->max_segs = 1024;
1981
1982         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
1983         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
1984         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1985         mmc->max_seg_size = mmc->max_req_size;
1986
1987         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1988                      MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
1989
1990         mmc->caps |= mmc_slot(host).caps;
1991         if (mmc->caps & MMC_CAP_8_BIT_DATA)
1992                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1993
1994         if (mmc_slot(host).nonremovable)
1995                 mmc->caps |= MMC_CAP_NONREMOVABLE;
1996
1997         omap_hsmmc_conf_bus_power(host);
1998
1999         /* Select DMA lines */
2000         switch (host->id) {
2001         case OMAP_MMC1_DEVID:
2002                 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
2003                 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
2004                 break;
2005         case OMAP_MMC2_DEVID:
2006                 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
2007                 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
2008                 break;
2009         case OMAP_MMC3_DEVID:
2010                 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
2011                 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
2012                 break;
2013         case OMAP_MMC4_DEVID:
2014                 host->dma_line_tx = OMAP44XX_DMA_MMC4_TX;
2015                 host->dma_line_rx = OMAP44XX_DMA_MMC4_RX;
2016                 break;
2017         case OMAP_MMC5_DEVID:
2018                 host->dma_line_tx = OMAP44XX_DMA_MMC5_TX;
2019                 host->dma_line_rx = OMAP44XX_DMA_MMC5_RX;
2020                 break;
2021         default:
2022                 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
2023                 goto err_irq;
2024         }
2025
2026         /* Request IRQ for MMC operations */
2027         ret = request_irq(host->irq, omap_hsmmc_irq, IRQF_DISABLED,
2028                         mmc_hostname(mmc), host);
2029         if (ret) {
2030                 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2031                 goto err_irq;
2032         }
2033
2034         if (pdata->init != NULL) {
2035                 if (pdata->init(&pdev->dev) != 0) {
2036                         dev_dbg(mmc_dev(host->mmc),
2037                                 "Unable to configure MMC IRQs\n");
2038                         goto err_irq_cd_init;
2039                 }
2040         }
2041
2042         if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
2043                 ret = omap_hsmmc_reg_get(host);
2044                 if (ret)
2045                         goto err_reg;
2046                 host->use_reg = 1;
2047         }
2048
2049         mmc->ocr_avail = mmc_slot(host).ocr_mask;
2050
2051         /* Request IRQ for card detect */
2052         if ((mmc_slot(host).card_detect_irq)) {
2053                 ret = request_irq(mmc_slot(host).card_detect_irq,
2054                                   omap_hsmmc_cd_handler,
2055                                   IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
2056                                           | IRQF_DISABLED,
2057                                   mmc_hostname(mmc), host);
2058                 if (ret) {
2059                         dev_dbg(mmc_dev(host->mmc),
2060                                 "Unable to grab MMC CD IRQ\n");
2061                         goto err_irq_cd;
2062                 }
2063                 pdata->suspend = omap_hsmmc_suspend_cdirq;
2064                 pdata->resume = omap_hsmmc_resume_cdirq;
2065         }
2066
2067         omap_hsmmc_disable_irq(host);
2068
2069         omap_hsmmc_protect_card(host);
2070
2071         mmc_add_host(mmc);
2072
2073         if (mmc_slot(host).name != NULL) {
2074                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2075                 if (ret < 0)
2076                         goto err_slot_name;
2077         }
2078         if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
2079                 ret = device_create_file(&mmc->class_dev,
2080                                         &dev_attr_cover_switch);
2081                 if (ret < 0)
2082                         goto err_slot_name;
2083         }
2084
2085         omap_hsmmc_debugfs(mmc);
2086         pm_runtime_mark_last_busy(host->dev);
2087         pm_runtime_put_autosuspend(host->dev);
2088
2089         return 0;
2090
2091 err_slot_name:
2092         mmc_remove_host(mmc);
2093         free_irq(mmc_slot(host).card_detect_irq, host);
2094 err_irq_cd:
2095         if (host->use_reg)
2096                 omap_hsmmc_reg_put(host);
2097 err_reg:
2098         if (host->pdata->cleanup)
2099                 host->pdata->cleanup(&pdev->dev);
2100 err_irq_cd_init:
2101         free_irq(host->irq, host);
2102 err_irq:
2103         pm_runtime_mark_last_busy(host->dev);
2104         pm_runtime_put_autosuspend(host->dev);
2105         clk_put(host->fclk);
2106         clk_put(host->iclk);
2107         if (host->got_dbclk) {
2108                 clk_disable(host->dbclk);
2109                 clk_put(host->dbclk);
2110         }
2111 err1:
2112         iounmap(host->base);
2113         platform_set_drvdata(pdev, NULL);
2114         mmc_free_host(mmc);
2115 err_alloc:
2116         omap_hsmmc_gpio_free(pdata);
2117 err:
2118         release_mem_region(res->start, resource_size(res));
2119         return ret;
2120 }
2121
2122 static int omap_hsmmc_remove(struct platform_device *pdev)
2123 {
2124         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2125         struct resource *res;
2126
2127         if (host) {
2128                 pm_runtime_get_sync(host->dev);
2129                 mmc_remove_host(host->mmc);
2130                 if (host->use_reg)
2131                         omap_hsmmc_reg_put(host);
2132                 if (host->pdata->cleanup)
2133                         host->pdata->cleanup(&pdev->dev);
2134                 free_irq(host->irq, host);
2135                 if (mmc_slot(host).card_detect_irq)
2136                         free_irq(mmc_slot(host).card_detect_irq, host);
2137                 flush_work_sync(&host->mmc_carddetect_work);
2138
2139                 pm_runtime_put_sync(host->dev);
2140                 pm_runtime_disable(host->dev);
2141                 clk_put(host->fclk);
2142                 clk_put(host->iclk);
2143                 if (host->got_dbclk) {
2144                         clk_disable(host->dbclk);
2145                         clk_put(host->dbclk);
2146                 }
2147
2148                 mmc_free_host(host->mmc);
2149                 iounmap(host->base);
2150                 omap_hsmmc_gpio_free(pdev->dev.platform_data);
2151         }
2152
2153         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2154         if (res)
2155                 release_mem_region(res->start, resource_size(res));
2156         platform_set_drvdata(pdev, NULL);
2157
2158         return 0;
2159 }
2160
2161 #ifdef CONFIG_PM
2162 static int omap_hsmmc_suspend(struct device *dev)
2163 {
2164         int ret = 0;
2165         struct platform_device *pdev = to_platform_device(dev);
2166         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2167
2168         if (host && host->suspended)
2169                 return 0;
2170
2171         if (host) {
2172                 pm_runtime_get_sync(host->dev);
2173                 host->suspended = 1;
2174                 if (host->pdata->suspend) {
2175                         ret = host->pdata->suspend(&pdev->dev,
2176                                                         host->slot_id);
2177                         if (ret) {
2178                                 dev_dbg(mmc_dev(host->mmc),
2179                                         "Unable to handle MMC board"
2180                                         " level suspend\n");
2181                                 host->suspended = 0;
2182                                 return ret;
2183                         }
2184                 }
2185                 cancel_work_sync(&host->mmc_carddetect_work);
2186                 ret = mmc_suspend_host(host->mmc);
2187
2188                 if (ret == 0) {
2189                         omap_hsmmc_disable_irq(host);
2190                         OMAP_HSMMC_WRITE(host->base, HCTL,
2191                                 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2192                         if (host->got_dbclk)
2193                                 clk_disable(host->dbclk);
2194                 } else {
2195                         host->suspended = 0;
2196                         if (host->pdata->resume) {
2197                                 ret = host->pdata->resume(&pdev->dev,
2198                                                           host->slot_id);
2199                                 if (ret)
2200                                         dev_dbg(mmc_dev(host->mmc),
2201                                                 "Unmask interrupt failed\n");
2202                         }
2203                 }
2204                 pm_runtime_put_sync(host->dev);
2205         }
2206         return ret;
2207 }
2208
2209 /* Routine to resume the MMC device */
2210 static int omap_hsmmc_resume(struct device *dev)
2211 {
2212         int ret = 0;
2213         struct platform_device *pdev = to_platform_device(dev);
2214         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2215
2216         if (host && !host->suspended)
2217                 return 0;
2218
2219         if (host) {
2220                 pm_runtime_get_sync(host->dev);
2221
2222                 if (host->got_dbclk)
2223                         clk_enable(host->dbclk);
2224
2225                 omap_hsmmc_conf_bus_power(host);
2226
2227                 if (host->pdata->resume) {
2228                         ret = host->pdata->resume(&pdev->dev, host->slot_id);
2229                         if (ret)
2230                                 dev_dbg(mmc_dev(host->mmc),
2231                                         "Unmask interrupt failed\n");
2232                 }
2233
2234                 omap_hsmmc_protect_card(host);
2235
2236                 /* Notify the core to resume the host */
2237                 ret = mmc_resume_host(host->mmc);
2238                 if (ret == 0)
2239                         host->suspended = 0;
2240
2241                 pm_runtime_mark_last_busy(host->dev);
2242                 pm_runtime_put_autosuspend(host->dev);
2243         }
2244
2245         return ret;
2246
2247 }
2248
2249 #else
2250 #define omap_hsmmc_suspend      NULL
2251 #define omap_hsmmc_resume               NULL
2252 #endif
2253
2254 static int omap_hsmmc_runtime_suspend(struct device *dev)
2255 {
2256         struct omap_hsmmc_host *host;
2257
2258         host = platform_get_drvdata(to_platform_device(dev));
2259         omap_hsmmc_context_save(host);
2260         dev_dbg(mmc_dev(host->mmc), "disabled\n");
2261
2262         return 0;
2263 }
2264
2265 static int omap_hsmmc_runtime_resume(struct device *dev)
2266 {
2267         struct omap_hsmmc_host *host;
2268
2269         host = platform_get_drvdata(to_platform_device(dev));
2270         omap_hsmmc_context_restore(host);
2271         dev_dbg(mmc_dev(host->mmc), "enabled\n");
2272
2273         return 0;
2274 }
2275
2276 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2277         .suspend        = omap_hsmmc_suspend,
2278         .resume         = omap_hsmmc_resume,
2279         .runtime_suspend = omap_hsmmc_runtime_suspend,
2280         .runtime_resume = omap_hsmmc_runtime_resume,
2281 };
2282
2283 static struct platform_driver omap_hsmmc_driver = {
2284         .remove         = omap_hsmmc_remove,
2285         .driver         = {
2286                 .name = DRIVER_NAME,
2287                 .owner = THIS_MODULE,
2288                 .pm = &omap_hsmmc_dev_pm_ops,
2289         },
2290 };
2291
2292 static int __init omap_hsmmc_init(void)
2293 {
2294         /* Register the MMC driver */
2295         return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe);
2296 }
2297
2298 static void __exit omap_hsmmc_cleanup(void)
2299 {
2300         /* Unregister MMC driver */
2301         platform_driver_unregister(&omap_hsmmc_driver);
2302 }
2303
2304 module_init(omap_hsmmc_init);
2305 module_exit(omap_hsmmc_cleanup);
2306
2307 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2308 MODULE_LICENSE("GPL");
2309 MODULE_ALIAS("platform:" DRIVER_NAME);
2310 MODULE_AUTHOR("Texas Instruments Inc");