drivers/mmc/host/omap_hsmmc.c

   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/kernel.h>
  21 #include <linux/debugfs.h>
  22 #include <linux/seq_file.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/delay.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/timer.h>
  28 #include <linux/clk.h>
  29 #include <linux/mmc/host.h>
  30 #include <linux/mmc/core.h>
  31 #include <linux/mmc/mmc.h>
  32 #include <linux/io.h>
  33 #include <linux/semaphore.h>
  34 #include <linux/gpio.h>
  35 #include <linux/regulator/consumer.h>
  36 #include <linux/pm_runtime.h>
  37 #include <plat/dma.h>
  38 #include <mach/hardware.h>
  39 #include <plat/board.h>
  40 #include <plat/mmc.h>
  41 #include <plat/cpu.h>
  42
  43 /* OMAP HSMMC Host Controller Registers */
  44 #define OMAP_HSMMC_SYSCONFIG    0x0010
  45 #define OMAP_HSMMC_SYSSTATUS    0x0014
  46 #define OMAP_HSMMC_CON          0x002C
  47 #define OMAP_HSMMC_BLK          0x0104
  48 #define OMAP_HSMMC_ARG          0x0108
  49 #define OMAP_HSMMC_CMD          0x010C
  50 #define OMAP_HSMMC_RSP10        0x0110
  51 #define OMAP_HSMMC_RSP32        0x0114
  52 #define OMAP_HSMMC_RSP54        0x0118
  53 #define OMAP_HSMMC_RSP76        0x011C
  54 #define OMAP_HSMMC_DATA         0x0120
  55 #define OMAP_HSMMC_HCTL         0x0128
  56 #define OMAP_HSMMC_SYSCTL       0x012C
  57 #define OMAP_HSMMC_STAT         0x0130
  58 #define OMAP_HSMMC_IE           0x0134
  59 #define OMAP_HSMMC_ISE          0x0138
  60 #define OMAP_HSMMC_CAPA         0x0140
  61
  62 #define VS18                    (1 << 26)
  63 #define VS30                    (1 << 25)
  64 #define SDVS18                  (0x5 << 9)
  65 #define SDVS30                  (0x6 << 9)
  66 #define SDVS33                  (0x7 << 9)
  67 #define SDVS_MASK               0x00000E00
  68 #define SDVSCLR                 0xFFFFF1FF
  69 #define SDVSDET                 0x00000400
  70 #define AUTOIDLE                0x1
  71 #define SDBP                    (1 << 8)
  72 #define DTO                     0xe
  73 #define ICE                     0x1
  74 #define ICS                     0x2
  75 #define CEN                     (1 << 2)
  76 #define CLKD_MASK               0x0000FFC0
  77 #define CLKD_SHIFT              6
  78 #define DTO_MASK                0x000F0000
  79 #define DTO_SHIFT               16
  80 #define INT_EN_MASK             0x307F0033
  81 #define BWR_ENABLE              (1 << 4)
  82 #define BRR_ENABLE              (1 << 5)
  83 #define DTO_ENABLE              (1 << 20)
  84 #define INIT_STREAM             (1 << 1)
  85 #define DP_SELECT               (1 << 21)
  86 #define DDIR                    (1 << 4)
  87 #define DMA_EN                  0x1
  88 #define MSBS                    (1 << 5)
  89 #define BCE                     (1 << 1)
  90 #define FOUR_BIT                (1 << 1)
  91 #define DW8                     (1 << 5)
  92 #define CC                      0x1
  93 #define TC                      0x02
  94 #define OD                      0x1
  95 #define ERR                     (1 << 15)
  96 #define CMD_TIMEOUT             (1 << 16)
  97 #define DATA_TIMEOUT            (1 << 20)
  98 #define CMD_CRC                 (1 << 17)
  99 #define DATA_CRC                (1 << 21)
 100 #define CARD_ERR                (1 << 28)
 101 #define STAT_CLEAR              0xFFFFFFFF
 102 #define INIT_STREAM_CMD         0x00000000
 103 #define DUAL_VOLT_OCR_BIT       7
 104 #define SRC                     (1 << 25)
 105 #define SRD                     (1 << 26)
 106 #define SOFTRESET               (1 << 1)
 107 #define RESETDONE               (1 << 0)
 108
 109 #define MMC_AUTOSUSPEND_DELAY   100
 110 #define MMC_TIMEOUT_MS          20
 111 #define OMAP_MMC_MIN_CLOCK      400000
 112 #define OMAP_MMC_MAX_CLOCK      52000000
 113 #define DRIVER_NAME             "omap_hsmmc"
 114
 115 /*
 116  * One controller can have multiple slots, like on some omap boards using
 117  * omap.c controller driver. Luckily this is not currently done on any known
 118  * omap_hsmmc.c device.
 119  */
 120 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
 121
 122 /*
 123  * MMC Host controller read/write API's
 124  */
 125 #define OMAP_HSMMC_READ(base, reg)      \
 126         __raw_readl((base) + OMAP_HSMMC_##reg)
 127
 128 #define OMAP_HSMMC_WRITE(base, reg, val) \
 129         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 130
 131 struct omap_hsmmc_next {
 132         unsigned int    dma_len;
 133         s32             cookie;
 134 };
 135
 136 struct omap_hsmmc_host {
 137         struct  device          *dev;
 138         struct  mmc_host        *mmc;
 139         struct  mmc_request     *mrq;
 140         struct  mmc_command     *cmd;
 141         struct  mmc_data        *data;
 142         struct  clk             *fclk;
 143         struct  clk             *dbclk;
 144         /*
 145          * vcc == configured supply
 146          * vcc_aux == optional
 147          *   -  MMC1, supply for DAT4..DAT7
 148          *   -  MMC2/MMC2, external level shifter voltage supply, for
 149          *      chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
 150          */
 151         struct  regulator       *vcc;
 152         struct  regulator       *vcc_aux;
 153         void    __iomem         *base;
 154         resource_size_t         mapbase;
 155         spinlock_t              irq_lock; /* Prevent races with irq handler */
 156         unsigned int            dma_len;
 157         unsigned int            dma_sg_idx;
 158         unsigned char           bus_mode;
 159         unsigned char           power_mode;
 160         u32                     *buffer;
 161         u32                     bytesleft;
 162         int                     suspended;
 163         int                     irq;
 164         int                     use_dma, dma_ch;
 165         int                     dma_line_tx, dma_line_rx;
 166         int                     slot_id;
 167         int                     got_dbclk;
 168         int                     response_busy;
 169         int                     context_loss;
 170         int                     vdd;
 171         int                     protect_card;
 172         int                     reqs_blocked;
 173         int                     use_reg;
 174         int                     req_in_progress;
 175         struct omap_hsmmc_next  next_data;
 176
 177         struct  omap_mmc_platform_data  *pdata;
 178 };
 179
 180 static int omap_hsmmc_card_detect(struct device *dev, int slot)
 181 {
 182         struct omap_mmc_platform_data *mmc = dev->platform_data;
 183
 184         /* NOTE: assumes card detect signal is active-low */
 185         return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
 186 }
 187
 188 static int omap_hsmmc_get_wp(struct device *dev, int slot)
 189 {
 190         struct omap_mmc_platform_data *mmc = dev->platform_data;
 191
 192         /* NOTE: assumes write protect signal is active-high */
 193         return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
 194 }
 195
 196 static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
 197 {
 198         struct omap_mmc_platform_data *mmc = dev->platform_data;
 199
 200         /* NOTE: assumes card detect signal is active-low */
 201         return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
 202 }
 203
 204 #ifdef CONFIG_PM
 205
 206 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
 207 {
 208         struct omap_mmc_platform_data *mmc = dev->platform_data;
 209
 210         disable_irq(mmc->slots[0].card_detect_irq);
 211         return 0;
 212 }
 213
 214 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
 215 {
 216         struct omap_mmc_platform_data *mmc = dev->platform_data;
 217
 218         enable_irq(mmc->slots[0].card_detect_irq);
 219         return 0;
 220 }
 221
 222 #else
 223
 224 #define omap_hsmmc_suspend_cdirq        NULL
 225 #define omap_hsmmc_resume_cdirq         NULL
 226
 227 #endif
 228
 229 #ifdef CONFIG_REGULATOR
 230
 231 static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on,
 232                                    int vdd)
 233 {
 234         struct omap_hsmmc_host *host =
 235                 platform_get_drvdata(to_platform_device(dev));
 236         int ret = 0;
 237
 238         /*
 239          * If we don't see a Vcc regulator, assume it's a fixed
 240          * voltage always-on regulator.
 241          */
 242         if (!host->vcc)
 243                 return 0;
 244
 245         if (mmc_slot(host).before_set_reg)
 246                 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
 247
 248         /*
 249          * Assume Vcc regulator is used only to power the card ... OMAP
 250          * VDDS is used to power the pins, optionally with a transceiver to
 251          * support cards using voltages other than VDDS (1.8V nominal).  When a
 252          * transceiver is used, DAT3..7 are muxed as transceiver control pins.
 253          *
 254          * In some cases this regulator won't support enable/disable;
 255          * e.g. it's a fixed rail for a WLAN chip.
 256          *
 257          * In other cases vcc_aux switches interface power.  Example, for
 258          * eMMC cards it represents VccQ.  Sometimes transceivers or SDIO
 259          * chips/cards need an interface voltage rail too.
 260          */
 261         if (power_on) {
 262                 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
 263                 /* Enable interface voltage rail, if needed */
 264                 if (ret == 0 && host->vcc_aux) {
 265                         ret = regulator_enable(host->vcc_aux);
 266                         if (ret < 0)
 267                                 ret = mmc_regulator_set_ocr(host->mmc,
 268                                                         host->vcc, 0);
 269                 }
 270         } else {
 271                 /* Shut down the rail */
 272                 if (host->vcc_aux)
 273                         ret = regulator_disable(host->vcc_aux);
 274                 if (!ret) {
 275                         /* Then proceed to shut down the local regulator */
 276                         ret = mmc_regulator_set_ocr(host->mmc,
 277                                                 host->vcc, 0);
 278                 }
 279         }
 280
 281         if (mmc_slot(host).after_set_reg)
 282                 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
 283
 284         return ret;
 285 }
 286
 287 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
 288 {
 289         struct regulator *reg;
 290         int ocr_value = 0;
 291
 292         mmc_slot(host).set_power = omap_hsmmc_set_power;
 293
 294         reg = regulator_get(host->dev, "vmmc");
 295         if (IS_ERR(reg)) {
 296                 dev_dbg(host->dev, "vmmc regulator missing\n");
 297         } else {
 298                 host->vcc = reg;
 299                 ocr_value = mmc_regulator_get_ocrmask(reg);
 300                 if (!mmc_slot(host).ocr_mask) {
 301                         mmc_slot(host).ocr_mask = ocr_value;
 302                 } else {
 303                         if (!(mmc_slot(host).ocr_mask & ocr_value)) {
 304                                 dev_err(host->dev, "ocrmask %x is not supported\n",
 305                                         mmc_slot(host).ocr_mask);
 306                                 mmc_slot(host).ocr_mask = 0;
 307                                 return -EINVAL;
 308                         }
 309                 }
 310
 311                 /* Allow an aux regulator */
 312                 reg = regulator_get(host->dev, "vmmc_aux");
 313                 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
 314
 315                 /* For eMMC do not power off when not in sleep state */
 316                 if (mmc_slot(host).no_regulator_off_init)
 317                         return 0;
 318                 /*
 319                 * UGLY HACK:  workaround regulator framework bugs.
 320                 * When the bootloader leaves a supply active, it's
 321                 * initialized with zero usecount ... and we can't
 322                 * disable it without first enabling it.  Until the
 323                 * framework is fixed, we need a workaround like this
 324                 * (which is safe for MMC, but not in general).
 325                 */
 326                 if (regulator_is_enabled(host->vcc) > 0 ||
 327                     (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
 328                         int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
 329
 330                         mmc_slot(host).set_power(host->dev, host->slot_id,
 331                                                  1, vdd);
 332                         mmc_slot(host).set_power(host->dev, host->slot_id,
 333                                                  0, 0);
 334                 }
 335         }
 336
 337         return 0;
 338 }
 339
 340 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
 341 {
 342         regulator_put(host->vcc);
 343         regulator_put(host->vcc_aux);
 344         mmc_slot(host).set_power = NULL;
 345 }
 346
 347 static inline int omap_hsmmc_have_reg(void)
 348 {
 349         return 1;
 350 }
 351
 352 #else
 353
 354 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
 355 {
 356         return -EINVAL;
 357 }
 358
 359 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
 360 {
 361 }
 362
 363 static inline int omap_hsmmc_have_reg(void)
 364 {
 365         return 0;
 366 }
 367
 368 #endif
 369
 370 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
 371 {
 372         int ret;
 373
 374         if (gpio_is_valid(pdata->slots[0].switch_pin)) {
 375                 if (pdata->slots[0].cover)
 376                         pdata->slots[0].get_cover_state =
 377                                         omap_hsmmc_get_cover_state;
 378                 else
 379                         pdata->slots[0].card_detect = omap_hsmmc_card_detect;
 380                 pdata->slots[0].card_detect_irq =
 381                                 gpio_to_irq(pdata->slots[0].switch_pin);
 382                 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
 383                 if (ret)
 384                         return ret;
 385                 ret = gpio_direction_input(pdata->slots[0].switch_pin);
 386                 if (ret)
 387                         goto err_free_sp;
 388         } else
 389                 pdata->slots[0].switch_pin = -EINVAL;
 390
 391         if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
 392                 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
 393                 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
 394                 if (ret)
 395                         goto err_free_cd;
 396                 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
 397                 if (ret)
 398                         goto err_free_wp;
 399         } else
 400                 pdata->slots[0].gpio_wp = -EINVAL;
 401
 402         return 0;
 403
 404 err_free_wp:
 405         gpio_free(pdata->slots[0].gpio_wp);
 406 err_free_cd:
 407         if (gpio_is_valid(pdata->slots[0].switch_pin))
 408 err_free_sp:
 409                 gpio_free(pdata->slots[0].switch_pin);
 410         return ret;
 411 }
 412
 413 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
 414 {
 415         if (gpio_is_valid(pdata->slots[0].gpio_wp))
 416                 gpio_free(pdata->slots[0].gpio_wp);
 417         if (gpio_is_valid(pdata->slots[0].switch_pin))
 418                 gpio_free(pdata->slots[0].switch_pin);
 419 }
 420
 421 /*
 422  * Start clock to the card
 423  */
 424 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
 425 {
 426         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 427                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 428 }
 429
 430 /*
 431  * Stop clock to the card
 432  */
 433 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
 434 {
 435         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 436                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 437         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 438                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
 439 }
 440
 441 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
 442                                   struct mmc_command *cmd)
 443 {
 444         unsigned int irq_mask;
 445
 446         if (host->use_dma)
 447                 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
 448         else
 449                 irq_mask = INT_EN_MASK;
 450
 451         /* Disable timeout for erases */
 452         if (cmd->opcode == MMC_ERASE)
 453                 irq_mask &= ~DTO_ENABLE;
 454
 455         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 456         OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
 457         OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
 458 }
 459
 460 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
 461 {
 462         OMAP_HSMMC_WRITE(host->base, ISE, 0);
 463         OMAP_HSMMC_WRITE(host->base, IE, 0);
 464         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 465 }
 466
 467 /* Calculate divisor for the given clock frequency */
 468 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
 469 {
 470         u16 dsor = 0;
 471
 472         if (ios->clock) {
 473                 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
 474                 if (dsor > 250)
 475                         dsor = 250;
 476         }
 477
 478         return dsor;
 479 }
 480
 481 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
 482 {
 483         struct mmc_ios *ios = &host->mmc->ios;
 484         unsigned long regval;
 485         unsigned long timeout;
 486
 487         dev_dbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
 488
 489         omap_hsmmc_stop_clock(host);
 490
 491         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
 492         regval = regval & ~(CLKD_MASK | DTO_MASK);
 493         regval = regval | (calc_divisor(host, ios) << 6) | (DTO << 16);
 494         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
 495         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 496                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 497
 498         /* Wait till the ICS bit is set */
 499         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 500         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
 501                 && time_before(jiffies, timeout))
 502                 cpu_relax();
 503
 504         omap_hsmmc_start_clock(host);
 505 }
 506
 507 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
 508 {
 509         struct mmc_ios *ios = &host->mmc->ios;
 510         u32 con;
 511
 512         con = OMAP_HSMMC_READ(host->base, CON);
 513         switch (ios->bus_width) {
 514         case MMC_BUS_WIDTH_8:
 515                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
 516                 break;
 517         case MMC_BUS_WIDTH_4:
 518                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 519                 OMAP_HSMMC_WRITE(host->base, HCTL,
 520                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 521                 break;
 522         case MMC_BUS_WIDTH_1:
 523                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 524                 OMAP_HSMMC_WRITE(host->base, HCTL,
 525                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 526                 break;
 527         }
 528 }
 529
 530 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
 531 {
 532         struct mmc_ios *ios = &host->mmc->ios;
 533         u32 con;
 534
 535         con = OMAP_HSMMC_READ(host->base, CON);
 536         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 537                 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
 538         else
 539                 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
 540 }
 541
 542 #ifdef CONFIG_PM
 543
 544 /*
 545  * Restore the MMC host context, if it was lost as result of a
 546  * power state change.
 547  */
 548 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 549 {
 550         struct mmc_ios *ios = &host->mmc->ios;
 551         struct omap_mmc_platform_data *pdata = host->pdata;
 552         int context_loss = 0;
 553         u32 hctl, capa;
 554         unsigned long timeout;
 555
 556         if (pdata->get_context_loss_count) {
 557                 context_loss = pdata->get_context_loss_count(host->dev);
 558                 if (context_loss < 0)
 559                         return 1;
 560         }
 561
 562         dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
 563                 context_loss == host->context_loss ? "not " : "");
 564         if (host->context_loss == context_loss)
 565                 return 1;
 566
 567         /* Wait for hardware reset */
 568         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 569         while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
 570                 && time_before(jiffies, timeout))
 571                 ;
 572
 573         /* Do software reset */
 574         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
 575         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 576         while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
 577                 && time_before(jiffies, timeout))
 578                 ;
 579
 580         OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
 581                         OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
 582
 583         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
 584                 if (host->power_mode != MMC_POWER_OFF &&
 585                     (1 << ios->vdd) <= MMC_VDD_23_24)
 586                         hctl = SDVS18;
 587                 else
 588                         hctl = SDVS30;
 589                 capa = VS30 | VS18;
 590         } else {
 591                 hctl = SDVS18;
 592                 capa = VS18;
 593         }
 594
 595         OMAP_HSMMC_WRITE(host->base, HCTL,
 596                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
 597
 598         OMAP_HSMMC_WRITE(host->base, CAPA,
 599                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
 600
 601         OMAP_HSMMC_WRITE(host->base, HCTL,
 602                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 603
 604         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 605         while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
 606                 && time_before(jiffies, timeout))
 607                 ;
 608
 609         omap_hsmmc_disable_irq(host);
 610
 611         /* Do not initialize card-specific things if the power is off */
 612         if (host->power_mode == MMC_POWER_OFF)
 613                 goto out;
 614
 615         omap_hsmmc_set_bus_width(host);
 616
 617         omap_hsmmc_set_clock(host);
 618
 619         omap_hsmmc_set_bus_mode(host);
 620
 621 out:
 622         host->context_loss = context_loss;
 623
 624         dev_dbg(mmc_dev(host->mmc), "context is restored\n");
 625         return 0;
 626 }
 627
 628 /*
 629  * Save the MMC host context (store the number of power state changes so far).
 630  */
 631 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 632 {
 633         struct omap_mmc_platform_data *pdata = host->pdata;
 634         int context_loss;
 635
 636         if (pdata->get_context_loss_count) {
 637                 context_loss = pdata->get_context_loss_count(host->dev);
 638                 if (context_loss < 0)
 639                         return;
 640                 host->context_loss = context_loss;
 641         }
 642 }
 643
 644 #else
 645
 646 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 647 {
 648         return 0;
 649 }
 650
 651 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 652 {
 653 }
 654
 655 #endif
 656
 657 /*
 658  * Send init stream sequence to card
 659  * before sending IDLE command
 660  */
 661 static void send_init_stream(struct omap_hsmmc_host *host)
 662 {
 663         int reg = 0;
 664         unsigned long timeout;
 665
 666         if (host->protect_card)
 667                 return;
 668
 669         disable_irq(host->irq);
 670
 671         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 672         OMAP_HSMMC_WRITE(host->base, CON,
 673                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 674         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 675
 676         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 677         while ((reg != CC) && time_before(jiffies, timeout))
 678                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
 679
 680         OMAP_HSMMC_WRITE(host->base, CON,
 681                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 682
 683         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 684         OMAP_HSMMC_READ(host->base, STAT);
 685
 686         enable_irq(host->irq);
 687 }
 688
 689 static inline
 690 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
 691 {
 692         int r = 1;
 693
 694         if (mmc_slot(host).get_cover_state)
 695                 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
 696         return r;
 697 }
 698
 699 static ssize_t
 700 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
 701                            char *buf)
 702 {
 703         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 704         struct omap_hsmmc_host *host = mmc_priv(mmc);
 705
 706         return sprintf(buf, "%s\n",
 707                         omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
 708 }
 709
 710 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
 711
 712 static ssize_t
 713 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
 714                         char *buf)
 715 {
 716         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 717         struct omap_hsmmc_host *host = mmc_priv(mmc);
 718
 719         return sprintf(buf, "%s\n", mmc_slot(host).name);
 720 }
 721
 722 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
 723
 724 /*
 725  * Configure the response type and send the cmd.
 726  */
 727 static void
 728 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
 729         struct mmc_data *data)
 730 {
 731         int cmdreg = 0, resptype = 0, cmdtype = 0;
 732
 733         dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 734                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 735         host->cmd = cmd;
 736
 737         omap_hsmmc_enable_irq(host, cmd);
 738
 739         host->response_busy = 0;
 740         if (cmd->flags & MMC_RSP_PRESENT) {
 741                 if (cmd->flags & MMC_RSP_136)
 742                         resptype = 1;
 743                 else if (cmd->flags & MMC_RSP_BUSY) {
 744                         resptype = 3;
 745                         host->response_busy = 1;
 746                 } else
 747                         resptype = 2;
 748         }
 749
 750         /*
 751          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 752          * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
 753          * a val of 0x3, rest 0x0.
 754          */
 755         if (cmd == host->mrq->stop)
 756                 cmdtype = 0x3;
 757
 758         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 759
 760         if (data) {
 761                 cmdreg |= DP_SELECT | MSBS | BCE;
 762                 if (data->flags & MMC_DATA_READ)
 763                         cmdreg |= DDIR;
 764                 else
 765                         cmdreg &= ~(DDIR);
 766         }
 767
 768         if (host->use_dma)
 769                 cmdreg |= DMA_EN;
 770
 771         host->req_in_progress = 1;
 772
 773         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 774         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 775 }
 776
 777 static int
 778 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
 779 {
 780         if (data->flags & MMC_DATA_WRITE)
 781                 return DMA_TO_DEVICE;
 782         else
 783                 return DMA_FROM_DEVICE;
 784 }
 785
 786 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
 787 {
 788         int dma_ch;
 789
 790         spin_lock(&host->irq_lock);
 791         host->req_in_progress = 0;
 792         dma_ch = host->dma_ch;
 793         spin_unlock(&host->irq_lock);
 794
 795         omap_hsmmc_disable_irq(host);
 796         /* Do not complete the request if DMA is still in progress */
 797         if (mrq->data && host->use_dma && dma_ch != -1)
 798                 return;
 799         host->mrq = NULL;
 800         mmc_request_done(host->mmc, mrq);
 801 }
 802
 803 /*
 804  * Notify the transfer complete to MMC core
 805  */
 806 static void
 807 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
 808 {
 809         if (!data) {
 810                 struct mmc_request *mrq = host->mrq;
 811
 812                 /* TC before CC from CMD6 - don't know why, but it happens */
 813                 if (host->cmd && host->cmd->opcode == 6 &&
 814                     host->response_busy) {
 815                         host->response_busy = 0;
 816                         return;
 817                 }
 818
 819                 omap_hsmmc_request_done(host, mrq);
 820                 return;
 821         }
 822
 823         host->data = NULL;
 824
 825         if (!data->error)
 826                 data->bytes_xfered += data->blocks * (data->blksz);
 827         else
 828                 data->bytes_xfered = 0;
 829
 830         if (!data->stop) {
 831                 omap_hsmmc_request_done(host, data->mrq);
 832                 return;
 833         }
 834         omap_hsmmc_start_command(host, data->stop, NULL);
 835 }
 836
 837 /*
 838  * Notify the core about command completion
 839  */
 840 static void
 841 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
 842 {
 843         host->cmd = NULL;
 844
 845         if (cmd->flags & MMC_RSP_PRESENT) {
 846                 if (cmd->flags & MMC_RSP_136) {
 847                         /* response type 2 */
 848                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
 849                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
 850                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
 851                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
 852                 } else {
 853                         /* response types 1, 1b, 3, 4, 5, 6 */
 854                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
 855                 }
 856         }
 857         if ((host->data == NULL && !host->response_busy) || cmd->error)
 858                 omap_hsmmc_request_done(host, cmd->mrq);
 859 }
 860
 861 /*
 862  * DMA clean up for command errors
 863  */
 864 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
 865 {
 866         int dma_ch;
 867
 868         host->data->error = errno;
 869
 870         spin_lock(&host->irq_lock);
 871         dma_ch = host->dma_ch;
 872         host->dma_ch = -1;
 873         spin_unlock(&host->irq_lock);
 874
 875         if (host->use_dma && dma_ch != -1) {
 876                 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg,
 877                         host->data->sg_len,
 878                         omap_hsmmc_get_dma_dir(host, host->data));
 879                 omap_free_dma(dma_ch);
 880                 host->data->host_cookie = 0;
 881         }
 882         host->data = NULL;
 883 }
 884
 885 /*
 886  * Readable error output
 887  */
 888 #ifdef CONFIG_MMC_DEBUG
 889 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
 890 {
 891         /* --- means reserved bit without definition at documentation */
 892         static const char *omap_hsmmc_status_bits[] = {
 893                 "CC"  , "TC"  , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
 894                 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
 895                 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
 896                 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
 897         };
 898         char res[256];
 899         char *buf = res;
 900         int len, i;
 901
 902         len = sprintf(buf, "MMC IRQ 0x%x :", status);
 903         buf += len;
 904
 905         for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
 906                 if (status & (1 << i)) {
 907                         len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
 908                         buf += len;
 909                 }
 910
 911         dev_dbg(mmc_dev(host->mmc), "%s\n", res);
 912 }
 913 #else
 914 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
 915                                              u32 status)
 916 {
 917 }
 918 #endif  /* CONFIG_MMC_DEBUG */
 919
 920 /*
 921  * MMC controller internal state machines reset
 922  *
 923  * Used to reset command or data internal state machines, using respectively
 924  *  SRC or SRD bit of SYSCTL register
 925  * Can be called from interrupt context
 926  */
 927 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
 928                                                    unsigned long bit)
 929 {
 930         unsigned long i = 0;
 931         unsigned long limit = (loops_per_jiffy *
 932                                 msecs_to_jiffies(MMC_TIMEOUT_MS));
 933
 934         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 935                          OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
 936
 937         /*
 938          * OMAP4 ES2 and greater has an updated reset logic.
 939          * Monitor a 0->1 transition first
 940          */
 941         if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
 942                 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
 943                                         && (i++ < limit))
 944                         cpu_relax();
 945         }
 946         i = 0;
 947
 948         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
 949                 (i++ < limit))
 950                 cpu_relax();
 951
 952         if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
 953                 dev_err(mmc_dev(host->mmc),
 954                         "Timeout waiting on controller reset in %s\n",
 955                         __func__);
 956 }
 957
 958 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
 959 {
 960         struct mmc_data *data;
 961         int end_cmd = 0, end_trans = 0;
 962
 963         if (!host->req_in_progress) {
 964                 do {
 965                         OMAP_HSMMC_WRITE(host->base, STAT, status);
 966                         /* Flush posted write */
 967                         status = OMAP_HSMMC_READ(host->base, STAT);
 968                 } while (status & INT_EN_MASK);
 969                 return;
 970         }
 971
 972         data = host->data;
 973         dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
 974
 975         if (status & ERR) {
 976                 omap_hsmmc_dbg_report_irq(host, status);
 977                 if ((status & CMD_TIMEOUT) ||
 978                         (status & CMD_CRC)) {
 979                         if (host->cmd) {
 980                                 if (status & CMD_TIMEOUT) {
 981                                         omap_hsmmc_reset_controller_fsm(host,
 982                                                                         SRC);
 983                                         host->cmd->error = -ETIMEDOUT;
 984                                 } else {
 985                                         host->cmd->error = -EILSEQ;
 986                                 }
 987                                 end_cmd = 1;
 988                         }
 989                         if (host->data || host->response_busy) {
 990                                 if (host->data)
 991                                         omap_hsmmc_dma_cleanup(host,
 992                                                                 -ETIMEDOUT);
 993                                 host->response_busy = 0;
 994                                 omap_hsmmc_reset_controller_fsm(host, SRD);
 995                         }
 996                 }
 997                 if ((status & DATA_TIMEOUT) ||
 998                         (status & DATA_CRC)) {
 999                         if (host->data || host->response_busy) {
1000                                 int err = (status & DATA_TIMEOUT) ?
1001                                                 -ETIMEDOUT : -EILSEQ;
1002
1003                                 if (host->data)
1004                                         omap_hsmmc_dma_cleanup(host, err);
1005                                 else
1006                                         host->mrq->cmd->error = err;
1007                                 host->response_busy = 0;
1008                                 omap_hsmmc_reset_controller_fsm(host, SRD);
1009                                 end_trans = 1;
1010                         }
1011                 }
1012                 if (status & CARD_ERR) {
1013                         dev_dbg(mmc_dev(host->mmc),
1014                                 "Ignoring card err CMD%d\n", host->cmd->opcode);
1015                         if (host->cmd)
1016                                 end_cmd = 1;
1017                         if (host->data)
1018                                 end_trans = 1;
1019                 }
1020         }
1021
1022         OMAP_HSMMC_WRITE(host->base, STAT, status);
1023
1024         if (end_cmd || ((status & CC) && host->cmd))
1025                 omap_hsmmc_cmd_done(host, host->cmd);
1026         if ((end_trans || (status & TC)) && host->mrq)
1027                 omap_hsmmc_xfer_done(host, data);
1028 }
1029
1030 /*
1031  * MMC controller IRQ handler
1032  */
1033 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1034 {
1035         struct omap_hsmmc_host *host = dev_id;
1036         int status;
1037
1038         status = OMAP_HSMMC_READ(host->base, STAT);
1039         do {
1040                 omap_hsmmc_do_irq(host, status);
1041                 /* Flush posted write */
1042                 status = OMAP_HSMMC_READ(host->base, STAT);
1043         } while (status & INT_EN_MASK);
1044
1045         return IRQ_HANDLED;
1046 }
1047
1048 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1049 {
1050         unsigned long i;
1051
1052         OMAP_HSMMC_WRITE(host->base, HCTL,
1053                          OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1054         for (i = 0; i < loops_per_jiffy; i++) {
1055                 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1056                         break;
1057                 cpu_relax();
1058         }
1059 }
1060
1061 /*
1062  * Switch MMC interface voltage ... only relevant for MMC1.
1063  *
1064  * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1065  * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1066  * Some chips, like eMMC ones, use internal transceivers.
1067  */
1068 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1069 {
1070         u32 reg_val = 0;
1071         int ret;
1072
1073         /* Disable the clocks */
1074         pm_runtime_put_sync(host->dev);
1075         if (host->got_dbclk)
1076                 clk_disable(host->dbclk);
1077
1078         /* Turn the power off */
1079         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1080
1081         /* Turn the power ON with given VDD 1.8 or 3.0v */
1082         if (!ret)
1083                 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1084                                                vdd);
1085         pm_runtime_get_sync(host->dev);
1086         if (host->got_dbclk)
1087                 clk_enable(host->dbclk);
1088
1089         if (ret != 0)
1090                 goto err;
1091
1092         OMAP_HSMMC_WRITE(host->base, HCTL,
1093                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1094         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1095
1096         /*
1097          * If a MMC dual voltage card is detected, the set_ios fn calls
1098          * this fn with VDD bit set for 1.8V. Upon card removal from the
1099          * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1100          *
1101          * Cope with a bit of slop in the range ... per data sheets:
1102          *  - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1103          *    but recommended values are 1.71V to 1.89V
1104          *  - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1105          *    but recommended values are 2.7V to 3.3V
1106          *
1107          * Board setup code shouldn't permit anything very out-of-range.
1108          * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1109          * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1110          */
1111         if ((1 << vdd) <= MMC_VDD_23_24)
1112                 reg_val |= SDVS18;
1113         else
1114                 reg_val |= SDVS30;
1115
1116         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1117         set_sd_bus_power(host);
1118
1119         return 0;
1120 err:
1121         dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1122         return ret;
1123 }
1124
1125 /* Protect the card while the cover is open */
1126 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1127 {
1128         if (!mmc_slot(host).get_cover_state)
1129                 return;
1130
1131         host->reqs_blocked = 0;
1132         if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1133                 if (host->protect_card) {
1134                         dev_info(host->dev, "%s: cover is closed, "
1135                                          "card is now accessible\n",
1136                                          mmc_hostname(host->mmc));
1137                         host->protect_card = 0;
1138                 }
1139         } else {
1140                 if (!host->protect_card) {
1141                         dev_info(host->dev, "%s: cover is open, "
1142                                          "card is now inaccessible\n",
1143                                          mmc_hostname(host->mmc));
1144                         host->protect_card = 1;
1145                 }
1146         }
1147 }
1148
1149 /*
1150  * irq handler to notify the core about card insertion/removal
1151  */
1152 static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
1153 {
1154         struct omap_hsmmc_host *host = dev_id;
1155         struct omap_mmc_slot_data *slot = &mmc_slot(host);
1156         int carddetect;
1157
1158         if (host->suspended)
1159                 return IRQ_HANDLED;
1160
1161         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1162
1163         if (slot->card_detect)
1164                 carddetect = slot->card_detect(host->dev, host->slot_id);
1165         else {
1166                 omap_hsmmc_protect_card(host);
1167                 carddetect = -ENOSYS;
1168         }
1169
1170         if (carddetect)
1171                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1172         else
1173                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1174         return IRQ_HANDLED;
1175 }
1176
1177 static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
1178                                      struct mmc_data *data)
1179 {
1180         int sync_dev;
1181
1182         if (data->flags & MMC_DATA_WRITE)
1183                 sync_dev = host->dma_line_tx;
1184         else
1185                 sync_dev = host->dma_line_rx;
1186         return sync_dev;
1187 }
1188
1189 static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
1190                                        struct mmc_data *data,
1191                                        struct scatterlist *sgl)
1192 {
1193         int blksz, nblk, dma_ch;
1194
1195         dma_ch = host->dma_ch;
1196         if (data->flags & MMC_DATA_WRITE) {
1197                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1198                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1199                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1200                         sg_dma_address(sgl), 0, 0);
1201         } else {
1202                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1203                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1204                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1205                         sg_dma_address(sgl), 0, 0);
1206         }
1207
1208         blksz = host->data->blksz;
1209         nblk = sg_dma_len(sgl) / blksz;
1210
1211         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1212                         blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
1213                         omap_hsmmc_get_dma_sync_dev(host, data),
1214                         !(data->flags & MMC_DATA_WRITE));
1215
1216         omap_start_dma(dma_ch);
1217 }
1218
1219 /*
1220  * DMA call back function
1221  */
1222 static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data)
1223 {
1224         struct omap_hsmmc_host *host = cb_data;
1225         struct mmc_data *data;
1226         int dma_ch, req_in_progress;
1227
1228         if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
1229                 dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
1230                         ch_status);
1231                 return;
1232         }
1233
1234         spin_lock(&host->irq_lock);
1235         if (host->dma_ch < 0) {
1236                 spin_unlock(&host->irq_lock);
1237                 return;
1238         }
1239
1240         data = host->mrq->data;
1241         host->dma_sg_idx++;
1242         if (host->dma_sg_idx < host->dma_len) {
1243                 /* Fire up the next transfer. */
1244                 omap_hsmmc_config_dma_params(host, data,
1245                                            data->sg + host->dma_sg_idx);
1246                 spin_unlock(&host->irq_lock);
1247                 return;
1248         }
1249
1250         if (!data->host_cookie)
1251                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1252                              omap_hsmmc_get_dma_dir(host, data));
1253
1254         req_in_progress = host->req_in_progress;
1255         dma_ch = host->dma_ch;
1256         host->dma_ch = -1;
1257         spin_unlock(&host->irq_lock);
1258
1259         omap_free_dma(dma_ch);
1260
1261         /* If DMA has finished after TC, complete the request */
1262         if (!req_in_progress) {
1263                 struct mmc_request *mrq = host->mrq;
1264
1265                 host->mrq = NULL;
1266                 mmc_request_done(host->mmc, mrq);
1267         }
1268 }
1269
1270 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1271                                        struct mmc_data *data,
1272                                        struct omap_hsmmc_next *next)
1273 {
1274         int dma_len;
1275
1276         if (!next && data->host_cookie &&
1277             data->host_cookie != host->next_data.cookie) {
1278                 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
1279                        " host->next_data.cookie %d\n",
1280                        __func__, data->host_cookie, host->next_data.cookie);
1281                 data->host_cookie = 0;
1282         }
1283
1284         /* Check if next job is already prepared */
1285         if (next ||
1286             (!next && data->host_cookie != host->next_data.cookie)) {
1287                 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1288                                      data->sg_len,
1289                                      omap_hsmmc_get_dma_dir(host, data));
1290
1291         } else {
1292                 dma_len = host->next_data.dma_len;
1293                 host->next_data.dma_len = 0;
1294         }
1295
1296
1297         if (dma_len == 0)
1298                 return -EINVAL;
1299
1300         if (next) {
1301                 next->dma_len = dma_len;
1302                 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1303         } else
1304                 host->dma_len = dma_len;
1305
1306         return 0;
1307 }
1308
1309 /*
1310  * Routine to configure and start DMA for the MMC card
1311  */
1312 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1313                                         struct mmc_request *req)
1314 {
1315         int dma_ch = 0, ret = 0, i;
1316         struct mmc_data *data = req->data;
1317
1318         /* Sanity check: all the SG entries must be aligned by block size. */
1319         for (i = 0; i < data->sg_len; i++) {
1320                 struct scatterlist *sgl;
1321
1322                 sgl = data->sg + i;
1323                 if (sgl->length % data->blksz)
1324                         return -EINVAL;
1325         }
1326         if ((data->blksz % 4) != 0)
1327                 /* REVISIT: The MMC buffer increments only when MSB is written.
1328                  * Return error for blksz which is non multiple of four.
1329                  */
1330                 return -EINVAL;
1331
1332         BUG_ON(host->dma_ch != -1);
1333
1334         ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1335                                "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
1336         if (ret != 0) {
1337                 dev_err(mmc_dev(host->mmc),
1338                         "%s: omap_request_dma() failed with %d\n",
1339                         mmc_hostname(host->mmc), ret);
1340                 return ret;
1341         }
1342         ret = omap_hsmmc_pre_dma_transfer(host, data, NULL);
1343         if (ret)
1344                 return ret;
1345
1346         host->dma_ch = dma_ch;
1347         host->dma_sg_idx = 0;
1348
1349         omap_hsmmc_config_dma_params(host, data, data->sg);
1350
1351         return 0;
1352 }
1353
1354 static void set_data_timeout(struct omap_hsmmc_host *host,
1355                              unsigned int timeout_ns,
1356                              unsigned int timeout_clks)
1357 {
1358         unsigned int timeout, cycle_ns;
1359         uint32_t reg, clkd, dto = 0;
1360
1361         reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1362         clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1363         if (clkd == 0)
1364                 clkd = 1;
1365
1366         cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
1367         timeout = timeout_ns / cycle_ns;
1368         timeout += timeout_clks;
1369         if (timeout) {
1370                 while ((timeout & 0x80000000) == 0) {
1371                         dto += 1;
1372                         timeout <<= 1;
1373                 }
1374                 dto = 31 - dto;
1375                 timeout <<= 1;
1376                 if (timeout && dto)
1377                         dto += 1;
1378                 if (dto >= 13)
1379                         dto -= 13;
1380                 else
1381                         dto = 0;
1382                 if (dto > 14)
1383                         dto = 14;
1384         }
1385
1386         reg &= ~DTO_MASK;
1387         reg |= dto << DTO_SHIFT;
1388         OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1389 }
1390
1391 /*
1392  * Configure block length for MMC/SD cards and initiate the transfer.
1393  */
1394 static int
1395 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1396 {
1397         int ret;
1398         host->data = req->data;
1399
1400         if (req->data == NULL) {
1401                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1402                 /*
1403                  * Set an arbitrary 100ms data timeout for commands with
1404                  * busy signal.
1405                  */
1406                 if (req->cmd->flags & MMC_RSP_BUSY)
1407                         set_data_timeout(host, 100000000U, 0);
1408                 return 0;
1409         }
1410
1411         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1412                                         | (req->data->blocks << 16));
1413         set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
1414
1415         if (host->use_dma) {
1416                 ret = omap_hsmmc_start_dma_transfer(host, req);
1417                 if (ret != 0) {
1418                         dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1419                         return ret;
1420                 }
1421         }
1422         return 0;
1423 }
1424
1425 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1426                                 int err)
1427 {
1428         struct omap_hsmmc_host *host = mmc_priv(mmc);
1429         struct mmc_data *data = mrq->data;
1430
1431         if (host->use_dma) {
1432                 if (data->host_cookie)
1433                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
1434                                      data->sg_len,
1435                                      omap_hsmmc_get_dma_dir(host, data));
1436                 data->host_cookie = 0;
1437         }
1438 }
1439
1440 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1441                                bool is_first_req)
1442 {
1443         struct omap_hsmmc_host *host = mmc_priv(mmc);
1444
1445         if (mrq->data->host_cookie) {
1446                 mrq->data->host_cookie = 0;
1447                 return ;
1448         }
1449
1450         if (host->use_dma)
1451                 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1452                                                 &host->next_data))
1453                         mrq->data->host_cookie = 0;
1454 }
1455
1456 /*
1457  * Request function. for read/write operation
1458  */
1459 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1460 {
1461         struct omap_hsmmc_host *host = mmc_priv(mmc);
1462         int err;
1463
1464         BUG_ON(host->req_in_progress);
1465         BUG_ON(host->dma_ch != -1);
1466         if (host->protect_card) {
1467                 if (host->reqs_blocked < 3) {
1468                         /*
1469                          * Ensure the controller is left in a consistent
1470                          * state by resetting the command and data state
1471                          * machines.
1472                          */
1473                         omap_hsmmc_reset_controller_fsm(host, SRD);
1474                         omap_hsmmc_reset_controller_fsm(host, SRC);
1475                         host->reqs_blocked += 1;
1476                 }
1477                 req->cmd->error = -EBADF;
1478                 if (req->data)
1479                         req->data->error = -EBADF;
1480                 req->cmd->retries = 0;
1481                 mmc_request_done(mmc, req);
1482                 return;
1483         } else if (host->reqs_blocked)
1484                 host->reqs_blocked = 0;
1485         WARN_ON(host->mrq != NULL);
1486         host->mrq = req;
1487         err = omap_hsmmc_prepare_data(host, req);
1488         if (err) {
1489                 req->cmd->error = err;
1490                 if (req->data)
1491                         req->data->error = err;
1492                 host->mrq = NULL;
1493                 mmc_request_done(mmc, req);
1494                 return;
1495         }
1496
1497         omap_hsmmc_start_command(host, req->cmd, req->data);
1498 }
1499
1500 /* Routine to configure clock values. Exposed API to core */
1501 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1502 {
1503         struct omap_hsmmc_host *host = mmc_priv(mmc);
1504         int do_send_init_stream = 0;
1505
1506         pm_runtime_get_sync(host->dev);
1507
1508         if (ios->power_mode != host->power_mode) {
1509                 switch (ios->power_mode) {
1510                 case MMC_POWER_OFF:
1511                         mmc_slot(host).set_power(host->dev, host->slot_id,
1512                                                  0, 0);
1513                         host->vdd = 0;
1514                         break;
1515                 case MMC_POWER_UP:
1516                         mmc_slot(host).set_power(host->dev, host->slot_id,
1517                                                  1, ios->vdd);
1518                         host->vdd = ios->vdd;
1519                         break;
1520                 case MMC_POWER_ON:
1521                         do_send_init_stream = 1;
1522                         break;
1523                 }
1524                 host->power_mode = ios->power_mode;
1525         }
1526
1527         /* FIXME: set registers based only on changes to ios */
1528
1529         omap_hsmmc_set_bus_width(host);
1530
1531         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1532                 /* Only MMC1 can interface at 3V without some flavor
1533                  * of external transceiver; but they all handle 1.8V.
1534                  */
1535                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1536                         (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1537                                 /*
1538                                  * The mmc_select_voltage fn of the core does
1539                                  * not seem to set the power_mode to
1540                                  * MMC_POWER_UP upon recalculating the voltage.
1541                                  * vdd 1.8v.
1542                                  */
1543                         if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1544                                 dev_dbg(mmc_dev(host->mmc),
1545                                                 "Switch operation failed\n");
1546                 }
1547         }
1548
1549         omap_hsmmc_set_clock(host);
1550
1551         if (do_send_init_stream)
1552                 send_init_stream(host);
1553
1554         omap_hsmmc_set_bus_mode(host);
1555
1556         pm_runtime_put_autosuspend(host->dev);
1557 }
1558
1559 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1560 {
1561         struct omap_hsmmc_host *host = mmc_priv(mmc);
1562
1563         if (!mmc_slot(host).card_detect)
1564                 return -ENOSYS;
1565         return mmc_slot(host).card_detect(host->dev, host->slot_id);
1566 }
1567
1568 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1569 {
1570         struct omap_hsmmc_host *host = mmc_priv(mmc);
1571
1572         if (!mmc_slot(host).get_ro)
1573                 return -ENOSYS;
1574         return mmc_slot(host).get_ro(host->dev, 0);
1575 }
1576
1577 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1578 {
1579         struct omap_hsmmc_host *host = mmc_priv(mmc);
1580
1581         if (mmc_slot(host).init_card)
1582                 mmc_slot(host).init_card(card);
1583 }
1584
1585 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1586 {
1587         u32 hctl, capa, value;
1588
1589         /* Only MMC1 supports 3.0V */
1590         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1591                 hctl = SDVS30;
1592                 capa = VS30 | VS18;
1593         } else {
1594                 hctl = SDVS18;
1595                 capa = VS18;
1596         }
1597
1598         value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1599         OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1600
1601         value = OMAP_HSMMC_READ(host->base, CAPA);
1602         OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1603
1604         /* Set the controller to AUTO IDLE mode */
1605         value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1606         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1607
1608         /* Set SD bus power bit */
1609         set_sd_bus_power(host);
1610 }
1611
1612 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1613 {
1614         struct omap_hsmmc_host *host = mmc_priv(mmc);
1615
1616         pm_runtime_get_sync(host->dev);
1617
1618         return 0;
1619 }
1620
1621 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc)
1622 {
1623         struct omap_hsmmc_host *host = mmc_priv(mmc);
1624
1625         pm_runtime_mark_last_busy(host->dev);
1626         pm_runtime_put_autosuspend(host->dev);
1627
1628         return 0;
1629 }
1630
1631 static const struct mmc_host_ops omap_hsmmc_ops = {
1632         .enable = omap_hsmmc_enable_fclk,
1633         .disable = omap_hsmmc_disable_fclk,
1634         .post_req = omap_hsmmc_post_req,
1635         .pre_req = omap_hsmmc_pre_req,
1636         .request = omap_hsmmc_request,
1637         .set_ios = omap_hsmmc_set_ios,
1638         .get_cd = omap_hsmmc_get_cd,
1639         .get_ro = omap_hsmmc_get_ro,
1640         .init_card = omap_hsmmc_init_card,
1641         /* NYET -- enable_sdio_irq */
1642 };
1643
1644 #ifdef CONFIG_DEBUG_FS
1645
1646 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1647 {
1648         struct mmc_host *mmc = s->private;
1649         struct omap_hsmmc_host *host = mmc_priv(mmc);
1650         int context_loss = 0;
1651
1652         if (host->pdata->get_context_loss_count)
1653                 context_loss = host->pdata->get_context_loss_count(host->dev);
1654
1655         seq_printf(s, "mmc%d:\n ctx_loss:\t%d:%d\n\nregs:\n",
1656                         mmc->index, host->context_loss, context_loss);
1657
1658         if (host->suspended) {
1659                 seq_printf(s, "host suspended, can't read registers\n");
1660                 return 0;
1661         }
1662
1663         pm_runtime_get_sync(host->dev);
1664
1665         seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1666                         OMAP_HSMMC_READ(host->base, SYSCONFIG));
1667         seq_printf(s, "CON:\t\t0x%08x\n",
1668                         OMAP_HSMMC_READ(host->base, CON));
1669         seq_printf(s, "HCTL:\t\t0x%08x\n",
1670                         OMAP_HSMMC_READ(host->base, HCTL));
1671         seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1672                         OMAP_HSMMC_READ(host->base, SYSCTL));
1673         seq_printf(s, "IE:\t\t0x%08x\n",
1674                         OMAP_HSMMC_READ(host->base, IE));
1675         seq_printf(s, "ISE:\t\t0x%08x\n",
1676                         OMAP_HSMMC_READ(host->base, ISE));
1677         seq_printf(s, "CAPA:\t\t0x%08x\n",
1678                         OMAP_HSMMC_READ(host->base, CAPA));
1679
1680         pm_runtime_mark_last_busy(host->dev);
1681         pm_runtime_put_autosuspend(host->dev);
1682
1683         return 0;
1684 }
1685
1686 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1687 {
1688         return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1689 }
1690
1691 static const struct file_operations mmc_regs_fops = {
1692         .open           = omap_hsmmc_regs_open,
1693         .read           = seq_read,
1694         .llseek         = seq_lseek,
1695         .release        = single_release,
1696 };
1697
1698 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1699 {
1700         if (mmc->debugfs_root)
1701                 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1702                         mmc, &mmc_regs_fops);
1703 }
1704
1705 #else
1706
1707 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1708 {
1709 }
1710
1711 #endif
1712
1713 static int __init omap_hsmmc_probe(struct platform_device *pdev)
1714 {
1715         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1716         struct mmc_host *mmc;
1717         struct omap_hsmmc_host *host = NULL;
1718         struct resource *res;
1719         int ret, irq;
1720
1721         if (pdata == NULL) {
1722                 dev_err(&pdev->dev, "Platform Data is missing\n");
1723                 return -ENXIO;
1724         }
1725
1726         if (pdata->nr_slots == 0) {
1727                 dev_err(&pdev->dev, "No Slots\n");
1728                 return -ENXIO;
1729         }
1730
1731         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1732         irq = platform_get_irq(pdev, 0);
1733         if (res == NULL || irq < 0)
1734                 return -ENXIO;
1735
1736         res->start += pdata->reg_offset;
1737         res->end += pdata->reg_offset;
1738         res = request_mem_region(res->start, resource_size(res), pdev->name);
1739         if (res == NULL)
1740                 return -EBUSY;
1741
1742         ret = omap_hsmmc_gpio_init(pdata);
1743         if (ret)
1744                 goto err;
1745
1746         mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1747         if (!mmc) {
1748                 ret = -ENOMEM;
1749                 goto err_alloc;
1750         }
1751
1752         host            = mmc_priv(mmc);
1753         host->mmc       = mmc;
1754         host->pdata     = pdata;
1755         host->dev       = &pdev->dev;
1756         host->use_dma   = 1;
1757         host->dev->dma_mask = &pdata->dma_mask;
1758         host->dma_ch    = -1;
1759         host->irq       = irq;
1760         host->slot_id   = 0;
1761         host->mapbase   = res->start;
1762         host->base      = ioremap(host->mapbase, SZ_4K);
1763         host->power_mode = MMC_POWER_OFF;
1764         host->next_data.cookie = 1;
1765
1766         platform_set_drvdata(pdev, host);
1767
1768         mmc->ops        = &omap_hsmmc_ops;
1769
1770         /*
1771          * If regulator_disable can only put vcc_aux to sleep then there is
1772          * no off state.
1773          */
1774         if (mmc_slot(host).vcc_aux_disable_is_sleep)
1775                 mmc_slot(host).no_off = 1;
1776
1777         mmc->f_min = OMAP_MMC_MIN_CLOCK;
1778
1779         if (pdata->max_freq > 0)
1780                 mmc->f_max = pdata->max_freq;
1781         else
1782                 mmc->f_max = OMAP_MMC_MAX_CLOCK;
1783
1784         spin_lock_init(&host->irq_lock);
1785
1786         host->fclk = clk_get(&pdev->dev, "fck");
1787         if (IS_ERR(host->fclk)) {
1788                 ret = PTR_ERR(host->fclk);
1789                 host->fclk = NULL;
1790                 goto err1;
1791         }
1792
1793         omap_hsmmc_context_save(host);
1794
1795         if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
1796                 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
1797                 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
1798         }
1799
1800         pm_runtime_enable(host->dev);
1801         pm_runtime_get_sync(host->dev);
1802         pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1803         pm_runtime_use_autosuspend(host->dev);
1804
1805         if (cpu_is_omap2430()) {
1806                 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1807                 /*
1808                  * MMC can still work without debounce clock.
1809                  */
1810                 if (IS_ERR(host->dbclk))
1811                         dev_warn(mmc_dev(host->mmc),
1812                                 "Failed to get debounce clock\n");
1813                 else
1814                         host->got_dbclk = 1;
1815
1816                 if (host->got_dbclk)
1817                         if (clk_enable(host->dbclk) != 0)
1818                                 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1819                                                         " clk failed\n");
1820         }
1821
1822         /* Since we do only SG emulation, we can have as many segs
1823          * as we want. */
1824         mmc->max_segs = 1024;
1825
1826         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
1827         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
1828         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1829         mmc->max_seg_size = mmc->max_req_size;
1830
1831         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1832                      MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
1833
1834         mmc->caps |= mmc_slot(host).caps;
1835         if (mmc->caps & MMC_CAP_8_BIT_DATA)
1836                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1837
1838         if (mmc_slot(host).nonremovable)
1839                 mmc->caps |= MMC_CAP_NONREMOVABLE;
1840
1841         mmc->pm_caps = mmc_slot(host).pm_caps;
1842
1843         omap_hsmmc_conf_bus_power(host);
1844
1845         res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1846         if (!res) {
1847                 dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
1848                 goto err_irq;
1849         }
1850         host->dma_line_tx = res->start;
1851
1852         res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1853         if (!res) {
1854                 dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
1855                 goto err_irq;
1856         }
1857         host->dma_line_rx = res->start;
1858
1859         /* Request IRQ for MMC operations */
1860         ret = request_irq(host->irq, omap_hsmmc_irq, 0,
1861                         mmc_hostname(mmc), host);
1862         if (ret) {
1863                 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1864                 goto err_irq;
1865         }
1866
1867         if (pdata->init != NULL) {
1868                 if (pdata->init(&pdev->dev) != 0) {
1869                         dev_dbg(mmc_dev(host->mmc),
1870                                 "Unable to configure MMC IRQs\n");
1871                         goto err_irq_cd_init;
1872                 }
1873         }
1874
1875         if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
1876                 ret = omap_hsmmc_reg_get(host);
1877                 if (ret)
1878                         goto err_reg;
1879                 host->use_reg = 1;
1880         }
1881
1882         mmc->ocr_avail = mmc_slot(host).ocr_mask;
1883
1884         /* Request IRQ for card detect */
1885         if ((mmc_slot(host).card_detect_irq)) {
1886                 ret = request_threaded_irq(mmc_slot(host).card_detect_irq,
1887                                            NULL,
1888                                            omap_hsmmc_detect,
1889                                            IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
1890                                            mmc_hostname(mmc), host);
1891                 if (ret) {
1892                         dev_dbg(mmc_dev(host->mmc),
1893                                 "Unable to grab MMC CD IRQ\n");
1894                         goto err_irq_cd;
1895                 }
1896                 pdata->suspend = omap_hsmmc_suspend_cdirq;
1897                 pdata->resume = omap_hsmmc_resume_cdirq;
1898         }
1899
1900         omap_hsmmc_disable_irq(host);
1901
1902         omap_hsmmc_protect_card(host);
1903
1904         mmc_add_host(mmc);
1905
1906         if (mmc_slot(host).name != NULL) {
1907                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1908                 if (ret < 0)
1909                         goto err_slot_name;
1910         }
1911         if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
1912                 ret = device_create_file(&mmc->class_dev,
1913                                         &dev_attr_cover_switch);
1914                 if (ret < 0)
1915                         goto err_slot_name;
1916         }
1917
1918         omap_hsmmc_debugfs(mmc);
1919         pm_runtime_mark_last_busy(host->dev);
1920         pm_runtime_put_autosuspend(host->dev);
1921
1922         return 0;
1923
1924 err_slot_name:
1925         mmc_remove_host(mmc);
1926         free_irq(mmc_slot(host).card_detect_irq, host);
1927 err_irq_cd:
1928         if (host->use_reg)
1929                 omap_hsmmc_reg_put(host);
1930 err_reg:
1931         if (host->pdata->cleanup)
1932                 host->pdata->cleanup(&pdev->dev);
1933 err_irq_cd_init:
1934         free_irq(host->irq, host);
1935 err_irq:
1936         pm_runtime_mark_last_busy(host->dev);
1937         pm_runtime_put_autosuspend(host->dev);
1938         pm_runtime_disable(host->dev);
1939         clk_put(host->fclk);
1940         if (host->got_dbclk) {
1941                 clk_disable(host->dbclk);
1942                 clk_put(host->dbclk);
1943         }
1944 err1:
1945         iounmap(host->base);
1946         platform_set_drvdata(pdev, NULL);
1947         mmc_free_host(mmc);
1948 err_alloc:
1949         omap_hsmmc_gpio_free(pdata);
1950 err:
1951         release_mem_region(res->start, resource_size(res));
1952         return ret;
1953 }
1954
1955 static int omap_hsmmc_remove(struct platform_device *pdev)
1956 {
1957         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
1958         struct resource *res;
1959
1960         if (host) {
1961                 pm_runtime_get_sync(host->dev);
1962                 mmc_remove_host(host->mmc);
1963                 if (host->use_reg)
1964                         omap_hsmmc_reg_put(host);
1965                 if (host->pdata->cleanup)
1966                         host->pdata->cleanup(&pdev->dev);
1967                 free_irq(host->irq, host);
1968                 if (mmc_slot(host).card_detect_irq)
1969                         free_irq(mmc_slot(host).card_detect_irq, host);
1970
1971                 pm_runtime_put_sync(host->dev);
1972                 pm_runtime_disable(host->dev);
1973                 clk_put(host->fclk);
1974                 if (host->got_dbclk) {
1975                         clk_disable(host->dbclk);
1976                         clk_put(host->dbclk);
1977                 }
1978
1979                 mmc_free_host(host->mmc);
1980                 iounmap(host->base);
1981                 omap_hsmmc_gpio_free(pdev->dev.platform_data);
1982         }
1983
1984         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1985         if (res)
1986                 release_mem_region(res->start, resource_size(res));
1987         platform_set_drvdata(pdev, NULL);
1988
1989         return 0;
1990 }
1991
1992 #ifdef CONFIG_PM
1993 static int omap_hsmmc_suspend(struct device *dev)
1994 {
1995         int ret = 0;
1996         struct platform_device *pdev = to_platform_device(dev);
1997         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
1998
1999         if (host && host->suspended)
2000                 return 0;
2001
2002         if (host) {
2003                 pm_runtime_get_sync(host->dev);
2004                 host->suspended = 1;
2005                 if (host->pdata->suspend) {
2006                         ret = host->pdata->suspend(&pdev->dev,
2007                                                         host->slot_id);
2008                         if (ret) {
2009                                 dev_dbg(mmc_dev(host->mmc),
2010                                         "Unable to handle MMC board"
2011                                         " level suspend\n");
2012                                 host->suspended = 0;
2013                                 return ret;
2014                         }
2015                 }
2016                 ret = mmc_suspend_host(host->mmc);
2017
2018                 if (ret) {
2019                         host->suspended = 0;
2020                         if (host->pdata->resume) {
2021                                 ret = host->pdata->resume(&pdev->dev,
2022                                                           host->slot_id);
2023                                 if (ret)
2024                                         dev_dbg(mmc_dev(host->mmc),
2025                                                 "Unmask interrupt failed\n");
2026                         }
2027                         goto err;
2028                 }
2029
2030                 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2031                         omap_hsmmc_disable_irq(host);
2032                         OMAP_HSMMC_WRITE(host->base, HCTL,
2033                                 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2034                 }
2035                 if (host->got_dbclk)
2036                         clk_disable(host->dbclk);
2037
2038         }
2039 err:
2040         pm_runtime_put_sync(host->dev);
2041         return ret;
2042 }
2043
2044 /* Routine to resume the MMC device */
2045 static int omap_hsmmc_resume(struct device *dev)
2046 {
2047         int ret = 0;
2048         struct platform_device *pdev = to_platform_device(dev);
2049         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2050
2051         if (host && !host->suspended)
2052                 return 0;
2053
2054         if (host) {
2055                 pm_runtime_get_sync(host->dev);
2056
2057                 if (host->got_dbclk)
2058                         clk_enable(host->dbclk);
2059
2060                 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2061                         omap_hsmmc_conf_bus_power(host);
2062
2063                 if (host->pdata->resume) {
2064                         ret = host->pdata->resume(&pdev->dev, host->slot_id);
2065                         if (ret)
2066                                 dev_dbg(mmc_dev(host->mmc),
2067                                         "Unmask interrupt failed\n");
2068                 }
2069
2070                 omap_hsmmc_protect_card(host);
2071
2072                 /* Notify the core to resume the host */
2073                 ret = mmc_resume_host(host->mmc);
2074                 if (ret == 0)
2075                         host->suspended = 0;
2076
2077                 pm_runtime_mark_last_busy(host->dev);
2078                 pm_runtime_put_autosuspend(host->dev);
2079         }
2080
2081         return ret;
2082
2083 }
2084
2085 #else
2086 #define omap_hsmmc_suspend      NULL
2087 #define omap_hsmmc_resume               NULL
2088 #endif
2089
2090 static int omap_hsmmc_runtime_suspend(struct device *dev)
2091 {
2092         struct omap_hsmmc_host *host;
2093
2094         host = platform_get_drvdata(to_platform_device(dev));
2095         omap_hsmmc_context_save(host);
2096         dev_dbg(mmc_dev(host->mmc), "disabled\n");
2097
2098         return 0;
2099 }
2100
2101 static int omap_hsmmc_runtime_resume(struct device *dev)
2102 {
2103         struct omap_hsmmc_host *host;
2104
2105         host = platform_get_drvdata(to_platform_device(dev));
2106         omap_hsmmc_context_restore(host);
2107         dev_dbg(mmc_dev(host->mmc), "enabled\n");
2108
2109         return 0;
2110 }
2111
2112 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2113         .suspend        = omap_hsmmc_suspend,
2114         .resume         = omap_hsmmc_resume,
2115         .runtime_suspend = omap_hsmmc_runtime_suspend,
2116         .runtime_resume = omap_hsmmc_runtime_resume,
2117 };
2118
2119 static struct platform_driver omap_hsmmc_driver = {
2120         .remove         = omap_hsmmc_remove,
2121         .driver         = {
2122                 .name = DRIVER_NAME,
2123                 .owner = THIS_MODULE,
2124                 .pm = &omap_hsmmc_dev_pm_ops,
2125         },
2126 };
2127
2128 static int __init omap_hsmmc_init(void)
2129 {
2130         /* Register the MMC driver */
2131         return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe);
2132 }
2133
2134 static void __exit omap_hsmmc_cleanup(void)
2135 {
2136         /* Unregister MMC driver */
2137         platform_driver_unregister(&omap_hsmmc_driver);
2138 }
2139
2140 module_init(omap_hsmmc_init);
2141 module_exit(omap_hsmmc_cleanup);
2142
2143 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2144 MODULE_LICENSE("GPL");
2145 MODULE_ALIAS("platform:" DRIVER_NAME);
2146 MODULE_AUTHOR("Texas Instruments Inc");