drivers/mmc/host/omap.c

   1 /*
   2  *  linux/drivers/mmc/host/omap.c
   3  *
   4  *  Copyright (C) 2004 Nokia Corporation
   5  *  Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
   6  *  Misc hacks here and there by Tony Lindgren <tony@atomide.com>
   7  *  Other hacks (DMA, SD, etc) by David Brownell
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/ioport.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/dmaengine.h>
  21 #include <linux/dma-mapping.h>
  22 #include <linux/delay.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/timer.h>
  25 #include <linux/omap-dma.h>
  26 #include <linux/mmc/host.h>
  27 #include <linux/mmc/card.h>
  28 #include <linux/clk.h>
  29 #include <linux/scatterlist.h>
  30 #include <linux/slab.h>
  31
  32 #include <plat/mmc.h>
  33 #include <plat/dma.h>
  34
  35 #define OMAP_MMC_REG_CMD        0x00
  36 #define OMAP_MMC_REG_ARGL       0x01
  37 #define OMAP_MMC_REG_ARGH       0x02
  38 #define OMAP_MMC_REG_CON        0x03
  39 #define OMAP_MMC_REG_STAT       0x04
  40 #define OMAP_MMC_REG_IE         0x05
  41 #define OMAP_MMC_REG_CTO        0x06
  42 #define OMAP_MMC_REG_DTO        0x07
  43 #define OMAP_MMC_REG_DATA       0x08
  44 #define OMAP_MMC_REG_BLEN       0x09
  45 #define OMAP_MMC_REG_NBLK       0x0a
  46 #define OMAP_MMC_REG_BUF        0x0b
  47 #define OMAP_MMC_REG_SDIO       0x0d
  48 #define OMAP_MMC_REG_REV        0x0f
  49 #define OMAP_MMC_REG_RSP0       0x10
  50 #define OMAP_MMC_REG_RSP1       0x11
  51 #define OMAP_MMC_REG_RSP2       0x12
  52 #define OMAP_MMC_REG_RSP3       0x13
  53 #define OMAP_MMC_REG_RSP4       0x14
  54 #define OMAP_MMC_REG_RSP5       0x15
  55 #define OMAP_MMC_REG_RSP6       0x16
  56 #define OMAP_MMC_REG_RSP7       0x17
  57 #define OMAP_MMC_REG_IOSR       0x18
  58 #define OMAP_MMC_REG_SYSC       0x19
  59 #define OMAP_MMC_REG_SYSS       0x1a
  60
  61 #define OMAP_MMC_STAT_CARD_ERR          (1 << 14)
  62 #define OMAP_MMC_STAT_CARD_IRQ          (1 << 13)
  63 #define OMAP_MMC_STAT_OCR_BUSY          (1 << 12)
  64 #define OMAP_MMC_STAT_A_EMPTY           (1 << 11)
  65 #define OMAP_MMC_STAT_A_FULL            (1 << 10)
  66 #define OMAP_MMC_STAT_CMD_CRC           (1 <<  8)
  67 #define OMAP_MMC_STAT_CMD_TOUT          (1 <<  7)
  68 #define OMAP_MMC_STAT_DATA_CRC          (1 <<  6)
  69 #define OMAP_MMC_STAT_DATA_TOUT         (1 <<  5)
  70 #define OMAP_MMC_STAT_END_BUSY          (1 <<  4)
  71 #define OMAP_MMC_STAT_END_OF_DATA       (1 <<  3)
  72 #define OMAP_MMC_STAT_CARD_BUSY         (1 <<  2)
  73 #define OMAP_MMC_STAT_END_OF_CMD        (1 <<  0)
  74
  75 #define OMAP_MMC_REG(host, reg)         (OMAP_MMC_REG_##reg << (host)->reg_shift)
  76 #define OMAP_MMC_READ(host, reg)        __raw_readw((host)->virt_base + OMAP_MMC_REG(host, reg))
  77 #define OMAP_MMC_WRITE(host, reg, val)  __raw_writew((val), (host)->virt_base + OMAP_MMC_REG(host, reg))
  78
  79 /*
  80  * Command types
  81  */
  82 #define OMAP_MMC_CMDTYPE_BC     0
  83 #define OMAP_MMC_CMDTYPE_BCR    1
  84 #define OMAP_MMC_CMDTYPE_AC     2
  85 #define OMAP_MMC_CMDTYPE_ADTC   3
  86
  87
  88 #define DRIVER_NAME "mmci-omap"
  89
  90 /* Specifies how often in millisecs to poll for card status changes
  91  * when the cover switch is open */
  92 #define OMAP_MMC_COVER_POLL_DELAY       500
  93
  94 struct mmc_omap_host;
  95
  96 struct mmc_omap_slot {
  97         int                     id;
  98         unsigned int            vdd;
  99         u16                     saved_con;
 100         u16                     bus_mode;
 101         unsigned int            fclk_freq;
 102
 103         struct tasklet_struct   cover_tasklet;
 104         struct timer_list       cover_timer;
 105         unsigned                cover_open;
 106
 107         struct mmc_request      *mrq;
 108         struct mmc_omap_host    *host;
 109         struct mmc_host         *mmc;
 110         struct omap_mmc_slot_data *pdata;
 111 };
 112
 113 struct mmc_omap_host {
 114         int                     initialized;
 115         int                     suspended;
 116         struct mmc_request *    mrq;
 117         struct mmc_command *    cmd;
 118         struct mmc_data *       data;
 119         struct mmc_host *       mmc;
 120         struct device *         dev;
 121         unsigned char           id; /* 16xx chips have 2 MMC blocks */
 122         struct clk *            iclk;
 123         struct clk *            fclk;
 124         struct dma_chan         *dma_rx;
 125         u32                     dma_rx_burst;
 126         struct dma_chan         *dma_tx;
 127         u32                     dma_tx_burst;
 128         struct resource         *mem_res;
 129         void __iomem            *virt_base;
 130         unsigned int            phys_base;
 131         int                     irq;
 132         unsigned char           bus_mode;
 133         unsigned int            reg_shift;
 134
 135         struct work_struct      cmd_abort_work;
 136         unsigned                abort:1;
 137         struct timer_list       cmd_abort_timer;
 138
 139         struct work_struct      slot_release_work;
 140         struct mmc_omap_slot    *next_slot;
 141         struct work_struct      send_stop_work;
 142         struct mmc_data         *stop_data;
 143
 144         unsigned int            sg_len;
 145         int                     sg_idx;
 146         u16 *                   buffer;
 147         u32                     buffer_bytes_left;
 148         u32                     total_bytes_left;
 149
 150         unsigned                use_dma:1;
 151         unsigned                brs_received:1, dma_done:1;
 152         unsigned                dma_in_use:1;
 153         spinlock_t              dma_lock;
 154
 155         struct mmc_omap_slot    *slots[OMAP_MMC_MAX_SLOTS];
 156         struct mmc_omap_slot    *current_slot;
 157         spinlock_t              slot_lock;
 158         wait_queue_head_t       slot_wq;
 159         int                     nr_slots;
 160
 161         struct timer_list       clk_timer;
 162         spinlock_t              clk_lock;     /* for changing enabled state */
 163         unsigned int            fclk_enabled:1;
 164         struct workqueue_struct *mmc_omap_wq;
 165
 166         struct omap_mmc_platform_data *pdata;
 167 };
 168
 169
 170 static void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot)
 171 {
 172         unsigned long tick_ns;
 173
 174         if (slot != NULL && slot->host->fclk_enabled && slot->fclk_freq > 0) {
 175                 tick_ns = (1000000000 + slot->fclk_freq - 1) / slot->fclk_freq;
 176                 ndelay(8 * tick_ns);
 177         }
 178 }
 179
 180 static void mmc_omap_fclk_enable(struct mmc_omap_host *host, unsigned int enable)
 181 {
 182         unsigned long flags;
 183
 184         spin_lock_irqsave(&host->clk_lock, flags);
 185         if (host->fclk_enabled != enable) {
 186                 host->fclk_enabled = enable;
 187                 if (enable)
 188                         clk_enable(host->fclk);
 189                 else
 190                         clk_disable(host->fclk);
 191         }
 192         spin_unlock_irqrestore(&host->clk_lock, flags);
 193 }
 194
 195 static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
 196 {
 197         struct mmc_omap_host *host = slot->host;
 198         unsigned long flags;
 199
 200         if (claimed)
 201                 goto no_claim;
 202         spin_lock_irqsave(&host->slot_lock, flags);
 203         while (host->mmc != NULL) {
 204                 spin_unlock_irqrestore(&host->slot_lock, flags);
 205                 wait_event(host->slot_wq, host->mmc == NULL);
 206                 spin_lock_irqsave(&host->slot_lock, flags);
 207         }
 208         host->mmc = slot->mmc;
 209         spin_unlock_irqrestore(&host->slot_lock, flags);
 210 no_claim:
 211         del_timer(&host->clk_timer);
 212         if (host->current_slot != slot || !claimed)
 213                 mmc_omap_fclk_offdelay(host->current_slot);
 214
 215         if (host->current_slot != slot) {
 216                 OMAP_MMC_WRITE(host, CON, slot->saved_con & 0xFC00);
 217                 if (host->pdata->switch_slot != NULL)
 218                         host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
 219                 host->current_slot = slot;
 220         }
 221
 222         if (claimed) {
 223                 mmc_omap_fclk_enable(host, 1);
 224
 225                 /* Doing the dummy read here seems to work around some bug
 226                  * at least in OMAP24xx silicon where the command would not
 227                  * start after writing the CMD register. Sigh. */
 228                 OMAP_MMC_READ(host, CON);
 229
 230                 OMAP_MMC_WRITE(host, CON, slot->saved_con);
 231         } else
 232                 mmc_omap_fclk_enable(host, 0);
 233 }
 234
 235 static void mmc_omap_start_request(struct mmc_omap_host *host,
 236                                    struct mmc_request *req);
 237
 238 static void mmc_omap_slot_release_work(struct work_struct *work)
 239 {
 240         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 241                                                   slot_release_work);
 242         struct mmc_omap_slot *next_slot = host->next_slot;
 243         struct mmc_request *rq;
 244
 245         host->next_slot = NULL;
 246         mmc_omap_select_slot(next_slot, 1);
 247
 248         rq = next_slot->mrq;
 249         next_slot->mrq = NULL;
 250         mmc_omap_start_request(host, rq);
 251 }
 252
 253 static void mmc_omap_release_slot(struct mmc_omap_slot *slot, int clk_enabled)
 254 {
 255         struct mmc_omap_host *host = slot->host;
 256         unsigned long flags;
 257         int i;
 258
 259         BUG_ON(slot == NULL || host->mmc == NULL);
 260
 261         if (clk_enabled)
 262                 /* Keeps clock running for at least 8 cycles on valid freq */
 263                 mod_timer(&host->clk_timer, jiffies  + HZ/10);
 264         else {
 265                 del_timer(&host->clk_timer);
 266                 mmc_omap_fclk_offdelay(slot);
 267                 mmc_omap_fclk_enable(host, 0);
 268         }
 269
 270         spin_lock_irqsave(&host->slot_lock, flags);
 271         /* Check for any pending requests */
 272         for (i = 0; i < host->nr_slots; i++) {
 273                 struct mmc_omap_slot *new_slot;
 274
 275                 if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
 276                         continue;
 277
 278                 BUG_ON(host->next_slot != NULL);
 279                 new_slot = host->slots[i];
 280                 /* The current slot should not have a request in queue */
 281                 BUG_ON(new_slot == host->current_slot);
 282
 283                 host->next_slot = new_slot;
 284                 host->mmc = new_slot->mmc;
 285                 spin_unlock_irqrestore(&host->slot_lock, flags);
 286                 queue_work(host->mmc_omap_wq, &host->slot_release_work);
 287                 return;
 288         }
 289
 290         host->mmc = NULL;
 291         wake_up(&host->slot_wq);
 292         spin_unlock_irqrestore(&host->slot_lock, flags);
 293 }
 294
 295 static inline
 296 int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)
 297 {
 298         if (slot->pdata->get_cover_state)
 299                 return slot->pdata->get_cover_state(mmc_dev(slot->mmc),
 300                                                     slot->id);
 301         return 0;
 302 }
 303
 304 static ssize_t
 305 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
 306                            char *buf)
 307 {
 308         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 309         struct mmc_omap_slot *slot = mmc_priv(mmc);
 310
 311         return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :
 312                        "closed");
 313 }
 314
 315 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
 316
 317 static ssize_t
 318 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
 319                         char *buf)
 320 {
 321         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 322         struct mmc_omap_slot *slot = mmc_priv(mmc);
 323
 324         return sprintf(buf, "%s\n", slot->pdata->name);
 325 }
 326
 327 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
 328
 329 static void
 330 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
 331 {
 332         u32 cmdreg;
 333         u32 resptype;
 334         u32 cmdtype;
 335
 336         host->cmd = cmd;
 337
 338         resptype = 0;
 339         cmdtype = 0;
 340
 341         /* Our hardware needs to know exact type */
 342         switch (mmc_resp_type(cmd)) {
 343         case MMC_RSP_NONE:
 344                 break;
 345         case MMC_RSP_R1:
 346         case MMC_RSP_R1B:
 347                 /* resp 1, 1b, 6, 7 */
 348                 resptype = 1;
 349                 break;
 350         case MMC_RSP_R2:
 351                 resptype = 2;
 352                 break;
 353         case MMC_RSP_R3:
 354                 resptype = 3;
 355                 break;
 356         default:
 357                 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
 358                 break;
 359         }
 360
 361         if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
 362                 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
 363         } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
 364                 cmdtype = OMAP_MMC_CMDTYPE_BC;
 365         } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
 366                 cmdtype = OMAP_MMC_CMDTYPE_BCR;
 367         } else {
 368                 cmdtype = OMAP_MMC_CMDTYPE_AC;
 369         }
 370
 371         cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
 372
 373         if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
 374                 cmdreg |= 1 << 6;
 375
 376         if (cmd->flags & MMC_RSP_BUSY)
 377                 cmdreg |= 1 << 11;
 378
 379         if (host->data && !(host->data->flags & MMC_DATA_WRITE))
 380                 cmdreg |= 1 << 15;
 381
 382         mod_timer(&host->cmd_abort_timer, jiffies + HZ/2);
 383
 384         OMAP_MMC_WRITE(host, CTO, 200);
 385         OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
 386         OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
 387         OMAP_MMC_WRITE(host, IE,
 388                        OMAP_MMC_STAT_A_EMPTY    | OMAP_MMC_STAT_A_FULL    |
 389                        OMAP_MMC_STAT_CMD_CRC    | OMAP_MMC_STAT_CMD_TOUT  |
 390                        OMAP_MMC_STAT_DATA_CRC   | OMAP_MMC_STAT_DATA_TOUT |
 391                        OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR  |
 392                        OMAP_MMC_STAT_END_OF_DATA);
 393         OMAP_MMC_WRITE(host, CMD, cmdreg);
 394 }
 395
 396 static void
 397 mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data,
 398                      int abort)
 399 {
 400         enum dma_data_direction dma_data_dir;
 401         struct device *dev = mmc_dev(host->mmc);
 402         struct dma_chan *c;
 403
 404         if (data->flags & MMC_DATA_WRITE) {
 405                 dma_data_dir = DMA_TO_DEVICE;
 406                 c = host->dma_tx;
 407         } else {
 408                 dma_data_dir = DMA_FROM_DEVICE;
 409                 c = host->dma_rx;
 410         }
 411         if (c) {
 412                 if (data->error) {
 413                         dmaengine_terminate_all(c);
 414                         /* Claim nothing transferred on error... */
 415                         data->bytes_xfered = 0;
 416                 }
 417                 dev = c->device->dev;
 418         }
 419         dma_unmap_sg(dev, data->sg, host->sg_len, dma_data_dir);
 420 }
 421
 422 static void mmc_omap_send_stop_work(struct work_struct *work)
 423 {
 424         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 425                                                   send_stop_work);
 426         struct mmc_omap_slot *slot = host->current_slot;
 427         struct mmc_data *data = host->stop_data;
 428         unsigned long tick_ns;
 429
 430         tick_ns = (1000000000 + slot->fclk_freq - 1)/slot->fclk_freq;
 431         ndelay(8*tick_ns);
 432
 433         mmc_omap_start_command(host, data->stop);
 434 }
 435
 436 static void
 437 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 438 {
 439         if (host->dma_in_use)
 440                 mmc_omap_release_dma(host, data, data->error);
 441
 442         host->data = NULL;
 443         host->sg_len = 0;
 444
 445         /* NOTE:  MMC layer will sometimes poll-wait CMD13 next, issuing
 446          * dozens of requests until the card finishes writing data.
 447          * It'd be cheaper to just wait till an EOFB interrupt arrives...
 448          */
 449
 450         if (!data->stop) {
 451                 struct mmc_host *mmc;
 452
 453                 host->mrq = NULL;
 454                 mmc = host->mmc;
 455                 mmc_omap_release_slot(host->current_slot, 1);
 456                 mmc_request_done(mmc, data->mrq);
 457                 return;
 458         }
 459
 460         host->stop_data = data;
 461         queue_work(host->mmc_omap_wq, &host->send_stop_work);
 462 }
 463
 464 static void
 465 mmc_omap_send_abort(struct mmc_omap_host *host, int maxloops)
 466 {
 467         struct mmc_omap_slot *slot = host->current_slot;
 468         unsigned int restarts, passes, timeout;
 469         u16 stat = 0;
 470
 471         /* Sending abort takes 80 clocks. Have some extra and round up */
 472         timeout = (120*1000000 + slot->fclk_freq - 1)/slot->fclk_freq;
 473         restarts = 0;
 474         while (restarts < maxloops) {
 475                 OMAP_MMC_WRITE(host, STAT, 0xFFFF);
 476                 OMAP_MMC_WRITE(host, CMD, (3 << 12) | (1 << 7));
 477
 478                 passes = 0;
 479                 while (passes < timeout) {
 480                         stat = OMAP_MMC_READ(host, STAT);
 481                         if (stat & OMAP_MMC_STAT_END_OF_CMD)
 482                                 goto out;
 483                         udelay(1);
 484                         passes++;
 485                 }
 486
 487                 restarts++;
 488         }
 489 out:
 490         OMAP_MMC_WRITE(host, STAT, stat);
 491 }
 492
 493 static void
 494 mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data)
 495 {
 496         if (host->dma_in_use)
 497                 mmc_omap_release_dma(host, data, 1);
 498
 499         host->data = NULL;
 500         host->sg_len = 0;
 501
 502         mmc_omap_send_abort(host, 10000);
 503 }
 504
 505 static void
 506 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
 507 {
 508         unsigned long flags;
 509         int done;
 510
 511         if (!host->dma_in_use) {
 512                 mmc_omap_xfer_done(host, data);
 513                 return;
 514         }
 515         done = 0;
 516         spin_lock_irqsave(&host->dma_lock, flags);
 517         if (host->dma_done)
 518                 done = 1;
 519         else
 520                 host->brs_received = 1;
 521         spin_unlock_irqrestore(&host->dma_lock, flags);
 522         if (done)
 523                 mmc_omap_xfer_done(host, data);
 524 }
 525
 526 static void
 527 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
 528 {
 529         unsigned long flags;
 530         int done;
 531
 532         done = 0;
 533         spin_lock_irqsave(&host->dma_lock, flags);
 534         if (host->brs_received)
 535                 done = 1;
 536         else
 537                 host->dma_done = 1;
 538         spin_unlock_irqrestore(&host->dma_lock, flags);
 539         if (done)
 540                 mmc_omap_xfer_done(host, data);
 541 }
 542
 543 static void
 544 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 545 {
 546         host->cmd = NULL;
 547
 548         del_timer(&host->cmd_abort_timer);
 549
 550         if (cmd->flags & MMC_RSP_PRESENT) {
 551                 if (cmd->flags & MMC_RSP_136) {
 552                         /* response type 2 */
 553                         cmd->resp[3] =
 554                                 OMAP_MMC_READ(host, RSP0) |
 555                                 (OMAP_MMC_READ(host, RSP1) << 16);
 556                         cmd->resp[2] =
 557                                 OMAP_MMC_READ(host, RSP2) |
 558                                 (OMAP_MMC_READ(host, RSP3) << 16);
 559                         cmd->resp[1] =
 560                                 OMAP_MMC_READ(host, RSP4) |
 561                                 (OMAP_MMC_READ(host, RSP5) << 16);
 562                         cmd->resp[0] =
 563                                 OMAP_MMC_READ(host, RSP6) |
 564                                 (OMAP_MMC_READ(host, RSP7) << 16);
 565                 } else {
 566                         /* response types 1, 1b, 3, 4, 5, 6 */
 567                         cmd->resp[0] =
 568                                 OMAP_MMC_READ(host, RSP6) |
 569                                 (OMAP_MMC_READ(host, RSP7) << 16);
 570                 }
 571         }
 572
 573         if (host->data == NULL || cmd->error) {
 574                 struct mmc_host *mmc;
 575
 576                 if (host->data != NULL)
 577                         mmc_omap_abort_xfer(host, host->data);
 578                 host->mrq = NULL;
 579                 mmc = host->mmc;
 580                 mmc_omap_release_slot(host->current_slot, 1);
 581                 mmc_request_done(mmc, cmd->mrq);
 582         }
 583 }
 584
 585 /*
 586  * Abort stuck command. Can occur when card is removed while it is being
 587  * read.
 588  */
 589 static void mmc_omap_abort_command(struct work_struct *work)
 590 {
 591         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 592                                                   cmd_abort_work);
 593         BUG_ON(!host->cmd);
 594
 595         dev_dbg(mmc_dev(host->mmc), "Aborting stuck command CMD%d\n",
 596                 host->cmd->opcode);
 597
 598         if (host->cmd->error == 0)
 599                 host->cmd->error = -ETIMEDOUT;
 600
 601         if (host->data == NULL) {
 602                 struct mmc_command *cmd;
 603                 struct mmc_host    *mmc;
 604
 605                 cmd = host->cmd;
 606                 host->cmd = NULL;
 607                 mmc_omap_send_abort(host, 10000);
 608
 609                 host->mrq = NULL;
 610                 mmc = host->mmc;
 611                 mmc_omap_release_slot(host->current_slot, 1);
 612                 mmc_request_done(mmc, cmd->mrq);
 613         } else
 614                 mmc_omap_cmd_done(host, host->cmd);
 615
 616         host->abort = 0;
 617         enable_irq(host->irq);
 618 }
 619
 620 static void
 621 mmc_omap_cmd_timer(unsigned long data)
 622 {
 623         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 624         unsigned long flags;
 625
 626         spin_lock_irqsave(&host->slot_lock, flags);
 627         if (host->cmd != NULL && !host->abort) {
 628                 OMAP_MMC_WRITE(host, IE, 0);
 629                 disable_irq(host->irq);
 630                 host->abort = 1;
 631                 queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
 632         }
 633         spin_unlock_irqrestore(&host->slot_lock, flags);
 634 }
 635
 636 /* PIO only */
 637 static void
 638 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
 639 {
 640         struct scatterlist *sg;
 641
 642         sg = host->data->sg + host->sg_idx;
 643         host->buffer_bytes_left = sg->length;
 644         host->buffer = sg_virt(sg);
 645         if (host->buffer_bytes_left > host->total_bytes_left)
 646                 host->buffer_bytes_left = host->total_bytes_left;
 647 }
 648
 649 static void
 650 mmc_omap_clk_timer(unsigned long data)
 651 {
 652         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 653
 654         mmc_omap_fclk_enable(host, 0);
 655 }
 656
 657 /* PIO only */
 658 static void
 659 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
 660 {
 661         int n, nwords;
 662
 663         if (host->buffer_bytes_left == 0) {
 664                 host->sg_idx++;
 665                 BUG_ON(host->sg_idx == host->sg_len);
 666                 mmc_omap_sg_to_buf(host);
 667         }
 668         n = 64;
 669         if (n > host->buffer_bytes_left)
 670                 n = host->buffer_bytes_left;
 671
 672         nwords = n / 2;
 673         nwords += n & 1; /* handle odd number of bytes to transfer */
 674
 675         host->buffer_bytes_left -= n;
 676         host->total_bytes_left -= n;
 677         host->data->bytes_xfered += n;
 678
 679         if (write) {
 680                 __raw_writesw(host->virt_base + OMAP_MMC_REG(host, DATA),
 681                               host->buffer, nwords);
 682         } else {
 683                 __raw_readsw(host->virt_base + OMAP_MMC_REG(host, DATA),
 684                              host->buffer, nwords);
 685         }
 686
 687         host->buffer += nwords;
 688 }
 689
 690 static inline void mmc_omap_report_irq(u16 status)
 691 {
 692         static const char *mmc_omap_status_bits[] = {
 693                 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
 694                 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
 695         };
 696         int i, c = 0;
 697
 698         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 699                 if (status & (1 << i)) {
 700                         if (c)
 701                                 printk(" ");
 702                         printk("%s", mmc_omap_status_bits[i]);
 703                         c++;
 704                 }
 705 }
 706
 707 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 708 {
 709         struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
 710         u16 status;
 711         int end_command;
 712         int end_transfer;
 713         int transfer_error, cmd_error;
 714
 715         if (host->cmd == NULL && host->data == NULL) {
 716                 status = OMAP_MMC_READ(host, STAT);
 717                 dev_info(mmc_dev(host->slots[0]->mmc),
 718                          "Spurious IRQ 0x%04x\n", status);
 719                 if (status != 0) {
 720                         OMAP_MMC_WRITE(host, STAT, status);
 721                         OMAP_MMC_WRITE(host, IE, 0);
 722                 }
 723                 return IRQ_HANDLED;
 724         }
 725
 726         end_command = 0;
 727         end_transfer = 0;
 728         transfer_error = 0;
 729         cmd_error = 0;
 730
 731         while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
 732                 int cmd;
 733
 734                 OMAP_MMC_WRITE(host, STAT, status);
 735                 if (host->cmd != NULL)
 736                         cmd = host->cmd->opcode;
 737                 else
 738                         cmd = -1;
 739 #ifdef CONFIG_MMC_DEBUG
 740                 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
 741                         status, cmd);
 742                 mmc_omap_report_irq(status);
 743                 printk("\n");
 744 #endif
 745                 if (host->total_bytes_left) {
 746                         if ((status & OMAP_MMC_STAT_A_FULL) ||
 747                             (status & OMAP_MMC_STAT_END_OF_DATA))
 748                                 mmc_omap_xfer_data(host, 0);
 749                         if (status & OMAP_MMC_STAT_A_EMPTY)
 750                                 mmc_omap_xfer_data(host, 1);
 751                 }
 752
 753                 if (status & OMAP_MMC_STAT_END_OF_DATA)
 754                         end_transfer = 1;
 755
 756                 if (status & OMAP_MMC_STAT_DATA_TOUT) {
 757                         dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n",
 758                                 cmd);
 759                         if (host->data) {
 760                                 host->data->error = -ETIMEDOUT;
 761                                 transfer_error = 1;
 762                         }
 763                 }
 764
 765                 if (status & OMAP_MMC_STAT_DATA_CRC) {
 766                         if (host->data) {
 767                                 host->data->error = -EILSEQ;
 768                                 dev_dbg(mmc_dev(host->mmc),
 769                                          "data CRC error, bytes left %d\n",
 770                                         host->total_bytes_left);
 771                                 transfer_error = 1;
 772                         } else {
 773                                 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
 774                         }
 775                 }
 776
 777                 if (status & OMAP_MMC_STAT_CMD_TOUT) {
 778                         /* Timeouts are routine with some commands */
 779                         if (host->cmd) {
 780                                 struct mmc_omap_slot *slot =
 781                                         host->current_slot;
 782                                 if (slot == NULL ||
 783                                     !mmc_omap_cover_is_open(slot))
 784                                         dev_err(mmc_dev(host->mmc),
 785                                                 "command timeout (CMD%d)\n",
 786                                                 cmd);
 787                                 host->cmd->error = -ETIMEDOUT;
 788                                 end_command = 1;
 789                                 cmd_error = 1;
 790                         }
 791                 }
 792
 793                 if (status & OMAP_MMC_STAT_CMD_CRC) {
 794                         if (host->cmd) {
 795                                 dev_err(mmc_dev(host->mmc),
 796                                         "command CRC error (CMD%d, arg 0x%08x)\n",
 797                                         cmd, host->cmd->arg);
 798                                 host->cmd->error = -EILSEQ;
 799                                 end_command = 1;
 800                                 cmd_error = 1;
 801                         } else
 802                                 dev_err(mmc_dev(host->mmc),
 803                                         "command CRC error without cmd?\n");
 804                 }
 805
 806                 if (status & OMAP_MMC_STAT_CARD_ERR) {
 807                         dev_dbg(mmc_dev(host->mmc),
 808                                 "ignoring card status error (CMD%d)\n",
 809                                 cmd);
 810                         end_command = 1;
 811                 }
 812
 813                 /*
 814                  * NOTE: On 1610 the END_OF_CMD may come too early when
 815                  * starting a write
 816                  */
 817                 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
 818                     (!(status & OMAP_MMC_STAT_A_EMPTY))) {
 819                         end_command = 1;
 820                 }
 821         }
 822
 823         if (cmd_error && host->data) {
 824                 del_timer(&host->cmd_abort_timer);
 825                 host->abort = 1;
 826                 OMAP_MMC_WRITE(host, IE, 0);
 827                 disable_irq_nosync(host->irq);
 828                 queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
 829                 return IRQ_HANDLED;
 830         }
 831
 832         if (end_command && host->cmd)
 833                 mmc_omap_cmd_done(host, host->cmd);
 834         if (host->data != NULL) {
 835                 if (transfer_error)
 836                         mmc_omap_xfer_done(host, host->data);
 837                 else if (end_transfer)
 838                         mmc_omap_end_of_data(host, host->data);
 839         }
 840
 841         return IRQ_HANDLED;
 842 }
 843
 844 void omap_mmc_notify_cover_event(struct device *dev, int num, int is_closed)
 845 {
 846         int cover_open;
 847         struct mmc_omap_host *host = dev_get_drvdata(dev);
 848         struct mmc_omap_slot *slot = host->slots[num];
 849
 850         BUG_ON(num >= host->nr_slots);
 851
 852         /* Other subsystems can call in here before we're initialised. */
 853         if (host->nr_slots == 0 || !host->slots[num])
 854                 return;
 855
 856         cover_open = mmc_omap_cover_is_open(slot);
 857         if (cover_open != slot->cover_open) {
 858                 slot->cover_open = cover_open;
 859                 sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");
 860         }
 861
 862         tasklet_hi_schedule(&slot->cover_tasklet);
 863 }
 864
 865 static void mmc_omap_cover_timer(unsigned long arg)
 866 {
 867         struct mmc_omap_slot *slot = (struct mmc_omap_slot *) arg;
 868         tasklet_schedule(&slot->cover_tasklet);
 869 }
 870
 871 static void mmc_omap_cover_handler(unsigned long param)
 872 {
 873         struct mmc_omap_slot *slot = (struct mmc_omap_slot *)param;
 874         int cover_open = mmc_omap_cover_is_open(slot);
 875
 876         mmc_detect_change(slot->mmc, 0);
 877         if (!cover_open)
 878                 return;
 879
 880         /*
 881          * If no card is inserted, we postpone polling until
 882          * the cover has been closed.
 883          */
 884         if (slot->mmc->card == NULL || !mmc_card_present(slot->mmc->card))
 885                 return;
 886
 887         mod_timer(&slot->cover_timer,
 888                   jiffies + msecs_to_jiffies(OMAP_MMC_COVER_POLL_DELAY));
 889 }
 890
 891 static void mmc_omap_dma_callback(void *priv)
 892 {
 893         struct mmc_omap_host *host = priv;
 894         struct mmc_data *data = host->data;
 895
 896         /* If we got to the end of DMA, assume everything went well */
 897         data->bytes_xfered += data->blocks * data->blksz;
 898
 899         mmc_omap_dma_done(host, data);
 900 }
 901
 902 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 903 {
 904         u16 reg;
 905
 906         reg = OMAP_MMC_READ(host, SDIO);
 907         reg &= ~(1 << 5);
 908         OMAP_MMC_WRITE(host, SDIO, reg);
 909         /* Set maximum timeout */
 910         OMAP_MMC_WRITE(host, CTO, 0xff);
 911 }
 912
 913 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 914 {
 915         unsigned int timeout, cycle_ns;
 916         u16 reg;
 917
 918         cycle_ns = 1000000000 / host->current_slot->fclk_freq;
 919         timeout = req->data->timeout_ns / cycle_ns;
 920         timeout += req->data->timeout_clks;
 921
 922         /* Check if we need to use timeout multiplier register */
 923         reg = OMAP_MMC_READ(host, SDIO);
 924         if (timeout > 0xffff) {
 925                 reg |= (1 << 5);
 926                 timeout /= 1024;
 927         } else
 928                 reg &= ~(1 << 5);
 929         OMAP_MMC_WRITE(host, SDIO, reg);
 930         OMAP_MMC_WRITE(host, DTO, timeout);
 931 }
 932
 933 static void
 934 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 935 {
 936         struct mmc_data *data = req->data;
 937         int i, use_dma, block_size;
 938         unsigned sg_len;
 939
 940         host->data = data;
 941         if (data == NULL) {
 942                 OMAP_MMC_WRITE(host, BLEN, 0);
 943                 OMAP_MMC_WRITE(host, NBLK, 0);
 944                 OMAP_MMC_WRITE(host, BUF, 0);
 945                 host->dma_in_use = 0;
 946                 set_cmd_timeout(host, req);
 947                 return;
 948         }
 949
 950         block_size = data->blksz;
 951
 952         OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
 953         OMAP_MMC_WRITE(host, BLEN, block_size - 1);
 954         set_data_timeout(host, req);
 955
 956         /* cope with calling layer confusion; it issues "single
 957          * block" writes using multi-block scatterlists.
 958          */
 959         sg_len = (data->blocks == 1) ? 1 : data->sg_len;
 960
 961         /* Only do DMA for entire blocks */
 962         use_dma = host->use_dma;
 963         if (use_dma) {
 964                 for (i = 0; i < sg_len; i++) {
 965                         if ((data->sg[i].length % block_size) != 0) {
 966                                 use_dma = 0;
 967                                 break;
 968                         }
 969                 }
 970         }
 971
 972         host->sg_idx = 0;
 973         if (use_dma) {
 974                 enum dma_data_direction dma_data_dir;
 975                 struct dma_async_tx_descriptor *tx;
 976                 struct dma_chan *c;
 977                 u32 burst, *bp;
 978                 u16 buf;
 979
 980                 /*
 981                  * FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx
 982                  * and 24xx. Use 16 or 32 word frames when the
 983                  * blocksize is at least that large. Blocksize is
 984                  * usually 512 bytes; but not for some SD reads.
 985                  */
 986                 burst = cpu_is_omap15xx() ? 32 : 64;
 987                 if (burst > data->blksz)
 988                         burst = data->blksz;
 989
 990                 burst >>= 1;
 991
 992                 if (data->flags & MMC_DATA_WRITE) {
 993                         c = host->dma_tx;
 994                         bp = &host->dma_tx_burst;
 995                         buf = 0x0f80 | (burst - 1) << 0;
 996                         dma_data_dir = DMA_TO_DEVICE;
 997                 } else {
 998                         c = host->dma_rx;
 999                         bp = &host->dma_rx_burst;
1000                         buf = 0x800f | (burst - 1) << 8;
1001                         dma_data_dir = DMA_FROM_DEVICE;
1002                 }
1003
1004                 if (!c)
1005                         goto use_pio;
1006
1007                 /* Only reconfigure if we have a different burst size */
1008                 if (*bp != burst) {
1009                         struct dma_slave_config cfg;
1010
1011                         cfg.src_addr = host->phys_base + OMAP_MMC_REG(host, DATA);
1012                         cfg.dst_addr = host->phys_base + OMAP_MMC_REG(host, DATA);
1013                         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1014                         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1015                         cfg.src_maxburst = burst;
1016                         cfg.dst_maxburst = burst;
1017
1018                         if (dmaengine_slave_config(c, &cfg))
1019                                 goto use_pio;
1020
1021                         *bp = burst;
1022                 }
1023
1024                 host->sg_len = dma_map_sg(c->device->dev, data->sg, sg_len,
1025                                           dma_data_dir);
1026                 if (host->sg_len == 0)
1027                         goto use_pio;
1028
1029                 tx = dmaengine_prep_slave_sg(c, data->sg, host->sg_len,
1030                         data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1031                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1032                 if (!tx)
1033                         goto use_pio;
1034
1035                 OMAP_MMC_WRITE(host, BUF, buf);
1036
1037                 tx->callback = mmc_omap_dma_callback;
1038                 tx->callback_param = host;
1039                 dmaengine_submit(tx);
1040                 host->brs_received = 0;
1041                 host->dma_done = 0;
1042                 host->dma_in_use = 1;
1043                 return;
1044         }
1045  use_pio:
1046
1047         /* Revert to PIO? */
1048         OMAP_MMC_WRITE(host, BUF, 0x1f1f);
1049         host->total_bytes_left = data->blocks * block_size;
1050         host->sg_len = sg_len;
1051         mmc_omap_sg_to_buf(host);
1052         host->dma_in_use = 0;
1053 }
1054
1055 static void mmc_omap_start_request(struct mmc_omap_host *host,
1056                                    struct mmc_request *req)
1057 {
1058         BUG_ON(host->mrq != NULL);
1059
1060         host->mrq = req;
1061
1062         /* only touch fifo AFTER the controller readies it */
1063         mmc_omap_prepare_data(host, req);
1064         mmc_omap_start_command(host, req->cmd);
1065         if (host->dma_in_use) {
1066                 struct dma_chan *c = host->data->flags & MMC_DATA_WRITE ?
1067                                 host->dma_tx : host->dma_rx;
1068
1069                 dma_async_issue_pending(c);
1070         }
1071 }
1072
1073 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
1074 {
1075         struct mmc_omap_slot *slot = mmc_priv(mmc);
1076         struct mmc_omap_host *host = slot->host;
1077         unsigned long flags;
1078
1079         spin_lock_irqsave(&host->slot_lock, flags);
1080         if (host->mmc != NULL) {
1081                 BUG_ON(slot->mrq != NULL);
1082                 slot->mrq = req;
1083                 spin_unlock_irqrestore(&host->slot_lock, flags);
1084                 return;
1085         } else
1086                 host->mmc = mmc;
1087         spin_unlock_irqrestore(&host->slot_lock, flags);
1088         mmc_omap_select_slot(slot, 1);
1089         mmc_omap_start_request(host, req);
1090 }
1091
1092 static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on,
1093                                 int vdd)
1094 {
1095         struct mmc_omap_host *host;
1096
1097         host = slot->host;
1098
1099         if (slot->pdata->set_power != NULL)
1100                 slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on,
1101                                         vdd);
1102
1103         if (cpu_is_omap24xx()) {
1104                 u16 w;
1105
1106                 if (power_on) {
1107                         w = OMAP_MMC_READ(host, CON);
1108                         OMAP_MMC_WRITE(host, CON, w | (1 << 11));
1109                 } else {
1110                         w = OMAP_MMC_READ(host, CON);
1111                         OMAP_MMC_WRITE(host, CON, w & ~(1 << 11));
1112                 }
1113         }
1114 }
1115
1116 static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
1117 {
1118         struct mmc_omap_slot *slot = mmc_priv(mmc);
1119         struct mmc_omap_host *host = slot->host;
1120         int func_clk_rate = clk_get_rate(host->fclk);
1121         int dsor;
1122
1123         if (ios->clock == 0)
1124                 return 0;
1125
1126         dsor = func_clk_rate / ios->clock;
1127         if (dsor < 1)
1128                 dsor = 1;
1129
1130         if (func_clk_rate / dsor > ios->clock)
1131                 dsor++;
1132
1133         if (dsor > 250)
1134                 dsor = 250;
1135
1136         slot->fclk_freq = func_clk_rate / dsor;
1137
1138         if (ios->bus_width == MMC_BUS_WIDTH_4)
1139                 dsor |= 1 << 15;
1140
1141         return dsor;
1142 }
1143
1144 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1145 {
1146         struct mmc_omap_slot *slot = mmc_priv(mmc);
1147         struct mmc_omap_host *host = slot->host;
1148         int i, dsor;
1149         int clk_enabled;
1150
1151         mmc_omap_select_slot(slot, 0);
1152
1153         dsor = mmc_omap_calc_divisor(mmc, ios);
1154
1155         if (ios->vdd != slot->vdd)
1156                 slot->vdd = ios->vdd;
1157
1158         clk_enabled = 0;
1159         switch (ios->power_mode) {
1160         case MMC_POWER_OFF:
1161                 mmc_omap_set_power(slot, 0, ios->vdd);
1162                 break;
1163         case MMC_POWER_UP:
1164                 /* Cannot touch dsor yet, just power up MMC */
1165                 mmc_omap_set_power(slot, 1, ios->vdd);
1166                 goto exit;
1167         case MMC_POWER_ON:
1168                 mmc_omap_fclk_enable(host, 1);
1169                 clk_enabled = 1;
1170                 dsor |= 1 << 11;
1171                 break;
1172         }
1173
1174         if (slot->bus_mode != ios->bus_mode) {
1175                 if (slot->pdata->set_bus_mode != NULL)
1176                         slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id,
1177                                                   ios->bus_mode);
1178                 slot->bus_mode = ios->bus_mode;
1179         }
1180
1181         /* On insanely high arm_per frequencies something sometimes
1182          * goes somehow out of sync, and the POW bit is not being set,
1183          * which results in the while loop below getting stuck.
1184          * Writing to the CON register twice seems to do the trick. */
1185         for (i = 0; i < 2; i++)
1186                 OMAP_MMC_WRITE(host, CON, dsor);
1187         slot->saved_con = dsor;
1188         if (ios->power_mode == MMC_POWER_ON) {
1189                 /* worst case at 400kHz, 80 cycles makes 200 microsecs */
1190                 int usecs = 250;
1191
1192                 /* Send clock cycles, poll completion */
1193                 OMAP_MMC_WRITE(host, IE, 0);
1194                 OMAP_MMC_WRITE(host, STAT, 0xffff);
1195                 OMAP_MMC_WRITE(host, CMD, 1 << 7);
1196                 while (usecs > 0 && (OMAP_MMC_READ(host, STAT) & 1) == 0) {
1197                         udelay(1);
1198                         usecs--;
1199                 }
1200                 OMAP_MMC_WRITE(host, STAT, 1);
1201         }
1202
1203 exit:
1204         mmc_omap_release_slot(slot, clk_enabled);
1205 }
1206
1207 static const struct mmc_host_ops mmc_omap_ops = {
1208         .request        = mmc_omap_request,
1209         .set_ios        = mmc_omap_set_ios,
1210 };
1211
1212 static int __devinit mmc_omap_new_slot(struct mmc_omap_host *host, int id)
1213 {
1214         struct mmc_omap_slot *slot = NULL;
1215         struct mmc_host *mmc;
1216         int r;
1217
1218         mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
1219         if (mmc == NULL)
1220                 return -ENOMEM;
1221
1222         slot = mmc_priv(mmc);
1223         slot->host = host;
1224         slot->mmc = mmc;
1225         slot->id = id;
1226         slot->pdata = &host->pdata->slots[id];
1227
1228         host->slots[id] = slot;
1229
1230         mmc->caps = 0;
1231         if (host->pdata->slots[id].wires >= 4)
1232                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1233
1234         mmc->ops = &mmc_omap_ops;
1235         mmc->f_min = 400000;
1236
1237         if (cpu_class_is_omap2())
1238                 mmc->f_max = 48000000;
1239         else
1240                 mmc->f_max = 24000000;
1241         if (host->pdata->max_freq)
1242                 mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
1243         mmc->ocr_avail = slot->pdata->ocr_mask;
1244
1245         /* Use scatterlist DMA to reduce per-transfer costs.
1246          * NOTE max_seg_size assumption that small blocks aren't
1247          * normally used (except e.g. for reading SD registers).
1248          */
1249         mmc->max_segs = 32;
1250         mmc->max_blk_size = 2048;       /* BLEN is 11 bits (+1) */
1251         mmc->max_blk_count = 2048;      /* NBLK is 11 bits (+1) */
1252         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1253         mmc->max_seg_size = mmc->max_req_size;
1254
1255         r = mmc_add_host(mmc);
1256         if (r < 0)
1257                 goto err_remove_host;
1258
1259         if (slot->pdata->name != NULL) {
1260                 r = device_create_file(&mmc->class_dev,
1261                                         &dev_attr_slot_name);
1262                 if (r < 0)
1263                         goto err_remove_host;
1264         }
1265
1266         if (slot->pdata->get_cover_state != NULL) {
1267                 r = device_create_file(&mmc->class_dev,
1268                                         &dev_attr_cover_switch);
1269                 if (r < 0)
1270                         goto err_remove_slot_name;
1271
1272                 setup_timer(&slot->cover_timer, mmc_omap_cover_timer,
1273                             (unsigned long)slot);
1274                 tasklet_init(&slot->cover_tasklet, mmc_omap_cover_handler,
1275                              (unsigned long)slot);
1276                 tasklet_schedule(&slot->cover_tasklet);
1277         }
1278
1279         return 0;
1280
1281 err_remove_slot_name:
1282         if (slot->pdata->name != NULL)
1283                 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1284 err_remove_host:
1285         mmc_remove_host(mmc);
1286         mmc_free_host(mmc);
1287         return r;
1288 }
1289
1290 static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
1291 {
1292         struct mmc_host *mmc = slot->mmc;
1293
1294         if (slot->pdata->name != NULL)
1295                 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1296         if (slot->pdata->get_cover_state != NULL)
1297                 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1298
1299         tasklet_kill(&slot->cover_tasklet);
1300         del_timer_sync(&slot->cover_timer);
1301         flush_workqueue(slot->host->mmc_omap_wq);
1302
1303         mmc_remove_host(mmc);
1304         mmc_free_host(mmc);
1305 }
1306
1307 static int __devinit mmc_omap_probe(struct platform_device *pdev)
1308 {
1309         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1310         struct mmc_omap_host *host = NULL;
1311         struct resource *res;
1312         dma_cap_mask_t mask;
1313         unsigned sig;
1314         int i, ret = 0;
1315         int irq;
1316
1317         if (pdata == NULL) {
1318                 dev_err(&pdev->dev, "platform data missing\n");
1319                 return -ENXIO;
1320         }
1321         if (pdata->nr_slots == 0) {
1322                 dev_err(&pdev->dev, "no slots\n");
1323                 return -ENXIO;
1324         }
1325
1326         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1327         irq = platform_get_irq(pdev, 0);
1328         if (res == NULL || irq < 0)
1329                 return -ENXIO;
1330
1331         res = request_mem_region(res->start, resource_size(res),
1332                                  pdev->name);
1333         if (res == NULL)
1334                 return -EBUSY;
1335
1336         host = kzalloc(sizeof(struct mmc_omap_host), GFP_KERNEL);
1337         if (host == NULL) {
1338                 ret = -ENOMEM;
1339                 goto err_free_mem_region;
1340         }
1341
1342         INIT_WORK(&host->slot_release_work, mmc_omap_slot_release_work);
1343         INIT_WORK(&host->send_stop_work, mmc_omap_send_stop_work);
1344
1345         INIT_WORK(&host->cmd_abort_work, mmc_omap_abort_command);
1346         setup_timer(&host->cmd_abort_timer, mmc_omap_cmd_timer,
1347                     (unsigned long) host);
1348
1349         spin_lock_init(&host->clk_lock);
1350         setup_timer(&host->clk_timer, mmc_omap_clk_timer, (unsigned long) host);
1351
1352         spin_lock_init(&host->dma_lock);
1353         spin_lock_init(&host->slot_lock);
1354         init_waitqueue_head(&host->slot_wq);
1355
1356         host->pdata = pdata;
1357         host->dev = &pdev->dev;
1358         platform_set_drvdata(pdev, host);
1359
1360         host->id = pdev->id;
1361         host->mem_res = res;
1362         host->irq = irq;
1363         host->use_dma = 1;
1364         host->irq = irq;
1365         host->phys_base = host->mem_res->start;
1366         host->virt_base = ioremap(res->start, resource_size(res));
1367         if (!host->virt_base)
1368                 goto err_ioremap;
1369
1370         host->iclk = clk_get(&pdev->dev, "ick");
1371         if (IS_ERR(host->iclk)) {
1372                 ret = PTR_ERR(host->iclk);
1373                 goto err_free_mmc_host;
1374         }
1375         clk_enable(host->iclk);
1376
1377         host->fclk = clk_get(&pdev->dev, "fck");
1378         if (IS_ERR(host->fclk)) {
1379                 ret = PTR_ERR(host->fclk);
1380                 goto err_free_iclk;
1381         }
1382
1383         dma_cap_zero(mask);
1384         dma_cap_set(DMA_SLAVE, mask);
1385
1386         host->dma_tx_burst = -1;
1387         host->dma_rx_burst = -1;
1388
1389         if (cpu_is_omap24xx())
1390                 sig = host->id == 0 ? OMAP24XX_DMA_MMC1_TX : OMAP24XX_DMA_MMC2_TX;
1391         else
1392                 sig = host->id == 0 ? OMAP_DMA_MMC_TX : OMAP_DMA_MMC2_TX;
1393         host->dma_tx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
1394 #if 0
1395         if (!host->dma_tx) {
1396                 dev_err(host->dev, "unable to obtain TX DMA engine channel %u\n",
1397                         sig);
1398                 goto err_dma;
1399         }
1400 #else
1401         if (!host->dma_tx)
1402                 dev_warn(host->dev, "unable to obtain TX DMA engine channel %u\n",
1403                         sig);
1404 #endif
1405         if (cpu_is_omap24xx())
1406                 sig = host->id == 0 ? OMAP24XX_DMA_MMC1_RX : OMAP24XX_DMA_MMC2_RX;
1407         else
1408                 sig = host->id == 0 ? OMAP_DMA_MMC_RX : OMAP_DMA_MMC2_RX;
1409         host->dma_rx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
1410 #if 0
1411         if (!host->dma_rx) {
1412                 dev_err(host->dev, "unable to obtain RX DMA engine channel %u\n",
1413                         sig);
1414                 goto err_dma;
1415         }
1416 #else
1417         if (!host->dma_rx)
1418                 dev_warn(host->dev, "unable to obtain RX DMA engine channel %u\n",
1419                         sig);
1420 #endif
1421
1422         ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1423         if (ret)
1424                 goto err_free_dma;
1425
1426         if (pdata->init != NULL) {
1427                 ret = pdata->init(&pdev->dev);
1428                 if (ret < 0)
1429                         goto err_free_irq;
1430         }
1431
1432         host->nr_slots = pdata->nr_slots;
1433         host->reg_shift = (cpu_is_omap7xx() ? 1 : 2);
1434
1435         host->mmc_omap_wq = alloc_workqueue("mmc_omap", 0, 0);
1436         if (!host->mmc_omap_wq)
1437                 goto err_plat_cleanup;
1438
1439         for (i = 0; i < pdata->nr_slots; i++) {
1440                 ret = mmc_omap_new_slot(host, i);
1441                 if (ret < 0) {
1442                         while (--i >= 0)
1443                                 mmc_omap_remove_slot(host->slots[i]);
1444
1445                         goto err_destroy_wq;
1446                 }
1447         }
1448
1449         return 0;
1450
1451 err_destroy_wq:
1452         destroy_workqueue(host->mmc_omap_wq);
1453 err_plat_cleanup:
1454         if (pdata->cleanup)
1455                 pdata->cleanup(&pdev->dev);
1456 err_free_irq:
1457         free_irq(host->irq, host);
1458 err_free_dma:
1459         if (host->dma_tx)
1460                 dma_release_channel(host->dma_tx);
1461         if (host->dma_rx)
1462                 dma_release_channel(host->dma_rx);
1463         clk_put(host->fclk);
1464 err_free_iclk:
1465         clk_disable(host->iclk);
1466         clk_put(host->iclk);
1467 err_free_mmc_host:
1468         iounmap(host->virt_base);
1469 err_ioremap:
1470         kfree(host);
1471 err_free_mem_region:
1472         release_mem_region(res->start, resource_size(res));
1473         return ret;
1474 }
1475
1476 static int __devexit mmc_omap_remove(struct platform_device *pdev)
1477 {
1478         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1479         int i;
1480
1481         platform_set_drvdata(pdev, NULL);
1482
1483         BUG_ON(host == NULL);
1484
1485         for (i = 0; i < host->nr_slots; i++)
1486                 mmc_omap_remove_slot(host->slots[i]);
1487
1488         if (host->pdata->cleanup)
1489                 host->pdata->cleanup(&pdev->dev);
1490
1491         mmc_omap_fclk_enable(host, 0);
1492         free_irq(host->irq, host);
1493         clk_put(host->fclk);
1494         clk_disable(host->iclk);
1495         clk_put(host->iclk);
1496
1497         if (host->dma_tx)
1498                 dma_release_channel(host->dma_tx);
1499         if (host->dma_rx)
1500                 dma_release_channel(host->dma_rx);
1501
1502         iounmap(host->virt_base);
1503         release_mem_region(pdev->resource[0].start,
1504                            pdev->resource[0].end - pdev->resource[0].start + 1);
1505         destroy_workqueue(host->mmc_omap_wq);
1506
1507         kfree(host);
1508
1509         return 0;
1510 }
1511
1512 #ifdef CONFIG_PM
1513 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
1514 {
1515         int i, ret = 0;
1516         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1517
1518         if (host == NULL || host->suspended)
1519                 return 0;
1520
1521         for (i = 0; i < host->nr_slots; i++) {
1522                 struct mmc_omap_slot *slot;
1523
1524                 slot = host->slots[i];
1525                 ret = mmc_suspend_host(slot->mmc);
1526                 if (ret < 0) {
1527                         while (--i >= 0) {
1528                                 slot = host->slots[i];
1529                                 mmc_resume_host(slot->mmc);
1530                         }
1531                         return ret;
1532                 }
1533         }
1534         host->suspended = 1;
1535         return 0;
1536 }
1537
1538 static int mmc_omap_resume(struct platform_device *pdev)
1539 {
1540         int i, ret = 0;
1541         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1542
1543         if (host == NULL || !host->suspended)
1544                 return 0;
1545
1546         for (i = 0; i < host->nr_slots; i++) {
1547                 struct mmc_omap_slot *slot;
1548                 slot = host->slots[i];
1549                 ret = mmc_resume_host(slot->mmc);
1550                 if (ret < 0)
1551                         return ret;
1552
1553                 host->suspended = 0;
1554         }
1555         return 0;
1556 }
1557 #else
1558 #define mmc_omap_suspend        NULL
1559 #define mmc_omap_resume         NULL
1560 #endif
1561
1562 static struct platform_driver mmc_omap_driver = {
1563         .probe          = mmc_omap_probe,
1564         .remove         = __devexit_p(mmc_omap_remove),
1565         .suspend        = mmc_omap_suspend,
1566         .resume         = mmc_omap_resume,
1567         .driver         = {
1568                 .name   = DRIVER_NAME,
1569                 .owner  = THIS_MODULE,
1570         },
1571 };
1572
1573 module_platform_driver(mmc_omap_driver);
1574 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1575 MODULE_LICENSE("GPL");
1576 MODULE_ALIAS("platform:" DRIVER_NAME);
1577 MODULE_AUTHOR("Juha Yrjölä");