1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/mmc/host/mxcmmc.c - Freescale i.MX MMCI driver
5 * This is a driver for the SDHC controller found in Freescale MX2/MX3
6 * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
7 * Unlike the hardware found on MX1, this hardware just works and does
8 * not need all the quirks found in imxmmc.c, hence the separate driver.
10 * Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
11 * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
13 * derived from pxamci.c by Russell King
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/ioport.h>
19 #include <linux/platform_device.h>
20 #include <linux/highmem.h>
21 #include <linux/interrupt.h>
22 #include <linux/irq.h>
23 #include <linux/blkdev.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/mmc/host.h>
26 #include <linux/mmc/card.h>
27 #include <linux/delay.h>
28 #include <linux/clk.h>
30 #include <linux/regulator/consumer.h>
31 #include <linux/dmaengine.h>
32 #include <linux/types.h>
34 #include <linux/of_dma.h>
35 #include <linux/mmc/slot-gpio.h>
39 #include <linux/platform_data/mmc-mxcmmc.h>
41 #include <linux/dma/imx-dma.h>
43 #define DRIVER_NAME "mxc-mmc"
44 #define MXCMCI_TIMEOUT_MS 10000
46 #define MMC_REG_STR_STP_CLK 0x00
47 #define MMC_REG_STATUS 0x04
48 #define MMC_REG_CLK_RATE 0x08
49 #define MMC_REG_CMD_DAT_CONT 0x0C
50 #define MMC_REG_RES_TO 0x10
51 #define MMC_REG_READ_TO 0x14
52 #define MMC_REG_BLK_LEN 0x18
53 #define MMC_REG_NOB 0x1C
54 #define MMC_REG_REV_NO 0x20
55 #define MMC_REG_INT_CNTR 0x24
56 #define MMC_REG_CMD 0x28
57 #define MMC_REG_ARG 0x2C
58 #define MMC_REG_RES_FIFO 0x34
59 #define MMC_REG_BUFFER_ACCESS 0x38
61 #define STR_STP_CLK_RESET (1 << 3)
62 #define STR_STP_CLK_START_CLK (1 << 1)
63 #define STR_STP_CLK_STOP_CLK (1 << 0)
65 #define STATUS_CARD_INSERTION (1 << 31)
66 #define STATUS_CARD_REMOVAL (1 << 30)
67 #define STATUS_YBUF_EMPTY (1 << 29)
68 #define STATUS_XBUF_EMPTY (1 << 28)
69 #define STATUS_YBUF_FULL (1 << 27)
70 #define STATUS_XBUF_FULL (1 << 26)
71 #define STATUS_BUF_UND_RUN (1 << 25)
72 #define STATUS_BUF_OVFL (1 << 24)
73 #define STATUS_SDIO_INT_ACTIVE (1 << 14)
74 #define STATUS_END_CMD_RESP (1 << 13)
75 #define STATUS_WRITE_OP_DONE (1 << 12)
76 #define STATUS_DATA_TRANS_DONE (1 << 11)
77 #define STATUS_READ_OP_DONE (1 << 11)
78 #define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10)
79 #define STATUS_CARD_BUS_CLK_RUN (1 << 8)
80 #define STATUS_BUF_READ_RDY (1 << 7)
81 #define STATUS_BUF_WRITE_RDY (1 << 6)
82 #define STATUS_RESP_CRC_ERR (1 << 5)
83 #define STATUS_CRC_READ_ERR (1 << 3)
84 #define STATUS_CRC_WRITE_ERR (1 << 2)
85 #define STATUS_TIME_OUT_RESP (1 << 1)
86 #define STATUS_TIME_OUT_READ (1 << 0)
87 #define STATUS_ERR_MASK 0x2f
89 #define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12)
90 #define CMD_DAT_CONT_STOP_READWAIT (1 << 11)
91 #define CMD_DAT_CONT_START_READWAIT (1 << 10)
92 #define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8)
93 #define CMD_DAT_CONT_INIT (1 << 7)
94 #define CMD_DAT_CONT_WRITE (1 << 4)
95 #define CMD_DAT_CONT_DATA_ENABLE (1 << 3)
96 #define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0)
97 #define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0)
98 #define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0)
100 #define INT_SDIO_INT_WKP_EN (1 << 18)
101 #define INT_CARD_INSERTION_WKP_EN (1 << 17)
102 #define INT_CARD_REMOVAL_WKP_EN (1 << 16)
103 #define INT_CARD_INSERTION_EN (1 << 15)
104 #define INT_CARD_REMOVAL_EN (1 << 14)
105 #define INT_SDIO_IRQ_EN (1 << 13)
106 #define INT_DAT0_EN (1 << 12)
107 #define INT_BUF_READ_EN (1 << 4)
108 #define INT_BUF_WRITE_EN (1 << 3)
109 #define INT_END_CMD_RES_EN (1 << 2)
110 #define INT_WRITE_OP_DONE_EN (1 << 1)
111 #define INT_READ_OP_EN (1 << 0)
120 struct mmc_host *mmc;
122 dma_addr_t phys_base;
124 struct dma_chan *dma;
125 struct dma_async_tx_descriptor *desc;
127 int default_irq_mask;
129 unsigned int power_mode;
130 struct imxmmc_platform_data *pdata;
132 struct mmc_request *req;
133 struct mmc_command *cmd;
134 struct mmc_data *data;
136 unsigned int datasize;
137 unsigned int dma_dir;
147 struct work_struct datawork;
152 struct dma_slave_config dma_slave_config;
153 struct imx_dma_data dma_data;
155 struct timer_list watchdog;
156 enum mxcmci_type devtype;
159 static const struct of_device_id mxcmci_of_match[] = {
161 .compatible = "fsl,imx21-mmc",
162 .data = (void *) IMX21_MMC,
164 .compatible = "fsl,imx31-mmc",
165 .data = (void *) IMX31_MMC,
167 .compatible = "fsl,mpc5121-sdhc",
168 .data = (void *) MPC512X_MMC,
173 MODULE_DEVICE_TABLE(of, mxcmci_of_match);
175 static inline int is_imx31_mmc(struct mxcmci_host *host)
177 return host->devtype == IMX31_MMC;
180 static inline int is_mpc512x_mmc(struct mxcmci_host *host)
182 return host->devtype == MPC512X_MMC;
185 static inline u32 mxcmci_readl(struct mxcmci_host *host, int reg)
187 if (IS_ENABLED(CONFIG_PPC_MPC512x))
188 return ioread32be(host->base + reg);
190 return readl(host->base + reg);
193 static inline void mxcmci_writel(struct mxcmci_host *host, u32 val, int reg)
195 if (IS_ENABLED(CONFIG_PPC_MPC512x))
196 iowrite32be(val, host->base + reg);
198 writel(val, host->base + reg);
201 static inline u16 mxcmci_readw(struct mxcmci_host *host, int reg)
203 if (IS_ENABLED(CONFIG_PPC_MPC512x))
204 return ioread32be(host->base + reg);
206 return readw(host->base + reg);
209 static inline void mxcmci_writew(struct mxcmci_host *host, u16 val, int reg)
211 if (IS_ENABLED(CONFIG_PPC_MPC512x))
212 iowrite32be(val, host->base + reg);
214 writew(val, host->base + reg);
217 static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios);
219 static void mxcmci_set_power(struct mxcmci_host *host, unsigned int vdd)
221 if (!IS_ERR(host->mmc->supply.vmmc)) {
222 if (host->power_mode == MMC_POWER_UP)
223 mmc_regulator_set_ocr(host->mmc,
224 host->mmc->supply.vmmc, vdd);
225 else if (host->power_mode == MMC_POWER_OFF)
226 mmc_regulator_set_ocr(host->mmc,
227 host->mmc->supply.vmmc, 0);
230 if (host->pdata && host->pdata->setpower)
231 host->pdata->setpower(mmc_dev(host->mmc), vdd);
234 static inline int mxcmci_use_dma(struct mxcmci_host *host)
239 static void mxcmci_softreset(struct mxcmci_host *host)
243 dev_dbg(mmc_dev(host->mmc), "mxcmci_softreset\n");
246 mxcmci_writew(host, STR_STP_CLK_RESET, MMC_REG_STR_STP_CLK);
247 mxcmci_writew(host, STR_STP_CLK_RESET | STR_STP_CLK_START_CLK,
248 MMC_REG_STR_STP_CLK);
250 for (i = 0; i < 8; i++)
251 mxcmci_writew(host, STR_STP_CLK_START_CLK, MMC_REG_STR_STP_CLK);
253 mxcmci_writew(host, 0xff, MMC_REG_RES_TO);
256 #if IS_ENABLED(CONFIG_PPC_MPC512x)
257 static inline void buffer_swap32(u32 *buf, int len)
261 for (i = 0; i < ((len + 3) / 4); i++) {
267 static void mxcmci_swap_buffers(struct mmc_data *data)
269 struct scatterlist *sg;
272 for_each_sg(data->sg, sg, data->sg_len, i)
273 buffer_swap32(sg_virt(sg), sg->length);
276 static inline void mxcmci_swap_buffers(struct mmc_data *data) {}
279 static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data)
281 unsigned int nob = data->blocks;
282 unsigned int blksz = data->blksz;
283 unsigned int datasize = nob * blksz;
284 struct scatterlist *sg;
285 enum dma_transfer_direction slave_dirn;
289 data->bytes_xfered = 0;
291 mxcmci_writew(host, nob, MMC_REG_NOB);
292 mxcmci_writew(host, blksz, MMC_REG_BLK_LEN);
293 host->datasize = datasize;
295 if (!mxcmci_use_dma(host))
298 for_each_sg(data->sg, sg, data->sg_len, i) {
299 if (sg->offset & 3 || sg->length & 3 || sg->length < 512) {
305 if (data->flags & MMC_DATA_READ) {
306 host->dma_dir = DMA_FROM_DEVICE;
307 slave_dirn = DMA_DEV_TO_MEM;
309 host->dma_dir = DMA_TO_DEVICE;
310 slave_dirn = DMA_MEM_TO_DEV;
312 mxcmci_swap_buffers(data);
315 nents = dma_map_sg(host->dma->device->dev, data->sg,
316 data->sg_len, host->dma_dir);
317 if (nents != data->sg_len)
320 host->desc = dmaengine_prep_slave_sg(host->dma,
321 data->sg, data->sg_len, slave_dirn,
322 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
325 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len,
328 return 0; /* Fall back to PIO */
332 dmaengine_submit(host->desc);
333 dma_async_issue_pending(host->dma);
335 mod_timer(&host->watchdog, jiffies + msecs_to_jiffies(MXCMCI_TIMEOUT_MS));
340 static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat);
341 static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat);
343 static void mxcmci_dma_callback(void *data)
345 struct mxcmci_host *host = data;
348 del_timer(&host->watchdog);
350 stat = mxcmci_readl(host, MMC_REG_STATUS);
352 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
354 mxcmci_data_done(host, stat);
357 static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd,
360 u32 int_cntr = host->default_irq_mask;
363 WARN_ON(host->cmd != NULL);
366 switch (mmc_resp_type(cmd)) {
367 case MMC_RSP_R1: /* short CRC, OPCODE */
368 case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */
369 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC;
371 case MMC_RSP_R2: /* long 136 bit + CRC */
372 cmdat |= CMD_DAT_CONT_RESPONSE_136BIT;
374 case MMC_RSP_R3: /* short */
375 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT;
380 dev_err(mmc_dev(host->mmc), "unhandled response type 0x%x\n",
382 cmd->error = -EINVAL;
386 int_cntr = INT_END_CMD_RES_EN;
388 if (mxcmci_use_dma(host)) {
389 if (host->dma_dir == DMA_FROM_DEVICE) {
390 host->desc->callback = mxcmci_dma_callback;
391 host->desc->callback_param = host;
393 int_cntr |= INT_WRITE_OP_DONE_EN;
397 spin_lock_irqsave(&host->lock, flags);
399 int_cntr |= INT_SDIO_IRQ_EN;
400 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
401 spin_unlock_irqrestore(&host->lock, flags);
403 mxcmci_writew(host, cmd->opcode, MMC_REG_CMD);
404 mxcmci_writel(host, cmd->arg, MMC_REG_ARG);
405 mxcmci_writew(host, cmdat, MMC_REG_CMD_DAT_CONT);
410 static void mxcmci_finish_request(struct mxcmci_host *host,
411 struct mmc_request *req)
413 u32 int_cntr = host->default_irq_mask;
416 spin_lock_irqsave(&host->lock, flags);
418 int_cntr |= INT_SDIO_IRQ_EN;
419 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
420 spin_unlock_irqrestore(&host->lock, flags);
426 mmc_request_done(host->mmc, req);
429 static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat)
431 struct mmc_data *data = host->data;
434 if (mxcmci_use_dma(host)) {
435 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len,
437 mxcmci_swap_buffers(data);
440 if (stat & STATUS_ERR_MASK) {
441 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n",
443 if (stat & STATUS_CRC_READ_ERR) {
444 dev_err(mmc_dev(host->mmc), "%s: -EILSEQ\n", __func__);
445 data->error = -EILSEQ;
446 } else if (stat & STATUS_CRC_WRITE_ERR) {
447 u32 err_code = (stat >> 9) & 0x3;
448 if (err_code == 2) { /* No CRC response */
449 dev_err(mmc_dev(host->mmc),
450 "%s: No CRC -ETIMEDOUT\n", __func__);
451 data->error = -ETIMEDOUT;
453 dev_err(mmc_dev(host->mmc),
454 "%s: -EILSEQ\n", __func__);
455 data->error = -EILSEQ;
457 } else if (stat & STATUS_TIME_OUT_READ) {
458 dev_err(mmc_dev(host->mmc),
459 "%s: read -ETIMEDOUT\n", __func__);
460 data->error = -ETIMEDOUT;
462 dev_err(mmc_dev(host->mmc), "%s: -EIO\n", __func__);
466 data->bytes_xfered = host->datasize;
469 data_error = data->error;
476 static void mxcmci_read_response(struct mxcmci_host *host, unsigned int stat)
478 struct mmc_command *cmd = host->cmd;
485 if (stat & STATUS_TIME_OUT_RESP) {
486 dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n");
487 cmd->error = -ETIMEDOUT;
488 } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
489 dev_dbg(mmc_dev(host->mmc), "cmd crc error\n");
490 cmd->error = -EILSEQ;
493 if (cmd->flags & MMC_RSP_PRESENT) {
494 if (cmd->flags & MMC_RSP_136) {
495 for (i = 0; i < 4; i++) {
496 a = mxcmci_readw(host, MMC_REG_RES_FIFO);
497 b = mxcmci_readw(host, MMC_REG_RES_FIFO);
498 cmd->resp[i] = a << 16 | b;
501 a = mxcmci_readw(host, MMC_REG_RES_FIFO);
502 b = mxcmci_readw(host, MMC_REG_RES_FIFO);
503 c = mxcmci_readw(host, MMC_REG_RES_FIFO);
504 cmd->resp[0] = a << 24 | b << 8 | c >> 8;
509 static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask)
512 unsigned long timeout = jiffies + HZ;
515 stat = mxcmci_readl(host, MMC_REG_STATUS);
516 if (stat & STATUS_ERR_MASK)
518 if (time_after(jiffies, timeout)) {
519 mxcmci_softreset(host);
520 mxcmci_set_clk_rate(host, host->clock);
521 return STATUS_TIME_OUT_READ;
529 static int mxcmci_pull(struct mxcmci_host *host, void *_buf, int bytes)
535 stat = mxcmci_poll_status(host,
536 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
539 *buf++ = cpu_to_le32(mxcmci_readl(host, MMC_REG_BUFFER_ACCESS));
547 stat = mxcmci_poll_status(host,
548 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
551 tmp = cpu_to_le32(mxcmci_readl(host, MMC_REG_BUFFER_ACCESS));
552 memcpy(b, &tmp, bytes);
558 static int mxcmci_push(struct mxcmci_host *host, void *_buf, int bytes)
564 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
567 mxcmci_writel(host, cpu_to_le32(*buf++), MMC_REG_BUFFER_ACCESS);
575 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
579 memcpy(&tmp, b, bytes);
580 mxcmci_writel(host, cpu_to_le32(tmp), MMC_REG_BUFFER_ACCESS);
583 return mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
586 static int mxcmci_transfer_data(struct mxcmci_host *host)
588 struct mmc_data *data = host->req->data;
589 struct scatterlist *sg;
595 if (data->flags & MMC_DATA_READ) {
596 for_each_sg(data->sg, sg, data->sg_len, i) {
597 stat = mxcmci_pull(host, sg_virt(sg), sg->length);
600 host->datasize += sg->length;
603 for_each_sg(data->sg, sg, data->sg_len, i) {
604 stat = mxcmci_push(host, sg_virt(sg), sg->length);
607 host->datasize += sg->length;
609 stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE);
616 static void mxcmci_datawork(struct work_struct *work)
618 struct mxcmci_host *host = container_of(work, struct mxcmci_host,
620 int datastat = mxcmci_transfer_data(host);
622 mxcmci_writel(host, STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE,
624 mxcmci_finish_data(host, datastat);
626 if (host->req->stop) {
627 if (mxcmci_start_cmd(host, host->req->stop, 0)) {
628 mxcmci_finish_request(host, host->req);
632 mxcmci_finish_request(host, host->req);
636 static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat)
638 struct mmc_request *req;
642 spin_lock_irqsave(&host->lock, flags);
645 spin_unlock_irqrestore(&host->lock, flags);
650 spin_unlock_irqrestore(&host->lock, flags);
656 host->req = NULL; /* we will handle finish req below */
658 data_error = mxcmci_finish_data(host, stat);
660 spin_unlock_irqrestore(&host->lock, flags);
665 mxcmci_read_response(host, stat);
669 if (mxcmci_start_cmd(host, req->stop, 0)) {
670 mxcmci_finish_request(host, req);
674 mxcmci_finish_request(host, req);
678 static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat)
680 mxcmci_read_response(host, stat);
683 if (!host->data && host->req) {
684 mxcmci_finish_request(host, host->req);
688 /* For the DMA case the DMA engine handles the data transfer
689 * automatically. For non DMA we have to do it ourselves.
690 * Don't do it in interrupt context though.
692 if (!mxcmci_use_dma(host) && host->data)
693 schedule_work(&host->datawork);
697 static irqreturn_t mxcmci_irq(int irq, void *devid)
699 struct mxcmci_host *host = devid;
703 stat = mxcmci_readl(host, MMC_REG_STATUS);
705 stat & ~(STATUS_SDIO_INT_ACTIVE | STATUS_DATA_TRANS_DONE |
706 STATUS_WRITE_OP_DONE),
709 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
711 spin_lock(&host->lock);
712 sdio_irq = (stat & STATUS_SDIO_INT_ACTIVE) && host->use_sdio;
713 spin_unlock(&host->lock);
715 if (mxcmci_use_dma(host) && (stat & (STATUS_WRITE_OP_DONE)))
716 mxcmci_writel(host, STATUS_WRITE_OP_DONE, MMC_REG_STATUS);
719 mxcmci_writel(host, STATUS_SDIO_INT_ACTIVE, MMC_REG_STATUS);
720 mmc_signal_sdio_irq(host->mmc);
723 if (stat & STATUS_END_CMD_RESP)
724 mxcmci_cmd_done(host, stat);
726 if (mxcmci_use_dma(host) && (stat & STATUS_WRITE_OP_DONE)) {
727 del_timer(&host->watchdog);
728 mxcmci_data_done(host, stat);
731 if (host->default_irq_mask &&
732 (stat & (STATUS_CARD_INSERTION | STATUS_CARD_REMOVAL)))
733 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
738 static void mxcmci_request(struct mmc_host *mmc, struct mmc_request *req)
740 struct mxcmci_host *host = mmc_priv(mmc);
741 unsigned int cmdat = host->cmdat;
744 WARN_ON(host->req != NULL);
747 host->cmdat &= ~CMD_DAT_CONT_INIT;
753 error = mxcmci_setup_data(host, req->data);
755 req->cmd->error = error;
760 cmdat |= CMD_DAT_CONT_DATA_ENABLE;
762 if (req->data->flags & MMC_DATA_WRITE)
763 cmdat |= CMD_DAT_CONT_WRITE;
766 error = mxcmci_start_cmd(host, req->cmd, cmdat);
770 mxcmci_finish_request(host, req);
773 static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios)
775 unsigned int divider;
777 unsigned int clk_in = clk_get_rate(host->clk_per);
779 while (prescaler <= 0x800) {
780 for (divider = 1; divider <= 0xF; divider++) {
783 x = (clk_in / (divider + 1));
786 x /= (prescaler * 2);
800 mxcmci_writew(host, (prescaler << 4) | divider, MMC_REG_CLK_RATE);
802 dev_dbg(mmc_dev(host->mmc), "scaler: %d divider: %d in: %d out: %d\n",
803 prescaler, divider, clk_in, clk_ios);
806 static int mxcmci_setup_dma(struct mmc_host *mmc)
808 struct mxcmci_host *host = mmc_priv(mmc);
809 struct dma_slave_config *config = &host->dma_slave_config;
811 config->dst_addr = host->phys_base + MMC_REG_BUFFER_ACCESS;
812 config->src_addr = host->phys_base + MMC_REG_BUFFER_ACCESS;
813 config->dst_addr_width = 4;
814 config->src_addr_width = 4;
815 config->dst_maxburst = host->burstlen;
816 config->src_maxburst = host->burstlen;
817 config->device_fc = false;
819 return dmaengine_slave_config(host->dma, config);
822 static void mxcmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
824 struct mxcmci_host *host = mmc_priv(mmc);
828 * use burstlen of 64 (16 words) in 4 bit mode (--> reg value 0)
829 * use burstlen of 16 (4 words) in 1 bit mode (--> reg value 16)
831 if (ios->bus_width == MMC_BUS_WIDTH_4)
836 if (mxcmci_use_dma(host) && burstlen != host->burstlen) {
837 host->burstlen = burstlen;
838 ret = mxcmci_setup_dma(mmc);
840 dev_err(mmc_dev(host->mmc),
841 "failed to config DMA channel. Falling back to PIO\n");
842 dma_release_channel(host->dma);
848 if (ios->bus_width == MMC_BUS_WIDTH_4)
849 host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
851 host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4;
853 if (host->power_mode != ios->power_mode) {
854 host->power_mode = ios->power_mode;
855 mxcmci_set_power(host, ios->vdd);
857 if (ios->power_mode == MMC_POWER_ON)
858 host->cmdat |= CMD_DAT_CONT_INIT;
862 mxcmci_set_clk_rate(host, ios->clock);
863 mxcmci_writew(host, STR_STP_CLK_START_CLK, MMC_REG_STR_STP_CLK);
865 mxcmci_writew(host, STR_STP_CLK_STOP_CLK, MMC_REG_STR_STP_CLK);
868 host->clock = ios->clock;
871 static irqreturn_t mxcmci_detect_irq(int irq, void *data)
873 struct mmc_host *mmc = data;
875 dev_dbg(mmc_dev(mmc), "%s\n", __func__);
877 mmc_detect_change(mmc, msecs_to_jiffies(250));
881 static int mxcmci_get_ro(struct mmc_host *mmc)
883 struct mxcmci_host *host = mmc_priv(mmc);
885 if (host->pdata && host->pdata->get_ro)
886 return !!host->pdata->get_ro(mmc_dev(mmc));
888 * If board doesn't support read only detection (no mmc_gpio
889 * context or gpio is invalid), then let the mmc core decide
892 return mmc_gpio_get_ro(mmc);
895 static void mxcmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
897 struct mxcmci_host *host = mmc_priv(mmc);
901 spin_lock_irqsave(&host->lock, flags);
902 host->use_sdio = enable;
903 int_cntr = mxcmci_readl(host, MMC_REG_INT_CNTR);
906 int_cntr |= INT_SDIO_IRQ_EN;
908 int_cntr &= ~INT_SDIO_IRQ_EN;
910 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
911 spin_unlock_irqrestore(&host->lock, flags);
914 static void mxcmci_init_card(struct mmc_host *host, struct mmc_card *card)
916 struct mxcmci_host *mxcmci = mmc_priv(host);
919 * MX3 SoCs have a silicon bug which corrupts CRC calculation of
920 * multi-block transfers when connected SDIO peripheral doesn't
921 * drive the BUSY line as required by the specs.
922 * One way to prevent this is to only allow 1-bit transfers.
925 if (is_imx31_mmc(mxcmci) && mmc_card_sdio(card))
926 host->caps &= ~MMC_CAP_4_BIT_DATA;
928 host->caps |= MMC_CAP_4_BIT_DATA;
931 static bool filter(struct dma_chan *chan, void *param)
933 struct mxcmci_host *host = param;
935 if (!imx_dma_is_general_purpose(chan))
938 chan->private = &host->dma_data;
943 static void mxcmci_watchdog(struct timer_list *t)
945 struct mxcmci_host *host = from_timer(host, t, watchdog);
946 struct mmc_request *req = host->req;
947 unsigned int stat = mxcmci_readl(host, MMC_REG_STATUS);
949 if (host->dma_dir == DMA_FROM_DEVICE) {
950 dmaengine_terminate_all(host->dma);
951 dev_err(mmc_dev(host->mmc),
952 "%s: read time out (status = 0x%08x)\n",
955 dev_err(mmc_dev(host->mmc),
956 "%s: write time out (status = 0x%08x)\n",
958 mxcmci_softreset(host);
961 /* Mark transfer as erroneus and inform the upper layers */
964 host->data->error = -ETIMEDOUT;
968 mmc_request_done(host->mmc, req);
971 static const struct mmc_host_ops mxcmci_ops = {
972 .request = mxcmci_request,
973 .set_ios = mxcmci_set_ios,
974 .get_ro = mxcmci_get_ro,
975 .enable_sdio_irq = mxcmci_enable_sdio_irq,
976 .init_card = mxcmci_init_card,
979 static int mxcmci_probe(struct platform_device *pdev)
981 struct mmc_host *mmc;
982 struct mxcmci_host *host;
983 struct resource *res;
985 bool dat3_card_detect = false;
987 struct imxmmc_platform_data *pdata = pdev->dev.platform_data;
989 pr_info("i.MX/MPC512x SDHC driver\n");
991 irq = platform_get_irq(pdev, 0);
995 mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
999 host = mmc_priv(mmc);
1001 host->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1002 if (IS_ERR(host->base)) {
1003 ret = PTR_ERR(host->base);
1007 host->phys_base = res->start;
1009 ret = mmc_of_parse(mmc);
1012 mmc->ops = &mxcmci_ops;
1014 /* For devicetree parsing, the bus width is read from devicetree */
1016 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1018 mmc->caps |= MMC_CAP_SDIO_IRQ;
1020 /* MMC core transfer sizes tunable parameters */
1021 mmc->max_blk_size = 2048;
1022 mmc->max_blk_count = 65535;
1023 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1024 mmc->max_seg_size = mmc->max_req_size;
1026 host->devtype = (uintptr_t)of_device_get_match_data(&pdev->dev);
1028 /* adjust max_segs after devtype detection */
1029 if (!is_mpc512x_mmc(host))
1033 host->pdata = pdata;
1034 spin_lock_init(&host->lock);
1037 dat3_card_detect = pdata->dat3_card_detect;
1038 else if (mmc_card_is_removable(mmc)
1039 && !of_property_read_bool(pdev->dev.of_node, "cd-gpios"))
1040 dat3_card_detect = true;
1042 ret = mmc_regulator_get_supply(mmc);
1046 if (!mmc->ocr_avail) {
1047 if (pdata && pdata->ocr_avail)
1048 mmc->ocr_avail = pdata->ocr_avail;
1050 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1053 if (dat3_card_detect)
1054 host->default_irq_mask =
1055 INT_CARD_INSERTION_EN | INT_CARD_REMOVAL_EN;
1057 host->default_irq_mask = 0;
1059 host->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1060 if (IS_ERR(host->clk_ipg)) {
1061 ret = PTR_ERR(host->clk_ipg);
1065 host->clk_per = devm_clk_get(&pdev->dev, "per");
1066 if (IS_ERR(host->clk_per)) {
1067 ret = PTR_ERR(host->clk_per);
1071 ret = clk_prepare_enable(host->clk_per);
1075 ret = clk_prepare_enable(host->clk_ipg);
1077 goto out_clk_per_put;
1079 mxcmci_softreset(host);
1081 host->rev_no = mxcmci_readw(host, MMC_REG_REV_NO);
1082 if (host->rev_no != 0x400) {
1084 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
1089 mmc->f_min = clk_get_rate(host->clk_per) >> 16;
1090 mmc->f_max = clk_get_rate(host->clk_per) >> 1;
1092 /* recommended in data sheet */
1093 mxcmci_writew(host, 0x2db4, MMC_REG_READ_TO);
1095 mxcmci_writel(host, host->default_irq_mask, MMC_REG_INT_CNTR);
1098 host->dma = dma_request_chan(&pdev->dev, "rx-tx");
1099 if (IS_ERR(host->dma)) {
1100 if (PTR_ERR(host->dma) == -EPROBE_DEFER) {
1101 ret = -EPROBE_DEFER;
1105 /* Ignore errors to fall back to PIO mode */
1109 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1111 host->dmareq = res->start;
1112 host->dma_data.peripheral_type = IMX_DMATYPE_SDHC;
1113 host->dma_data.priority = DMA_PRIO_LOW;
1114 host->dma_data.dma_request = host->dmareq;
1116 dma_cap_set(DMA_SLAVE, mask);
1117 host->dma = dma_request_channel(mask, filter, host);
1121 mmc->max_seg_size = dma_get_max_seg_size(
1122 host->dma->device->dev);
1124 dev_info(mmc_dev(host->mmc), "dma not available. Using PIO\n");
1126 INIT_WORK(&host->datawork, mxcmci_datawork);
1128 ret = devm_request_irq(&pdev->dev, irq, mxcmci_irq, 0,
1129 dev_name(&pdev->dev), host);
1133 platform_set_drvdata(pdev, mmc);
1135 if (host->pdata && host->pdata->init) {
1136 ret = host->pdata->init(&pdev->dev, mxcmci_detect_irq,
1142 timer_setup(&host->watchdog, mxcmci_watchdog, 0);
1144 ret = mmc_add_host(mmc);
1152 dma_release_channel(host->dma);
1155 clk_disable_unprepare(host->clk_ipg);
1157 clk_disable_unprepare(host->clk_per);
1165 static void mxcmci_remove(struct platform_device *pdev)
1167 struct mmc_host *mmc = platform_get_drvdata(pdev);
1168 struct mxcmci_host *host = mmc_priv(mmc);
1170 mmc_remove_host(mmc);
1172 if (host->pdata && host->pdata->exit)
1173 host->pdata->exit(&pdev->dev, mmc);
1176 dma_release_channel(host->dma);
1178 clk_disable_unprepare(host->clk_per);
1179 clk_disable_unprepare(host->clk_ipg);
1184 static int mxcmci_suspend(struct device *dev)
1186 struct mmc_host *mmc = dev_get_drvdata(dev);
1187 struct mxcmci_host *host = mmc_priv(mmc);
1189 clk_disable_unprepare(host->clk_per);
1190 clk_disable_unprepare(host->clk_ipg);
1194 static int mxcmci_resume(struct device *dev)
1196 struct mmc_host *mmc = dev_get_drvdata(dev);
1197 struct mxcmci_host *host = mmc_priv(mmc);
1200 ret = clk_prepare_enable(host->clk_per);
1204 ret = clk_prepare_enable(host->clk_ipg);
1206 clk_disable_unprepare(host->clk_per);
1211 static DEFINE_SIMPLE_DEV_PM_OPS(mxcmci_pm_ops, mxcmci_suspend, mxcmci_resume);
1213 static struct platform_driver mxcmci_driver = {
1214 .probe = mxcmci_probe,
1215 .remove_new = mxcmci_remove,
1217 .name = DRIVER_NAME,
1218 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1219 .pm = pm_sleep_ptr(&mxcmci_pm_ops),
1220 .of_match_table = mxcmci_of_match,
1224 module_platform_driver(mxcmci_driver);
1226 MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver");
1227 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1228 MODULE_LICENSE("GPL");
1229 MODULE_ALIAS("platform:mxc-mmc");