2 * linux/drivers/mmc/host/mxcmmc.c - Freescale i.MX MMCI driver
4 * This is a driver for the SDHC controller found in Freescale MX2/MX3
5 * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
6 * Unlike the hardware found on MX1, this hardware just works and does
7 * not need all the quirks found in imxmmc.c, hence the separate driver.
9 * Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
10 * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
12 * derived from pxamci.c by Russell King
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/ioport.h>
23 #include <linux/platform_device.h>
24 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/blkdev.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/mmc/host.h>
29 #include <linux/mmc/card.h>
30 #include <linux/delay.h>
31 #include <linux/clk.h>
33 #include <linux/gpio.h>
34 #include <linux/regulator/consumer.h>
35 #include <linux/dmaengine.h>
39 #include <asm/sizes.h>
43 #include <mach/hardware.h>
45 #define DRIVER_NAME "mxc-mmc"
47 #define MMC_REG_STR_STP_CLK 0x00
48 #define MMC_REG_STATUS 0x04
49 #define MMC_REG_CLK_RATE 0x08
50 #define MMC_REG_CMD_DAT_CONT 0x0C
51 #define MMC_REG_RES_TO 0x10
52 #define MMC_REG_READ_TO 0x14
53 #define MMC_REG_BLK_LEN 0x18
54 #define MMC_REG_NOB 0x1C
55 #define MMC_REG_REV_NO 0x20
56 #define MMC_REG_INT_CNTR 0x24
57 #define MMC_REG_CMD 0x28
58 #define MMC_REG_ARG 0x2C
59 #define MMC_REG_RES_FIFO 0x34
60 #define MMC_REG_BUFFER_ACCESS 0x38
62 #define STR_STP_CLK_RESET (1 << 3)
63 #define STR_STP_CLK_START_CLK (1 << 1)
64 #define STR_STP_CLK_STOP_CLK (1 << 0)
66 #define STATUS_CARD_INSERTION (1 << 31)
67 #define STATUS_CARD_REMOVAL (1 << 30)
68 #define STATUS_YBUF_EMPTY (1 << 29)
69 #define STATUS_XBUF_EMPTY (1 << 28)
70 #define STATUS_YBUF_FULL (1 << 27)
71 #define STATUS_XBUF_FULL (1 << 26)
72 #define STATUS_BUF_UND_RUN (1 << 25)
73 #define STATUS_BUF_OVFL (1 << 24)
74 #define STATUS_SDIO_INT_ACTIVE (1 << 14)
75 #define STATUS_END_CMD_RESP (1 << 13)
76 #define STATUS_WRITE_OP_DONE (1 << 12)
77 #define STATUS_DATA_TRANS_DONE (1 << 11)
78 #define STATUS_READ_OP_DONE (1 << 11)
79 #define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10)
80 #define STATUS_CARD_BUS_CLK_RUN (1 << 8)
81 #define STATUS_BUF_READ_RDY (1 << 7)
82 #define STATUS_BUF_WRITE_RDY (1 << 6)
83 #define STATUS_RESP_CRC_ERR (1 << 5)
84 #define STATUS_CRC_READ_ERR (1 << 3)
85 #define STATUS_CRC_WRITE_ERR (1 << 2)
86 #define STATUS_TIME_OUT_RESP (1 << 1)
87 #define STATUS_TIME_OUT_READ (1 << 0)
88 #define STATUS_ERR_MASK 0x2f
90 #define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12)
91 #define CMD_DAT_CONT_STOP_READWAIT (1 << 11)
92 #define CMD_DAT_CONT_START_READWAIT (1 << 10)
93 #define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8)
94 #define CMD_DAT_CONT_INIT (1 << 7)
95 #define CMD_DAT_CONT_WRITE (1 << 4)
96 #define CMD_DAT_CONT_DATA_ENABLE (1 << 3)
97 #define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0)
98 #define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0)
99 #define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0)
101 #define INT_SDIO_INT_WKP_EN (1 << 18)
102 #define INT_CARD_INSERTION_WKP_EN (1 << 17)
103 #define INT_CARD_REMOVAL_WKP_EN (1 << 16)
104 #define INT_CARD_INSERTION_EN (1 << 15)
105 #define INT_CARD_REMOVAL_EN (1 << 14)
106 #define INT_SDIO_IRQ_EN (1 << 13)
107 #define INT_DAT0_EN (1 << 12)
108 #define INT_BUF_READ_EN (1 << 4)
109 #define INT_BUF_WRITE_EN (1 << 3)
110 #define INT_END_CMD_RES_EN (1 << 2)
111 #define INT_WRITE_OP_DONE_EN (1 << 1)
112 #define INT_READ_OP_EN (1 << 0)
115 struct mmc_host *mmc;
116 struct resource *res;
120 struct dma_chan *dma;
121 struct dma_async_tx_descriptor *desc;
123 int default_irq_mask;
125 unsigned int power_mode;
126 struct imxmmc_platform_data *pdata;
128 struct mmc_request *req;
129 struct mmc_command *cmd;
130 struct mmc_data *data;
132 unsigned int datasize;
133 unsigned int dma_dir;
142 struct work_struct datawork;
145 struct regulator *vcc;
149 struct dma_slave_config dma_slave_config;
150 struct imx_dma_data dma_data;
153 static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios);
155 static inline void mxcmci_init_ocr(struct mxcmci_host *host)
157 host->vcc = regulator_get(mmc_dev(host->mmc), "vmmc");
159 if (IS_ERR(host->vcc)) {
162 host->mmc->ocr_avail = mmc_regulator_get_ocrmask(host->vcc);
163 if (host->pdata && host->pdata->ocr_avail)
164 dev_warn(mmc_dev(host->mmc),
165 "pdata->ocr_avail will not be used\n");
168 if (host->vcc == NULL) {
169 /* fall-back to platform data */
170 if (host->pdata && host->pdata->ocr_avail)
171 host->mmc->ocr_avail = host->pdata->ocr_avail;
173 host->mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
177 static inline void mxcmci_set_power(struct mxcmci_host *host,
178 unsigned char power_mode,
182 if (power_mode == MMC_POWER_UP)
183 mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
184 else if (power_mode == MMC_POWER_OFF)
185 mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
188 if (host->pdata && host->pdata->setpower)
189 host->pdata->setpower(mmc_dev(host->mmc), vdd);
192 static inline int mxcmci_use_dma(struct mxcmci_host *host)
197 static void mxcmci_softreset(struct mxcmci_host *host)
201 dev_dbg(mmc_dev(host->mmc), "mxcmci_softreset\n");
204 writew(STR_STP_CLK_RESET, host->base + MMC_REG_STR_STP_CLK);
205 writew(STR_STP_CLK_RESET | STR_STP_CLK_START_CLK,
206 host->base + MMC_REG_STR_STP_CLK);
208 for (i = 0; i < 8; i++)
209 writew(STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
211 writew(0xff, host->base + MMC_REG_RES_TO);
213 static int mxcmci_setup_dma(struct mmc_host *mmc);
215 static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data)
217 unsigned int nob = data->blocks;
218 unsigned int blksz = data->blksz;
219 unsigned int datasize = nob * blksz;
220 struct scatterlist *sg;
221 enum dma_transfer_direction slave_dirn;
224 if (data->flags & MMC_DATA_STREAM)
228 data->bytes_xfered = 0;
230 writew(nob, host->base + MMC_REG_NOB);
231 writew(blksz, host->base + MMC_REG_BLK_LEN);
232 host->datasize = datasize;
234 if (!mxcmci_use_dma(host))
237 for_each_sg(data->sg, sg, data->sg_len, i) {
238 if (sg->offset & 3 || sg->length & 3) {
244 if (data->flags & MMC_DATA_READ) {
245 host->dma_dir = DMA_FROM_DEVICE;
246 slave_dirn = DMA_DEV_TO_MEM;
248 host->dma_dir = DMA_TO_DEVICE;
249 slave_dirn = DMA_MEM_TO_DEV;
252 nents = dma_map_sg(host->dma->device->dev, data->sg,
253 data->sg_len, host->dma_dir);
254 if (nents != data->sg_len)
257 host->desc = host->dma->device->device_prep_slave_sg(host->dma,
258 data->sg, data->sg_len, slave_dirn,
259 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
262 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len,
265 return 0; /* Fall back to PIO */
269 dmaengine_submit(host->desc);
270 dma_async_issue_pending(host->dma);
275 static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd,
278 u32 int_cntr = host->default_irq_mask;
281 WARN_ON(host->cmd != NULL);
284 switch (mmc_resp_type(cmd)) {
285 case MMC_RSP_R1: /* short CRC, OPCODE */
286 case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */
287 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC;
289 case MMC_RSP_R2: /* long 136 bit + CRC */
290 cmdat |= CMD_DAT_CONT_RESPONSE_136BIT;
292 case MMC_RSP_R3: /* short */
293 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT;
298 dev_err(mmc_dev(host->mmc), "unhandled response type 0x%x\n",
300 cmd->error = -EINVAL;
304 int_cntr = INT_END_CMD_RES_EN;
306 if (mxcmci_use_dma(host))
307 int_cntr |= INT_READ_OP_EN | INT_WRITE_OP_DONE_EN;
309 spin_lock_irqsave(&host->lock, flags);
311 int_cntr |= INT_SDIO_IRQ_EN;
312 writel(int_cntr, host->base + MMC_REG_INT_CNTR);
313 spin_unlock_irqrestore(&host->lock, flags);
315 writew(cmd->opcode, host->base + MMC_REG_CMD);
316 writel(cmd->arg, host->base + MMC_REG_ARG);
317 writew(cmdat, host->base + MMC_REG_CMD_DAT_CONT);
322 static void mxcmci_finish_request(struct mxcmci_host *host,
323 struct mmc_request *req)
325 u32 int_cntr = host->default_irq_mask;
328 spin_lock_irqsave(&host->lock, flags);
330 int_cntr |= INT_SDIO_IRQ_EN;
331 writel(int_cntr, host->base + MMC_REG_INT_CNTR);
332 spin_unlock_irqrestore(&host->lock, flags);
338 mmc_request_done(host->mmc, req);
341 static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat)
343 struct mmc_data *data = host->data;
346 if (mxcmci_use_dma(host)) {
347 dmaengine_terminate_all(host->dma);
348 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len,
352 if (stat & STATUS_ERR_MASK) {
353 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n",
355 if (stat & STATUS_CRC_READ_ERR) {
356 dev_err(mmc_dev(host->mmc), "%s: -EILSEQ\n", __func__);
357 data->error = -EILSEQ;
358 } else if (stat & STATUS_CRC_WRITE_ERR) {
359 u32 err_code = (stat >> 9) & 0x3;
360 if (err_code == 2) { /* No CRC response */
361 dev_err(mmc_dev(host->mmc),
362 "%s: No CRC -ETIMEDOUT\n", __func__);
363 data->error = -ETIMEDOUT;
365 dev_err(mmc_dev(host->mmc),
366 "%s: -EILSEQ\n", __func__);
367 data->error = -EILSEQ;
369 } else if (stat & STATUS_TIME_OUT_READ) {
370 dev_err(mmc_dev(host->mmc),
371 "%s: read -ETIMEDOUT\n", __func__);
372 data->error = -ETIMEDOUT;
374 dev_err(mmc_dev(host->mmc), "%s: -EIO\n", __func__);
378 data->bytes_xfered = host->datasize;
381 data_error = data->error;
388 static void mxcmci_read_response(struct mxcmci_host *host, unsigned int stat)
390 struct mmc_command *cmd = host->cmd;
397 if (stat & STATUS_TIME_OUT_RESP) {
398 dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n");
399 cmd->error = -ETIMEDOUT;
400 } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
401 dev_dbg(mmc_dev(host->mmc), "cmd crc error\n");
402 cmd->error = -EILSEQ;
405 if (cmd->flags & MMC_RSP_PRESENT) {
406 if (cmd->flags & MMC_RSP_136) {
407 for (i = 0; i < 4; i++) {
408 a = readw(host->base + MMC_REG_RES_FIFO);
409 b = readw(host->base + MMC_REG_RES_FIFO);
410 cmd->resp[i] = a << 16 | b;
413 a = readw(host->base + MMC_REG_RES_FIFO);
414 b = readw(host->base + MMC_REG_RES_FIFO);
415 c = readw(host->base + MMC_REG_RES_FIFO);
416 cmd->resp[0] = a << 24 | b << 8 | c >> 8;
421 static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask)
424 unsigned long timeout = jiffies + HZ;
427 stat = readl(host->base + MMC_REG_STATUS);
428 if (stat & STATUS_ERR_MASK)
430 if (time_after(jiffies, timeout)) {
431 mxcmci_softreset(host);
432 mxcmci_set_clk_rate(host, host->clock);
433 return STATUS_TIME_OUT_READ;
441 static int mxcmci_pull(struct mxcmci_host *host, void *_buf, int bytes)
447 stat = mxcmci_poll_status(host,
448 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
451 *buf++ = readl(host->base + MMC_REG_BUFFER_ACCESS);
459 stat = mxcmci_poll_status(host,
460 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
463 tmp = readl(host->base + MMC_REG_BUFFER_ACCESS);
464 memcpy(b, &tmp, bytes);
470 static int mxcmci_push(struct mxcmci_host *host, void *_buf, int bytes)
476 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
479 writel(*buf++, host->base + MMC_REG_BUFFER_ACCESS);
487 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
491 memcpy(&tmp, b, bytes);
492 writel(tmp, host->base + MMC_REG_BUFFER_ACCESS);
495 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
502 static int mxcmci_transfer_data(struct mxcmci_host *host)
504 struct mmc_data *data = host->req->data;
505 struct scatterlist *sg;
511 if (data->flags & MMC_DATA_READ) {
512 for_each_sg(data->sg, sg, data->sg_len, i) {
513 stat = mxcmci_pull(host, sg_virt(sg), sg->length);
516 host->datasize += sg->length;
519 for_each_sg(data->sg, sg, data->sg_len, i) {
520 stat = mxcmci_push(host, sg_virt(sg), sg->length);
523 host->datasize += sg->length;
525 stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE);
532 static void mxcmci_datawork(struct work_struct *work)
534 struct mxcmci_host *host = container_of(work, struct mxcmci_host,
536 int datastat = mxcmci_transfer_data(host);
538 writel(STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE,
539 host->base + MMC_REG_STATUS);
540 mxcmci_finish_data(host, datastat);
542 if (host->req->stop) {
543 if (mxcmci_start_cmd(host, host->req->stop, 0)) {
544 mxcmci_finish_request(host, host->req);
548 mxcmci_finish_request(host, host->req);
552 static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat)
554 struct mmc_data *data = host->data;
560 data_error = mxcmci_finish_data(host, stat);
562 mxcmci_read_response(host, stat);
565 if (host->req->stop) {
566 if (mxcmci_start_cmd(host, host->req->stop, 0)) {
567 mxcmci_finish_request(host, host->req);
571 mxcmci_finish_request(host, host->req);
575 static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat)
577 mxcmci_read_response(host, stat);
580 if (!host->data && host->req) {
581 mxcmci_finish_request(host, host->req);
585 /* For the DMA case the DMA engine handles the data transfer
586 * automatically. For non DMA we have to do it ourselves.
587 * Don't do it in interrupt context though.
589 if (!mxcmci_use_dma(host) && host->data)
590 schedule_work(&host->datawork);
594 static irqreturn_t mxcmci_irq(int irq, void *devid)
596 struct mxcmci_host *host = devid;
601 stat = readl(host->base + MMC_REG_STATUS);
602 writel(stat & ~(STATUS_SDIO_INT_ACTIVE | STATUS_DATA_TRANS_DONE |
603 STATUS_WRITE_OP_DONE), host->base + MMC_REG_STATUS);
605 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
607 spin_lock_irqsave(&host->lock, flags);
608 sdio_irq = (stat & STATUS_SDIO_INT_ACTIVE) && host->use_sdio;
609 spin_unlock_irqrestore(&host->lock, flags);
611 if (mxcmci_use_dma(host) &&
612 (stat & (STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE)))
613 writel(STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE,
614 host->base + MMC_REG_STATUS);
617 writel(STATUS_SDIO_INT_ACTIVE, host->base + MMC_REG_STATUS);
618 mmc_signal_sdio_irq(host->mmc);
621 if (stat & STATUS_END_CMD_RESP)
622 mxcmci_cmd_done(host, stat);
624 if (mxcmci_use_dma(host) &&
625 (stat & (STATUS_DATA_TRANS_DONE | STATUS_WRITE_OP_DONE)))
626 mxcmci_data_done(host, stat);
628 if (host->default_irq_mask &&
629 (stat & (STATUS_CARD_INSERTION | STATUS_CARD_REMOVAL)))
630 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
635 static void mxcmci_request(struct mmc_host *mmc, struct mmc_request *req)
637 struct mxcmci_host *host = mmc_priv(mmc);
638 unsigned int cmdat = host->cmdat;
641 WARN_ON(host->req != NULL);
644 host->cmdat &= ~CMD_DAT_CONT_INIT;
650 error = mxcmci_setup_data(host, req->data);
652 req->cmd->error = error;
657 cmdat |= CMD_DAT_CONT_DATA_ENABLE;
659 if (req->data->flags & MMC_DATA_WRITE)
660 cmdat |= CMD_DAT_CONT_WRITE;
663 error = mxcmci_start_cmd(host, req->cmd, cmdat);
667 mxcmci_finish_request(host, req);
670 static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios)
672 unsigned int divider;
674 unsigned int clk_in = clk_get_rate(host->clk);
676 while (prescaler <= 0x800) {
677 for (divider = 1; divider <= 0xF; divider++) {
680 x = (clk_in / (divider + 1));
683 x /= (prescaler * 2);
697 writew((prescaler << 4) | divider, host->base + MMC_REG_CLK_RATE);
699 dev_dbg(mmc_dev(host->mmc), "scaler: %d divider: %d in: %d out: %d\n",
700 prescaler, divider, clk_in, clk_ios);
703 static int mxcmci_setup_dma(struct mmc_host *mmc)
705 struct mxcmci_host *host = mmc_priv(mmc);
706 struct dma_slave_config *config = &host->dma_slave_config;
708 config->dst_addr = host->res->start + MMC_REG_BUFFER_ACCESS;
709 config->src_addr = host->res->start + MMC_REG_BUFFER_ACCESS;
710 config->dst_addr_width = 4;
711 config->src_addr_width = 4;
712 config->dst_maxburst = host->burstlen;
713 config->src_maxburst = host->burstlen;
715 return dmaengine_slave_config(host->dma, config);
718 static void mxcmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
720 struct mxcmci_host *host = mmc_priv(mmc);
724 * use burstlen of 64 (16 words) in 4 bit mode (--> reg value 0)
725 * use burstlen of 16 (4 words) in 1 bit mode (--> reg value 16)
727 if (ios->bus_width == MMC_BUS_WIDTH_4)
732 if (mxcmci_use_dma(host) && burstlen != host->burstlen) {
733 host->burstlen = burstlen;
734 ret = mxcmci_setup_dma(mmc);
736 dev_err(mmc_dev(host->mmc),
737 "failed to config DMA channel. Falling back to PIO\n");
738 dma_release_channel(host->dma);
744 if (ios->bus_width == MMC_BUS_WIDTH_4)
745 host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
747 host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4;
749 if (host->power_mode != ios->power_mode) {
750 mxcmci_set_power(host, ios->power_mode, ios->vdd);
751 host->power_mode = ios->power_mode;
753 if (ios->power_mode == MMC_POWER_ON)
754 host->cmdat |= CMD_DAT_CONT_INIT;
758 mxcmci_set_clk_rate(host, ios->clock);
759 writew(STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
761 writew(STR_STP_CLK_STOP_CLK, host->base + MMC_REG_STR_STP_CLK);
764 host->clock = ios->clock;
767 static irqreturn_t mxcmci_detect_irq(int irq, void *data)
769 struct mmc_host *mmc = data;
771 dev_dbg(mmc_dev(mmc), "%s\n", __func__);
773 mmc_detect_change(mmc, msecs_to_jiffies(250));
777 static int mxcmci_get_ro(struct mmc_host *mmc)
779 struct mxcmci_host *host = mmc_priv(mmc);
781 if (host->pdata && host->pdata->get_ro)
782 return !!host->pdata->get_ro(mmc_dev(mmc));
784 * Board doesn't support read only detection; let the mmc core
790 static void mxcmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
792 struct mxcmci_host *host = mmc_priv(mmc);
796 spin_lock_irqsave(&host->lock, flags);
797 host->use_sdio = enable;
798 int_cntr = readl(host->base + MMC_REG_INT_CNTR);
801 int_cntr |= INT_SDIO_IRQ_EN;
803 int_cntr &= ~INT_SDIO_IRQ_EN;
805 writel(int_cntr, host->base + MMC_REG_INT_CNTR);
806 spin_unlock_irqrestore(&host->lock, flags);
809 static void mxcmci_init_card(struct mmc_host *host, struct mmc_card *card)
812 * MX3 SoCs have a silicon bug which corrupts CRC calculation of
813 * multi-block transfers when connected SDIO peripheral doesn't
814 * drive the BUSY line as required by the specs.
815 * One way to prevent this is to only allow 1-bit transfers.
818 if (cpu_is_mx3() && card->type == MMC_TYPE_SDIO)
819 host->caps &= ~MMC_CAP_4_BIT_DATA;
821 host->caps |= MMC_CAP_4_BIT_DATA;
824 static bool filter(struct dma_chan *chan, void *param)
826 struct mxcmci_host *host = param;
828 if (!imx_dma_is_general_purpose(chan))
831 chan->private = &host->dma_data;
836 static const struct mmc_host_ops mxcmci_ops = {
837 .request = mxcmci_request,
838 .set_ios = mxcmci_set_ios,
839 .get_ro = mxcmci_get_ro,
840 .enable_sdio_irq = mxcmci_enable_sdio_irq,
841 .init_card = mxcmci_init_card,
844 static int mxcmci_probe(struct platform_device *pdev)
846 struct mmc_host *mmc;
847 struct mxcmci_host *host = NULL;
848 struct resource *iores, *r;
852 pr_info("i.MX SDHC driver\n");
854 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
855 irq = platform_get_irq(pdev, 0);
856 if (!iores || irq < 0)
859 r = request_mem_region(iores->start, resource_size(iores), pdev->name);
863 mmc = mmc_alloc_host(sizeof(struct mxcmci_host), &pdev->dev);
866 goto out_release_mem;
869 mmc->ops = &mxcmci_ops;
870 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
872 /* MMC core transfer sizes tunable parameters */
874 mmc->max_blk_size = 2048;
875 mmc->max_blk_count = 65535;
876 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
877 mmc->max_seg_size = mmc->max_req_size;
879 host = mmc_priv(mmc);
880 host->base = ioremap(r->start, resource_size(r));
887 host->pdata = pdev->dev.platform_data;
888 spin_lock_init(&host->lock);
890 mxcmci_init_ocr(host);
892 if (host->pdata && host->pdata->dat3_card_detect)
893 host->default_irq_mask =
894 INT_CARD_INSERTION_EN | INT_CARD_REMOVAL_EN;
896 host->default_irq_mask = 0;
901 host->clk = clk_get(&pdev->dev, NULL);
902 if (IS_ERR(host->clk)) {
903 ret = PTR_ERR(host->clk);
906 clk_enable(host->clk);
908 mxcmci_softreset(host);
910 host->rev_no = readw(host->base + MMC_REG_REV_NO);
911 if (host->rev_no != 0x400) {
913 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
918 mmc->f_min = clk_get_rate(host->clk) >> 16;
919 mmc->f_max = clk_get_rate(host->clk) >> 1;
921 /* recommended in data sheet */
922 writew(0x2db4, host->base + MMC_REG_READ_TO);
924 writel(host->default_irq_mask, host->base + MMC_REG_INT_CNTR);
926 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
928 host->dmareq = r->start;
929 host->dma_data.peripheral_type = IMX_DMATYPE_SDHC;
930 host->dma_data.priority = DMA_PRIO_LOW;
931 host->dma_data.dma_request = host->dmareq;
933 dma_cap_set(DMA_SLAVE, mask);
934 host->dma = dma_request_channel(mask, filter, host);
936 mmc->max_seg_size = dma_get_max_seg_size(
937 host->dma->device->dev);
941 dev_info(mmc_dev(host->mmc), "dma not available. Using PIO\n");
943 INIT_WORK(&host->datawork, mxcmci_datawork);
945 ret = request_irq(host->irq, mxcmci_irq, 0, DRIVER_NAME, host);
949 platform_set_drvdata(pdev, mmc);
951 if (host->pdata && host->pdata->init) {
952 ret = host->pdata->init(&pdev->dev, mxcmci_detect_irq,
963 free_irq(host->irq, host);
966 dma_release_channel(host->dma);
968 clk_disable(host->clk);
975 release_mem_region(iores->start, resource_size(iores));
979 static int mxcmci_remove(struct platform_device *pdev)
981 struct mmc_host *mmc = platform_get_drvdata(pdev);
982 struct mxcmci_host *host = mmc_priv(mmc);
984 platform_set_drvdata(pdev, NULL);
986 mmc_remove_host(mmc);
989 regulator_put(host->vcc);
991 if (host->pdata && host->pdata->exit)
992 host->pdata->exit(&pdev->dev, mmc);
994 free_irq(host->irq, host);
998 dma_release_channel(host->dma);
1000 clk_disable(host->clk);
1003 release_mem_region(host->res->start, resource_size(host->res));
1011 static int mxcmci_suspend(struct device *dev)
1013 struct mmc_host *mmc = dev_get_drvdata(dev);
1014 struct mxcmci_host *host = mmc_priv(mmc);
1018 ret = mmc_suspend_host(mmc);
1019 clk_disable(host->clk);
1024 static int mxcmci_resume(struct device *dev)
1026 struct mmc_host *mmc = dev_get_drvdata(dev);
1027 struct mxcmci_host *host = mmc_priv(mmc);
1030 clk_enable(host->clk);
1032 ret = mmc_resume_host(mmc);
1037 static const struct dev_pm_ops mxcmci_pm_ops = {
1038 .suspend = mxcmci_suspend,
1039 .resume = mxcmci_resume,
1043 static struct platform_driver mxcmci_driver = {
1044 .probe = mxcmci_probe,
1045 .remove = mxcmci_remove,
1047 .name = DRIVER_NAME,
1048 .owner = THIS_MODULE,
1050 .pm = &mxcmci_pm_ops,
1055 module_platform_driver(mxcmci_driver);
1057 MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver");
1058 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1059 MODULE_LICENSE("GPL");
1060 MODULE_ALIAS("platform:imx-mmc");