2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
5 * Copyright (C) 2010 ST-Ericsson SA
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/device.h>
16 #include <linux/interrupt.h>
17 #include <linux/kernel.h>
18 #include <linux/slab.h>
19 #include <linux/delay.h>
20 #include <linux/err.h>
21 #include <linux/highmem.h>
22 #include <linux/log2.h>
23 #include <linux/mmc/pm.h>
24 #include <linux/mmc/host.h>
25 #include <linux/mmc/card.h>
26 #include <linux/amba/bus.h>
27 #include <linux/clk.h>
28 #include <linux/scatterlist.h>
29 #include <linux/gpio.h>
30 #include <linux/of_gpio.h>
31 #include <linux/regulator/consumer.h>
32 #include <linux/dmaengine.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/amba/mmci.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/types.h>
37 #include <linux/pinctrl/consumer.h>
39 #include <asm/div64.h>
41 #include <asm/sizes.h>
45 #define DRIVER_NAME "mmci-pl18x"
47 static unsigned int fmax = 515633;
50 * struct variant_data - MMCI variant-specific quirks
51 * @clkreg: default value for MCICLOCK register
52 * @clkreg_enable: enable value for MMCICLOCK register
53 * @datalength_bits: number of bits in the MMCIDATALENGTH register
54 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
55 * is asserted (likewise for RX)
56 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
57 * is asserted (likewise for RX)
58 * @sdio: variant supports SDIO
59 * @st_clkdiv: true if using a ST-specific clock divider algorithm
60 * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register
61 * @pwrreg_powerup: power up value for MMCIPOWER register
62 * @signal_direction: input/out direction of bus signals can be indicated
63 * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock
67 unsigned int clkreg_enable;
68 unsigned int datalength_bits;
69 unsigned int fifosize;
70 unsigned int fifohalfsize;
73 bool blksz_datactrl16;
75 bool signal_direction;
79 static struct variant_data variant_arm = {
81 .fifohalfsize = 8 * 4,
82 .datalength_bits = 16,
83 .pwrreg_powerup = MCI_PWR_UP,
86 static struct variant_data variant_arm_extended_fifo = {
88 .fifohalfsize = 64 * 4,
89 .datalength_bits = 16,
90 .pwrreg_powerup = MCI_PWR_UP,
93 static struct variant_data variant_arm_extended_fifo_hwfc = {
95 .fifohalfsize = 64 * 4,
96 .clkreg_enable = MCI_ARM_HWFCEN,
97 .datalength_bits = 16,
98 .pwrreg_powerup = MCI_PWR_UP,
101 static struct variant_data variant_u300 = {
103 .fifohalfsize = 8 * 4,
104 .clkreg_enable = MCI_ST_U300_HWFCEN,
105 .datalength_bits = 16,
107 .pwrreg_powerup = MCI_PWR_ON,
108 .signal_direction = true,
109 .pwrreg_clkgate = true,
112 static struct variant_data variant_nomadik = {
114 .fifohalfsize = 8 * 4,
115 .clkreg = MCI_CLK_ENABLE,
116 .datalength_bits = 24,
119 .pwrreg_powerup = MCI_PWR_ON,
120 .signal_direction = true,
121 .pwrreg_clkgate = true,
124 static struct variant_data variant_ux500 = {
126 .fifohalfsize = 8 * 4,
127 .clkreg = MCI_CLK_ENABLE,
128 .clkreg_enable = MCI_ST_UX500_HWFCEN,
129 .datalength_bits = 24,
132 .pwrreg_powerup = MCI_PWR_ON,
133 .signal_direction = true,
134 .pwrreg_clkgate = true,
137 static struct variant_data variant_ux500v2 = {
139 .fifohalfsize = 8 * 4,
140 .clkreg = MCI_CLK_ENABLE,
141 .clkreg_enable = MCI_ST_UX500_HWFCEN,
142 .datalength_bits = 24,
145 .blksz_datactrl16 = true,
146 .pwrreg_powerup = MCI_PWR_ON,
147 .signal_direction = true,
148 .pwrreg_clkgate = true,
152 * Validate mmc prerequisites
154 static int mmci_validate_data(struct mmci_host *host,
155 struct mmc_data *data)
160 if (!is_power_of_2(data->blksz)) {
161 dev_err(mmc_dev(host->mmc),
162 "unsupported block size (%d bytes)\n", data->blksz);
170 * This must be called with host->lock held
172 static void mmci_write_clkreg(struct mmci_host *host, u32 clk)
174 if (host->clk_reg != clk) {
176 writel(clk, host->base + MMCICLOCK);
181 * This must be called with host->lock held
183 static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr)
185 if (host->pwr_reg != pwr) {
187 writel(pwr, host->base + MMCIPOWER);
192 * This must be called with host->lock held
194 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
196 struct variant_data *variant = host->variant;
197 u32 clk = variant->clkreg;
199 /* Make sure cclk reflects the current calculated clock */
203 if (desired >= host->mclk) {
204 clk = MCI_CLK_BYPASS;
205 if (variant->st_clkdiv)
206 clk |= MCI_ST_UX500_NEG_EDGE;
207 host->cclk = host->mclk;
208 } else if (variant->st_clkdiv) {
210 * DB8500 TRM says f = mclk / (clkdiv + 2)
211 * => clkdiv = (mclk / f) - 2
212 * Round the divider up so we don't exceed the max
215 clk = DIV_ROUND_UP(host->mclk, desired) - 2;
218 host->cclk = host->mclk / (clk + 2);
221 * PL180 TRM says f = mclk / (2 * (clkdiv + 1))
222 * => clkdiv = mclk / (2 * f) - 1
224 clk = host->mclk / (2 * desired) - 1;
227 host->cclk = host->mclk / (2 * (clk + 1));
230 clk |= variant->clkreg_enable;
231 clk |= MCI_CLK_ENABLE;
232 /* This hasn't proven to be worthwhile */
233 /* clk |= MCI_CLK_PWRSAVE; */
236 /* Set actual clock for debug */
237 host->mmc->actual_clock = host->cclk;
239 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
241 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
242 clk |= MCI_ST_8BIT_BUS;
244 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50)
245 clk |= MCI_ST_UX500_NEG_EDGE;
247 mmci_write_clkreg(host, clk);
251 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
253 writel(0, host->base + MMCICOMMAND);
260 mmc_request_done(host->mmc, mrq);
262 pm_runtime_mark_last_busy(mmc_dev(host->mmc));
263 pm_runtime_put_autosuspend(mmc_dev(host->mmc));
266 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
268 void __iomem *base = host->base;
270 if (host->singleirq) {
271 unsigned int mask0 = readl(base + MMCIMASK0);
273 mask0 &= ~MCI_IRQ1MASK;
276 writel(mask0, base + MMCIMASK0);
279 writel(mask, base + MMCIMASK1);
282 static void mmci_stop_data(struct mmci_host *host)
284 writel(0, host->base + MMCIDATACTRL);
285 mmci_set_mask1(host, 0);
289 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
291 unsigned int flags = SG_MITER_ATOMIC;
293 if (data->flags & MMC_DATA_READ)
294 flags |= SG_MITER_TO_SG;
296 flags |= SG_MITER_FROM_SG;
298 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
302 * All the DMA operation mode stuff goes inside this ifdef.
303 * This assumes that you have a generic DMA device interface,
304 * no custom DMA interfaces are supported.
306 #ifdef CONFIG_DMA_ENGINE
307 static void mmci_dma_setup(struct mmci_host *host)
309 struct mmci_platform_data *plat = host->plat;
310 const char *rxname, *txname;
313 if (!plat || !plat->dma_filter) {
314 dev_info(mmc_dev(host->mmc), "no DMA platform data\n");
318 /* initialize pre request cookie */
319 host->next_data.cookie = 1;
321 /* Try to acquire a generic DMA engine slave channel */
323 dma_cap_set(DMA_SLAVE, mask);
326 * If only an RX channel is specified, the driver will
327 * attempt to use it bidirectionally, however if it is
328 * is specified but cannot be located, DMA will be disabled.
330 if (plat->dma_rx_param) {
331 host->dma_rx_channel = dma_request_channel(mask,
334 /* E.g if no DMA hardware is present */
335 if (!host->dma_rx_channel)
336 dev_err(mmc_dev(host->mmc), "no RX DMA channel\n");
339 if (plat->dma_tx_param) {
340 host->dma_tx_channel = dma_request_channel(mask,
343 if (!host->dma_tx_channel)
344 dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n");
346 host->dma_tx_channel = host->dma_rx_channel;
349 if (host->dma_rx_channel)
350 rxname = dma_chan_name(host->dma_rx_channel);
354 if (host->dma_tx_channel)
355 txname = dma_chan_name(host->dma_tx_channel);
359 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n",
363 * Limit the maximum segment size in any SG entry according to
364 * the parameters of the DMA engine device.
366 if (host->dma_tx_channel) {
367 struct device *dev = host->dma_tx_channel->device->dev;
368 unsigned int max_seg_size = dma_get_max_seg_size(dev);
370 if (max_seg_size < host->mmc->max_seg_size)
371 host->mmc->max_seg_size = max_seg_size;
373 if (host->dma_rx_channel) {
374 struct device *dev = host->dma_rx_channel->device->dev;
375 unsigned int max_seg_size = dma_get_max_seg_size(dev);
377 if (max_seg_size < host->mmc->max_seg_size)
378 host->mmc->max_seg_size = max_seg_size;
383 * This is used in or so inline it
384 * so it can be discarded.
386 static inline void mmci_dma_release(struct mmci_host *host)
388 struct mmci_platform_data *plat = host->plat;
390 if (host->dma_rx_channel)
391 dma_release_channel(host->dma_rx_channel);
392 if (host->dma_tx_channel && plat->dma_tx_param)
393 dma_release_channel(host->dma_tx_channel);
394 host->dma_rx_channel = host->dma_tx_channel = NULL;
397 static void mmci_dma_data_error(struct mmci_host *host)
399 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n");
400 dmaengine_terminate_all(host->dma_current);
401 host->dma_current = NULL;
402 host->dma_desc_current = NULL;
403 host->data->host_cookie = 0;
406 static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
408 struct dma_chan *chan;
409 enum dma_data_direction dir;
411 if (data->flags & MMC_DATA_READ) {
412 dir = DMA_FROM_DEVICE;
413 chan = host->dma_rx_channel;
416 chan = host->dma_tx_channel;
419 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir);
422 static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data)
427 /* Wait up to 1ms for the DMA to complete */
429 status = readl(host->base + MMCISTATUS);
430 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100)
436 * Check to see whether we still have some data left in the FIFO -
437 * this catches DMA controllers which are unable to monitor the
438 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non-
439 * contiguous buffers. On TX, we'll get a FIFO underrun error.
441 if (status & MCI_RXDATAAVLBLMASK) {
442 mmci_dma_data_error(host);
447 if (!data->host_cookie)
448 mmci_dma_unmap(host, data);
451 * Use of DMA with scatter-gather is impossible.
452 * Give up with DMA and switch back to PIO mode.
454 if (status & MCI_RXDATAAVLBLMASK) {
455 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n");
456 mmci_dma_release(host);
459 host->dma_current = NULL;
460 host->dma_desc_current = NULL;
463 /* prepares DMA channel and DMA descriptor, returns non-zero on failure */
464 static int __mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data,
465 struct dma_chan **dma_chan,
466 struct dma_async_tx_descriptor **dma_desc)
468 struct variant_data *variant = host->variant;
469 struct dma_slave_config conf = {
470 .src_addr = host->phybase + MMCIFIFO,
471 .dst_addr = host->phybase + MMCIFIFO,
472 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
473 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
474 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */
475 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */
478 struct dma_chan *chan;
479 struct dma_device *device;
480 struct dma_async_tx_descriptor *desc;
481 enum dma_data_direction buffer_dirn;
484 if (data->flags & MMC_DATA_READ) {
485 conf.direction = DMA_DEV_TO_MEM;
486 buffer_dirn = DMA_FROM_DEVICE;
487 chan = host->dma_rx_channel;
489 conf.direction = DMA_MEM_TO_DEV;
490 buffer_dirn = DMA_TO_DEVICE;
491 chan = host->dma_tx_channel;
494 /* If there's no DMA channel, fall back to PIO */
498 /* If less than or equal to the fifo size, don't bother with DMA */
499 if (data->blksz * data->blocks <= variant->fifosize)
502 device = chan->device;
503 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn);
507 dmaengine_slave_config(chan, &conf);
508 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg,
509 conf.direction, DMA_CTRL_ACK);
519 dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn);
523 static inline int mmci_dma_prep_data(struct mmci_host *host,
524 struct mmc_data *data)
526 /* Check if next job is already prepared. */
527 if (host->dma_current && host->dma_desc_current)
530 /* No job were prepared thus do it now. */
531 return __mmci_dma_prep_data(host, data, &host->dma_current,
532 &host->dma_desc_current);
535 static inline int mmci_dma_prep_next(struct mmci_host *host,
536 struct mmc_data *data)
538 struct mmci_host_next *nd = &host->next_data;
539 return __mmci_dma_prep_data(host, data, &nd->dma_chan, &nd->dma_desc);
542 static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
545 struct mmc_data *data = host->data;
547 ret = mmci_dma_prep_data(host, host->data);
551 /* Okay, go for it. */
552 dev_vdbg(mmc_dev(host->mmc),
553 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n",
554 data->sg_len, data->blksz, data->blocks, data->flags);
555 dmaengine_submit(host->dma_desc_current);
556 dma_async_issue_pending(host->dma_current);
558 datactrl |= MCI_DPSM_DMAENABLE;
560 /* Trigger the DMA transfer */
561 writel(datactrl, host->base + MMCIDATACTRL);
564 * Let the MMCI say when the data is ended and it's time
565 * to fire next DMA request. When that happens, MMCI will
566 * call mmci_data_end()
568 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK,
569 host->base + MMCIMASK0);
573 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
575 struct mmci_host_next *next = &host->next_data;
577 WARN_ON(data->host_cookie && data->host_cookie != next->cookie);
578 WARN_ON(!data->host_cookie && (next->dma_desc || next->dma_chan));
580 host->dma_desc_current = next->dma_desc;
581 host->dma_current = next->dma_chan;
582 next->dma_desc = NULL;
583 next->dma_chan = NULL;
586 static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq,
589 struct mmci_host *host = mmc_priv(mmc);
590 struct mmc_data *data = mrq->data;
591 struct mmci_host_next *nd = &host->next_data;
596 BUG_ON(data->host_cookie);
598 if (mmci_validate_data(host, data))
601 if (!mmci_dma_prep_next(host, data))
602 data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie;
605 static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq,
608 struct mmci_host *host = mmc_priv(mmc);
609 struct mmc_data *data = mrq->data;
611 if (!data || !data->host_cookie)
614 mmci_dma_unmap(host, data);
617 struct mmci_host_next *next = &host->next_data;
618 struct dma_chan *chan;
619 if (data->flags & MMC_DATA_READ)
620 chan = host->dma_rx_channel;
622 chan = host->dma_tx_channel;
623 dmaengine_terminate_all(chan);
625 next->dma_desc = NULL;
626 next->dma_chan = NULL;
631 /* Blank functions if the DMA engine is not available */
632 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
635 static inline void mmci_dma_setup(struct mmci_host *host)
639 static inline void mmci_dma_release(struct mmci_host *host)
643 static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
647 static inline void mmci_dma_finalize(struct mmci_host *host,
648 struct mmc_data *data)
652 static inline void mmci_dma_data_error(struct mmci_host *host)
656 static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
661 #define mmci_pre_request NULL
662 #define mmci_post_request NULL
666 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
668 struct variant_data *variant = host->variant;
669 unsigned int datactrl, timeout, irqmask;
670 unsigned long long clks;
674 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n",
675 data->blksz, data->blocks, data->flags);
678 host->size = data->blksz * data->blocks;
679 data->bytes_xfered = 0;
681 clks = (unsigned long long)data->timeout_ns * host->cclk;
682 do_div(clks, 1000000000UL);
684 timeout = data->timeout_clks + (unsigned int)clks;
687 writel(timeout, base + MMCIDATATIMER);
688 writel(host->size, base + MMCIDATALENGTH);
690 blksz_bits = ffs(data->blksz) - 1;
691 BUG_ON(1 << blksz_bits != data->blksz);
693 if (variant->blksz_datactrl16)
694 datactrl = MCI_DPSM_ENABLE | (data->blksz << 16);
696 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4;
698 if (data->flags & MMC_DATA_READ)
699 datactrl |= MCI_DPSM_DIRECTION;
701 /* The ST Micro variants has a special bit to enable SDIO */
702 if (variant->sdio && host->mmc->card)
703 if (mmc_card_sdio(host->mmc->card)) {
705 * The ST Micro variants has a special bit
710 datactrl |= MCI_ST_DPSM_SDIOEN;
713 * The ST Micro variant for SDIO small write transfers
714 * needs to have clock H/W flow control disabled,
715 * otherwise the transfer will not start. The threshold
716 * depends on the rate of MCLK.
718 if (data->flags & MMC_DATA_WRITE &&
720 (host->size <= 8 && host->mclk > 50000000)))
721 clk = host->clk_reg & ~variant->clkreg_enable;
723 clk = host->clk_reg | variant->clkreg_enable;
725 mmci_write_clkreg(host, clk);
728 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50)
729 datactrl |= MCI_ST_DPSM_DDRMODE;
732 * Attempt to use DMA operation mode, if this
733 * should fail, fall back to PIO mode
735 if (!mmci_dma_start_data(host, datactrl))
738 /* IRQ mode, map the SG list for CPU reading/writing */
739 mmci_init_sg(host, data);
741 if (data->flags & MMC_DATA_READ) {
742 irqmask = MCI_RXFIFOHALFFULLMASK;
745 * If we have less than the fifo 'half-full' threshold to
746 * transfer, trigger a PIO interrupt as soon as any data
749 if (host->size < variant->fifohalfsize)
750 irqmask |= MCI_RXDATAAVLBLMASK;
753 * We don't actually need to include "FIFO empty" here
754 * since its implicit in "FIFO half empty".
756 irqmask = MCI_TXFIFOHALFEMPTYMASK;
759 writel(datactrl, base + MMCIDATACTRL);
760 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
761 mmci_set_mask1(host, irqmask);
765 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
767 void __iomem *base = host->base;
769 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
770 cmd->opcode, cmd->arg, cmd->flags);
772 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
773 writel(0, base + MMCICOMMAND);
777 c |= cmd->opcode | MCI_CPSM_ENABLE;
778 if (cmd->flags & MMC_RSP_PRESENT) {
779 if (cmd->flags & MMC_RSP_136)
780 c |= MCI_CPSM_LONGRSP;
781 c |= MCI_CPSM_RESPONSE;
784 c |= MCI_CPSM_INTERRUPT;
788 writel(cmd->arg, base + MMCIARGUMENT);
789 writel(c, base + MMCICOMMAND);
793 mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
796 /* First check for errors */
797 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR|
798 MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
801 /* Terminate the DMA transfer */
802 if (dma_inprogress(host)) {
803 mmci_dma_data_error(host);
804 mmci_dma_unmap(host, data);
808 * Calculate how far we are into the transfer. Note that
809 * the data counter gives the number of bytes transferred
810 * on the MMC bus, not on the host side. On reads, this
811 * can be as much as a FIFO-worth of data ahead. This
812 * matters for FIFO overruns only.
814 remain = readl(host->base + MMCIDATACNT);
815 success = data->blksz * data->blocks - remain;
817 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n",
819 if (status & MCI_DATACRCFAIL) {
820 /* Last block was not successful */
822 data->error = -EILSEQ;
823 } else if (status & MCI_DATATIMEOUT) {
824 data->error = -ETIMEDOUT;
825 } else if (status & MCI_STARTBITERR) {
826 data->error = -ECOMM;
827 } else if (status & MCI_TXUNDERRUN) {
829 } else if (status & MCI_RXOVERRUN) {
830 if (success > host->variant->fifosize)
831 success -= host->variant->fifosize;
836 data->bytes_xfered = round_down(success, data->blksz);
839 if (status & MCI_DATABLOCKEND)
840 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n");
842 if (status & MCI_DATAEND || data->error) {
843 if (dma_inprogress(host))
844 mmci_dma_finalize(host, data);
845 mmci_stop_data(host);
848 /* The error clause is handled above, success! */
849 data->bytes_xfered = data->blksz * data->blocks;
852 mmci_request_end(host, data->mrq);
854 mmci_start_command(host, data->stop, 0);
860 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
863 void __iomem *base = host->base;
867 if (status & MCI_CMDTIMEOUT) {
868 cmd->error = -ETIMEDOUT;
869 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
870 cmd->error = -EILSEQ;
872 cmd->resp[0] = readl(base + MMCIRESPONSE0);
873 cmd->resp[1] = readl(base + MMCIRESPONSE1);
874 cmd->resp[2] = readl(base + MMCIRESPONSE2);
875 cmd->resp[3] = readl(base + MMCIRESPONSE3);
878 if (!cmd->data || cmd->error) {
880 /* Terminate the DMA transfer */
881 if (dma_inprogress(host)) {
882 mmci_dma_data_error(host);
883 mmci_dma_unmap(host, host->data);
885 mmci_stop_data(host);
887 mmci_request_end(host, cmd->mrq);
888 } else if (!(cmd->data->flags & MMC_DATA_READ)) {
889 mmci_start_data(host, cmd->data);
893 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
895 void __iomem *base = host->base;
898 int host_remain = host->size;
901 int count = host_remain - (readl(base + MMCIFIFOCNT) << 2);
910 * SDIO especially may want to send something that is
911 * not divisible by 4 (as opposed to card sectors
912 * etc). Therefore make sure to always read the last bytes
913 * while only doing full 32-bit reads towards the FIFO.
915 if (unlikely(count & 0x3)) {
917 unsigned char buf[4];
918 ioread32_rep(base + MMCIFIFO, buf, 1);
919 memcpy(ptr, buf, count);
921 ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
925 ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
930 host_remain -= count;
935 status = readl(base + MMCISTATUS);
936 } while (status & MCI_RXDATAAVLBL);
941 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
943 struct variant_data *variant = host->variant;
944 void __iomem *base = host->base;
948 unsigned int count, maxcnt;
950 maxcnt = status & MCI_TXFIFOEMPTY ?
951 variant->fifosize : variant->fifohalfsize;
952 count = min(remain, maxcnt);
955 * SDIO especially may want to send something that is
956 * not divisible by 4 (as opposed to card sectors
957 * etc), and the FIFO only accept full 32-bit writes.
958 * So compensate by adding +3 on the count, a single
959 * byte become a 32bit write, 7 bytes will be two
962 iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2);
970 status = readl(base + MMCISTATUS);
971 } while (status & MCI_TXFIFOHALFEMPTY);
977 * PIO data transfer IRQ handler.
979 static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
981 struct mmci_host *host = dev_id;
982 struct sg_mapping_iter *sg_miter = &host->sg_miter;
983 struct variant_data *variant = host->variant;
984 void __iomem *base = host->base;
988 status = readl(base + MMCISTATUS);
990 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
992 local_irq_save(flags);
995 unsigned int remain, len;
999 * For write, we only need to test the half-empty flag
1000 * here - if the FIFO is completely empty, then by
1001 * definition it is more than half empty.
1003 * For read, check for data available.
1005 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
1008 if (!sg_miter_next(sg_miter))
1011 buffer = sg_miter->addr;
1012 remain = sg_miter->length;
1015 if (status & MCI_RXACTIVE)
1016 len = mmci_pio_read(host, buffer, remain);
1017 if (status & MCI_TXACTIVE)
1018 len = mmci_pio_write(host, buffer, remain, status);
1020 sg_miter->consumed = len;
1028 status = readl(base + MMCISTATUS);
1031 sg_miter_stop(sg_miter);
1033 local_irq_restore(flags);
1036 * If we have less than the fifo 'half-full' threshold to transfer,
1037 * trigger a PIO interrupt as soon as any data is available.
1039 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize)
1040 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK);
1043 * If we run out of data, disable the data IRQs; this
1044 * prevents a race where the FIFO becomes empty before
1045 * the chip itself has disabled the data path, and
1046 * stops us racing with our data end IRQ.
1048 if (host->size == 0) {
1049 mmci_set_mask1(host, 0);
1050 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
1057 * Handle completion of command and data transfers.
1059 static irqreturn_t mmci_irq(int irq, void *dev_id)
1061 struct mmci_host *host = dev_id;
1065 spin_lock(&host->lock);
1068 struct mmc_command *cmd;
1069 struct mmc_data *data;
1071 status = readl(host->base + MMCISTATUS);
1073 if (host->singleirq) {
1074 if (status & readl(host->base + MMCIMASK1))
1075 mmci_pio_irq(irq, dev_id);
1077 status &= ~MCI_IRQ1MASK;
1080 status &= readl(host->base + MMCIMASK0);
1081 writel(status, host->base + MMCICLEAR);
1083 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
1086 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR|
1087 MCI_TXUNDERRUN|MCI_RXOVERRUN|MCI_DATAEND|
1088 MCI_DATABLOCKEND) && data)
1089 mmci_data_irq(host, data, status);
1092 if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd)
1093 mmci_cmd_irq(host, cmd, status);
1098 spin_unlock(&host->lock);
1100 return IRQ_RETVAL(ret);
1103 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1105 struct mmci_host *host = mmc_priv(mmc);
1106 unsigned long flags;
1108 WARN_ON(host->mrq != NULL);
1110 mrq->cmd->error = mmci_validate_data(host, mrq->data);
1111 if (mrq->cmd->error) {
1112 mmc_request_done(mmc, mrq);
1116 pm_runtime_get_sync(mmc_dev(mmc));
1118 spin_lock_irqsave(&host->lock, flags);
1123 mmci_get_next_data(host, mrq->data);
1125 if (mrq->data && mrq->data->flags & MMC_DATA_READ)
1126 mmci_start_data(host, mrq->data);
1128 mmci_start_command(host, mrq->cmd, 0);
1130 spin_unlock_irqrestore(&host->lock, flags);
1133 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1135 struct mmci_host *host = mmc_priv(mmc);
1136 struct variant_data *variant = host->variant;
1138 unsigned long flags;
1141 pm_runtime_get_sync(mmc_dev(mmc));
1143 if (host->plat->ios_handler &&
1144 host->plat->ios_handler(mmc_dev(mmc), ios))
1145 dev_err(mmc_dev(mmc), "platform ios_handler failed\n");
1147 switch (ios->power_mode) {
1149 if (!IS_ERR(mmc->supply.vmmc))
1150 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1152 if (!IS_ERR(mmc->supply.vqmmc) &&
1153 regulator_is_enabled(mmc->supply.vqmmc))
1154 regulator_disable(mmc->supply.vqmmc);
1158 if (!IS_ERR(mmc->supply.vmmc))
1159 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
1162 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP
1163 * and instead uses MCI_PWR_ON so apply whatever value is
1164 * configured in the variant data.
1166 pwr |= variant->pwrreg_powerup;
1170 if (!IS_ERR(mmc->supply.vqmmc) &&
1171 !regulator_is_enabled(mmc->supply.vqmmc)) {
1172 ret = regulator_enable(mmc->supply.vqmmc);
1174 dev_err(mmc_dev(mmc),
1175 "failed to enable vqmmc regulator\n");
1182 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) {
1184 * The ST Micro variant has some additional bits
1185 * indicating signal direction for the signals in
1186 * the SD/MMC bus and feedback-clock usage.
1188 pwr |= host->plat->sigdir;
1190 if (ios->bus_width == MMC_BUS_WIDTH_4)
1191 pwr &= ~MCI_ST_DATA74DIREN;
1192 else if (ios->bus_width == MMC_BUS_WIDTH_1)
1193 pwr &= (~MCI_ST_DATA74DIREN &
1194 ~MCI_ST_DATA31DIREN &
1195 ~MCI_ST_DATA2DIREN);
1198 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
1199 if (host->hw_designer != AMBA_VENDOR_ST)
1203 * The ST Micro variant use the ROD bit for something
1204 * else and only has OD (Open Drain).
1211 * If clock = 0 and the variant requires the MMCIPOWER to be used for
1212 * gating the clock, the MCI_PWR_ON bit is cleared.
1214 if (!ios->clock && variant->pwrreg_clkgate)
1217 spin_lock_irqsave(&host->lock, flags);
1219 mmci_set_clkreg(host, ios->clock);
1220 mmci_write_pwrreg(host, pwr);
1222 spin_unlock_irqrestore(&host->lock, flags);
1224 pm_runtime_mark_last_busy(mmc_dev(mmc));
1225 pm_runtime_put_autosuspend(mmc_dev(mmc));
1228 static int mmci_get_ro(struct mmc_host *mmc)
1230 struct mmci_host *host = mmc_priv(mmc);
1232 if (host->gpio_wp == -ENOSYS)
1235 return gpio_get_value_cansleep(host->gpio_wp);
1238 static int mmci_get_cd(struct mmc_host *mmc)
1240 struct mmci_host *host = mmc_priv(mmc);
1241 struct mmci_platform_data *plat = host->plat;
1242 unsigned int status;
1244 if (host->gpio_cd == -ENOSYS) {
1246 return 1; /* Assume always present */
1248 status = plat->status(mmc_dev(host->mmc));
1250 status = !!gpio_get_value_cansleep(host->gpio_cd)
1254 * Use positive logic throughout - status is zero for no card,
1255 * non-zero for card inserted.
1260 static irqreturn_t mmci_cd_irq(int irq, void *dev_id)
1262 struct mmci_host *host = dev_id;
1264 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
1269 static const struct mmc_host_ops mmci_ops = {
1270 .request = mmci_request,
1271 .pre_req = mmci_pre_request,
1272 .post_req = mmci_post_request,
1273 .set_ios = mmci_set_ios,
1274 .get_ro = mmci_get_ro,
1275 .get_cd = mmci_get_cd,
1279 static void mmci_dt_populate_generic_pdata(struct device_node *np,
1280 struct mmci_platform_data *pdata)
1284 pdata->gpio_wp = of_get_named_gpio(np, "wp-gpios", 0);
1285 pdata->gpio_cd = of_get_named_gpio(np, "cd-gpios", 0);
1287 if (of_get_property(np, "cd-inverted", NULL))
1288 pdata->cd_invert = true;
1290 pdata->cd_invert = false;
1292 of_property_read_u32(np, "max-frequency", &pdata->f_max);
1294 pr_warn("%s has no 'max-frequency' property\n", np->full_name);
1296 if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL))
1297 pdata->capabilities |= MMC_CAP_MMC_HIGHSPEED;
1298 if (of_get_property(np, "mmc-cap-sd-highspeed", NULL))
1299 pdata->capabilities |= MMC_CAP_SD_HIGHSPEED;
1301 of_property_read_u32(np, "bus-width", &bus_width);
1302 switch (bus_width) {
1304 /* No bus-width supplied. */
1307 pdata->capabilities |= MMC_CAP_4_BIT_DATA;
1310 pdata->capabilities |= MMC_CAP_8_BIT_DATA;
1313 pr_warn("%s: Unsupported bus width\n", np->full_name);
1317 static void mmci_dt_populate_generic_pdata(struct device_node *np,
1318 struct mmci_platform_data *pdata)
1324 static int mmci_probe(struct amba_device *dev,
1325 const struct amba_id *id)
1327 struct mmci_platform_data *plat = dev->dev.platform_data;
1328 struct device_node *np = dev->dev.of_node;
1329 struct variant_data *variant = id->data;
1330 struct mmci_host *host;
1331 struct mmc_host *mmc;
1334 /* Must have platform data or Device Tree. */
1336 dev_err(&dev->dev, "No plat data or DT found\n");
1341 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL);
1347 mmci_dt_populate_generic_pdata(np, plat);
1349 ret = amba_request_regions(dev, DRIVER_NAME);
1353 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
1359 host = mmc_priv(mmc);
1362 host->gpio_wp = -ENOSYS;
1363 host->gpio_cd = -ENOSYS;
1364 host->gpio_cd_irq = -1;
1366 host->hw_designer = amba_manf(dev);
1367 host->hw_revision = amba_rev(dev);
1368 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
1369 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
1371 host->clk = devm_clk_get(&dev->dev, NULL);
1372 if (IS_ERR(host->clk)) {
1373 ret = PTR_ERR(host->clk);
1377 ret = clk_prepare_enable(host->clk);
1382 host->variant = variant;
1383 host->mclk = clk_get_rate(host->clk);
1385 * According to the spec, mclk is max 100 MHz,
1386 * so we try to adjust the clock down to this,
1389 if (host->mclk > 100000000) {
1390 ret = clk_set_rate(host->clk, 100000000);
1393 host->mclk = clk_get_rate(host->clk);
1394 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n",
1397 host->phybase = dev->res.start;
1398 host->base = ioremap(dev->res.start, resource_size(&dev->res));
1404 mmc->ops = &mmci_ops;
1406 * The ARM and ST versions of the block have slightly different
1407 * clock divider equations which means that the minimum divider
1410 if (variant->st_clkdiv)
1411 mmc->f_min = DIV_ROUND_UP(host->mclk, 257);
1413 mmc->f_min = DIV_ROUND_UP(host->mclk, 512);
1415 * If the platform data supplies a maximum operating
1416 * frequency, this takes precedence. Else, we fall back
1417 * to using the module parameter, which has a (low)
1418 * default value in case it is not specified. Either
1419 * value must not exceed the clock rate into the block,
1423 mmc->f_max = min(host->mclk, plat->f_max);
1425 mmc->f_max = min(host->mclk, fmax);
1426 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);
1428 host->pinctrl = devm_pinctrl_get(&dev->dev);
1429 if (IS_ERR(host->pinctrl)) {
1430 ret = PTR_ERR(host->pinctrl);
1434 host->pins_default = pinctrl_lookup_state(host->pinctrl,
1435 PINCTRL_STATE_DEFAULT);
1437 /* enable pins to be muxed in and configured */
1438 if (!IS_ERR(host->pins_default)) {
1439 ret = pinctrl_select_state(host->pinctrl, host->pins_default);
1441 dev_warn(&dev->dev, "could not set default pins\n");
1443 dev_warn(&dev->dev, "could not get default pinstate\n");
1445 /* Get regulators and the supported OCR mask */
1446 mmc_regulator_get_supply(mmc);
1447 if (!mmc->ocr_avail)
1448 mmc->ocr_avail = plat->ocr_mask;
1449 else if (plat->ocr_mask)
1450 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n");
1452 mmc->caps = plat->capabilities;
1453 mmc->caps2 = plat->capabilities2;
1455 /* We support these PM capabilities. */
1456 mmc->pm_caps = MMC_PM_KEEP_POWER;
1461 mmc->max_segs = NR_SG;
1464 * Since only a certain number of bits are valid in the data length
1465 * register, we must ensure that we don't exceed 2^num-1 bytes in a
1468 mmc->max_req_size = (1 << variant->datalength_bits) - 1;
1471 * Set the maximum segment size. Since we aren't doing DMA
1472 * (yet) we are only limited by the data length register.
1474 mmc->max_seg_size = mmc->max_req_size;
1477 * Block size can be up to 2048 bytes, but must be a power of two.
1479 mmc->max_blk_size = 1 << 11;
1482 * Limit the number of blocks transferred so that we don't overflow
1483 * the maximum request size.
1485 mmc->max_blk_count = mmc->max_req_size >> 11;
1487 spin_lock_init(&host->lock);
1489 writel(0, host->base + MMCIMASK0);
1490 writel(0, host->base + MMCIMASK1);
1491 writel(0xfff, host->base + MMCICLEAR);
1493 if (plat->gpio_cd == -EPROBE_DEFER) {
1494 ret = -EPROBE_DEFER;
1497 if (gpio_is_valid(plat->gpio_cd)) {
1498 ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)");
1500 ret = gpio_direction_input(plat->gpio_cd);
1502 host->gpio_cd = plat->gpio_cd;
1503 else if (ret != -ENOSYS)
1507 * A gpio pin that will detect cards when inserted and removed
1508 * will most likely want to trigger on the edges if it is
1509 * 0 when ejected and 1 when inserted (or mutatis mutandis
1510 * for the inverted case) so we request triggers on both
1513 ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd),
1515 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
1516 DRIVER_NAME " (cd)", host);
1518 host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd);
1520 if (plat->gpio_wp == -EPROBE_DEFER) {
1521 ret = -EPROBE_DEFER;
1524 if (gpio_is_valid(plat->gpio_wp)) {
1525 ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)");
1527 ret = gpio_direction_input(plat->gpio_wp);
1529 host->gpio_wp = plat->gpio_wp;
1530 else if (ret != -ENOSYS)
1534 if ((host->plat->status || host->gpio_cd != -ENOSYS)
1535 && host->gpio_cd_irq < 0)
1536 mmc->caps |= MMC_CAP_NEEDS_POLL;
1538 ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host);
1543 host->singleirq = true;
1545 ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED,
1546 DRIVER_NAME " (pio)", host);
1551 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1553 amba_set_drvdata(dev, mmc);
1555 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n",
1556 mmc_hostname(mmc), amba_part(dev), amba_manf(dev),
1557 amba_rev(dev), (unsigned long long)dev->res.start,
1558 dev->irq[0], dev->irq[1]);
1560 mmci_dma_setup(host);
1562 pm_runtime_set_autosuspend_delay(&dev->dev, 50);
1563 pm_runtime_use_autosuspend(&dev->dev);
1564 pm_runtime_put(&dev->dev);
1571 free_irq(dev->irq[0], host);
1573 if (host->gpio_wp != -ENOSYS)
1574 gpio_free(host->gpio_wp);
1576 if (host->gpio_cd_irq >= 0)
1577 free_irq(host->gpio_cd_irq, host);
1578 if (host->gpio_cd != -ENOSYS)
1579 gpio_free(host->gpio_cd);
1581 iounmap(host->base);
1583 clk_disable_unprepare(host->clk);
1587 amba_release_regions(dev);
1592 static int mmci_remove(struct amba_device *dev)
1594 struct mmc_host *mmc = amba_get_drvdata(dev);
1596 amba_set_drvdata(dev, NULL);
1599 struct mmci_host *host = mmc_priv(mmc);
1602 * Undo pm_runtime_put() in probe. We use the _sync
1603 * version here so that we can access the primecell.
1605 pm_runtime_get_sync(&dev->dev);
1607 mmc_remove_host(mmc);
1609 writel(0, host->base + MMCIMASK0);
1610 writel(0, host->base + MMCIMASK1);
1612 writel(0, host->base + MMCICOMMAND);
1613 writel(0, host->base + MMCIDATACTRL);
1615 mmci_dma_release(host);
1616 free_irq(dev->irq[0], host);
1617 if (!host->singleirq)
1618 free_irq(dev->irq[1], host);
1620 if (host->gpio_wp != -ENOSYS)
1621 gpio_free(host->gpio_wp);
1622 if (host->gpio_cd_irq >= 0)
1623 free_irq(host->gpio_cd_irq, host);
1624 if (host->gpio_cd != -ENOSYS)
1625 gpio_free(host->gpio_cd);
1627 iounmap(host->base);
1628 clk_disable_unprepare(host->clk);
1632 amba_release_regions(dev);
1638 #ifdef CONFIG_SUSPEND
1639 static int mmci_suspend(struct device *dev)
1641 struct amba_device *adev = to_amba_device(dev);
1642 struct mmc_host *mmc = amba_get_drvdata(adev);
1646 struct mmci_host *host = mmc_priv(mmc);
1648 ret = mmc_suspend_host(mmc);
1650 pm_runtime_get_sync(dev);
1651 writel(0, host->base + MMCIMASK0);
1658 static int mmci_resume(struct device *dev)
1660 struct amba_device *adev = to_amba_device(dev);
1661 struct mmc_host *mmc = amba_get_drvdata(adev);
1665 struct mmci_host *host = mmc_priv(mmc);
1667 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1668 pm_runtime_put(dev);
1670 ret = mmc_resume_host(mmc);
1677 #ifdef CONFIG_PM_RUNTIME
1678 static int mmci_runtime_suspend(struct device *dev)
1680 struct amba_device *adev = to_amba_device(dev);
1681 struct mmc_host *mmc = amba_get_drvdata(adev);
1684 struct mmci_host *host = mmc_priv(mmc);
1685 clk_disable_unprepare(host->clk);
1691 static int mmci_runtime_resume(struct device *dev)
1693 struct amba_device *adev = to_amba_device(dev);
1694 struct mmc_host *mmc = amba_get_drvdata(adev);
1697 struct mmci_host *host = mmc_priv(mmc);
1698 clk_prepare_enable(host->clk);
1705 static const struct dev_pm_ops mmci_dev_pm_ops = {
1706 SET_SYSTEM_SLEEP_PM_OPS(mmci_suspend, mmci_resume)
1707 SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL)
1710 static struct amba_id mmci_ids[] = {
1714 .data = &variant_arm,
1719 .data = &variant_arm_extended_fifo,
1724 .data = &variant_arm_extended_fifo_hwfc,
1729 .data = &variant_arm,
1731 /* ST Micro variants */
1735 .data = &variant_u300,
1740 .data = &variant_nomadik,
1745 .data = &variant_u300,
1750 .data = &variant_ux500,
1755 .data = &variant_ux500v2,
1760 MODULE_DEVICE_TABLE(amba, mmci_ids);
1762 static struct amba_driver mmci_driver = {
1764 .name = DRIVER_NAME,
1765 .pm = &mmci_dev_pm_ops,
1767 .probe = mmci_probe,
1768 .remove = mmci_remove,
1769 .id_table = mmci_ids,
1772 module_amba_driver(mmci_driver);
1774 module_param(fmax, uint, 0444);
1776 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
1777 MODULE_LICENSE("GPL");