2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
5 * Copyright (C) 2010 ST-Ericsson SA
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/device.h>
17 #include <linux/interrupt.h>
18 #include <linux/kernel.h>
19 #include <linux/slab.h>
20 #include <linux/delay.h>
21 #include <linux/err.h>
22 #include <linux/highmem.h>
23 #include <linux/log2.h>
24 #include <linux/mmc/pm.h>
25 #include <linux/mmc/host.h>
26 #include <linux/mmc/card.h>
27 #include <linux/mmc/slot-gpio.h>
28 #include <linux/amba/bus.h>
29 #include <linux/clk.h>
30 #include <linux/scatterlist.h>
32 #include <linux/regulator/consumer.h>
33 #include <linux/dmaengine.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/amba/mmci.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/types.h>
38 #include <linux/pinctrl/consumer.h>
40 #include <asm/div64.h>
44 #include "mmci_qcom_dml.h"
46 #define DRIVER_NAME "mmci-pl18x"
48 #ifdef CONFIG_DMA_ENGINE
49 void mmci_variant_init(struct mmci_host *host);
51 static inline void mmci_variant_init(struct mmci_host *host) {}
54 static unsigned int fmax = 515633;
56 static struct variant_data variant_arm = {
58 .fifohalfsize = 8 * 4,
59 .datalength_bits = 16,
60 .datactrl_blocksz = 11,
61 .pwrreg_powerup = MCI_PWR_UP,
63 .reversed_irq_handling = true,
65 .start_err = MCI_STARTBITERR,
67 .init = mmci_variant_init,
70 static struct variant_data variant_arm_extended_fifo = {
72 .fifohalfsize = 64 * 4,
73 .datalength_bits = 16,
74 .datactrl_blocksz = 11,
75 .pwrreg_powerup = MCI_PWR_UP,
78 .start_err = MCI_STARTBITERR,
80 .init = mmci_variant_init,
83 static struct variant_data variant_arm_extended_fifo_hwfc = {
85 .fifohalfsize = 64 * 4,
86 .clkreg_enable = MCI_ARM_HWFCEN,
87 .datalength_bits = 16,
88 .datactrl_blocksz = 11,
89 .pwrreg_powerup = MCI_PWR_UP,
92 .start_err = MCI_STARTBITERR,
94 .init = mmci_variant_init,
97 static struct variant_data variant_u300 = {
99 .fifohalfsize = 8 * 4,
100 .clkreg_enable = MCI_ST_U300_HWFCEN,
101 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
102 .datalength_bits = 16,
103 .datactrl_blocksz = 11,
104 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
106 .pwrreg_powerup = MCI_PWR_ON,
108 .signal_direction = true,
109 .pwrreg_clkgate = true,
110 .pwrreg_nopower = true,
112 .start_err = MCI_STARTBITERR,
114 .init = mmci_variant_init,
117 static struct variant_data variant_nomadik = {
119 .fifohalfsize = 8 * 4,
120 .clkreg = MCI_CLK_ENABLE,
121 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
122 .datalength_bits = 24,
123 .datactrl_blocksz = 11,
124 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
127 .pwrreg_powerup = MCI_PWR_ON,
129 .signal_direction = true,
130 .pwrreg_clkgate = true,
131 .pwrreg_nopower = true,
133 .start_err = MCI_STARTBITERR,
135 .init = mmci_variant_init,
138 static struct variant_data variant_ux500 = {
140 .fifohalfsize = 8 * 4,
141 .clkreg = MCI_CLK_ENABLE,
142 .clkreg_enable = MCI_ST_UX500_HWFCEN,
143 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
144 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
145 .datalength_bits = 24,
146 .datactrl_blocksz = 11,
147 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
150 .pwrreg_powerup = MCI_PWR_ON,
152 .signal_direction = true,
153 .pwrreg_clkgate = true,
155 .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE,
156 .busy_detect_flag = MCI_ST_CARDBUSY,
157 .busy_detect_mask = MCI_ST_BUSYENDMASK,
158 .pwrreg_nopower = true,
160 .start_err = MCI_STARTBITERR,
162 .init = mmci_variant_init,
165 static struct variant_data variant_ux500v2 = {
167 .fifohalfsize = 8 * 4,
168 .clkreg = MCI_CLK_ENABLE,
169 .clkreg_enable = MCI_ST_UX500_HWFCEN,
170 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
171 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
172 .datactrl_mask_ddrmode = MCI_DPSM_ST_DDRMODE,
173 .datalength_bits = 24,
174 .datactrl_blocksz = 11,
175 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
178 .blksz_datactrl16 = true,
179 .pwrreg_powerup = MCI_PWR_ON,
181 .signal_direction = true,
182 .pwrreg_clkgate = true,
184 .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE,
185 .busy_detect_flag = MCI_ST_CARDBUSY,
186 .busy_detect_mask = MCI_ST_BUSYENDMASK,
187 .pwrreg_nopower = true,
189 .start_err = MCI_STARTBITERR,
191 .init = mmci_variant_init,
194 static struct variant_data variant_stm32 = {
196 .fifohalfsize = 8 * 4,
197 .clkreg = MCI_CLK_ENABLE,
198 .clkreg_enable = MCI_ST_UX500_HWFCEN,
199 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
200 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
201 .datalength_bits = 24,
202 .datactrl_blocksz = 11,
203 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
206 .pwrreg_powerup = MCI_PWR_ON,
208 .pwrreg_clkgate = true,
209 .pwrreg_nopower = true,
210 .init = mmci_variant_init,
213 static struct variant_data variant_qcom = {
215 .fifohalfsize = 8 * 4,
216 .clkreg = MCI_CLK_ENABLE,
217 .clkreg_enable = MCI_QCOM_CLK_FLOWENA |
218 MCI_QCOM_CLK_SELECT_IN_FBCLK,
219 .clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8,
220 .datactrl_mask_ddrmode = MCI_QCOM_CLK_SELECT_IN_DDR_MODE,
221 .data_cmd_enable = MCI_CPSM_QCOM_DATCMD,
222 .blksz_datactrl4 = true,
223 .datalength_bits = 24,
224 .datactrl_blocksz = 11,
225 .pwrreg_powerup = MCI_PWR_UP,
227 .explicit_mclk_control = true,
231 .start_err = MCI_STARTBITERR,
232 .opendrain = MCI_ROD,
233 .init = qcom_variant_init,
236 /* Busy detection for the ST Micro variant */
237 static int mmci_card_busy(struct mmc_host *mmc)
239 struct mmci_host *host = mmc_priv(mmc);
243 spin_lock_irqsave(&host->lock, flags);
244 if (readl(host->base + MMCISTATUS) & host->variant->busy_detect_flag)
246 spin_unlock_irqrestore(&host->lock, flags);
251 static void mmci_reg_delay(struct mmci_host *host)
254 * According to the spec, at least three feedback clock cycles
255 * of max 52 MHz must pass between two writes to the MMCICLOCK reg.
256 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes.
257 * Worst delay time during card init is at 100 kHz => 30 us.
258 * Worst delay time when up and running is at 25 MHz => 120 ns.
260 if (host->cclk < 25000000)
267 * This must be called with host->lock held
269 void mmci_write_clkreg(struct mmci_host *host, u32 clk)
271 if (host->clk_reg != clk) {
273 writel(clk, host->base + MMCICLOCK);
278 * This must be called with host->lock held
280 void mmci_write_pwrreg(struct mmci_host *host, u32 pwr)
282 if (host->pwr_reg != pwr) {
284 writel(pwr, host->base + MMCIPOWER);
289 * This must be called with host->lock held
291 static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl)
293 /* Keep busy mode in DPSM if enabled */
294 datactrl |= host->datactrl_reg & host->variant->busy_dpsm_flag;
296 if (host->datactrl_reg != datactrl) {
297 host->datactrl_reg = datactrl;
298 writel(datactrl, host->base + MMCIDATACTRL);
303 * This must be called with host->lock held
305 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
307 struct variant_data *variant = host->variant;
308 u32 clk = variant->clkreg;
310 /* Make sure cclk reflects the current calculated clock */
314 if (variant->explicit_mclk_control) {
315 host->cclk = host->mclk;
316 } else if (desired >= host->mclk) {
317 clk = MCI_CLK_BYPASS;
318 if (variant->st_clkdiv)
319 clk |= MCI_ST_UX500_NEG_EDGE;
320 host->cclk = host->mclk;
321 } else if (variant->st_clkdiv) {
323 * DB8500 TRM says f = mclk / (clkdiv + 2)
324 * => clkdiv = (mclk / f) - 2
325 * Round the divider up so we don't exceed the max
328 clk = DIV_ROUND_UP(host->mclk, desired) - 2;
331 host->cclk = host->mclk / (clk + 2);
334 * PL180 TRM says f = mclk / (2 * (clkdiv + 1))
335 * => clkdiv = mclk / (2 * f) - 1
337 clk = host->mclk / (2 * desired) - 1;
340 host->cclk = host->mclk / (2 * (clk + 1));
343 clk |= variant->clkreg_enable;
344 clk |= MCI_CLK_ENABLE;
345 /* This hasn't proven to be worthwhile */
346 /* clk |= MCI_CLK_PWRSAVE; */
349 /* Set actual clock for debug */
350 host->mmc->actual_clock = host->cclk;
352 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
354 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
355 clk |= variant->clkreg_8bit_bus_enable;
357 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
358 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
359 clk |= variant->clkreg_neg_edge_enable;
361 mmci_write_clkreg(host, clk);
364 void mmci_dma_release(struct mmci_host *host)
366 if (host->ops && host->ops->dma_release)
367 host->ops->dma_release(host);
369 host->use_dma = false;
372 void mmci_dma_setup(struct mmci_host *host)
374 if (!host->ops || !host->ops->dma_setup)
377 if (host->ops->dma_setup(host))
380 /* initialize pre request cookie */
381 host->next_cookie = 1;
383 host->use_dma = true;
387 * Validate mmc prerequisites
389 static int mmci_validate_data(struct mmci_host *host,
390 struct mmc_data *data)
395 if (!is_power_of_2(data->blksz)) {
396 dev_err(mmc_dev(host->mmc),
397 "unsupported block size (%d bytes)\n", data->blksz);
401 if (host->ops && host->ops->validate_data)
402 return host->ops->validate_data(host, data);
407 int mmci_prep_data(struct mmci_host *host, struct mmc_data *data, bool next)
411 if (!host->ops || !host->ops->prep_data)
414 err = host->ops->prep_data(host, data, next);
417 data->host_cookie = ++host->next_cookie < 0 ?
418 1 : host->next_cookie;
423 void mmci_unprep_data(struct mmci_host *host, struct mmc_data *data,
426 if (host->ops && host->ops->unprep_data)
427 host->ops->unprep_data(host, data, err);
429 data->host_cookie = 0;
432 void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
434 WARN_ON(data->host_cookie && data->host_cookie != host->next_cookie);
436 if (host->ops && host->ops->get_next_data)
437 host->ops->get_next_data(host, data);
440 int mmci_dma_start(struct mmci_host *host, unsigned int datactrl)
442 struct mmc_data *data = host->data;
448 ret = mmci_prep_data(host, data, false);
452 if (!host->ops || !host->ops->dma_start)
455 /* Okay, go for it. */
456 dev_vdbg(mmc_dev(host->mmc),
457 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n",
458 data->sg_len, data->blksz, data->blocks, data->flags);
460 host->ops->dma_start(host, &datactrl);
462 /* Trigger the DMA transfer */
463 mmci_write_datactrlreg(host, datactrl);
466 * Let the MMCI say when the data is ended and it's time
467 * to fire next DMA request. When that happens, MMCI will
468 * call mmci_data_end()
470 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK,
471 host->base + MMCIMASK0);
475 void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data)
480 if (host->ops && host->ops->dma_finalize)
481 host->ops->dma_finalize(host, data);
484 void mmci_dma_error(struct mmci_host *host)
489 if (host->ops && host->ops->dma_error)
490 host->ops->dma_error(host);
494 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
496 writel(0, host->base + MMCICOMMAND);
503 mmc_request_done(host->mmc, mrq);
506 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
508 void __iomem *base = host->base;
509 struct variant_data *variant = host->variant;
511 if (host->singleirq) {
512 unsigned int mask0 = readl(base + MMCIMASK0);
514 mask0 &= ~MCI_IRQ1MASK;
517 writel(mask0, base + MMCIMASK0);
520 if (variant->mmcimask1)
521 writel(mask, base + MMCIMASK1);
523 host->mask1_reg = mask;
526 static void mmci_stop_data(struct mmci_host *host)
528 mmci_write_datactrlreg(host, 0);
529 mmci_set_mask1(host, 0);
533 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
535 unsigned int flags = SG_MITER_ATOMIC;
537 if (data->flags & MMC_DATA_READ)
538 flags |= SG_MITER_TO_SG;
540 flags |= SG_MITER_FROM_SG;
542 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
546 * All the DMA operation mode stuff goes inside this ifdef.
547 * This assumes that you have a generic DMA device interface,
548 * no custom DMA interfaces are supported.
550 #ifdef CONFIG_DMA_ENGINE
551 struct mmci_dmae_next {
552 struct dma_async_tx_descriptor *desc;
553 struct dma_chan *chan;
556 struct mmci_dmae_priv {
557 struct dma_chan *cur;
558 struct dma_chan *rx_channel;
559 struct dma_chan *tx_channel;
560 struct dma_async_tx_descriptor *desc_current;
561 struct mmci_dmae_next next_data;
564 int mmci_dmae_setup(struct mmci_host *host)
566 const char *rxname, *txname;
567 struct mmci_dmae_priv *dmae;
569 dmae = devm_kzalloc(mmc_dev(host->mmc), sizeof(*dmae), GFP_KERNEL);
573 host->dma_priv = dmae;
575 dmae->rx_channel = dma_request_slave_channel(mmc_dev(host->mmc),
577 dmae->tx_channel = dma_request_slave_channel(mmc_dev(host->mmc),
581 * If only an RX channel is specified, the driver will
582 * attempt to use it bidirectionally, however if it is
583 * is specified but cannot be located, DMA will be disabled.
585 if (dmae->rx_channel && !dmae->tx_channel)
586 dmae->tx_channel = dmae->rx_channel;
588 if (dmae->rx_channel)
589 rxname = dma_chan_name(dmae->rx_channel);
593 if (dmae->tx_channel)
594 txname = dma_chan_name(dmae->tx_channel);
598 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n",
602 * Limit the maximum segment size in any SG entry according to
603 * the parameters of the DMA engine device.
605 if (dmae->tx_channel) {
606 struct device *dev = dmae->tx_channel->device->dev;
607 unsigned int max_seg_size = dma_get_max_seg_size(dev);
609 if (max_seg_size < host->mmc->max_seg_size)
610 host->mmc->max_seg_size = max_seg_size;
612 if (dmae->rx_channel) {
613 struct device *dev = dmae->rx_channel->device->dev;
614 unsigned int max_seg_size = dma_get_max_seg_size(dev);
616 if (max_seg_size < host->mmc->max_seg_size)
617 host->mmc->max_seg_size = max_seg_size;
620 if (!dmae->tx_channel || !dmae->rx_channel) {
621 mmci_dmae_release(host);
629 * This is used in or so inline it
630 * so it can be discarded.
632 void mmci_dmae_release(struct mmci_host *host)
634 struct mmci_dmae_priv *dmae = host->dma_priv;
636 if (dmae->rx_channel)
637 dma_release_channel(dmae->rx_channel);
638 if (dmae->tx_channel)
639 dma_release_channel(dmae->tx_channel);
640 dmae->rx_channel = dmae->tx_channel = NULL;
643 static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
645 struct mmci_dmae_priv *dmae = host->dma_priv;
646 struct dma_chan *chan;
648 if (data->flags & MMC_DATA_READ)
649 chan = dmae->rx_channel;
651 chan = dmae->tx_channel;
653 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len,
654 mmc_get_dma_dir(data));
657 void mmci_dmae_error(struct mmci_host *host)
659 struct mmci_dmae_priv *dmae = host->dma_priv;
661 if (!dma_inprogress(host))
664 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n");
665 dmaengine_terminate_all(dmae->cur);
666 host->dma_in_progress = false;
668 dmae->desc_current = NULL;
669 host->data->host_cookie = 0;
671 mmci_dma_unmap(host, host->data);
674 void mmci_dmae_finalize(struct mmci_host *host, struct mmc_data *data)
676 struct mmci_dmae_priv *dmae = host->dma_priv;
680 if (!dma_inprogress(host))
683 /* Wait up to 1ms for the DMA to complete */
685 status = readl(host->base + MMCISTATUS);
686 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100)
692 * Check to see whether we still have some data left in the FIFO -
693 * this catches DMA controllers which are unable to monitor the
694 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non-
695 * contiguous buffers. On TX, we'll get a FIFO underrun error.
697 if (status & MCI_RXDATAAVLBLMASK) {
698 mmci_dma_error(host);
701 } else if (!data->host_cookie) {
702 mmci_dma_unmap(host, data);
706 * Use of DMA with scatter-gather is impossible.
707 * Give up with DMA and switch back to PIO mode.
709 if (status & MCI_RXDATAAVLBLMASK) {
710 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n");
711 mmci_dma_release(host);
714 host->dma_in_progress = false;
716 dmae->desc_current = NULL;
719 /* prepares DMA channel and DMA descriptor, returns non-zero on failure */
720 static int _mmci_dmae_prep_data(struct mmci_host *host, struct mmc_data *data,
721 struct dma_chan **dma_chan,
722 struct dma_async_tx_descriptor **dma_desc)
724 struct mmci_dmae_priv *dmae = host->dma_priv;
725 struct variant_data *variant = host->variant;
726 struct dma_slave_config conf = {
727 .src_addr = host->phybase + MMCIFIFO,
728 .dst_addr = host->phybase + MMCIFIFO,
729 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
730 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
731 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */
732 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */
735 struct dma_chan *chan;
736 struct dma_device *device;
737 struct dma_async_tx_descriptor *desc;
739 unsigned long flags = DMA_CTRL_ACK;
741 if (data->flags & MMC_DATA_READ) {
742 conf.direction = DMA_DEV_TO_MEM;
743 chan = dmae->rx_channel;
745 conf.direction = DMA_MEM_TO_DEV;
746 chan = dmae->tx_channel;
749 /* If there's no DMA channel, fall back to PIO */
753 /* If less than or equal to the fifo size, don't bother with DMA */
754 if (data->blksz * data->blocks <= variant->fifosize)
757 device = chan->device;
758 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len,
759 mmc_get_dma_dir(data));
763 if (host->variant->qcom_dml)
764 flags |= DMA_PREP_INTERRUPT;
766 dmaengine_slave_config(chan, &conf);
767 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg,
768 conf.direction, flags);
778 dma_unmap_sg(device->dev, data->sg, data->sg_len,
779 mmc_get_dma_dir(data));
783 int mmci_dmae_prep_data(struct mmci_host *host,
784 struct mmc_data *data,
787 struct mmci_dmae_priv *dmae = host->dma_priv;
788 struct mmci_dmae_next *nd = &dmae->next_data;
794 return _mmci_dmae_prep_data(host, data, &nd->chan, &nd->desc);
795 /* Check if next job is already prepared. */
796 if (dmae->cur && dmae->desc_current)
799 /* No job were prepared thus do it now. */
800 return _mmci_dmae_prep_data(host, data, &dmae->cur,
801 &dmae->desc_current);
804 int mmci_dmae_start(struct mmci_host *host, unsigned int *datactrl)
806 struct mmci_dmae_priv *dmae = host->dma_priv;
807 struct mmc_data *data = host->data;
809 host->dma_in_progress = true;
810 dmaengine_submit(dmae->desc_current);
811 dma_async_issue_pending(dmae->cur);
813 if (host->variant->qcom_dml)
814 dml_start_xfer(host, data);
816 *datactrl |= MCI_DPSM_DMAENABLE;
821 void mmci_dmae_get_next_data(struct mmci_host *host, struct mmc_data *data)
823 struct mmci_dmae_priv *dmae = host->dma_priv;
824 struct mmci_dmae_next *next = &dmae->next_data;
829 WARN_ON(!data->host_cookie && (next->desc || next->chan));
831 dmae->desc_current = next->desc;
832 dmae->cur = next->chan;
837 void mmci_dmae_unprep_data(struct mmci_host *host,
838 struct mmc_data *data, int err)
841 struct mmci_dmae_priv *dmae = host->dma_priv;
846 mmci_dma_unmap(host, data);
849 struct mmci_dmae_next *next = &dmae->next_data;
850 struct dma_chan *chan;
851 if (data->flags & MMC_DATA_READ)
852 chan = dmae->rx_channel;
854 chan = dmae->tx_channel;
855 dmaengine_terminate_all(chan);
857 if (dmae->desc_current == next->desc)
858 dmae->desc_current = NULL;
860 if (dmae->cur == next->chan) {
861 host->dma_in_progress = false;
870 static struct mmci_host_ops mmci_variant_ops = {
871 .prep_data = mmci_dmae_prep_data,
872 .unprep_data = mmci_dmae_unprep_data,
873 .get_next_data = mmci_dmae_get_next_data,
874 .dma_setup = mmci_dmae_setup,
875 .dma_release = mmci_dmae_release,
876 .dma_start = mmci_dmae_start,
877 .dma_finalize = mmci_dmae_finalize,
878 .dma_error = mmci_dmae_error,
881 void mmci_variant_init(struct mmci_host *host)
883 host->ops = &mmci_variant_ops;
887 static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq)
889 struct mmci_host *host = mmc_priv(mmc);
890 struct mmc_data *data = mrq->data;
895 WARN_ON(data->host_cookie);
897 if (mmci_validate_data(host, data))
900 mmci_prep_data(host, data, true);
903 static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq,
906 struct mmci_host *host = mmc_priv(mmc);
907 struct mmc_data *data = mrq->data;
909 if (!data || !data->host_cookie)
912 mmci_unprep_data(host, data, err);
915 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
917 struct variant_data *variant = host->variant;
918 unsigned int datactrl, timeout, irqmask;
919 unsigned long long clks;
923 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n",
924 data->blksz, data->blocks, data->flags);
927 host->size = data->blksz * data->blocks;
928 data->bytes_xfered = 0;
930 clks = (unsigned long long)data->timeout_ns * host->cclk;
931 do_div(clks, NSEC_PER_SEC);
933 timeout = data->timeout_clks + (unsigned int)clks;
936 writel(timeout, base + MMCIDATATIMER);
937 writel(host->size, base + MMCIDATALENGTH);
939 blksz_bits = ffs(data->blksz) - 1;
940 BUG_ON(1 << blksz_bits != data->blksz);
942 if (variant->blksz_datactrl16)
943 datactrl = MCI_DPSM_ENABLE | (data->blksz << 16);
944 else if (variant->blksz_datactrl4)
945 datactrl = MCI_DPSM_ENABLE | (data->blksz << 4);
947 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4;
949 if (data->flags & MMC_DATA_READ)
950 datactrl |= MCI_DPSM_DIRECTION;
952 if (host->mmc->card && mmc_card_sdio(host->mmc->card)) {
955 datactrl |= variant->datactrl_mask_sdio;
958 * The ST Micro variant for SDIO small write transfers
959 * needs to have clock H/W flow control disabled,
960 * otherwise the transfer will not start. The threshold
961 * depends on the rate of MCLK.
963 if (variant->st_sdio && data->flags & MMC_DATA_WRITE &&
965 (host->size <= 8 && host->mclk > 50000000)))
966 clk = host->clk_reg & ~variant->clkreg_enable;
968 clk = host->clk_reg | variant->clkreg_enable;
970 mmci_write_clkreg(host, clk);
973 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
974 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
975 datactrl |= variant->datactrl_mask_ddrmode;
978 * Attempt to use DMA operation mode, if this
979 * should fail, fall back to PIO mode
981 if (!mmci_dma_start(host, datactrl))
984 /* IRQ mode, map the SG list for CPU reading/writing */
985 mmci_init_sg(host, data);
987 if (data->flags & MMC_DATA_READ) {
988 irqmask = MCI_RXFIFOHALFFULLMASK;
991 * If we have less than the fifo 'half-full' threshold to
992 * transfer, trigger a PIO interrupt as soon as any data
995 if (host->size < variant->fifohalfsize)
996 irqmask |= MCI_RXDATAAVLBLMASK;
999 * We don't actually need to include "FIFO empty" here
1000 * since its implicit in "FIFO half empty".
1002 irqmask = MCI_TXFIFOHALFEMPTYMASK;
1005 mmci_write_datactrlreg(host, datactrl);
1006 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
1007 mmci_set_mask1(host, irqmask);
1011 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
1013 void __iomem *base = host->base;
1015 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
1016 cmd->opcode, cmd->arg, cmd->flags);
1018 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
1019 writel(0, base + MMCICOMMAND);
1020 mmci_reg_delay(host);
1023 c |= cmd->opcode | MCI_CPSM_ENABLE;
1024 if (cmd->flags & MMC_RSP_PRESENT) {
1025 if (cmd->flags & MMC_RSP_136)
1026 c |= MCI_CPSM_LONGRSP;
1027 c |= MCI_CPSM_RESPONSE;
1030 c |= MCI_CPSM_INTERRUPT;
1032 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC)
1033 c |= host->variant->data_cmd_enable;
1037 writel(cmd->arg, base + MMCIARGUMENT);
1038 writel(c, base + MMCICOMMAND);
1042 mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
1043 unsigned int status)
1045 /* Make sure we have data to handle */
1049 /* First check for errors */
1050 if (status & (MCI_DATACRCFAIL | MCI_DATATIMEOUT |
1051 host->variant->start_err |
1052 MCI_TXUNDERRUN | MCI_RXOVERRUN)) {
1053 u32 remain, success;
1055 /* Terminate the DMA transfer */
1056 mmci_dma_error(host);
1059 * Calculate how far we are into the transfer. Note that
1060 * the data counter gives the number of bytes transferred
1061 * on the MMC bus, not on the host side. On reads, this
1062 * can be as much as a FIFO-worth of data ahead. This
1063 * matters for FIFO overruns only.
1065 remain = readl(host->base + MMCIDATACNT);
1066 success = data->blksz * data->blocks - remain;
1068 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n",
1070 if (status & MCI_DATACRCFAIL) {
1071 /* Last block was not successful */
1073 data->error = -EILSEQ;
1074 } else if (status & MCI_DATATIMEOUT) {
1075 data->error = -ETIMEDOUT;
1076 } else if (status & MCI_STARTBITERR) {
1077 data->error = -ECOMM;
1078 } else if (status & MCI_TXUNDERRUN) {
1080 } else if (status & MCI_RXOVERRUN) {
1081 if (success > host->variant->fifosize)
1082 success -= host->variant->fifosize;
1087 data->bytes_xfered = round_down(success, data->blksz);
1090 if (status & MCI_DATABLOCKEND)
1091 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n");
1093 if (status & MCI_DATAEND || data->error) {
1094 mmci_dma_finalize(host, data);
1096 mmci_stop_data(host);
1099 /* The error clause is handled above, success! */
1100 data->bytes_xfered = data->blksz * data->blocks;
1102 if (!data->stop || host->mrq->sbc) {
1103 mmci_request_end(host, data->mrq);
1105 mmci_start_command(host, data->stop, 0);
1111 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
1112 unsigned int status)
1114 void __iomem *base = host->base;
1120 sbc = (cmd == host->mrq->sbc);
1123 * We need to be one of these interrupts to be considered worth
1124 * handling. Note that we tag on any latent IRQs postponed
1125 * due to waiting for busy status.
1127 if (!((status|host->busy_status) &
1128 (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND)))
1132 * ST Micro variant: handle busy detection.
1134 if (host->variant->busy_detect) {
1135 bool busy_resp = !!(cmd->flags & MMC_RSP_BUSY);
1137 /* We are busy with a command, return */
1138 if (host->busy_status &&
1139 (status & host->variant->busy_detect_flag))
1143 * We were not busy, but we now got a busy response on
1144 * something that was not an error, and we double-check
1145 * that the special busy status bit is still set before
1148 if (!host->busy_status && busy_resp &&
1149 !(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) &&
1150 (readl(base + MMCISTATUS) & host->variant->busy_detect_flag)) {
1152 /* Clear the busy start IRQ */
1153 writel(host->variant->busy_detect_mask,
1154 host->base + MMCICLEAR);
1156 /* Unmask the busy end IRQ */
1157 writel(readl(base + MMCIMASK0) |
1158 host->variant->busy_detect_mask,
1161 * Now cache the last response status code (until
1162 * the busy bit goes low), and return.
1165 status & (MCI_CMDSENT|MCI_CMDRESPEND);
1170 * At this point we are not busy with a command, we have
1171 * not received a new busy request, clear and mask the busy
1172 * end IRQ and fall through to process the IRQ.
1174 if (host->busy_status) {
1176 writel(host->variant->busy_detect_mask,
1177 host->base + MMCICLEAR);
1179 writel(readl(base + MMCIMASK0) &
1180 ~host->variant->busy_detect_mask,
1182 host->busy_status = 0;
1188 if (status & MCI_CMDTIMEOUT) {
1189 cmd->error = -ETIMEDOUT;
1190 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
1191 cmd->error = -EILSEQ;
1193 cmd->resp[0] = readl(base + MMCIRESPONSE0);
1194 cmd->resp[1] = readl(base + MMCIRESPONSE1);
1195 cmd->resp[2] = readl(base + MMCIRESPONSE2);
1196 cmd->resp[3] = readl(base + MMCIRESPONSE3);
1199 if ((!sbc && !cmd->data) || cmd->error) {
1201 /* Terminate the DMA transfer */
1202 mmci_dma_error(host);
1204 mmci_stop_data(host);
1206 mmci_request_end(host, host->mrq);
1208 mmci_start_command(host, host->mrq->cmd, 0);
1209 } else if (!(cmd->data->flags & MMC_DATA_READ)) {
1210 mmci_start_data(host, cmd->data);
1214 static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain)
1216 return remain - (readl(host->base + MMCIFIFOCNT) << 2);
1219 static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r)
1222 * on qcom SDCC4 only 8 words are used in each burst so only 8 addresses
1223 * from the fifo range should be used
1225 if (status & MCI_RXFIFOHALFFULL)
1226 return host->variant->fifohalfsize;
1227 else if (status & MCI_RXDATAAVLBL)
1233 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
1235 void __iomem *base = host->base;
1237 u32 status = readl(host->base + MMCISTATUS);
1238 int host_remain = host->size;
1241 int count = host->get_rx_fifocnt(host, status, host_remain);
1250 * SDIO especially may want to send something that is
1251 * not divisible by 4 (as opposed to card sectors
1252 * etc). Therefore make sure to always read the last bytes
1253 * while only doing full 32-bit reads towards the FIFO.
1255 if (unlikely(count & 0x3)) {
1257 unsigned char buf[4];
1258 ioread32_rep(base + MMCIFIFO, buf, 1);
1259 memcpy(ptr, buf, count);
1261 ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
1265 ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
1270 host_remain -= count;
1275 status = readl(base + MMCISTATUS);
1276 } while (status & MCI_RXDATAAVLBL);
1278 return ptr - buffer;
1281 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
1283 struct variant_data *variant = host->variant;
1284 void __iomem *base = host->base;
1288 unsigned int count, maxcnt;
1290 maxcnt = status & MCI_TXFIFOEMPTY ?
1291 variant->fifosize : variant->fifohalfsize;
1292 count = min(remain, maxcnt);
1295 * SDIO especially may want to send something that is
1296 * not divisible by 4 (as opposed to card sectors
1297 * etc), and the FIFO only accept full 32-bit writes.
1298 * So compensate by adding +3 on the count, a single
1299 * byte become a 32bit write, 7 bytes will be two
1302 iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2);
1310 status = readl(base + MMCISTATUS);
1311 } while (status & MCI_TXFIFOHALFEMPTY);
1313 return ptr - buffer;
1317 * PIO data transfer IRQ handler.
1319 static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
1321 struct mmci_host *host = dev_id;
1322 struct sg_mapping_iter *sg_miter = &host->sg_miter;
1323 struct variant_data *variant = host->variant;
1324 void __iomem *base = host->base;
1327 status = readl(base + MMCISTATUS);
1329 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
1332 unsigned int remain, len;
1336 * For write, we only need to test the half-empty flag
1337 * here - if the FIFO is completely empty, then by
1338 * definition it is more than half empty.
1340 * For read, check for data available.
1342 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
1345 if (!sg_miter_next(sg_miter))
1348 buffer = sg_miter->addr;
1349 remain = sg_miter->length;
1352 if (status & MCI_RXACTIVE)
1353 len = mmci_pio_read(host, buffer, remain);
1354 if (status & MCI_TXACTIVE)
1355 len = mmci_pio_write(host, buffer, remain, status);
1357 sg_miter->consumed = len;
1365 status = readl(base + MMCISTATUS);
1368 sg_miter_stop(sg_miter);
1371 * If we have less than the fifo 'half-full' threshold to transfer,
1372 * trigger a PIO interrupt as soon as any data is available.
1374 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize)
1375 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK);
1378 * If we run out of data, disable the data IRQs; this
1379 * prevents a race where the FIFO becomes empty before
1380 * the chip itself has disabled the data path, and
1381 * stops us racing with our data end IRQ.
1383 if (host->size == 0) {
1384 mmci_set_mask1(host, 0);
1385 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
1392 * Handle completion of command and data transfers.
1394 static irqreturn_t mmci_irq(int irq, void *dev_id)
1396 struct mmci_host *host = dev_id;
1400 spin_lock(&host->lock);
1403 status = readl(host->base + MMCISTATUS);
1405 if (host->singleirq) {
1406 if (status & host->mask1_reg)
1407 mmci_pio_irq(irq, dev_id);
1409 status &= ~MCI_IRQ1MASK;
1413 * We intentionally clear the MCI_ST_CARDBUSY IRQ (if it's
1414 * enabled) in mmci_cmd_irq() function where ST Micro busy
1415 * detection variant is handled. Considering the HW seems to be
1416 * triggering the IRQ on both edges while monitoring DAT0 for
1417 * busy completion and that same status bit is used to monitor
1418 * start and end of busy detection, special care must be taken
1419 * to make sure that both start and end interrupts are always
1420 * cleared one after the other.
1422 status &= readl(host->base + MMCIMASK0);
1423 if (host->variant->busy_detect)
1424 writel(status & ~host->variant->busy_detect_mask,
1425 host->base + MMCICLEAR);
1427 writel(status, host->base + MMCICLEAR);
1429 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
1431 if (host->variant->reversed_irq_handling) {
1432 mmci_data_irq(host, host->data, status);
1433 mmci_cmd_irq(host, host->cmd, status);
1435 mmci_cmd_irq(host, host->cmd, status);
1436 mmci_data_irq(host, host->data, status);
1440 * Don't poll for busy completion in irq context.
1442 if (host->variant->busy_detect && host->busy_status)
1443 status &= ~host->variant->busy_detect_flag;
1448 spin_unlock(&host->lock);
1450 return IRQ_RETVAL(ret);
1453 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1455 struct mmci_host *host = mmc_priv(mmc);
1456 unsigned long flags;
1458 WARN_ON(host->mrq != NULL);
1460 mrq->cmd->error = mmci_validate_data(host, mrq->data);
1461 if (mrq->cmd->error) {
1462 mmc_request_done(mmc, mrq);
1466 spin_lock_irqsave(&host->lock, flags);
1471 mmci_get_next_data(host, mrq->data);
1473 if (mrq->data && mrq->data->flags & MMC_DATA_READ)
1474 mmci_start_data(host, mrq->data);
1477 mmci_start_command(host, mrq->sbc, 0);
1479 mmci_start_command(host, mrq->cmd, 0);
1481 spin_unlock_irqrestore(&host->lock, flags);
1484 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1486 struct mmci_host *host = mmc_priv(mmc);
1487 struct variant_data *variant = host->variant;
1489 unsigned long flags;
1492 if (host->plat->ios_handler &&
1493 host->plat->ios_handler(mmc_dev(mmc), ios))
1494 dev_err(mmc_dev(mmc), "platform ios_handler failed\n");
1496 switch (ios->power_mode) {
1498 if (!IS_ERR(mmc->supply.vmmc))
1499 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1501 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1502 regulator_disable(mmc->supply.vqmmc);
1503 host->vqmmc_enabled = false;
1508 if (!IS_ERR(mmc->supply.vmmc))
1509 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
1512 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP
1513 * and instead uses MCI_PWR_ON so apply whatever value is
1514 * configured in the variant data.
1516 pwr |= variant->pwrreg_powerup;
1520 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1521 ret = regulator_enable(mmc->supply.vqmmc);
1523 dev_err(mmc_dev(mmc),
1524 "failed to enable vqmmc regulator\n");
1526 host->vqmmc_enabled = true;
1533 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) {
1535 * The ST Micro variant has some additional bits
1536 * indicating signal direction for the signals in
1537 * the SD/MMC bus and feedback-clock usage.
1539 pwr |= host->pwr_reg_add;
1541 if (ios->bus_width == MMC_BUS_WIDTH_4)
1542 pwr &= ~MCI_ST_DATA74DIREN;
1543 else if (ios->bus_width == MMC_BUS_WIDTH_1)
1544 pwr &= (~MCI_ST_DATA74DIREN &
1545 ~MCI_ST_DATA31DIREN &
1546 ~MCI_ST_DATA2DIREN);
1549 if (variant->opendrain) {
1550 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
1551 pwr |= variant->opendrain;
1554 * If the variant cannot configure the pads by its own, then we
1555 * expect the pinctrl to be able to do that for us
1557 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
1558 pinctrl_select_state(host->pinctrl, host->pins_opendrain);
1560 pinctrl_select_state(host->pinctrl, host->pins_default);
1564 * If clock = 0 and the variant requires the MMCIPOWER to be used for
1565 * gating the clock, the MCI_PWR_ON bit is cleared.
1567 if (!ios->clock && variant->pwrreg_clkgate)
1570 if (host->variant->explicit_mclk_control &&
1571 ios->clock != host->clock_cache) {
1572 ret = clk_set_rate(host->clk, ios->clock);
1574 dev_err(mmc_dev(host->mmc),
1575 "Error setting clock rate (%d)\n", ret);
1577 host->mclk = clk_get_rate(host->clk);
1579 host->clock_cache = ios->clock;
1581 spin_lock_irqsave(&host->lock, flags);
1583 if (host->ops && host->ops->set_clkreg)
1584 host->ops->set_clkreg(host, ios->clock);
1586 mmci_set_clkreg(host, ios->clock);
1588 if (host->ops && host->ops->set_pwrreg)
1589 host->ops->set_pwrreg(host, pwr);
1591 mmci_write_pwrreg(host, pwr);
1593 mmci_reg_delay(host);
1595 spin_unlock_irqrestore(&host->lock, flags);
1598 static int mmci_get_cd(struct mmc_host *mmc)
1600 struct mmci_host *host = mmc_priv(mmc);
1601 struct mmci_platform_data *plat = host->plat;
1602 unsigned int status = mmc_gpio_get_cd(mmc);
1604 if (status == -ENOSYS) {
1606 return 1; /* Assume always present */
1608 status = plat->status(mmc_dev(host->mmc));
1613 static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
1617 if (!IS_ERR(mmc->supply.vqmmc)) {
1619 switch (ios->signal_voltage) {
1620 case MMC_SIGNAL_VOLTAGE_330:
1621 ret = regulator_set_voltage(mmc->supply.vqmmc,
1624 case MMC_SIGNAL_VOLTAGE_180:
1625 ret = regulator_set_voltage(mmc->supply.vqmmc,
1628 case MMC_SIGNAL_VOLTAGE_120:
1629 ret = regulator_set_voltage(mmc->supply.vqmmc,
1635 dev_warn(mmc_dev(mmc), "Voltage switch failed\n");
1641 static struct mmc_host_ops mmci_ops = {
1642 .request = mmci_request,
1643 .pre_req = mmci_pre_request,
1644 .post_req = mmci_post_request,
1645 .set_ios = mmci_set_ios,
1646 .get_ro = mmc_gpio_get_ro,
1647 .get_cd = mmci_get_cd,
1648 .start_signal_voltage_switch = mmci_sig_volt_switch,
1651 static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc)
1653 struct mmci_host *host = mmc_priv(mmc);
1654 int ret = mmc_of_parse(mmc);
1659 if (of_get_property(np, "st,sig-dir-dat0", NULL))
1660 host->pwr_reg_add |= MCI_ST_DATA0DIREN;
1661 if (of_get_property(np, "st,sig-dir-dat2", NULL))
1662 host->pwr_reg_add |= MCI_ST_DATA2DIREN;
1663 if (of_get_property(np, "st,sig-dir-dat31", NULL))
1664 host->pwr_reg_add |= MCI_ST_DATA31DIREN;
1665 if (of_get_property(np, "st,sig-dir-dat74", NULL))
1666 host->pwr_reg_add |= MCI_ST_DATA74DIREN;
1667 if (of_get_property(np, "st,sig-dir-cmd", NULL))
1668 host->pwr_reg_add |= MCI_ST_CMDDIREN;
1669 if (of_get_property(np, "st,sig-pin-fbclk", NULL))
1670 host->pwr_reg_add |= MCI_ST_FBCLKEN;
1672 if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL))
1673 mmc->caps |= MMC_CAP_MMC_HIGHSPEED;
1674 if (of_get_property(np, "mmc-cap-sd-highspeed", NULL))
1675 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1680 static int mmci_probe(struct amba_device *dev,
1681 const struct amba_id *id)
1683 struct mmci_platform_data *plat = dev->dev.platform_data;
1684 struct device_node *np = dev->dev.of_node;
1685 struct variant_data *variant = id->data;
1686 struct mmci_host *host;
1687 struct mmc_host *mmc;
1690 /* Must have platform data or Device Tree. */
1692 dev_err(&dev->dev, "No plat data or DT found\n");
1697 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL);
1702 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
1706 ret = mmci_of_parse(np, mmc);
1710 host = mmc_priv(mmc);
1714 * Some variant (STM32) doesn't have opendrain bit, nevertheless
1715 * pins can be set accordingly using pinctrl
1717 if (!variant->opendrain) {
1718 host->pinctrl = devm_pinctrl_get(&dev->dev);
1719 if (IS_ERR(host->pinctrl)) {
1720 dev_err(&dev->dev, "failed to get pinctrl");
1721 ret = PTR_ERR(host->pinctrl);
1725 host->pins_default = pinctrl_lookup_state(host->pinctrl,
1726 PINCTRL_STATE_DEFAULT);
1727 if (IS_ERR(host->pins_default)) {
1728 dev_err(mmc_dev(mmc), "Can't select default pins\n");
1729 ret = PTR_ERR(host->pins_default);
1733 host->pins_opendrain = pinctrl_lookup_state(host->pinctrl,
1734 MMCI_PINCTRL_STATE_OPENDRAIN);
1735 if (IS_ERR(host->pins_opendrain)) {
1736 dev_err(mmc_dev(mmc), "Can't select opendrain pins\n");
1737 ret = PTR_ERR(host->pins_opendrain);
1742 host->hw_designer = amba_manf(dev);
1743 host->hw_revision = amba_rev(dev);
1744 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
1745 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
1747 host->clk = devm_clk_get(&dev->dev, NULL);
1748 if (IS_ERR(host->clk)) {
1749 ret = PTR_ERR(host->clk);
1753 ret = clk_prepare_enable(host->clk);
1757 if (variant->qcom_fifo)
1758 host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt;
1760 host->get_rx_fifocnt = mmci_get_rx_fifocnt;
1763 host->variant = variant;
1764 host->mclk = clk_get_rate(host->clk);
1766 * According to the spec, mclk is max 100 MHz,
1767 * so we try to adjust the clock down to this,
1770 if (host->mclk > variant->f_max) {
1771 ret = clk_set_rate(host->clk, variant->f_max);
1774 host->mclk = clk_get_rate(host->clk);
1775 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n",
1779 host->phybase = dev->res.start;
1780 host->base = devm_ioremap_resource(&dev->dev, &dev->res);
1781 if (IS_ERR(host->base)) {
1782 ret = PTR_ERR(host->base);
1787 variant->init(host);
1790 * The ARM and ST versions of the block have slightly different
1791 * clock divider equations which means that the minimum divider
1793 * on Qualcomm like controllers get the nearest minimum clock to 100Khz
1795 if (variant->st_clkdiv)
1796 mmc->f_min = DIV_ROUND_UP(host->mclk, 257);
1797 else if (variant->explicit_mclk_control)
1798 mmc->f_min = clk_round_rate(host->clk, 100000);
1800 mmc->f_min = DIV_ROUND_UP(host->mclk, 512);
1802 * If no maximum operating frequency is supplied, fall back to use
1803 * the module parameter, which has a (low) default value in case it
1804 * is not specified. Either value must not exceed the clock rate into
1805 * the block, of course.
1808 mmc->f_max = variant->explicit_mclk_control ?
1809 min(variant->f_max, mmc->f_max) :
1810 min(host->mclk, mmc->f_max);
1812 mmc->f_max = variant->explicit_mclk_control ?
1813 fmax : min(host->mclk, fmax);
1816 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);
1818 /* Get regulators and the supported OCR mask */
1819 ret = mmc_regulator_get_supply(mmc);
1823 if (!mmc->ocr_avail)
1824 mmc->ocr_avail = plat->ocr_mask;
1825 else if (plat->ocr_mask)
1826 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n");
1828 /* We support these capabilities. */
1829 mmc->caps |= MMC_CAP_CMD23;
1832 * Enable busy detection.
1834 if (variant->busy_detect) {
1835 mmci_ops.card_busy = mmci_card_busy;
1837 * Not all variants have a flag to enable busy detection
1838 * in the DPSM, but if they do, set it here.
1840 if (variant->busy_dpsm_flag)
1841 mmci_write_datactrlreg(host,
1842 host->variant->busy_dpsm_flag);
1843 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
1844 mmc->max_busy_timeout = 0;
1847 mmc->ops = &mmci_ops;
1849 /* We support these PM capabilities. */
1850 mmc->pm_caps |= MMC_PM_KEEP_POWER;
1855 mmc->max_segs = NR_SG;
1858 * Since only a certain number of bits are valid in the data length
1859 * register, we must ensure that we don't exceed 2^num-1 bytes in a
1862 mmc->max_req_size = (1 << variant->datalength_bits) - 1;
1865 * Set the maximum segment size. Since we aren't doing DMA
1866 * (yet) we are only limited by the data length register.
1868 mmc->max_seg_size = mmc->max_req_size;
1871 * Block size can be up to 2048 bytes, but must be a power of two.
1873 mmc->max_blk_size = 1 << variant->datactrl_blocksz;
1876 * Limit the number of blocks transferred so that we don't overflow
1877 * the maximum request size.
1879 mmc->max_blk_count = mmc->max_req_size >> variant->datactrl_blocksz;
1881 spin_lock_init(&host->lock);
1883 writel(0, host->base + MMCIMASK0);
1885 if (variant->mmcimask1)
1886 writel(0, host->base + MMCIMASK1);
1888 writel(0xfff, host->base + MMCICLEAR);
1892 * - not using DT but using a descriptor table, or
1893 * - using a table of descriptors ALONGSIDE DT, or
1894 * look up these descriptors named "cd" and "wp" right here, fail
1895 * silently of these do not exist
1898 ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0, NULL);
1899 if (ret == -EPROBE_DEFER)
1902 ret = mmc_gpiod_request_ro(mmc, "wp", 0, false, 0, NULL);
1903 if (ret == -EPROBE_DEFER)
1907 ret = devm_request_irq(&dev->dev, dev->irq[0], mmci_irq, IRQF_SHARED,
1908 DRIVER_NAME " (cmd)", host);
1913 host->singleirq = true;
1915 ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq,
1916 IRQF_SHARED, DRIVER_NAME " (pio)", host);
1921 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1923 amba_set_drvdata(dev, mmc);
1925 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n",
1926 mmc_hostname(mmc), amba_part(dev), amba_manf(dev),
1927 amba_rev(dev), (unsigned long long)dev->res.start,
1928 dev->irq[0], dev->irq[1]);
1930 mmci_dma_setup(host);
1932 pm_runtime_set_autosuspend_delay(&dev->dev, 50);
1933 pm_runtime_use_autosuspend(&dev->dev);
1937 pm_runtime_put(&dev->dev);
1941 clk_disable_unprepare(host->clk);
1947 static int mmci_remove(struct amba_device *dev)
1949 struct mmc_host *mmc = amba_get_drvdata(dev);
1952 struct mmci_host *host = mmc_priv(mmc);
1953 struct variant_data *variant = host->variant;
1956 * Undo pm_runtime_put() in probe. We use the _sync
1957 * version here so that we can access the primecell.
1959 pm_runtime_get_sync(&dev->dev);
1961 mmc_remove_host(mmc);
1963 writel(0, host->base + MMCIMASK0);
1965 if (variant->mmcimask1)
1966 writel(0, host->base + MMCIMASK1);
1968 writel(0, host->base + MMCICOMMAND);
1969 writel(0, host->base + MMCIDATACTRL);
1971 mmci_dma_release(host);
1972 clk_disable_unprepare(host->clk);
1980 static void mmci_save(struct mmci_host *host)
1982 unsigned long flags;
1984 spin_lock_irqsave(&host->lock, flags);
1986 writel(0, host->base + MMCIMASK0);
1987 if (host->variant->pwrreg_nopower) {
1988 writel(0, host->base + MMCIDATACTRL);
1989 writel(0, host->base + MMCIPOWER);
1990 writel(0, host->base + MMCICLOCK);
1992 mmci_reg_delay(host);
1994 spin_unlock_irqrestore(&host->lock, flags);
1997 static void mmci_restore(struct mmci_host *host)
1999 unsigned long flags;
2001 spin_lock_irqsave(&host->lock, flags);
2003 if (host->variant->pwrreg_nopower) {
2004 writel(host->clk_reg, host->base + MMCICLOCK);
2005 writel(host->datactrl_reg, host->base + MMCIDATACTRL);
2006 writel(host->pwr_reg, host->base + MMCIPOWER);
2008 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
2009 mmci_reg_delay(host);
2011 spin_unlock_irqrestore(&host->lock, flags);
2014 static int mmci_runtime_suspend(struct device *dev)
2016 struct amba_device *adev = to_amba_device(dev);
2017 struct mmc_host *mmc = amba_get_drvdata(adev);
2020 struct mmci_host *host = mmc_priv(mmc);
2021 pinctrl_pm_select_sleep_state(dev);
2023 clk_disable_unprepare(host->clk);
2029 static int mmci_runtime_resume(struct device *dev)
2031 struct amba_device *adev = to_amba_device(dev);
2032 struct mmc_host *mmc = amba_get_drvdata(adev);
2035 struct mmci_host *host = mmc_priv(mmc);
2036 clk_prepare_enable(host->clk);
2038 pinctrl_pm_select_default_state(dev);
2045 static const struct dev_pm_ops mmci_dev_pm_ops = {
2046 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2047 pm_runtime_force_resume)
2048 SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL)
2051 static const struct amba_id mmci_ids[] = {
2055 .data = &variant_arm,
2060 .data = &variant_arm_extended_fifo,
2065 .data = &variant_arm_extended_fifo_hwfc,
2070 .data = &variant_arm,
2072 /* ST Micro variants */
2076 .data = &variant_u300,
2081 .data = &variant_nomadik,
2086 .data = &variant_nomadik,
2091 .data = &variant_ux500,
2096 .data = &variant_ux500v2,
2101 .data = &variant_stm32,
2103 /* Qualcomm variants */
2107 .data = &variant_qcom,
2112 MODULE_DEVICE_TABLE(amba, mmci_ids);
2114 static struct amba_driver mmci_driver = {
2116 .name = DRIVER_NAME,
2117 .pm = &mmci_dev_pm_ops,
2119 .probe = mmci_probe,
2120 .remove = mmci_remove,
2121 .id_table = mmci_ids,
2124 module_amba_driver(mmci_driver);
2126 module_param(fmax, uint, 0444);
2128 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
2129 MODULE_LICENSE("GPL");