2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/blkdev.h>
15 #include <linux/clk.h>
16 #include <linux/debugfs.h>
17 #include <linux/device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/ioport.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/seq_file.h>
26 #include <linux/slab.h>
27 #include <linux/stat.h>
28 #include <linux/delay.h>
29 #include <linux/irq.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/host.h>
32 #include <linux/mmc/mmc.h>
33 #include <linux/mmc/sd.h>
34 #include <linux/mmc/sdio.h>
35 #include <linux/mmc/dw_mmc.h>
36 #include <linux/bitops.h>
37 #include <linux/regulator/consumer.h>
39 #include <linux/of_gpio.h>
40 #include <linux/mmc/slot-gpio.h>
44 /* Common flag combinations */
45 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
46 SDMMC_INT_HTO | SDMMC_INT_SBE | \
47 SDMMC_INT_EBE | SDMMC_INT_HLE)
48 #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
49 SDMMC_INT_RESP_ERR | SDMMC_INT_HLE)
50 #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
51 DW_MCI_CMD_ERROR_FLAGS)
52 #define DW_MCI_SEND_STATUS 1
53 #define DW_MCI_RECV_STATUS 2
54 #define DW_MCI_DMA_THRESHOLD 16
56 #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */
57 #define DW_MCI_FREQ_MIN 100000 /* unit: HZ */
59 #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
60 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
61 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
64 #define DESC_RING_BUF_SZ PAGE_SIZE
66 struct idmac_desc_64addr {
67 u32 des0; /* Control Descriptor */
69 u32 des1; /* Reserved */
71 u32 des2; /*Buffer sizes */
72 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
73 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
74 ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
76 u32 des3; /* Reserved */
78 u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/
79 u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/
81 u32 des6; /* Lower 32-bits of Next Descriptor Address */
82 u32 des7; /* Upper 32-bits of Next Descriptor Address */
86 __le32 des0; /* Control Descriptor */
87 #define IDMAC_DES0_DIC BIT(1)
88 #define IDMAC_DES0_LD BIT(2)
89 #define IDMAC_DES0_FD BIT(3)
90 #define IDMAC_DES0_CH BIT(4)
91 #define IDMAC_DES0_ER BIT(5)
92 #define IDMAC_DES0_CES BIT(30)
93 #define IDMAC_DES0_OWN BIT(31)
95 __le32 des1; /* Buffer sizes */
96 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
97 ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff)))
99 __le32 des2; /* buffer 1 physical address */
101 __le32 des3; /* buffer 2 physical address */
104 /* Each descriptor can transfer up to 4KB of data in chained mode */
105 #define DW_MCI_DESC_DATA_LENGTH 0x1000
107 static bool dw_mci_reset(struct dw_mci *host);
108 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
109 static int dw_mci_card_busy(struct mmc_host *mmc);
110 static int dw_mci_get_cd(struct mmc_host *mmc);
112 #if defined(CONFIG_DEBUG_FS)
113 static int dw_mci_req_show(struct seq_file *s, void *v)
115 struct dw_mci_slot *slot = s->private;
116 struct mmc_request *mrq;
117 struct mmc_command *cmd;
118 struct mmc_command *stop;
119 struct mmc_data *data;
121 /* Make sure we get a consistent snapshot */
122 spin_lock_bh(&slot->host->lock);
132 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
133 cmd->opcode, cmd->arg, cmd->flags,
134 cmd->resp[0], cmd->resp[1], cmd->resp[2],
135 cmd->resp[2], cmd->error);
137 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
138 data->bytes_xfered, data->blocks,
139 data->blksz, data->flags, data->error);
142 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
143 stop->opcode, stop->arg, stop->flags,
144 stop->resp[0], stop->resp[1], stop->resp[2],
145 stop->resp[2], stop->error);
148 spin_unlock_bh(&slot->host->lock);
153 static int dw_mci_req_open(struct inode *inode, struct file *file)
155 return single_open(file, dw_mci_req_show, inode->i_private);
158 static const struct file_operations dw_mci_req_fops = {
159 .owner = THIS_MODULE,
160 .open = dw_mci_req_open,
163 .release = single_release,
166 static int dw_mci_regs_show(struct seq_file *s, void *v)
168 struct dw_mci *host = s->private;
170 seq_printf(s, "STATUS:\t0x%08x\n", mci_readl(host, STATUS));
171 seq_printf(s, "RINTSTS:\t0x%08x\n", mci_readl(host, RINTSTS));
172 seq_printf(s, "CMD:\t0x%08x\n", mci_readl(host, CMD));
173 seq_printf(s, "CTRL:\t0x%08x\n", mci_readl(host, CTRL));
174 seq_printf(s, "INTMASK:\t0x%08x\n", mci_readl(host, INTMASK));
175 seq_printf(s, "CLKENA:\t0x%08x\n", mci_readl(host, CLKENA));
180 static int dw_mci_regs_open(struct inode *inode, struct file *file)
182 return single_open(file, dw_mci_regs_show, inode->i_private);
185 static const struct file_operations dw_mci_regs_fops = {
186 .owner = THIS_MODULE,
187 .open = dw_mci_regs_open,
190 .release = single_release,
193 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
195 struct mmc_host *mmc = slot->mmc;
196 struct dw_mci *host = slot->host;
200 root = mmc->debugfs_root;
204 node = debugfs_create_file("regs", S_IRUSR, root, host,
209 node = debugfs_create_file("req", S_IRUSR, root, slot,
214 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
218 node = debugfs_create_x32("pending_events", S_IRUSR, root,
219 (u32 *)&host->pending_events);
223 node = debugfs_create_x32("completed_events", S_IRUSR, root,
224 (u32 *)&host->completed_events);
231 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
233 #endif /* defined(CONFIG_DEBUG_FS) */
235 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg);
237 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
239 struct mmc_data *data;
240 struct dw_mci_slot *slot = mmc_priv(mmc);
241 struct dw_mci *host = slot->host;
244 cmd->error = -EINPROGRESS;
247 if (cmd->opcode == MMC_STOP_TRANSMISSION ||
248 cmd->opcode == MMC_GO_IDLE_STATE ||
249 cmd->opcode == MMC_GO_INACTIVE_STATE ||
250 (cmd->opcode == SD_IO_RW_DIRECT &&
251 ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
252 cmdr |= SDMMC_CMD_STOP;
253 else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
254 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
256 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
259 /* Special bit makes CMD11 not die */
260 cmdr |= SDMMC_CMD_VOLT_SWITCH;
262 /* Change state to continue to handle CMD11 weirdness */
263 WARN_ON(slot->host->state != STATE_SENDING_CMD);
264 slot->host->state = STATE_SENDING_CMD11;
267 * We need to disable low power mode (automatic clock stop)
268 * while doing voltage switch so we don't confuse the card,
269 * since stopping the clock is a specific part of the UHS
270 * voltage change dance.
272 * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
273 * unconditionally turned back on in dw_mci_setup_bus() if it's
274 * ever called with a non-zero clock. That shouldn't happen
275 * until the voltage change is all done.
277 clk_en_a = mci_readl(host, CLKENA);
278 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
279 mci_writel(host, CLKENA, clk_en_a);
280 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
281 SDMMC_CMD_PRV_DAT_WAIT, 0);
284 if (cmd->flags & MMC_RSP_PRESENT) {
285 /* We expect a response, so set this bit */
286 cmdr |= SDMMC_CMD_RESP_EXP;
287 if (cmd->flags & MMC_RSP_136)
288 cmdr |= SDMMC_CMD_RESP_LONG;
291 if (cmd->flags & MMC_RSP_CRC)
292 cmdr |= SDMMC_CMD_RESP_CRC;
296 cmdr |= SDMMC_CMD_DAT_EXP;
297 if (data->flags & MMC_DATA_WRITE)
298 cmdr |= SDMMC_CMD_DAT_WR;
301 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags))
302 cmdr |= SDMMC_CMD_USE_HOLD_REG;
307 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
309 struct mmc_command *stop;
315 stop = &host->stop_abort;
317 memset(stop, 0, sizeof(struct mmc_command));
319 if (cmdr == MMC_READ_SINGLE_BLOCK ||
320 cmdr == MMC_READ_MULTIPLE_BLOCK ||
321 cmdr == MMC_WRITE_BLOCK ||
322 cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
323 cmdr == MMC_SEND_TUNING_BLOCK ||
324 cmdr == MMC_SEND_TUNING_BLOCK_HS200) {
325 stop->opcode = MMC_STOP_TRANSMISSION;
327 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
328 } else if (cmdr == SD_IO_RW_EXTENDED) {
329 stop->opcode = SD_IO_RW_DIRECT;
330 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
331 ((cmd->arg >> 28) & 0x7);
332 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
337 cmdr = stop->opcode | SDMMC_CMD_STOP |
338 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
340 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &host->cur_slot->flags))
341 cmdr |= SDMMC_CMD_USE_HOLD_REG;
346 static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
348 unsigned long timeout = jiffies + msecs_to_jiffies(500);
351 * Databook says that before issuing a new data transfer command
352 * we need to check to see if the card is busy. Data transfer commands
353 * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
355 * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
358 if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) &&
359 !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) {
360 while (mci_readl(host, STATUS) & SDMMC_STATUS_BUSY) {
361 if (time_after(jiffies, timeout)) {
362 /* Command will fail; we'll pass error then */
363 dev_err(host->dev, "Busy; trying anyway\n");
371 static void dw_mci_start_command(struct dw_mci *host,
372 struct mmc_command *cmd, u32 cmd_flags)
376 "start command: ARGR=0x%08x CMDR=0x%08x\n",
377 cmd->arg, cmd_flags);
379 mci_writel(host, CMDARG, cmd->arg);
380 wmb(); /* drain writebuffer */
381 dw_mci_wait_while_busy(host, cmd_flags);
383 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
386 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
388 struct mmc_command *stop = data->stop ? data->stop : &host->stop_abort;
390 dw_mci_start_command(host, stop, host->stop_cmdr);
393 /* DMA interface functions */
394 static void dw_mci_stop_dma(struct dw_mci *host)
396 if (host->using_dma) {
397 host->dma_ops->stop(host);
398 host->dma_ops->cleanup(host);
401 /* Data transfer was stopped by the interrupt handler */
402 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
405 static int dw_mci_get_dma_dir(struct mmc_data *data)
407 if (data->flags & MMC_DATA_WRITE)
408 return DMA_TO_DEVICE;
410 return DMA_FROM_DEVICE;
413 static void dw_mci_dma_cleanup(struct dw_mci *host)
415 struct mmc_data *data = host->data;
418 if (!data->host_cookie)
419 dma_unmap_sg(host->dev,
422 dw_mci_get_dma_dir(data));
425 static void dw_mci_idmac_reset(struct dw_mci *host)
427 u32 bmod = mci_readl(host, BMOD);
428 /* Software reset of DMA */
429 bmod |= SDMMC_IDMAC_SWRESET;
430 mci_writel(host, BMOD, bmod);
433 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
437 /* Disable and reset the IDMAC interface */
438 temp = mci_readl(host, CTRL);
439 temp &= ~SDMMC_CTRL_USE_IDMAC;
440 temp |= SDMMC_CTRL_DMA_RESET;
441 mci_writel(host, CTRL, temp);
443 /* Stop the IDMAC running */
444 temp = mci_readl(host, BMOD);
445 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
446 temp |= SDMMC_IDMAC_SWRESET;
447 mci_writel(host, BMOD, temp);
450 static void dw_mci_dmac_complete_dma(void *arg)
452 struct dw_mci *host = arg;
453 struct mmc_data *data = host->data;
455 dev_vdbg(host->dev, "DMA complete\n");
457 if ((host->use_dma == TRANS_MODE_EDMAC) &&
458 data && (data->flags & MMC_DATA_READ))
459 /* Invalidate cache after read */
460 dma_sync_sg_for_cpu(mmc_dev(host->cur_slot->mmc),
465 host->dma_ops->cleanup(host);
468 * If the card was removed, data will be NULL. No point in trying to
469 * send the stop command or waiting for NBUSY in this case.
472 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
473 tasklet_schedule(&host->tasklet);
477 static int dw_mci_idmac_init(struct dw_mci *host)
481 if (host->dma_64bit_address == 1) {
482 struct idmac_desc_64addr *p;
483 /* Number of descriptors in the ring buffer */
485 DESC_RING_BUF_SZ / sizeof(struct idmac_desc_64addr);
487 /* Forward link the descriptor list */
488 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
490 p->des6 = (host->sg_dma +
491 (sizeof(struct idmac_desc_64addr) *
492 (i + 1))) & 0xffffffff;
494 p->des7 = (u64)(host->sg_dma +
495 (sizeof(struct idmac_desc_64addr) *
497 /* Initialize reserved and buffer size fields to "0" */
503 /* Set the last descriptor as the end-of-ring descriptor */
504 p->des6 = host->sg_dma & 0xffffffff;
505 p->des7 = (u64)host->sg_dma >> 32;
506 p->des0 = IDMAC_DES0_ER;
509 struct idmac_desc *p;
510 /* Number of descriptors in the ring buffer */
512 DESC_RING_BUF_SZ / sizeof(struct idmac_desc);
514 /* Forward link the descriptor list */
515 for (i = 0, p = host->sg_cpu;
516 i < host->ring_size - 1;
518 p->des3 = cpu_to_le32(host->sg_dma +
519 (sizeof(struct idmac_desc) * (i + 1)));
523 /* Set the last descriptor as the end-of-ring descriptor */
524 p->des3 = cpu_to_le32(host->sg_dma);
525 p->des0 = cpu_to_le32(IDMAC_DES0_ER);
528 dw_mci_idmac_reset(host);
530 if (host->dma_64bit_address == 1) {
531 /* Mask out interrupts - get Tx & Rx complete only */
532 mci_writel(host, IDSTS64, IDMAC_INT_CLR);
533 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
534 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
536 /* Set the descriptor base address */
537 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
538 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
541 /* Mask out interrupts - get Tx & Rx complete only */
542 mci_writel(host, IDSTS, IDMAC_INT_CLR);
543 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
544 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
546 /* Set the descriptor base address */
547 mci_writel(host, DBADDR, host->sg_dma);
553 static inline int dw_mci_prepare_desc64(struct dw_mci *host,
554 struct mmc_data *data,
557 unsigned int desc_len;
558 struct idmac_desc_64addr *desc_first, *desc_last, *desc;
559 unsigned long timeout;
562 desc_first = desc_last = desc = host->sg_cpu;
564 for (i = 0; i < sg_len; i++) {
565 unsigned int length = sg_dma_len(&data->sg[i]);
567 u64 mem_addr = sg_dma_address(&data->sg[i]);
569 for ( ; length ; desc++) {
570 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
571 length : DW_MCI_DESC_DATA_LENGTH;
576 * Wait for the former clear OWN bit operation
577 * of IDMAC to make sure that this descriptor
578 * isn't still owned by IDMAC as IDMAC's write
579 * ops and CPU's read ops are asynchronous.
581 timeout = jiffies + msecs_to_jiffies(100);
582 while (readl(&desc->des0) & IDMAC_DES0_OWN) {
583 if (time_after(jiffies, timeout))
589 * Set the OWN bit and disable interrupts
590 * for this descriptor
592 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
596 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len);
598 /* Physical address to DMA to/from */
599 desc->des4 = mem_addr & 0xffffffff;
600 desc->des5 = mem_addr >> 32;
602 /* Update physical address for the next desc */
603 mem_addr += desc_len;
605 /* Save pointer to the last descriptor */
610 /* Set first descriptor */
611 desc_first->des0 |= IDMAC_DES0_FD;
613 /* Set last descriptor */
614 desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
615 desc_last->des0 |= IDMAC_DES0_LD;
619 /* restore the descriptor chain as it's polluted */
620 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
621 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
622 dw_mci_idmac_init(host);
627 static inline int dw_mci_prepare_desc32(struct dw_mci *host,
628 struct mmc_data *data,
631 unsigned int desc_len;
632 struct idmac_desc *desc_first, *desc_last, *desc;
633 unsigned long timeout;
636 desc_first = desc_last = desc = host->sg_cpu;
638 for (i = 0; i < sg_len; i++) {
639 unsigned int length = sg_dma_len(&data->sg[i]);
641 u32 mem_addr = sg_dma_address(&data->sg[i]);
643 for ( ; length ; desc++) {
644 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
645 length : DW_MCI_DESC_DATA_LENGTH;
650 * Wait for the former clear OWN bit operation
651 * of IDMAC to make sure that this descriptor
652 * isn't still owned by IDMAC as IDMAC's write
653 * ops and CPU's read ops are asynchronous.
655 timeout = jiffies + msecs_to_jiffies(100);
656 while (readl(&desc->des0) &
657 cpu_to_le32(IDMAC_DES0_OWN)) {
658 if (time_after(jiffies, timeout))
664 * Set the OWN bit and disable interrupts
665 * for this descriptor
667 desc->des0 = cpu_to_le32(IDMAC_DES0_OWN |
672 IDMAC_SET_BUFFER1_SIZE(desc, desc_len);
674 /* Physical address to DMA to/from */
675 desc->des2 = cpu_to_le32(mem_addr);
677 /* Update physical address for the next desc */
678 mem_addr += desc_len;
680 /* Save pointer to the last descriptor */
685 /* Set first descriptor */
686 desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD);
688 /* Set last descriptor */
689 desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH |
691 desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD);
695 /* restore the descriptor chain as it's polluted */
696 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
697 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
698 dw_mci_idmac_init(host);
702 static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
707 if (host->dma_64bit_address == 1)
708 ret = dw_mci_prepare_desc64(host, host->data, sg_len);
710 ret = dw_mci_prepare_desc32(host, host->data, sg_len);
715 /* drain writebuffer */
718 /* Make sure to reset DMA in case we did PIO before this */
719 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
720 dw_mci_idmac_reset(host);
722 /* Select IDMAC interface */
723 temp = mci_readl(host, CTRL);
724 temp |= SDMMC_CTRL_USE_IDMAC;
725 mci_writel(host, CTRL, temp);
727 /* drain writebuffer */
730 /* Enable the IDMAC */
731 temp = mci_readl(host, BMOD);
732 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
733 mci_writel(host, BMOD, temp);
735 /* Start it running */
736 mci_writel(host, PLDMND, 1);
742 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
743 .init = dw_mci_idmac_init,
744 .start = dw_mci_idmac_start_dma,
745 .stop = dw_mci_idmac_stop_dma,
746 .complete = dw_mci_dmac_complete_dma,
747 .cleanup = dw_mci_dma_cleanup,
750 static void dw_mci_edmac_stop_dma(struct dw_mci *host)
752 dmaengine_terminate_async(host->dms->ch);
755 static int dw_mci_edmac_start_dma(struct dw_mci *host,
758 struct dma_slave_config cfg;
759 struct dma_async_tx_descriptor *desc = NULL;
760 struct scatterlist *sgl = host->data->sg;
761 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
762 u32 sg_elems = host->data->sg_len;
764 u32 fifo_offset = host->fifo_reg - host->regs;
767 /* Set external dma config: burst size, burst width */
768 cfg.dst_addr = host->phy_regs + fifo_offset;
769 cfg.src_addr = cfg.dst_addr;
770 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
771 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
773 /* Match burst msize with external dma config */
774 fifoth_val = mci_readl(host, FIFOTH);
775 cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7];
776 cfg.src_maxburst = cfg.dst_maxburst;
778 if (host->data->flags & MMC_DATA_WRITE)
779 cfg.direction = DMA_MEM_TO_DEV;
781 cfg.direction = DMA_DEV_TO_MEM;
783 ret = dmaengine_slave_config(host->dms->ch, &cfg);
785 dev_err(host->dev, "Failed to config edmac.\n");
789 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl,
790 sg_len, cfg.direction,
791 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
793 dev_err(host->dev, "Can't prepare slave sg.\n");
797 /* Set dw_mci_dmac_complete_dma as callback */
798 desc->callback = dw_mci_dmac_complete_dma;
799 desc->callback_param = (void *)host;
800 dmaengine_submit(desc);
802 /* Flush cache before write */
803 if (host->data->flags & MMC_DATA_WRITE)
804 dma_sync_sg_for_device(mmc_dev(host->cur_slot->mmc), sgl,
805 sg_elems, DMA_TO_DEVICE);
807 dma_async_issue_pending(host->dms->ch);
812 static int dw_mci_edmac_init(struct dw_mci *host)
814 /* Request external dma channel */
815 host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
819 host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx");
820 if (!host->dms->ch) {
821 dev_err(host->dev, "Failed to get external DMA channel.\n");
830 static void dw_mci_edmac_exit(struct dw_mci *host)
834 dma_release_channel(host->dms->ch);
835 host->dms->ch = NULL;
842 static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
843 .init = dw_mci_edmac_init,
844 .exit = dw_mci_edmac_exit,
845 .start = dw_mci_edmac_start_dma,
846 .stop = dw_mci_edmac_stop_dma,
847 .complete = dw_mci_dmac_complete_dma,
848 .cleanup = dw_mci_dma_cleanup,
851 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
852 struct mmc_data *data,
855 struct scatterlist *sg;
856 unsigned int i, sg_len;
858 if (!next && data->host_cookie)
859 return data->host_cookie;
862 * We don't do DMA on "complex" transfers, i.e. with
863 * non-word-aligned buffers or lengths. Also, we don't bother
864 * with all the DMA setup overhead for short transfers.
866 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
872 for_each_sg(data->sg, sg, data->sg_len, i) {
873 if (sg->offset & 3 || sg->length & 3)
877 sg_len = dma_map_sg(host->dev,
880 dw_mci_get_dma_dir(data));
885 data->host_cookie = sg_len;
890 static void dw_mci_pre_req(struct mmc_host *mmc,
891 struct mmc_request *mrq,
894 struct dw_mci_slot *slot = mmc_priv(mmc);
895 struct mmc_data *data = mrq->data;
897 if (!slot->host->use_dma || !data)
900 if (data->host_cookie) {
901 data->host_cookie = 0;
905 if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
906 data->host_cookie = 0;
909 static void dw_mci_post_req(struct mmc_host *mmc,
910 struct mmc_request *mrq,
913 struct dw_mci_slot *slot = mmc_priv(mmc);
914 struct mmc_data *data = mrq->data;
916 if (!slot->host->use_dma || !data)
919 if (data->host_cookie)
920 dma_unmap_sg(slot->host->dev,
923 dw_mci_get_dma_dir(data));
924 data->host_cookie = 0;
927 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
929 unsigned int blksz = data->blksz;
930 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
931 u32 fifo_width = 1 << host->data_shift;
932 u32 blksz_depth = blksz / fifo_width, fifoth_val;
933 u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
934 int idx = ARRAY_SIZE(mszs) - 1;
936 /* pio should ship this scenario */
940 tx_wmark = (host->fifo_depth) / 2;
941 tx_wmark_invers = host->fifo_depth - tx_wmark;
945 * if blksz is not a multiple of the FIFO width
947 if (blksz % fifo_width)
951 if (!((blksz_depth % mszs[idx]) ||
952 (tx_wmark_invers % mszs[idx]))) {
954 rx_wmark = mszs[idx] - 1;
959 * If idx is '0', it won't be tried
960 * Thus, initial values are uesed
963 fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
964 mci_writel(host, FIFOTH, fifoth_val);
967 static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data)
969 unsigned int blksz = data->blksz;
970 u32 blksz_depth, fifo_depth;
975 * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
976 * in the FIFO region, so we really shouldn't access it).
978 if (host->verid < DW_MMC_240A ||
979 (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE))
983 * Card write Threshold is introduced since 2.80a
984 * It's used when HS400 mode is enabled.
986 if (data->flags & MMC_DATA_WRITE &&
987 !(host->timing != MMC_TIMING_MMC_HS400))
990 if (data->flags & MMC_DATA_WRITE)
991 enable = SDMMC_CARD_WR_THR_EN;
993 enable = SDMMC_CARD_RD_THR_EN;
995 if (host->timing != MMC_TIMING_MMC_HS200 &&
996 host->timing != MMC_TIMING_UHS_SDR104)
999 blksz_depth = blksz / (1 << host->data_shift);
1000 fifo_depth = host->fifo_depth;
1002 if (blksz_depth > fifo_depth)
1006 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
1007 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz
1008 * Currently just choose blksz.
1011 mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable));
1015 mci_writel(host, CDTHRCTL, 0);
1018 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
1020 unsigned long irqflags;
1024 host->using_dma = 0;
1026 /* If we don't have a channel, we can't do DMA */
1030 sg_len = dw_mci_pre_dma_transfer(host, data, 0);
1032 host->dma_ops->stop(host);
1036 host->using_dma = 1;
1038 if (host->use_dma == TRANS_MODE_IDMAC)
1040 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
1041 (unsigned long)host->sg_cpu,
1042 (unsigned long)host->sg_dma,
1046 * Decide the MSIZE and RX/TX Watermark.
1047 * If current block size is same with previous size,
1048 * no need to update fifoth.
1050 if (host->prev_blksz != data->blksz)
1051 dw_mci_adjust_fifoth(host, data);
1053 /* Enable the DMA interface */
1054 temp = mci_readl(host, CTRL);
1055 temp |= SDMMC_CTRL_DMA_ENABLE;
1056 mci_writel(host, CTRL, temp);
1058 /* Disable RX/TX IRQs, let DMA handle it */
1059 spin_lock_irqsave(&host->irq_lock, irqflags);
1060 temp = mci_readl(host, INTMASK);
1061 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
1062 mci_writel(host, INTMASK, temp);
1063 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1065 if (host->dma_ops->start(host, sg_len)) {
1066 host->dma_ops->stop(host);
1067 /* We can't do DMA, try PIO for this one */
1069 "%s: fall back to PIO mode for current transfer\n",
1077 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
1079 unsigned long irqflags;
1080 int flags = SG_MITER_ATOMIC;
1083 data->error = -EINPROGRESS;
1085 WARN_ON(host->data);
1089 if (data->flags & MMC_DATA_READ)
1090 host->dir_status = DW_MCI_RECV_STATUS;
1092 host->dir_status = DW_MCI_SEND_STATUS;
1094 dw_mci_ctrl_thld(host, data);
1096 if (dw_mci_submit_data_dma(host, data)) {
1097 if (host->data->flags & MMC_DATA_READ)
1098 flags |= SG_MITER_TO_SG;
1100 flags |= SG_MITER_FROM_SG;
1102 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1103 host->sg = data->sg;
1104 host->part_buf_start = 0;
1105 host->part_buf_count = 0;
1107 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
1109 spin_lock_irqsave(&host->irq_lock, irqflags);
1110 temp = mci_readl(host, INTMASK);
1111 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
1112 mci_writel(host, INTMASK, temp);
1113 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1115 temp = mci_readl(host, CTRL);
1116 temp &= ~SDMMC_CTRL_DMA_ENABLE;
1117 mci_writel(host, CTRL, temp);
1120 * Use the initial fifoth_val for PIO mode.
1121 * If next issued data may be transfered by DMA mode,
1122 * prev_blksz should be invalidated.
1124 mci_writel(host, FIFOTH, host->fifoth_val);
1125 host->prev_blksz = 0;
1128 * Keep the current block size.
1129 * It will be used to decide whether to update
1130 * fifoth register next time.
1132 host->prev_blksz = data->blksz;
1136 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
1138 struct dw_mci *host = slot->host;
1139 unsigned long timeout = jiffies + msecs_to_jiffies(500);
1140 unsigned int cmd_status = 0;
1142 mci_writel(host, CMDARG, arg);
1143 wmb(); /* drain writebuffer */
1144 dw_mci_wait_while_busy(host, cmd);
1145 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
1147 while (time_before(jiffies, timeout)) {
1148 cmd_status = mci_readl(host, CMD);
1149 if (!(cmd_status & SDMMC_CMD_START))
1152 dev_err(&slot->mmc->class_dev,
1153 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
1154 cmd, arg, cmd_status);
1157 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
1159 struct dw_mci *host = slot->host;
1160 unsigned int clock = slot->clock;
1163 u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
1165 /* We must continue to set bit 28 in CMD until the change is complete */
1166 if (host->state == STATE_WAITING_CMD11_DONE)
1167 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
1170 mci_writel(host, CLKENA, 0);
1171 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1172 } else if (clock != host->current_speed || force_clkinit) {
1173 div = host->bus_hz / clock;
1174 if (host->bus_hz % clock && host->bus_hz > clock)
1176 * move the + 1 after the divide to prevent
1177 * over-clocking the card.
1181 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
1183 if (clock != slot->__clk_old || force_clkinit)
1184 dev_info(&slot->mmc->class_dev,
1185 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1186 slot->id, host->bus_hz, clock,
1187 div ? ((host->bus_hz / div) >> 1) :
1191 mci_writel(host, CLKENA, 0);
1192 mci_writel(host, CLKSRC, 0);
1195 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1197 /* set clock to desired speed */
1198 mci_writel(host, CLKDIV, div);
1201 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1203 /* enable clock; only low power if no SDIO */
1204 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
1205 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
1206 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1207 mci_writel(host, CLKENA, clk_en_a);
1210 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1212 /* keep the last clock value that was requested from core */
1213 slot->__clk_old = clock;
1216 host->current_speed = clock;
1218 /* Set the current slot bus width */
1219 mci_writel(host, CTYPE, (slot->ctype << slot->id));
1222 static void __dw_mci_start_request(struct dw_mci *host,
1223 struct dw_mci_slot *slot,
1224 struct mmc_command *cmd)
1226 struct mmc_request *mrq;
1227 struct mmc_data *data;
1232 host->cur_slot = slot;
1235 host->pending_events = 0;
1236 host->completed_events = 0;
1237 host->cmd_status = 0;
1238 host->data_status = 0;
1239 host->dir_status = 0;
1243 mci_writel(host, TMOUT, 0xFFFFFFFF);
1244 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1245 mci_writel(host, BLKSIZ, data->blksz);
1248 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1250 /* this is the first command, send the initialization clock */
1251 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1252 cmdflags |= SDMMC_CMD_INIT;
1255 dw_mci_submit_data(host, data);
1256 wmb(); /* drain writebuffer */
1259 dw_mci_start_command(host, cmd, cmdflags);
1261 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
1262 unsigned long irqflags;
1265 * Databook says to fail after 2ms w/ no response, but evidence
1266 * shows that sometimes the cmd11 interrupt takes over 130ms.
1267 * We'll set to 500ms, plus an extra jiffy just in case jiffies
1268 * is just about to roll over.
1270 * We do this whole thing under spinlock and only if the
1271 * command hasn't already completed (indicating the the irq
1272 * already ran so we don't want the timeout).
1274 spin_lock_irqsave(&host->irq_lock, irqflags);
1275 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1276 mod_timer(&host->cmd11_timer,
1277 jiffies + msecs_to_jiffies(500) + 1);
1278 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1282 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
1284 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
1287 static void dw_mci_start_request(struct dw_mci *host,
1288 struct dw_mci_slot *slot)
1290 struct mmc_request *mrq = slot->mrq;
1291 struct mmc_command *cmd;
1293 cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1294 __dw_mci_start_request(host, slot, cmd);
1297 /* must be called with host->lock held */
1298 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1299 struct mmc_request *mrq)
1301 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1306 if (host->state == STATE_WAITING_CMD11_DONE) {
1307 dev_warn(&slot->mmc->class_dev,
1308 "Voltage change didn't complete\n");
1310 * this case isn't expected to happen, so we can
1311 * either crash here or just try to continue on
1312 * in the closest possible state
1314 host->state = STATE_IDLE;
1317 if (host->state == STATE_IDLE) {
1318 host->state = STATE_SENDING_CMD;
1319 dw_mci_start_request(host, slot);
1321 list_add_tail(&slot->queue_node, &host->queue);
1325 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1327 struct dw_mci_slot *slot = mmc_priv(mmc);
1328 struct dw_mci *host = slot->host;
1333 * The check for card presence and queueing of the request must be
1334 * atomic, otherwise the card could be removed in between and the
1335 * request wouldn't fail until another card was inserted.
1338 if (!dw_mci_get_cd(mmc)) {
1339 mrq->cmd->error = -ENOMEDIUM;
1340 mmc_request_done(mmc, mrq);
1344 spin_lock_bh(&host->lock);
1346 dw_mci_queue_request(host, slot, mrq);
1348 spin_unlock_bh(&host->lock);
1351 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1353 struct dw_mci_slot *slot = mmc_priv(mmc);
1354 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1358 switch (ios->bus_width) {
1359 case MMC_BUS_WIDTH_4:
1360 slot->ctype = SDMMC_CTYPE_4BIT;
1362 case MMC_BUS_WIDTH_8:
1363 slot->ctype = SDMMC_CTYPE_8BIT;
1366 /* set default 1 bit mode */
1367 slot->ctype = SDMMC_CTYPE_1BIT;
1370 regs = mci_readl(slot->host, UHS_REG);
1373 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
1374 ios->timing == MMC_TIMING_UHS_DDR50 ||
1375 ios->timing == MMC_TIMING_MMC_HS400)
1376 regs |= ((0x1 << slot->id) << 16);
1378 regs &= ~((0x1 << slot->id) << 16);
1380 mci_writel(slot->host, UHS_REG, regs);
1381 slot->host->timing = ios->timing;
1384 * Use mirror of ios->clock to prevent race with mmc
1385 * core ios update when finding the minimum.
1387 slot->clock = ios->clock;
1389 if (drv_data && drv_data->set_ios)
1390 drv_data->set_ios(slot->host, ios);
1392 switch (ios->power_mode) {
1394 if (!IS_ERR(mmc->supply.vmmc)) {
1395 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1398 dev_err(slot->host->dev,
1399 "failed to enable vmmc regulator\n");
1400 /*return, if failed turn on vmmc*/
1404 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1405 regs = mci_readl(slot->host, PWREN);
1406 regs |= (1 << slot->id);
1407 mci_writel(slot->host, PWREN, regs);
1410 if (!slot->host->vqmmc_enabled) {
1411 if (!IS_ERR(mmc->supply.vqmmc)) {
1412 ret = regulator_enable(mmc->supply.vqmmc);
1414 dev_err(slot->host->dev,
1415 "failed to enable vqmmc\n");
1417 slot->host->vqmmc_enabled = true;
1420 /* Keep track so we don't reset again */
1421 slot->host->vqmmc_enabled = true;
1424 /* Reset our state machine after powering on */
1425 dw_mci_ctrl_reset(slot->host,
1426 SDMMC_CTRL_ALL_RESET_FLAGS);
1429 /* Adjust clock / bus width after power is up */
1430 dw_mci_setup_bus(slot, false);
1434 /* Turn clock off before power goes down */
1435 dw_mci_setup_bus(slot, false);
1437 if (!IS_ERR(mmc->supply.vmmc))
1438 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1440 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
1441 regulator_disable(mmc->supply.vqmmc);
1442 slot->host->vqmmc_enabled = false;
1444 regs = mci_readl(slot->host, PWREN);
1445 regs &= ~(1 << slot->id);
1446 mci_writel(slot->host, PWREN, regs);
1452 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1453 slot->host->state = STATE_IDLE;
1456 static int dw_mci_card_busy(struct mmc_host *mmc)
1458 struct dw_mci_slot *slot = mmc_priv(mmc);
1462 * Check the busy bit which is low when DAT[3:0]
1463 * (the data lines) are 0000
1465 status = mci_readl(slot->host, STATUS);
1467 return !!(status & SDMMC_STATUS_BUSY);
1470 static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1472 struct dw_mci_slot *slot = mmc_priv(mmc);
1473 struct dw_mci *host = slot->host;
1474 const struct dw_mci_drv_data *drv_data = host->drv_data;
1476 u32 v18 = SDMMC_UHS_18V << slot->id;
1479 if (drv_data && drv_data->switch_voltage)
1480 return drv_data->switch_voltage(mmc, ios);
1483 * Program the voltage. Note that some instances of dw_mmc may use
1484 * the UHS_REG for this. For other instances (like exynos) the UHS_REG
1485 * does no harm but you need to set the regulator directly. Try both.
1487 uhs = mci_readl(host, UHS_REG);
1488 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1493 if (!IS_ERR(mmc->supply.vqmmc)) {
1494 ret = mmc_regulator_set_vqmmc(mmc, ios);
1497 dev_dbg(&mmc->class_dev,
1498 "Regulator set error %d - %s V\n",
1499 ret, uhs & v18 ? "1.8" : "3.3");
1503 mci_writel(host, UHS_REG, uhs);
1508 static int dw_mci_get_ro(struct mmc_host *mmc)
1511 struct dw_mci_slot *slot = mmc_priv(mmc);
1512 int gpio_ro = mmc_gpio_get_ro(mmc);
1514 /* Use platform get_ro function, else try on board write protect */
1516 read_only = gpio_ro;
1519 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1521 dev_dbg(&mmc->class_dev, "card is %s\n",
1522 read_only ? "read-only" : "read-write");
1527 static int dw_mci_get_cd(struct mmc_host *mmc)
1530 struct dw_mci_slot *slot = mmc_priv(mmc);
1531 struct dw_mci *host = slot->host;
1532 int gpio_cd = mmc_gpio_get_cd(mmc);
1534 /* Use platform get_cd function, else try onboard card detect */
1535 if ((mmc->caps & MMC_CAP_NEEDS_POLL) || !mmc_card_is_removable(mmc))
1537 else if (gpio_cd >= 0)
1540 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
1543 spin_lock_bh(&host->lock);
1544 if (present && !test_and_set_bit(DW_MMC_CARD_PRESENT, &slot->flags))
1545 dev_dbg(&mmc->class_dev, "card is present\n");
1546 else if (!test_and_clear_bit(DW_MMC_CARD_PRESENT, &slot->flags))
1547 dev_dbg(&mmc->class_dev, "card is not present\n");
1548 spin_unlock_bh(&host->lock);
1553 static void dw_mci_hw_reset(struct mmc_host *mmc)
1555 struct dw_mci_slot *slot = mmc_priv(mmc);
1556 struct dw_mci *host = slot->host;
1559 if (host->use_dma == TRANS_MODE_IDMAC)
1560 dw_mci_idmac_reset(host);
1562 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET |
1563 SDMMC_CTRL_FIFO_RESET))
1567 * According to eMMC spec, card reset procedure:
1568 * tRstW >= 1us: RST_n pulse width
1569 * tRSCA >= 200us: RST_n to Command time
1570 * tRSTH >= 1us: RST_n high period
1572 reset = mci_readl(host, RST_N);
1573 reset &= ~(SDMMC_RST_HWACTIVE << slot->id);
1574 mci_writel(host, RST_N, reset);
1576 reset |= SDMMC_RST_HWACTIVE << slot->id;
1577 mci_writel(host, RST_N, reset);
1578 usleep_range(200, 300);
1581 static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card)
1583 struct dw_mci_slot *slot = mmc_priv(mmc);
1584 struct dw_mci *host = slot->host;
1587 * Low power mode will stop the card clock when idle. According to the
1588 * description of the CLKENA register we should disable low power mode
1589 * for SDIO cards if we need SDIO interrupts to work.
1591 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1592 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1596 clk_en_a_old = mci_readl(host, CLKENA);
1598 if (card->type == MMC_TYPE_SDIO ||
1599 card->type == MMC_TYPE_SD_COMBO) {
1600 set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1601 clk_en_a = clk_en_a_old & ~clken_low_pwr;
1603 clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1604 clk_en_a = clk_en_a_old | clken_low_pwr;
1607 if (clk_en_a != clk_en_a_old) {
1608 mci_writel(host, CLKENA, clk_en_a);
1609 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1610 SDMMC_CMD_PRV_DAT_WAIT, 0);
1615 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1617 struct dw_mci_slot *slot = mmc_priv(mmc);
1618 struct dw_mci *host = slot->host;
1619 unsigned long irqflags;
1622 spin_lock_irqsave(&host->irq_lock, irqflags);
1624 /* Enable/disable Slot Specific SDIO interrupt */
1625 int_mask = mci_readl(host, INTMASK);
1627 int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
1629 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
1630 mci_writel(host, INTMASK, int_mask);
1632 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1635 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1637 struct dw_mci_slot *slot = mmc_priv(mmc);
1638 struct dw_mci *host = slot->host;
1639 const struct dw_mci_drv_data *drv_data = host->drv_data;
1642 if (drv_data && drv_data->execute_tuning)
1643 err = drv_data->execute_tuning(slot, opcode);
1647 static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc,
1648 struct mmc_ios *ios)
1650 struct dw_mci_slot *slot = mmc_priv(mmc);
1651 struct dw_mci *host = slot->host;
1652 const struct dw_mci_drv_data *drv_data = host->drv_data;
1654 if (drv_data && drv_data->prepare_hs400_tuning)
1655 return drv_data->prepare_hs400_tuning(host, ios);
1660 static const struct mmc_host_ops dw_mci_ops = {
1661 .request = dw_mci_request,
1662 .pre_req = dw_mci_pre_req,
1663 .post_req = dw_mci_post_req,
1664 .set_ios = dw_mci_set_ios,
1665 .get_ro = dw_mci_get_ro,
1666 .get_cd = dw_mci_get_cd,
1667 .hw_reset = dw_mci_hw_reset,
1668 .enable_sdio_irq = dw_mci_enable_sdio_irq,
1669 .execute_tuning = dw_mci_execute_tuning,
1670 .card_busy = dw_mci_card_busy,
1671 .start_signal_voltage_switch = dw_mci_switch_voltage,
1672 .init_card = dw_mci_init_card,
1673 .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning,
1676 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1677 __releases(&host->lock)
1678 __acquires(&host->lock)
1680 struct dw_mci_slot *slot;
1681 struct mmc_host *prev_mmc = host->cur_slot->mmc;
1683 WARN_ON(host->cmd || host->data);
1685 host->cur_slot->mrq = NULL;
1687 if (!list_empty(&host->queue)) {
1688 slot = list_entry(host->queue.next,
1689 struct dw_mci_slot, queue_node);
1690 list_del(&slot->queue_node);
1691 dev_vdbg(host->dev, "list not empty: %s is next\n",
1692 mmc_hostname(slot->mmc));
1693 host->state = STATE_SENDING_CMD;
1694 dw_mci_start_request(host, slot);
1696 dev_vdbg(host->dev, "list empty\n");
1698 if (host->state == STATE_SENDING_CMD11)
1699 host->state = STATE_WAITING_CMD11_DONE;
1701 host->state = STATE_IDLE;
1704 spin_unlock(&host->lock);
1705 mmc_request_done(prev_mmc, mrq);
1706 spin_lock(&host->lock);
1709 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
1711 u32 status = host->cmd_status;
1713 host->cmd_status = 0;
1715 /* Read the response from the card (up to 16 bytes) */
1716 if (cmd->flags & MMC_RSP_PRESENT) {
1717 if (cmd->flags & MMC_RSP_136) {
1718 cmd->resp[3] = mci_readl(host, RESP0);
1719 cmd->resp[2] = mci_readl(host, RESP1);
1720 cmd->resp[1] = mci_readl(host, RESP2);
1721 cmd->resp[0] = mci_readl(host, RESP3);
1723 cmd->resp[0] = mci_readl(host, RESP0);
1730 if (status & SDMMC_INT_RTO)
1731 cmd->error = -ETIMEDOUT;
1732 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1733 cmd->error = -EILSEQ;
1734 else if (status & SDMMC_INT_RESP_ERR)
1742 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1744 u32 status = host->data_status;
1746 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1747 if (status & SDMMC_INT_DRTO) {
1748 data->error = -ETIMEDOUT;
1749 } else if (status & SDMMC_INT_DCRC) {
1750 data->error = -EILSEQ;
1751 } else if (status & SDMMC_INT_EBE) {
1752 if (host->dir_status ==
1753 DW_MCI_SEND_STATUS) {
1755 * No data CRC status was returned.
1756 * The number of bytes transferred
1757 * will be exaggerated in PIO mode.
1759 data->bytes_xfered = 0;
1760 data->error = -ETIMEDOUT;
1761 } else if (host->dir_status ==
1762 DW_MCI_RECV_STATUS) {
1763 data->error = -EILSEQ;
1766 /* SDMMC_INT_SBE is included */
1767 data->error = -EILSEQ;
1770 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
1773 * After an error, there may be data lingering
1778 data->bytes_xfered = data->blocks * data->blksz;
1785 static void dw_mci_set_drto(struct dw_mci *host)
1787 unsigned int drto_clks;
1788 unsigned int drto_ms;
1790 drto_clks = mci_readl(host, TMOUT) >> 8;
1791 drto_ms = DIV_ROUND_UP(drto_clks, host->bus_hz / 1000);
1793 /* add a bit spare time */
1796 mod_timer(&host->dto_timer, jiffies + msecs_to_jiffies(drto_ms));
1799 static void dw_mci_tasklet_func(unsigned long priv)
1801 struct dw_mci *host = (struct dw_mci *)priv;
1802 struct mmc_data *data;
1803 struct mmc_command *cmd;
1804 struct mmc_request *mrq;
1805 enum dw_mci_state state;
1806 enum dw_mci_state prev_state;
1809 spin_lock(&host->lock);
1811 state = host->state;
1820 case STATE_WAITING_CMD11_DONE:
1823 case STATE_SENDING_CMD11:
1824 case STATE_SENDING_CMD:
1825 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1826 &host->pending_events))
1831 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
1832 err = dw_mci_command_complete(host, cmd);
1833 if (cmd == mrq->sbc && !err) {
1834 prev_state = state = STATE_SENDING_CMD;
1835 __dw_mci_start_request(host, host->cur_slot,
1840 if (cmd->data && err) {
1842 * During UHS tuning sequence, sending the stop
1843 * command after the response CRC error would
1844 * throw the system into a confused state
1845 * causing all future tuning phases to report
1848 * In such case controller will move into a data
1849 * transfer state after a response error or
1850 * response CRC error. Let's let that finish
1851 * before trying to send a stop, so we'll go to
1852 * STATE_SENDING_DATA.
1854 * Although letting the data transfer take place
1855 * will waste a bit of time (we already know
1856 * the command was bad), it can't cause any
1857 * errors since it's possible it would have
1858 * taken place anyway if this tasklet got
1859 * delayed. Allowing the transfer to take place
1860 * avoids races and keeps things simple.
1862 if ((err != -ETIMEDOUT) &&
1863 (cmd->opcode == MMC_SEND_TUNING_BLOCK)) {
1864 state = STATE_SENDING_DATA;
1868 dw_mci_stop_dma(host);
1869 send_stop_abort(host, data);
1870 state = STATE_SENDING_STOP;
1874 if (!cmd->data || err) {
1875 dw_mci_request_end(host, mrq);
1879 prev_state = state = STATE_SENDING_DATA;
1882 case STATE_SENDING_DATA:
1884 * We could get a data error and never a transfer
1885 * complete so we'd better check for it here.
1887 * Note that we don't really care if we also got a
1888 * transfer complete; stopping the DMA and sending an
1891 if (test_and_clear_bit(EVENT_DATA_ERROR,
1892 &host->pending_events)) {
1893 dw_mci_stop_dma(host);
1895 !(host->data_status & (SDMMC_INT_DRTO |
1897 send_stop_abort(host, data);
1898 state = STATE_DATA_ERROR;
1902 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1903 &host->pending_events)) {
1905 * If all data-related interrupts don't come
1906 * within the given time in reading data state.
1908 if (host->dir_status == DW_MCI_RECV_STATUS)
1909 dw_mci_set_drto(host);
1913 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
1916 * Handle an EVENT_DATA_ERROR that might have shown up
1917 * before the transfer completed. This might not have
1918 * been caught by the check above because the interrupt
1919 * could have gone off between the previous check and
1920 * the check for transfer complete.
1922 * Technically this ought not be needed assuming we
1923 * get a DATA_COMPLETE eventually (we'll notice the
1924 * error and end the request), but it shouldn't hurt.
1926 * This has the advantage of sending the stop command.
1928 if (test_and_clear_bit(EVENT_DATA_ERROR,
1929 &host->pending_events)) {
1930 dw_mci_stop_dma(host);
1932 !(host->data_status & (SDMMC_INT_DRTO |
1934 send_stop_abort(host, data);
1935 state = STATE_DATA_ERROR;
1938 prev_state = state = STATE_DATA_BUSY;
1942 case STATE_DATA_BUSY:
1943 if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
1944 &host->pending_events)) {
1946 * If data error interrupt comes but data over
1947 * interrupt doesn't come within the given time.
1948 * in reading data state.
1950 if (host->dir_status == DW_MCI_RECV_STATUS)
1951 dw_mci_set_drto(host);
1956 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
1957 err = dw_mci_data_complete(host, data);
1960 if (!data->stop || mrq->sbc) {
1961 if (mrq->sbc && data->stop)
1962 data->stop->error = 0;
1963 dw_mci_request_end(host, mrq);
1967 /* stop command for open-ended transfer*/
1969 send_stop_abort(host, data);
1972 * If we don't have a command complete now we'll
1973 * never get one since we just reset everything;
1974 * better end the request.
1976 * If we do have a command complete we'll fall
1977 * through to the SENDING_STOP command and
1978 * everything will be peachy keen.
1980 if (!test_bit(EVENT_CMD_COMPLETE,
1981 &host->pending_events)) {
1983 dw_mci_request_end(host, mrq);
1989 * If err has non-zero,
1990 * stop-abort command has been already issued.
1992 prev_state = state = STATE_SENDING_STOP;
1996 case STATE_SENDING_STOP:
1997 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1998 &host->pending_events))
2001 /* CMD error in data command */
2002 if (mrq->cmd->error && mrq->data)
2009 dw_mci_command_complete(host, mrq->stop);
2011 host->cmd_status = 0;
2013 dw_mci_request_end(host, mrq);
2016 case STATE_DATA_ERROR:
2017 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2018 &host->pending_events))
2021 state = STATE_DATA_BUSY;
2024 } while (state != prev_state);
2026 host->state = state;
2028 spin_unlock(&host->lock);
2032 /* push final bytes to part_buf, only use during push */
2033 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
2035 memcpy((void *)&host->part_buf, buf, cnt);
2036 host->part_buf_count = cnt;
2039 /* append bytes to part_buf, only use during push */
2040 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
2042 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
2043 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
2044 host->part_buf_count += cnt;
2048 /* pull first bytes from part_buf, only use during pull */
2049 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
2051 cnt = min_t(int, cnt, host->part_buf_count);
2053 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
2055 host->part_buf_count -= cnt;
2056 host->part_buf_start += cnt;
2061 /* pull final bytes from the part_buf, assuming it's just been filled */
2062 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
2064 memcpy(buf, &host->part_buf, cnt);
2065 host->part_buf_start = cnt;
2066 host->part_buf_count = (1 << host->data_shift) - cnt;
2069 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
2071 struct mmc_data *data = host->data;
2074 /* try and push anything in the part_buf */
2075 if (unlikely(host->part_buf_count)) {
2076 int len = dw_mci_push_part_bytes(host, buf, cnt);
2080 if (host->part_buf_count == 2) {
2081 mci_fifo_writew(host->fifo_reg, host->part_buf16);
2082 host->part_buf_count = 0;
2085 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2086 if (unlikely((unsigned long)buf & 0x1)) {
2088 u16 aligned_buf[64];
2089 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2090 int items = len >> 1;
2092 /* memcpy from input buffer into aligned buffer */
2093 memcpy(aligned_buf, buf, len);
2096 /* push data from aligned buffer into fifo */
2097 for (i = 0; i < items; ++i)
2098 mci_fifo_writew(host->fifo_reg, aligned_buf[i]);
2105 for (; cnt >= 2; cnt -= 2)
2106 mci_fifo_writew(host->fifo_reg, *pdata++);
2109 /* put anything remaining in the part_buf */
2111 dw_mci_set_part_bytes(host, buf, cnt);
2112 /* Push data if we have reached the expected data length */
2113 if ((data->bytes_xfered + init_cnt) ==
2114 (data->blksz * data->blocks))
2115 mci_fifo_writew(host->fifo_reg, host->part_buf16);
2119 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2121 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2122 if (unlikely((unsigned long)buf & 0x1)) {
2124 /* pull data from fifo into aligned buffer */
2125 u16 aligned_buf[64];
2126 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2127 int items = len >> 1;
2130 for (i = 0; i < items; ++i)
2131 aligned_buf[i] = mci_fifo_readw(host->fifo_reg);
2132 /* memcpy from aligned buffer into output buffer */
2133 memcpy(buf, aligned_buf, len);
2142 for (; cnt >= 2; cnt -= 2)
2143 *pdata++ = mci_fifo_readw(host->fifo_reg);
2147 host->part_buf16 = mci_fifo_readw(host->fifo_reg);
2148 dw_mci_pull_final_bytes(host, buf, cnt);
2152 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2154 struct mmc_data *data = host->data;
2157 /* try and push anything in the part_buf */
2158 if (unlikely(host->part_buf_count)) {
2159 int len = dw_mci_push_part_bytes(host, buf, cnt);
2163 if (host->part_buf_count == 4) {
2164 mci_fifo_writel(host->fifo_reg, host->part_buf32);
2165 host->part_buf_count = 0;
2168 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2169 if (unlikely((unsigned long)buf & 0x3)) {
2171 u32 aligned_buf[32];
2172 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2173 int items = len >> 2;
2175 /* memcpy from input buffer into aligned buffer */
2176 memcpy(aligned_buf, buf, len);
2179 /* push data from aligned buffer into fifo */
2180 for (i = 0; i < items; ++i)
2181 mci_fifo_writel(host->fifo_reg, aligned_buf[i]);
2188 for (; cnt >= 4; cnt -= 4)
2189 mci_fifo_writel(host->fifo_reg, *pdata++);
2192 /* put anything remaining in the part_buf */
2194 dw_mci_set_part_bytes(host, buf, cnt);
2195 /* Push data if we have reached the expected data length */
2196 if ((data->bytes_xfered + init_cnt) ==
2197 (data->blksz * data->blocks))
2198 mci_fifo_writel(host->fifo_reg, host->part_buf32);
2202 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2204 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2205 if (unlikely((unsigned long)buf & 0x3)) {
2207 /* pull data from fifo into aligned buffer */
2208 u32 aligned_buf[32];
2209 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2210 int items = len >> 2;
2213 for (i = 0; i < items; ++i)
2214 aligned_buf[i] = mci_fifo_readl(host->fifo_reg);
2215 /* memcpy from aligned buffer into output buffer */
2216 memcpy(buf, aligned_buf, len);
2225 for (; cnt >= 4; cnt -= 4)
2226 *pdata++ = mci_fifo_readl(host->fifo_reg);
2230 host->part_buf32 = mci_fifo_readl(host->fifo_reg);
2231 dw_mci_pull_final_bytes(host, buf, cnt);
2235 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2237 struct mmc_data *data = host->data;
2240 /* try and push anything in the part_buf */
2241 if (unlikely(host->part_buf_count)) {
2242 int len = dw_mci_push_part_bytes(host, buf, cnt);
2247 if (host->part_buf_count == 8) {
2248 mci_fifo_writeq(host->fifo_reg, host->part_buf);
2249 host->part_buf_count = 0;
2252 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2253 if (unlikely((unsigned long)buf & 0x7)) {
2255 u64 aligned_buf[16];
2256 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2257 int items = len >> 3;
2259 /* memcpy from input buffer into aligned buffer */
2260 memcpy(aligned_buf, buf, len);
2263 /* push data from aligned buffer into fifo */
2264 for (i = 0; i < items; ++i)
2265 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]);
2272 for (; cnt >= 8; cnt -= 8)
2273 mci_fifo_writeq(host->fifo_reg, *pdata++);
2276 /* put anything remaining in the part_buf */
2278 dw_mci_set_part_bytes(host, buf, cnt);
2279 /* Push data if we have reached the expected data length */
2280 if ((data->bytes_xfered + init_cnt) ==
2281 (data->blksz * data->blocks))
2282 mci_fifo_writeq(host->fifo_reg, host->part_buf);
2286 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2288 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2289 if (unlikely((unsigned long)buf & 0x7)) {
2291 /* pull data from fifo into aligned buffer */
2292 u64 aligned_buf[16];
2293 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2294 int items = len >> 3;
2297 for (i = 0; i < items; ++i)
2298 aligned_buf[i] = mci_fifo_readq(host->fifo_reg);
2300 /* memcpy from aligned buffer into output buffer */
2301 memcpy(buf, aligned_buf, len);
2310 for (; cnt >= 8; cnt -= 8)
2311 *pdata++ = mci_fifo_readq(host->fifo_reg);
2315 host->part_buf = mci_fifo_readq(host->fifo_reg);
2316 dw_mci_pull_final_bytes(host, buf, cnt);
2320 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2324 /* get remaining partial bytes */
2325 len = dw_mci_pull_part_bytes(host, buf, cnt);
2326 if (unlikely(len == cnt))
2331 /* get the rest of the data */
2332 host->pull_data(host, buf, cnt);
2335 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
2337 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2339 unsigned int offset;
2340 struct mmc_data *data = host->data;
2341 int shift = host->data_shift;
2344 unsigned int remain, fcnt;
2347 if (!sg_miter_next(sg_miter))
2350 host->sg = sg_miter->piter.sg;
2351 buf = sg_miter->addr;
2352 remain = sg_miter->length;
2356 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2357 << shift) + host->part_buf_count;
2358 len = min(remain, fcnt);
2361 dw_mci_pull_data(host, (void *)(buf + offset), len);
2362 data->bytes_xfered += len;
2367 sg_miter->consumed = offset;
2368 status = mci_readl(host, MINTSTS);
2369 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2370 /* if the RXDR is ready read again */
2371 } while ((status & SDMMC_INT_RXDR) ||
2372 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
2375 if (!sg_miter_next(sg_miter))
2377 sg_miter->consumed = 0;
2379 sg_miter_stop(sg_miter);
2383 sg_miter_stop(sg_miter);
2385 smp_wmb(); /* drain writebuffer */
2386 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2389 static void dw_mci_write_data_pio(struct dw_mci *host)
2391 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2393 unsigned int offset;
2394 struct mmc_data *data = host->data;
2395 int shift = host->data_shift;
2398 unsigned int fifo_depth = host->fifo_depth;
2399 unsigned int remain, fcnt;
2402 if (!sg_miter_next(sg_miter))
2405 host->sg = sg_miter->piter.sg;
2406 buf = sg_miter->addr;
2407 remain = sg_miter->length;
2411 fcnt = ((fifo_depth -
2412 SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2413 << shift) - host->part_buf_count;
2414 len = min(remain, fcnt);
2417 host->push_data(host, (void *)(buf + offset), len);
2418 data->bytes_xfered += len;
2423 sg_miter->consumed = offset;
2424 status = mci_readl(host, MINTSTS);
2425 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2426 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
2429 if (!sg_miter_next(sg_miter))
2431 sg_miter->consumed = 0;
2433 sg_miter_stop(sg_miter);
2437 sg_miter_stop(sg_miter);
2439 smp_wmb(); /* drain writebuffer */
2440 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2443 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2445 if (!host->cmd_status)
2446 host->cmd_status = status;
2448 smp_wmb(); /* drain writebuffer */
2450 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2451 tasklet_schedule(&host->tasklet);
2454 static void dw_mci_handle_cd(struct dw_mci *host)
2458 for (i = 0; i < host->num_slots; i++) {
2459 struct dw_mci_slot *slot = host->slot[i];
2464 if (slot->mmc->ops->card_event)
2465 slot->mmc->ops->card_event(slot->mmc);
2466 mmc_detect_change(slot->mmc,
2467 msecs_to_jiffies(host->pdata->detect_delay_ms));
2471 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2473 struct dw_mci *host = dev_id;
2477 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2480 /* Check volt switch first, since it can look like an error */
2481 if ((host->state == STATE_SENDING_CMD11) &&
2482 (pending & SDMMC_INT_VOLT_SWITCH)) {
2483 unsigned long irqflags;
2485 mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
2486 pending &= ~SDMMC_INT_VOLT_SWITCH;
2489 * Hold the lock; we know cmd11_timer can't be kicked
2490 * off after the lock is released, so safe to delete.
2492 spin_lock_irqsave(&host->irq_lock, irqflags);
2493 dw_mci_cmd_interrupt(host, pending);
2494 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2496 del_timer(&host->cmd11_timer);
2499 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2500 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
2501 host->cmd_status = pending;
2502 smp_wmb(); /* drain writebuffer */
2503 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2506 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2507 /* if there is an error report DATA_ERROR */
2508 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2509 host->data_status = pending;
2510 smp_wmb(); /* drain writebuffer */
2511 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2512 tasklet_schedule(&host->tasklet);
2515 if (pending & SDMMC_INT_DATA_OVER) {
2516 del_timer(&host->dto_timer);
2518 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2519 if (!host->data_status)
2520 host->data_status = pending;
2521 smp_wmb(); /* drain writebuffer */
2522 if (host->dir_status == DW_MCI_RECV_STATUS) {
2523 if (host->sg != NULL)
2524 dw_mci_read_data_pio(host, true);
2526 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2527 tasklet_schedule(&host->tasklet);
2530 if (pending & SDMMC_INT_RXDR) {
2531 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2532 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2533 dw_mci_read_data_pio(host, false);
2536 if (pending & SDMMC_INT_TXDR) {
2537 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2538 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2539 dw_mci_write_data_pio(host);
2542 if (pending & SDMMC_INT_CMD_DONE) {
2543 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2544 dw_mci_cmd_interrupt(host, pending);
2547 if (pending & SDMMC_INT_CD) {
2548 mci_writel(host, RINTSTS, SDMMC_INT_CD);
2549 dw_mci_handle_cd(host);
2552 /* Handle SDIO Interrupts */
2553 for (i = 0; i < host->num_slots; i++) {
2554 struct dw_mci_slot *slot = host->slot[i];
2559 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
2560 mci_writel(host, RINTSTS,
2561 SDMMC_INT_SDIO(slot->sdio_id));
2562 mmc_signal_sdio_irq(slot->mmc);
2568 if (host->use_dma != TRANS_MODE_IDMAC)
2571 /* Handle IDMA interrupts */
2572 if (host->dma_64bit_address == 1) {
2573 pending = mci_readl(host, IDSTS64);
2574 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2575 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2576 SDMMC_IDMAC_INT_RI);
2577 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
2578 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2579 host->dma_ops->complete((void *)host);
2582 pending = mci_readl(host, IDSTS);
2583 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2584 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2585 SDMMC_IDMAC_INT_RI);
2586 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
2587 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2588 host->dma_ops->complete((void *)host);
2595 static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
2597 struct mmc_host *mmc;
2598 struct dw_mci_slot *slot;
2599 const struct dw_mci_drv_data *drv_data = host->drv_data;
2603 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
2607 slot = mmc_priv(mmc);
2609 slot->sdio_id = host->sdio_id0 + id;
2612 host->slot[id] = slot;
2614 mmc->ops = &dw_mci_ops;
2615 if (of_property_read_u32_array(host->dev->of_node,
2616 "clock-freq-min-max", freq, 2)) {
2617 mmc->f_min = DW_MCI_FREQ_MIN;
2618 mmc->f_max = DW_MCI_FREQ_MAX;
2620 mmc->f_min = freq[0];
2621 mmc->f_max = freq[1];
2624 /*if there are external regulators, get them*/
2625 ret = mmc_regulator_get_supply(mmc);
2626 if (ret == -EPROBE_DEFER)
2627 goto err_host_allocated;
2629 if (!mmc->ocr_avail)
2630 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2632 if (host->pdata->caps)
2633 mmc->caps = host->pdata->caps;
2636 * Support MMC_CAP_ERASE by default.
2637 * It needs to use trim/discard/erase commands.
2639 mmc->caps |= MMC_CAP_ERASE;
2641 if (host->pdata->pm_caps)
2642 mmc->pm_caps = host->pdata->pm_caps;
2644 if (host->dev->of_node) {
2645 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2649 ctrl_id = to_platform_device(host->dev)->id;
2651 if (drv_data && drv_data->caps)
2652 mmc->caps |= drv_data->caps[ctrl_id];
2654 if (host->pdata->caps2)
2655 mmc->caps2 = host->pdata->caps2;
2657 ret = mmc_of_parse(mmc);
2659 goto err_host_allocated;
2661 /* Useful defaults if platform data is unset. */
2662 if (host->use_dma == TRANS_MODE_IDMAC) {
2663 mmc->max_segs = host->ring_size;
2664 mmc->max_blk_size = 65535;
2665 mmc->max_seg_size = 0x1000;
2666 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2667 mmc->max_blk_count = mmc->max_req_size / 512;
2668 } else if (host->use_dma == TRANS_MODE_EDMAC) {
2670 mmc->max_blk_size = 65535;
2671 mmc->max_blk_count = 65535;
2673 mmc->max_blk_size * mmc->max_blk_count;
2674 mmc->max_seg_size = mmc->max_req_size;
2676 /* TRANS_MODE_PIO */
2678 mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */
2679 mmc->max_blk_count = 512;
2680 mmc->max_req_size = mmc->max_blk_size *
2682 mmc->max_seg_size = mmc->max_req_size;
2687 ret = mmc_add_host(mmc);
2689 goto err_host_allocated;
2691 #if defined(CONFIG_DEBUG_FS)
2692 dw_mci_init_debugfs(slot);
2702 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
2704 /* Debugfs stuff is cleaned up by mmc core */
2705 mmc_remove_host(slot->mmc);
2706 slot->host->slot[id] = NULL;
2707 mmc_free_host(slot->mmc);
2710 static void dw_mci_init_dma(struct dw_mci *host)
2713 struct device *dev = host->dev;
2714 struct device_node *np = dev->of_node;
2717 * Check tansfer mode from HCON[17:16]
2718 * Clear the ambiguous description of dw_mmc databook:
2719 * 2b'00: No DMA Interface -> Actually means using Internal DMA block
2720 * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block
2721 * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block
2722 * 2b'11: Non DW DMA Interface -> pio only
2723 * Compared to DesignWare DMA Interface, Generic DMA Interface has a
2724 * simpler request/acknowledge handshake mechanism and both of them
2725 * are regarded as external dma master for dw_mmc.
2727 host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
2728 if (host->use_dma == DMA_INTERFACE_IDMA) {
2729 host->use_dma = TRANS_MODE_IDMAC;
2730 } else if (host->use_dma == DMA_INTERFACE_DWDMA ||
2731 host->use_dma == DMA_INTERFACE_GDMA) {
2732 host->use_dma = TRANS_MODE_EDMAC;
2737 /* Determine which DMA interface to use */
2738 if (host->use_dma == TRANS_MODE_IDMAC) {
2740 * Check ADDR_CONFIG bit in HCON to find
2741 * IDMAC address bus width
2743 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
2745 if (addr_config == 1) {
2746 /* host supports IDMAC in 64-bit address mode */
2747 host->dma_64bit_address = 1;
2749 "IDMAC supports 64-bit address mode.\n");
2750 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
2751 dma_set_coherent_mask(host->dev,
2754 /* host supports IDMAC in 32-bit address mode */
2755 host->dma_64bit_address = 0;
2757 "IDMAC supports 32-bit address mode.\n");
2760 /* Alloc memory for sg translation */
2761 host->sg_cpu = dmam_alloc_coherent(host->dev,
2763 &host->sg_dma, GFP_KERNEL);
2764 if (!host->sg_cpu) {
2766 "%s: could not alloc DMA memory\n",
2771 host->dma_ops = &dw_mci_idmac_ops;
2772 dev_info(host->dev, "Using internal DMA controller.\n");
2774 /* TRANS_MODE_EDMAC: check dma bindings again */
2775 if ((of_property_count_strings(np, "dma-names") < 0) ||
2776 (!of_find_property(np, "dmas", NULL))) {
2779 host->dma_ops = &dw_mci_edmac_ops;
2780 dev_info(host->dev, "Using external DMA controller.\n");
2783 if (host->dma_ops->init && host->dma_ops->start &&
2784 host->dma_ops->stop && host->dma_ops->cleanup) {
2785 if (host->dma_ops->init(host)) {
2786 dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n",
2791 dev_err(host->dev, "DMA initialization not found.\n");
2798 dev_info(host->dev, "Using PIO mode.\n");
2799 host->use_dma = TRANS_MODE_PIO;
2802 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
2804 unsigned long timeout = jiffies + msecs_to_jiffies(500);
2807 ctrl = mci_readl(host, CTRL);
2809 mci_writel(host, CTRL, ctrl);
2811 /* wait till resets clear */
2813 ctrl = mci_readl(host, CTRL);
2814 if (!(ctrl & reset))
2816 } while (time_before(jiffies, timeout));
2819 "Timeout resetting block (ctrl reset %#x)\n",
2825 static bool dw_mci_reset(struct dw_mci *host)
2827 u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
2831 * Reseting generates a block interrupt, hence setting
2832 * the scatter-gather pointer to NULL.
2835 sg_miter_stop(&host->sg_miter);
2840 flags |= SDMMC_CTRL_DMA_RESET;
2842 if (dw_mci_ctrl_reset(host, flags)) {
2844 * In all cases we clear the RAWINTS register to clear any
2847 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2849 /* if using dma we wait for dma_req to clear */
2850 if (host->use_dma) {
2851 unsigned long timeout = jiffies + msecs_to_jiffies(500);
2855 status = mci_readl(host, STATUS);
2856 if (!(status & SDMMC_STATUS_DMA_REQ))
2859 } while (time_before(jiffies, timeout));
2861 if (status & SDMMC_STATUS_DMA_REQ) {
2863 "%s: Timeout waiting for dma_req to clear during reset\n",
2868 /* when using DMA next we reset the fifo again */
2869 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
2873 /* if the controller reset bit did clear, then set clock regs */
2874 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
2876 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
2882 if (host->use_dma == TRANS_MODE_IDMAC)
2883 /* It is also recommended that we reset and reprogram idmac */
2884 dw_mci_idmac_reset(host);
2889 /* After a CTRL reset we need to have CIU set clock registers */
2890 mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0);
2895 static void dw_mci_cmd11_timer(unsigned long arg)
2897 struct dw_mci *host = (struct dw_mci *)arg;
2899 if (host->state != STATE_SENDING_CMD11) {
2900 dev_warn(host->dev, "Unexpected CMD11 timeout\n");
2904 host->cmd_status = SDMMC_INT_RTO;
2905 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2906 tasklet_schedule(&host->tasklet);
2909 static void dw_mci_dto_timer(unsigned long arg)
2911 struct dw_mci *host = (struct dw_mci *)arg;
2913 switch (host->state) {
2914 case STATE_SENDING_DATA:
2915 case STATE_DATA_BUSY:
2917 * If DTO interrupt does NOT come in sending data state,
2918 * we should notify the driver to terminate current transfer
2919 * and report a data timeout to the core.
2921 host->data_status = SDMMC_INT_DRTO;
2922 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2923 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2924 tasklet_schedule(&host->tasklet);
2932 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2934 struct dw_mci_board *pdata;
2935 struct device *dev = host->dev;
2936 struct device_node *np = dev->of_node;
2937 const struct dw_mci_drv_data *drv_data = host->drv_data;
2939 u32 clock_frequency;
2941 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2943 return ERR_PTR(-ENOMEM);
2945 /* find reset controller when exist */
2946 pdata->rstc = devm_reset_control_get_optional(dev, "reset");
2947 if (IS_ERR(pdata->rstc)) {
2948 if (PTR_ERR(pdata->rstc) == -EPROBE_DEFER)
2949 return ERR_PTR(-EPROBE_DEFER);
2952 /* find out number of slots supported */
2953 of_property_read_u32(np, "num-slots", &pdata->num_slots);
2955 if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
2957 "fifo-depth property not found, using value of FIFOTH register as default\n");
2959 of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
2961 if (!of_property_read_u32(np, "clock-frequency", &clock_frequency))
2962 pdata->bus_hz = clock_frequency;
2964 if (drv_data && drv_data->parse_dt) {
2965 ret = drv_data->parse_dt(host);
2967 return ERR_PTR(ret);
2973 #else /* CONFIG_OF */
2974 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2976 return ERR_PTR(-EINVAL);
2978 #endif /* CONFIG_OF */
2980 static void dw_mci_enable_cd(struct dw_mci *host)
2982 unsigned long irqflags;
2985 struct dw_mci_slot *slot;
2988 * No need for CD if all slots have a non-error GPIO
2989 * as well as broken card detection is found.
2991 for (i = 0; i < host->num_slots; i++) {
2992 slot = host->slot[i];
2993 if (slot->mmc->caps & MMC_CAP_NEEDS_POLL)
2996 if (mmc_gpio_get_cd(slot->mmc) < 0)
2999 if (i == host->num_slots)
3002 spin_lock_irqsave(&host->irq_lock, irqflags);
3003 temp = mci_readl(host, INTMASK);
3004 temp |= SDMMC_INT_CD;
3005 mci_writel(host, INTMASK, temp);
3006 spin_unlock_irqrestore(&host->irq_lock, irqflags);
3009 int dw_mci_probe(struct dw_mci *host)
3011 const struct dw_mci_drv_data *drv_data = host->drv_data;
3012 int width, i, ret = 0;
3017 host->pdata = dw_mci_parse_dt(host);
3018 if (PTR_ERR(host->pdata) == -EPROBE_DEFER) {
3019 return -EPROBE_DEFER;
3020 } else if (IS_ERR(host->pdata)) {
3021 dev_err(host->dev, "platform data not available\n");
3026 host->biu_clk = devm_clk_get(host->dev, "biu");
3027 if (IS_ERR(host->biu_clk)) {
3028 dev_dbg(host->dev, "biu clock not available\n");
3030 ret = clk_prepare_enable(host->biu_clk);
3032 dev_err(host->dev, "failed to enable biu clock\n");
3037 host->ciu_clk = devm_clk_get(host->dev, "ciu");
3038 if (IS_ERR(host->ciu_clk)) {
3039 dev_dbg(host->dev, "ciu clock not available\n");
3040 host->bus_hz = host->pdata->bus_hz;
3042 ret = clk_prepare_enable(host->ciu_clk);
3044 dev_err(host->dev, "failed to enable ciu clock\n");
3048 if (host->pdata->bus_hz) {
3049 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
3052 "Unable to set bus rate to %uHz\n",
3053 host->pdata->bus_hz);
3055 host->bus_hz = clk_get_rate(host->ciu_clk);
3058 if (!host->bus_hz) {
3060 "Platform data must supply bus speed\n");
3065 if (drv_data && drv_data->init) {
3066 ret = drv_data->init(host);
3069 "implementation specific init failed\n");
3074 if (!IS_ERR(host->pdata->rstc)) {
3075 reset_control_assert(host->pdata->rstc);
3076 usleep_range(10, 50);
3077 reset_control_deassert(host->pdata->rstc);
3080 setup_timer(&host->cmd11_timer,
3081 dw_mci_cmd11_timer, (unsigned long)host);
3083 setup_timer(&host->dto_timer,
3084 dw_mci_dto_timer, (unsigned long)host);
3086 spin_lock_init(&host->lock);
3087 spin_lock_init(&host->irq_lock);
3088 INIT_LIST_HEAD(&host->queue);
3091 * Get the host data width - this assumes that HCON has been set with
3092 * the correct values.
3094 i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));
3096 host->push_data = dw_mci_push_data16;
3097 host->pull_data = dw_mci_pull_data16;
3099 host->data_shift = 1;
3100 } else if (i == 2) {
3101 host->push_data = dw_mci_push_data64;
3102 host->pull_data = dw_mci_pull_data64;
3104 host->data_shift = 3;
3106 /* Check for a reserved value, and warn if it is */
3108 "HCON reports a reserved host data width!\n"
3109 "Defaulting to 32-bit access.\n");
3110 host->push_data = dw_mci_push_data32;
3111 host->pull_data = dw_mci_pull_data32;
3113 host->data_shift = 2;
3116 /* Reset all blocks */
3117 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3122 host->dma_ops = host->pdata->dma_ops;
3123 dw_mci_init_dma(host);
3125 /* Clear the interrupts for the host controller */
3126 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3127 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3129 /* Put in max timeout */
3130 mci_writel(host, TMOUT, 0xFFFFFFFF);
3133 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
3134 * Tx Mark = fifo_size / 2 DMA Size = 8
3136 if (!host->pdata->fifo_depth) {
3138 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
3139 * have been overwritten by the bootloader, just like we're
3140 * about to do, so if you know the value for your hardware, you
3141 * should put it in the platform data.
3143 fifo_size = mci_readl(host, FIFOTH);
3144 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
3146 fifo_size = host->pdata->fifo_depth;
3148 host->fifo_depth = fifo_size;
3150 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
3151 mci_writel(host, FIFOTH, host->fifoth_val);
3153 /* disable clock to CIU */
3154 mci_writel(host, CLKENA, 0);
3155 mci_writel(host, CLKSRC, 0);
3158 * In 2.40a spec, Data offset is changed.
3159 * Need to check the version-id and set data-offset for DATA register.
3161 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
3162 dev_info(host->dev, "Version ID is %04x\n", host->verid);
3164 if (host->verid < DW_MMC_240A)
3165 host->fifo_reg = host->regs + DATA_OFFSET;
3167 host->fifo_reg = host->regs + DATA_240A_OFFSET;
3169 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
3170 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
3171 host->irq_flags, "dw-mci", host);
3175 if (host->pdata->num_slots)
3176 host->num_slots = host->pdata->num_slots;
3178 host->num_slots = 1;
3180 if (host->num_slots < 1 ||
3181 host->num_slots > SDMMC_GET_SLOT_NUM(mci_readl(host, HCON))) {
3183 "Platform data must supply correct num_slots.\n");
3189 * Enable interrupts for command done, data over, data empty,
3190 * receive ready and error such as transmit, receive timeout, crc error
3192 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3193 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3194 DW_MCI_ERROR_FLAGS);
3195 /* Enable mci interrupt */
3196 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3199 "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n",
3200 host->irq, width, fifo_size);
3202 /* We need at least one slot to succeed */
3203 for (i = 0; i < host->num_slots; i++) {
3204 ret = dw_mci_init_slot(host, i);
3206 dev_dbg(host->dev, "slot %d init failed\n", i);
3212 dev_info(host->dev, "%d slots initialized\n", init_slots);
3215 "attempted to initialize %d slots, but failed on all\n",
3220 /* Now that slots are all setup, we can enable card detect */
3221 dw_mci_enable_cd(host);
3226 if (host->use_dma && host->dma_ops->exit)
3227 host->dma_ops->exit(host);
3229 if (!IS_ERR(host->pdata->rstc))
3230 reset_control_assert(host->pdata->rstc);
3233 clk_disable_unprepare(host->ciu_clk);
3236 clk_disable_unprepare(host->biu_clk);
3240 EXPORT_SYMBOL(dw_mci_probe);
3242 void dw_mci_remove(struct dw_mci *host)
3246 for (i = 0; i < host->num_slots; i++) {
3247 dev_dbg(host->dev, "remove slot %d\n", i);
3249 dw_mci_cleanup_slot(host->slot[i], i);
3252 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3253 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3255 /* disable clock to CIU */
3256 mci_writel(host, CLKENA, 0);
3257 mci_writel(host, CLKSRC, 0);
3259 if (host->use_dma && host->dma_ops->exit)
3260 host->dma_ops->exit(host);
3262 if (!IS_ERR(host->pdata->rstc))
3263 reset_control_assert(host->pdata->rstc);
3265 clk_disable_unprepare(host->ciu_clk);
3266 clk_disable_unprepare(host->biu_clk);
3268 EXPORT_SYMBOL(dw_mci_remove);
3273 int dw_mci_runtime_suspend(struct device *dev)
3275 struct dw_mci *host = dev_get_drvdata(dev);
3277 if (host->use_dma && host->dma_ops->exit)
3278 host->dma_ops->exit(host);
3280 clk_disable_unprepare(host->ciu_clk);
3282 if (host->cur_slot &&
3283 (mmc_can_gpio_cd(host->cur_slot->mmc) ||
3284 !mmc_card_is_removable(host->cur_slot->mmc)))
3285 clk_disable_unprepare(host->biu_clk);
3289 EXPORT_SYMBOL(dw_mci_runtime_suspend);
3291 int dw_mci_runtime_resume(struct device *dev)
3294 struct dw_mci *host = dev_get_drvdata(dev);
3296 if (host->cur_slot &&
3297 (mmc_can_gpio_cd(host->cur_slot->mmc) ||
3298 !mmc_card_is_removable(host->cur_slot->mmc))) {
3299 ret = clk_prepare_enable(host->biu_clk);
3304 ret = clk_prepare_enable(host->ciu_clk);
3308 if (host->use_dma && host->dma_ops->init)
3309 host->dma_ops->init(host);
3312 * Restore the initial value at FIFOTH register
3313 * And Invalidate the prev_blksz with zero
3315 mci_writel(host, FIFOTH, host->fifoth_val);
3316 host->prev_blksz = 0;
3318 /* Put in max timeout */
3319 mci_writel(host, TMOUT, 0xFFFFFFFF);
3321 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3322 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3323 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3324 DW_MCI_ERROR_FLAGS);
3325 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3327 for (i = 0; i < host->num_slots; i++) {
3328 struct dw_mci_slot *slot = host->slot[i];
3332 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
3333 dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
3334 dw_mci_setup_bus(slot, true);
3338 /* Now that slots are all setup, we can enable card detect */
3339 dw_mci_enable_cd(host);
3343 EXPORT_SYMBOL(dw_mci_runtime_resume);
3344 #endif /* CONFIG_PM */
3346 static int __init dw_mci_init(void)
3348 pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
3352 static void __exit dw_mci_exit(void)
3356 module_init(dw_mci_init);
3357 module_exit(dw_mci_exit);
3359 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
3360 MODULE_AUTHOR("NXP Semiconductor VietNam");
3361 MODULE_AUTHOR("Imagination Technologies Ltd");
3362 MODULE_LICENSE("GPL v2");