drivers/mmc/host/dw_mmc.c

   1 /*
   2  * Synopsys DesignWare Multimedia Card Interface driver
   3  *  (Based on NXP driver for lpc 31xx)
   4  *
   5  * Copyright (C) 2009 NXP Semiconductors
   6  * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/blkdev.h>
  15 #include <linux/clk.h>
  16 #include <linux/debugfs.h>
  17 #include <linux/device.h>
  18 #include <linux/dma-mapping.h>
  19 #include <linux/err.h>
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/ioport.h>
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/seq_file.h>
  26 #include <linux/slab.h>
  27 #include <linux/stat.h>
  28 #include <linux/delay.h>
  29 #include <linux/irq.h>
  30 #include <linux/mmc/host.h>
  31 #include <linux/mmc/mmc.h>
  32 #include <linux/mmc/dw_mmc.h>
  33 #include <linux/bitops.h>
  34 #include <linux/regulator/consumer.h>
  35 #include <linux/workqueue.h>
  36 #include <linux/of.h>
  37
  38 #include "dw_mmc.h"
  39
  40 /* Common flag combinations */
  41 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DTO | SDMMC_INT_DCRC | \
  42                                  SDMMC_INT_HTO | SDMMC_INT_SBE  | \
  43                                  SDMMC_INT_EBE)
  44 #define DW_MCI_CMD_ERROR_FLAGS  (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
  45                                  SDMMC_INT_RESP_ERR)
  46 #define DW_MCI_ERROR_FLAGS      (DW_MCI_DATA_ERROR_FLAGS | \
  47                                  DW_MCI_CMD_ERROR_FLAGS  | SDMMC_INT_HLE)
  48 #define DW_MCI_SEND_STATUS      1
  49 #define DW_MCI_RECV_STATUS      2
  50 #define DW_MCI_DMA_THRESHOLD    16
  51
  52 #ifdef CONFIG_MMC_DW_IDMAC
  53 struct idmac_desc {
  54         u32             des0;   /* Control Descriptor */
  55 #define IDMAC_DES0_DIC  BIT(1)
  56 #define IDMAC_DES0_LD   BIT(2)
  57 #define IDMAC_DES0_FD   BIT(3)
  58 #define IDMAC_DES0_CH   BIT(4)
  59 #define IDMAC_DES0_ER   BIT(5)
  60 #define IDMAC_DES0_CES  BIT(30)
  61 #define IDMAC_DES0_OWN  BIT(31)
  62
  63         u32             des1;   /* Buffer sizes */
  64 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
  65         ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
  66
  67         u32             des2;   /* buffer 1 physical address */
  68
  69         u32             des3;   /* buffer 2 physical address */
  70 };
  71 #endif /* CONFIG_MMC_DW_IDMAC */
  72
  73 /**
  74  * struct dw_mci_slot - MMC slot state
  75  * @mmc: The mmc_host representing this slot.
  76  * @host: The MMC controller this slot is using.
  77  * @ctype: Card type for this slot.
  78  * @mrq: mmc_request currently being processed or waiting to be
  79  *      processed, or NULL when the slot is idle.
  80  * @queue_node: List node for placing this node in the @queue list of
  81  *      &struct dw_mci.
  82  * @clock: Clock rate configured by set_ios(). Protected by host->lock.
  83  * @flags: Random state bits associated with the slot.
  84  * @id: Number of this slot.
  85  * @last_detect_state: Most recently observed card detect state.
  86  */
  87 struct dw_mci_slot {
  88         struct mmc_host         *mmc;
  89         struct dw_mci           *host;
  90
  91         u32                     ctype;
  92
  93         struct mmc_request      *mrq;
  94         struct list_head        queue_node;
  95
  96         unsigned int            clock;
  97         unsigned long           flags;
  98 #define DW_MMC_CARD_PRESENT     0
  99 #define DW_MMC_CARD_NEED_INIT   1
 100         int                     id;
 101         int                     last_detect_state;
 102 };
 103
 104 #if defined(CONFIG_DEBUG_FS)
 105 static int dw_mci_req_show(struct seq_file *s, void *v)
 106 {
 107         struct dw_mci_slot *slot = s->private;
 108         struct mmc_request *mrq;
 109         struct mmc_command *cmd;
 110         struct mmc_command *stop;
 111         struct mmc_data *data;
 112
 113         /* Make sure we get a consistent snapshot */
 114         spin_lock_bh(&slot->host->lock);
 115         mrq = slot->mrq;
 116
 117         if (mrq) {
 118                 cmd = mrq->cmd;
 119                 data = mrq->data;
 120                 stop = mrq->stop;
 121
 122                 if (cmd)
 123                         seq_printf(s,
 124                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 125                                    cmd->opcode, cmd->arg, cmd->flags,
 126                                    cmd->resp[0], cmd->resp[1], cmd->resp[2],
 127                                    cmd->resp[2], cmd->error);
 128                 if (data)
 129                         seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
 130                                    data->bytes_xfered, data->blocks,
 131                                    data->blksz, data->flags, data->error);
 132                 if (stop)
 133                         seq_printf(s,
 134                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 135                                    stop->opcode, stop->arg, stop->flags,
 136                                    stop->resp[0], stop->resp[1], stop->resp[2],
 137                                    stop->resp[2], stop->error);
 138         }
 139
 140         spin_unlock_bh(&slot->host->lock);
 141
 142         return 0;
 143 }
 144
 145 static int dw_mci_req_open(struct inode *inode, struct file *file)
 146 {
 147         return single_open(file, dw_mci_req_show, inode->i_private);
 148 }
 149
 150 static const struct file_operations dw_mci_req_fops = {
 151         .owner          = THIS_MODULE,
 152         .open           = dw_mci_req_open,
 153         .read           = seq_read,
 154         .llseek         = seq_lseek,
 155         .release        = single_release,
 156 };
 157
 158 static int dw_mci_regs_show(struct seq_file *s, void *v)
 159 {
 160         seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
 161         seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
 162         seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
 163         seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
 164         seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
 165         seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
 166
 167         return 0;
 168 }
 169
 170 static int dw_mci_regs_open(struct inode *inode, struct file *file)
 171 {
 172         return single_open(file, dw_mci_regs_show, inode->i_private);
 173 }
 174
 175 static const struct file_operations dw_mci_regs_fops = {
 176         .owner          = THIS_MODULE,
 177         .open           = dw_mci_regs_open,
 178         .read           = seq_read,
 179         .llseek         = seq_lseek,
 180         .release        = single_release,
 181 };
 182
 183 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
 184 {
 185         struct mmc_host *mmc = slot->mmc;
 186         struct dw_mci *host = slot->host;
 187         struct dentry *root;
 188         struct dentry *node;
 189
 190         root = mmc->debugfs_root;
 191         if (!root)
 192                 return;
 193
 194         node = debugfs_create_file("regs", S_IRUSR, root, host,
 195                                    &dw_mci_regs_fops);
 196         if (!node)
 197                 goto err;
 198
 199         node = debugfs_create_file("req", S_IRUSR, root, slot,
 200                                    &dw_mci_req_fops);
 201         if (!node)
 202                 goto err;
 203
 204         node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
 205         if (!node)
 206                 goto err;
 207
 208         node = debugfs_create_x32("pending_events", S_IRUSR, root,
 209                                   (u32 *)&host->pending_events);
 210         if (!node)
 211                 goto err;
 212
 213         node = debugfs_create_x32("completed_events", S_IRUSR, root,
 214                                   (u32 *)&host->completed_events);
 215         if (!node)
 216                 goto err;
 217
 218         return;
 219
 220 err:
 221         dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
 222 }
 223 #endif /* defined(CONFIG_DEBUG_FS) */
 224
 225 static void dw_mci_set_timeout(struct dw_mci *host)
 226 {
 227         /* timeout (maximum) */
 228         mci_writel(host, TMOUT, 0xffffffff);
 229 }
 230
 231 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
 232 {
 233         struct mmc_data *data;
 234         struct dw_mci_slot *slot = mmc_priv(mmc);
 235         u32 cmdr;
 236         cmd->error = -EINPROGRESS;
 237
 238         cmdr = cmd->opcode;
 239
 240         if (cmdr == MMC_STOP_TRANSMISSION)
 241                 cmdr |= SDMMC_CMD_STOP;
 242         else
 243                 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
 244
 245         if (cmd->flags & MMC_RSP_PRESENT) {
 246                 /* We expect a response, so set this bit */
 247                 cmdr |= SDMMC_CMD_RESP_EXP;
 248                 if (cmd->flags & MMC_RSP_136)
 249                         cmdr |= SDMMC_CMD_RESP_LONG;
 250         }
 251
 252         if (cmd->flags & MMC_RSP_CRC)
 253                 cmdr |= SDMMC_CMD_RESP_CRC;
 254
 255         data = cmd->data;
 256         if (data) {
 257                 cmdr |= SDMMC_CMD_DAT_EXP;
 258                 if (data->flags & MMC_DATA_STREAM)
 259                         cmdr |= SDMMC_CMD_STRM_MODE;
 260                 if (data->flags & MMC_DATA_WRITE)
 261                         cmdr |= SDMMC_CMD_DAT_WR;
 262         }
 263
 264         if (slot->host->drv_data->prepare_command)
 265                 slot->host->drv_data->prepare_command(slot->host, &cmdr);
 266
 267         return cmdr;
 268 }
 269
 270 static void dw_mci_start_command(struct dw_mci *host,
 271                                  struct mmc_command *cmd, u32 cmd_flags)
 272 {
 273         host->cmd = cmd;
 274         dev_vdbg(host->dev,
 275                  "start command: ARGR=0x%08x CMDR=0x%08x\n",
 276                  cmd->arg, cmd_flags);
 277
 278         mci_writel(host, CMDARG, cmd->arg);
 279         wmb();
 280
 281         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
 282 }
 283
 284 static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data)
 285 {
 286         dw_mci_start_command(host, data->stop, host->stop_cmdr);
 287 }
 288
 289 /* DMA interface functions */
 290 static void dw_mci_stop_dma(struct dw_mci *host)
 291 {
 292         if (host->using_dma) {
 293                 host->dma_ops->stop(host);
 294                 host->dma_ops->cleanup(host);
 295         } else {
 296                 /* Data transfer was stopped by the interrupt handler */
 297                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 298         }
 299 }
 300
 301 static int dw_mci_get_dma_dir(struct mmc_data *data)
 302 {
 303         if (data->flags & MMC_DATA_WRITE)
 304                 return DMA_TO_DEVICE;
 305         else
 306                 return DMA_FROM_DEVICE;
 307 }
 308
 309 #ifdef CONFIG_MMC_DW_IDMAC
 310 static void dw_mci_dma_cleanup(struct dw_mci *host)
 311 {
 312         struct mmc_data *data = host->data;
 313
 314         if (data)
 315                 if (!data->host_cookie)
 316                         dma_unmap_sg(host->dev,
 317                                      data->sg,
 318                                      data->sg_len,
 319                                      dw_mci_get_dma_dir(data));
 320 }
 321
 322 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
 323 {
 324         u32 temp;
 325
 326         /* Disable and reset the IDMAC interface */
 327         temp = mci_readl(host, CTRL);
 328         temp &= ~SDMMC_CTRL_USE_IDMAC;
 329         temp |= SDMMC_CTRL_DMA_RESET;
 330         mci_writel(host, CTRL, temp);
 331
 332         /* Stop the IDMAC running */
 333         temp = mci_readl(host, BMOD);
 334         temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
 335         mci_writel(host, BMOD, temp);
 336 }
 337
 338 static void dw_mci_idmac_complete_dma(struct dw_mci *host)
 339 {
 340         struct mmc_data *data = host->data;
 341
 342         dev_vdbg(host->dev, "DMA complete\n");
 343
 344         host->dma_ops->cleanup(host);
 345
 346         /*
 347          * If the card was removed, data will be NULL. No point in trying to
 348          * send the stop command or waiting for NBUSY in this case.
 349          */
 350         if (data) {
 351                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 352                 tasklet_schedule(&host->tasklet);
 353         }
 354 }
 355
 356 static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
 357                                     unsigned int sg_len)
 358 {
 359         int i;
 360         struct idmac_desc *desc = host->sg_cpu;
 361
 362         for (i = 0; i < sg_len; i++, desc++) {
 363                 unsigned int length = sg_dma_len(&data->sg[i]);
 364                 u32 mem_addr = sg_dma_address(&data->sg[i]);
 365
 366                 /* Set the OWN bit and disable interrupts for this descriptor */
 367                 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH;
 368
 369                 /* Buffer length */
 370                 IDMAC_SET_BUFFER1_SIZE(desc, length);
 371
 372                 /* Physical address to DMA to/from */
 373                 desc->des2 = mem_addr;
 374         }
 375
 376         /* Set first descriptor */
 377         desc = host->sg_cpu;
 378         desc->des0 |= IDMAC_DES0_FD;
 379
 380         /* Set last descriptor */
 381         desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
 382         desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
 383         desc->des0 |= IDMAC_DES0_LD;
 384
 385         wmb();
 386 }
 387
 388 static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
 389 {
 390         u32 temp;
 391
 392         dw_mci_translate_sglist(host, host->data, sg_len);
 393
 394         /* Select IDMAC interface */
 395         temp = mci_readl(host, CTRL);
 396         temp |= SDMMC_CTRL_USE_IDMAC;
 397         mci_writel(host, CTRL, temp);
 398
 399         wmb();
 400
 401         /* Enable the IDMAC */
 402         temp = mci_readl(host, BMOD);
 403         temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
 404         mci_writel(host, BMOD, temp);
 405
 406         /* Start it running */
 407         mci_writel(host, PLDMND, 1);
 408 }
 409
 410 static int dw_mci_idmac_init(struct dw_mci *host)
 411 {
 412         struct idmac_desc *p;
 413         int i, dma_support;
 414
 415         /* Number of descriptors in the ring buffer */
 416         host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
 417
 418         /* Check if Hardware Configuration Register has support for DMA */
 419         dma_support = (mci_readl(host, HCON) >> 16) & 0x3;
 420
 421         if (!dma_support || dma_support > 2) {
 422                 dev_err(host->dev,
 423                         "Host Controller does not support IDMA Tx.\n");
 424                 host->dma_ops = NULL;
 425                 return -ENODEV;
 426         }
 427
 428         dev_info(host->dev, "Using internal DMA controller.\n");
 429
 430         /* Forward link the descriptor list */
 431         for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++)
 432                 p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1));
 433
 434         /* Set the last descriptor as the end-of-ring descriptor */
 435         p->des3 = host->sg_dma;
 436         p->des0 = IDMAC_DES0_ER;
 437
 438         mci_writel(host, BMOD, SDMMC_IDMAC_SWRESET);
 439
 440         /* Mask out interrupts - get Tx & Rx complete only */
 441         mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI |
 442                    SDMMC_IDMAC_INT_TI);
 443
 444         /* Set the descriptor base address */
 445         mci_writel(host, DBADDR, host->sg_dma);
 446         return 0;
 447 }
 448
 449 static struct dw_mci_dma_ops dw_mci_idmac_ops = {
 450         .init = dw_mci_idmac_init,
 451         .start = dw_mci_idmac_start_dma,
 452         .stop = dw_mci_idmac_stop_dma,
 453         .complete = dw_mci_idmac_complete_dma,
 454         .cleanup = dw_mci_dma_cleanup,
 455 };
 456 #endif /* CONFIG_MMC_DW_IDMAC */
 457
 458 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
 459                                    struct mmc_data *data,
 460                                    bool next)
 461 {
 462         struct scatterlist *sg;
 463         unsigned int i, sg_len;
 464
 465         if (!next && data->host_cookie)
 466                 return data->host_cookie;
 467
 468         /*
 469          * We don't do DMA on "complex" transfers, i.e. with
 470          * non-word-aligned buffers or lengths. Also, we don't bother
 471          * with all the DMA setup overhead for short transfers.
 472          */
 473         if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
 474                 return -EINVAL;
 475
 476         if (data->blksz & 3)
 477                 return -EINVAL;
 478
 479         for_each_sg(data->sg, sg, data->sg_len, i) {
 480                 if (sg->offset & 3 || sg->length & 3)
 481                         return -EINVAL;
 482         }
 483
 484         sg_len = dma_map_sg(host->dev,
 485                             data->sg,
 486                             data->sg_len,
 487                             dw_mci_get_dma_dir(data));
 488         if (sg_len == 0)
 489                 return -EINVAL;
 490
 491         if (next)
 492                 data->host_cookie = sg_len;
 493
 494         return sg_len;
 495 }
 496
 497 static void dw_mci_pre_req(struct mmc_host *mmc,
 498                            struct mmc_request *mrq,
 499                            bool is_first_req)
 500 {
 501         struct dw_mci_slot *slot = mmc_priv(mmc);
 502         struct mmc_data *data = mrq->data;
 503
 504         if (!slot->host->use_dma || !data)
 505                 return;
 506
 507         if (data->host_cookie) {
 508                 data->host_cookie = 0;
 509                 return;
 510         }
 511
 512         if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
 513                 data->host_cookie = 0;
 514 }
 515
 516 static void dw_mci_post_req(struct mmc_host *mmc,
 517                             struct mmc_request *mrq,
 518                             int err)
 519 {
 520         struct dw_mci_slot *slot = mmc_priv(mmc);
 521         struct mmc_data *data = mrq->data;
 522
 523         if (!slot->host->use_dma || !data)
 524                 return;
 525
 526         if (data->host_cookie)
 527                 dma_unmap_sg(slot->host->dev,
 528                              data->sg,
 529                              data->sg_len,
 530                              dw_mci_get_dma_dir(data));
 531         data->host_cookie = 0;
 532 }
 533
 534 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
 535 {
 536         int sg_len;
 537         u32 temp;
 538
 539         host->using_dma = 0;
 540
 541         /* If we don't have a channel, we can't do DMA */
 542         if (!host->use_dma)
 543                 return -ENODEV;
 544
 545         sg_len = dw_mci_pre_dma_transfer(host, data, 0);
 546         if (sg_len < 0) {
 547                 host->dma_ops->stop(host);
 548                 return sg_len;
 549         }
 550
 551         host->using_dma = 1;
 552
 553         dev_vdbg(host->dev,
 554                  "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
 555                  (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
 556                  sg_len);
 557
 558         /* Enable the DMA interface */
 559         temp = mci_readl(host, CTRL);
 560         temp |= SDMMC_CTRL_DMA_ENABLE;
 561         mci_writel(host, CTRL, temp);
 562
 563         /* Disable RX/TX IRQs, let DMA handle it */
 564         temp = mci_readl(host, INTMASK);
 565         temp  &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
 566         mci_writel(host, INTMASK, temp);
 567
 568         host->dma_ops->start(host, sg_len);
 569
 570         return 0;
 571 }
 572
 573 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
 574 {
 575         u32 temp;
 576
 577         data->error = -EINPROGRESS;
 578
 579         WARN_ON(host->data);
 580         host->sg = NULL;
 581         host->data = data;
 582
 583         if (data->flags & MMC_DATA_READ)
 584                 host->dir_status = DW_MCI_RECV_STATUS;
 585         else
 586                 host->dir_status = DW_MCI_SEND_STATUS;
 587
 588         if (dw_mci_submit_data_dma(host, data)) {
 589                 int flags = SG_MITER_ATOMIC;
 590                 if (host->data->flags & MMC_DATA_READ)
 591                         flags |= SG_MITER_TO_SG;
 592                 else
 593                         flags |= SG_MITER_FROM_SG;
 594
 595                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 596                 host->sg = data->sg;
 597                 host->part_buf_start = 0;
 598                 host->part_buf_count = 0;
 599
 600                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
 601                 temp = mci_readl(host, INTMASK);
 602                 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
 603                 mci_writel(host, INTMASK, temp);
 604
 605                 temp = mci_readl(host, CTRL);
 606                 temp &= ~SDMMC_CTRL_DMA_ENABLE;
 607                 mci_writel(host, CTRL, temp);
 608         }
 609 }
 610
 611 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
 612 {
 613         struct dw_mci *host = slot->host;
 614         unsigned long timeout = jiffies + msecs_to_jiffies(500);
 615         unsigned int cmd_status = 0;
 616
 617         mci_writel(host, CMDARG, arg);
 618         wmb();
 619         mci_writel(host, CMD, SDMMC_CMD_START | cmd);
 620
 621         while (time_before(jiffies, timeout)) {
 622                 cmd_status = mci_readl(host, CMD);
 623                 if (!(cmd_status & SDMMC_CMD_START))
 624                         return;
 625         }
 626         dev_err(&slot->mmc->class_dev,
 627                 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
 628                 cmd, arg, cmd_status);
 629 }
 630
 631 static void dw_mci_setup_bus(struct dw_mci_slot *slot)
 632 {
 633         struct dw_mci *host = slot->host;
 634         u32 div;
 635         u32 clk_en_a;
 636
 637         if (slot->clock != host->current_speed) {
 638                 div = host->bus_hz / slot->clock;
 639                 if (host->bus_hz % slot->clock && host->bus_hz > slot->clock)
 640                         /*
 641                          * move the + 1 after the divide to prevent
 642                          * over-clocking the card.
 643                          */
 644                         div += 1;
 645
 646                 div = (host->bus_hz != slot->clock) ? DIV_ROUND_UP(div, 2) : 0;
 647
 648                 dev_info(&slot->mmc->class_dev,
 649                          "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ"
 650                          " div = %d)\n", slot->id, host->bus_hz, slot->clock,
 651                          div ? ((host->bus_hz / div) >> 1) : host->bus_hz, div);
 652
 653                 /* disable clock */
 654                 mci_writel(host, CLKENA, 0);
 655                 mci_writel(host, CLKSRC, 0);
 656
 657                 /* inform CIU */
 658                 mci_send_cmd(slot,
 659                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
 660
 661                 /* set clock to desired speed */
 662                 mci_writel(host, CLKDIV, div);
 663
 664                 /* inform CIU */
 665                 mci_send_cmd(slot,
 666                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
 667
 668                 /* enable clock; only low power if no SDIO */
 669                 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
 670                 if (!(mci_readl(host, INTMASK) & SDMMC_INT_SDIO(slot->id)))
 671                         clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
 672                 mci_writel(host, CLKENA, clk_en_a);
 673
 674                 /* inform CIU */
 675                 mci_send_cmd(slot,
 676                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
 677
 678                 host->current_speed = slot->clock;
 679         }
 680
 681         /* Set the current slot bus width */
 682         mci_writel(host, CTYPE, (slot->ctype << slot->id));
 683 }
 684
 685 static void __dw_mci_start_request(struct dw_mci *host,
 686                                    struct dw_mci_slot *slot,
 687                                    struct mmc_command *cmd)
 688 {
 689         struct mmc_request *mrq;
 690         struct mmc_data *data;
 691         u32 cmdflags;
 692
 693         mrq = slot->mrq;
 694         if (host->pdata->select_slot)
 695                 host->pdata->select_slot(slot->id);
 696
 697         /* Slot specific timing and width adjustment */
 698         dw_mci_setup_bus(slot);
 699
 700         host->cur_slot = slot;
 701         host->mrq = mrq;
 702
 703         host->pending_events = 0;
 704         host->completed_events = 0;
 705         host->data_status = 0;
 706
 707         data = cmd->data;
 708         if (data) {
 709                 dw_mci_set_timeout(host);
 710                 mci_writel(host, BYTCNT, data->blksz*data->blocks);
 711                 mci_writel(host, BLKSIZ, data->blksz);
 712         }
 713
 714         cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
 715
 716         /* this is the first command, send the initialization clock */
 717         if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
 718                 cmdflags |= SDMMC_CMD_INIT;
 719
 720         if (data) {
 721                 dw_mci_submit_data(host, data);
 722                 wmb();
 723         }
 724
 725         dw_mci_start_command(host, cmd, cmdflags);
 726
 727         if (mrq->stop)
 728                 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
 729 }
 730
 731 static void dw_mci_start_request(struct dw_mci *host,
 732                                  struct dw_mci_slot *slot)
 733 {
 734         struct mmc_request *mrq = slot->mrq;
 735         struct mmc_command *cmd;
 736
 737         cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
 738         __dw_mci_start_request(host, slot, cmd);
 739 }
 740
 741 /* must be called with host->lock held */
 742 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
 743                                  struct mmc_request *mrq)
 744 {
 745         dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
 746                  host->state);
 747
 748         slot->mrq = mrq;
 749
 750         if (host->state == STATE_IDLE) {
 751                 host->state = STATE_SENDING_CMD;
 752                 dw_mci_start_request(host, slot);
 753         } else {
 754                 list_add_tail(&slot->queue_node, &host->queue);
 755         }
 756 }
 757
 758 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
 759 {
 760         struct dw_mci_slot *slot = mmc_priv(mmc);
 761         struct dw_mci *host = slot->host;
 762
 763         WARN_ON(slot->mrq);
 764
 765         /*
 766          * The check for card presence and queueing of the request must be
 767          * atomic, otherwise the card could be removed in between and the
 768          * request wouldn't fail until another card was inserted.
 769          */
 770         spin_lock_bh(&host->lock);
 771
 772         if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
 773                 spin_unlock_bh(&host->lock);
 774                 mrq->cmd->error = -ENOMEDIUM;
 775                 mmc_request_done(mmc, mrq);
 776                 return;
 777         }
 778
 779         dw_mci_queue_request(host, slot, mrq);
 780
 781         spin_unlock_bh(&host->lock);
 782 }
 783
 784 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 785 {
 786         struct dw_mci_slot *slot = mmc_priv(mmc);
 787         u32 regs;
 788
 789         /* set default 1 bit mode */
 790         slot->ctype = SDMMC_CTYPE_1BIT;
 791
 792         switch (ios->bus_width) {
 793         case MMC_BUS_WIDTH_1:
 794                 slot->ctype = SDMMC_CTYPE_1BIT;
 795                 break;
 796         case MMC_BUS_WIDTH_4:
 797                 slot->ctype = SDMMC_CTYPE_4BIT;
 798                 break;
 799         case MMC_BUS_WIDTH_8:
 800                 slot->ctype = SDMMC_CTYPE_8BIT;
 801                 break;
 802         }
 803
 804         regs = mci_readl(slot->host, UHS_REG);
 805
 806         /* DDR mode set */
 807         if (ios->timing == MMC_TIMING_UHS_DDR50)
 808                 regs |= (0x1 << slot->id) << 16;
 809         else
 810                 regs &= ~(0x1 << slot->id) << 16;
 811
 812         mci_writel(slot->host, UHS_REG, regs);
 813
 814         if (ios->clock) {
 815                 /*
 816                  * Use mirror of ios->clock to prevent race with mmc
 817                  * core ios update when finding the minimum.
 818                  */
 819                 slot->clock = ios->clock;
 820         }
 821
 822         if (slot->host->drv_data->set_ios)
 823                 slot->host->drv_data->set_ios(slot->host, ios);
 824
 825         switch (ios->power_mode) {
 826         case MMC_POWER_UP:
 827                 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
 828                 break;
 829         default:
 830                 break;
 831         }
 832 }
 833
 834 static int dw_mci_get_ro(struct mmc_host *mmc)
 835 {
 836         int read_only;
 837         struct dw_mci_slot *slot = mmc_priv(mmc);
 838         struct dw_mci_board *brd = slot->host->pdata;
 839
 840         /* Use platform get_ro function, else try on board write protect */
 841         if (brd->quirks & DW_MCI_QUIRK_NO_WRITE_PROTECT)
 842                 read_only = 0;
 843         else if (brd->get_ro)
 844                 read_only = brd->get_ro(slot->id);
 845         else
 846                 read_only =
 847                         mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
 848
 849         dev_dbg(&mmc->class_dev, "card is %s\n",
 850                 read_only ? "read-only" : "read-write");
 851
 852         return read_only;
 853 }
 854
 855 static int dw_mci_get_cd(struct mmc_host *mmc)
 856 {
 857         int present;
 858         struct dw_mci_slot *slot = mmc_priv(mmc);
 859         struct dw_mci_board *brd = slot->host->pdata;
 860
 861         /* Use platform get_cd function, else try onboard card detect */
 862         if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
 863                 present = 1;
 864         else if (brd->get_cd)
 865                 present = !brd->get_cd(slot->id);
 866         else
 867                 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
 868                         == 0 ? 1 : 0;
 869
 870         if (present)
 871                 dev_dbg(&mmc->class_dev, "card is present\n");
 872         else
 873                 dev_dbg(&mmc->class_dev, "card is not present\n");
 874
 875         return present;
 876 }
 877
 878 /*
 879  * Disable lower power mode.
 880  *
 881  * Low power mode will stop the card clock when idle.  According to the
 882  * description of the CLKENA register we should disable low power mode
 883  * for SDIO cards if we need SDIO interrupts to work.
 884  *
 885  * This function is fast if low power mode is already disabled.
 886  */
 887 static void dw_mci_disable_low_power(struct dw_mci_slot *slot)
 888 {
 889         struct dw_mci *host = slot->host;
 890         u32 clk_en_a;
 891         const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
 892
 893         clk_en_a = mci_readl(host, CLKENA);
 894
 895         if (clk_en_a & clken_low_pwr) {
 896                 mci_writel(host, CLKENA, clk_en_a & ~clken_low_pwr);
 897                 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
 898                              SDMMC_CMD_PRV_DAT_WAIT, 0);
 899         }
 900 }
 901
 902 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
 903 {
 904         struct dw_mci_slot *slot = mmc_priv(mmc);
 905         struct dw_mci *host = slot->host;
 906         u32 int_mask;
 907
 908         /* Enable/disable Slot Specific SDIO interrupt */
 909         int_mask = mci_readl(host, INTMASK);
 910         if (enb) {
 911                 /*
 912                  * Turn off low power mode if it was enabled.  This is a bit of
 913                  * a heavy operation and we disable / enable IRQs a lot, so
 914                  * we'll leave low power mode disabled and it will get
 915                  * re-enabled again in dw_mci_setup_bus().
 916                  */
 917                 dw_mci_disable_low_power(slot);
 918
 919                 mci_writel(host, INTMASK,
 920                            (int_mask | SDMMC_INT_SDIO(slot->id)));
 921         } else {
 922                 mci_writel(host, INTMASK,
 923                            (int_mask & ~SDMMC_INT_SDIO(slot->id)));
 924         }
 925 }
 926
 927 static const struct mmc_host_ops dw_mci_ops = {
 928         .request                = dw_mci_request,
 929         .pre_req                = dw_mci_pre_req,
 930         .post_req               = dw_mci_post_req,
 931         .set_ios                = dw_mci_set_ios,
 932         .get_ro                 = dw_mci_get_ro,
 933         .get_cd                 = dw_mci_get_cd,
 934         .enable_sdio_irq        = dw_mci_enable_sdio_irq,
 935 };
 936
 937 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
 938         __releases(&host->lock)
 939         __acquires(&host->lock)
 940 {
 941         struct dw_mci_slot *slot;
 942         struct mmc_host *prev_mmc = host->cur_slot->mmc;
 943
 944         WARN_ON(host->cmd || host->data);
 945
 946         host->cur_slot->mrq = NULL;
 947         host->mrq = NULL;
 948         if (!list_empty(&host->queue)) {
 949                 slot = list_entry(host->queue.next,
 950                                   struct dw_mci_slot, queue_node);
 951                 list_del(&slot->queue_node);
 952                 dev_vdbg(host->dev, "list not empty: %s is next\n",
 953                          mmc_hostname(slot->mmc));
 954                 host->state = STATE_SENDING_CMD;
 955                 dw_mci_start_request(host, slot);
 956         } else {
 957                 dev_vdbg(host->dev, "list empty\n");
 958                 host->state = STATE_IDLE;
 959         }
 960
 961         spin_unlock(&host->lock);
 962         mmc_request_done(prev_mmc, mrq);
 963         spin_lock(&host->lock);
 964 }
 965
 966 static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
 967 {
 968         u32 status = host->cmd_status;
 969
 970         host->cmd_status = 0;
 971
 972         /* Read the response from the card (up to 16 bytes) */
 973         if (cmd->flags & MMC_RSP_PRESENT) {
 974                 if (cmd->flags & MMC_RSP_136) {
 975                         cmd->resp[3] = mci_readl(host, RESP0);
 976                         cmd->resp[2] = mci_readl(host, RESP1);
 977                         cmd->resp[1] = mci_readl(host, RESP2);
 978                         cmd->resp[0] = mci_readl(host, RESP3);
 979                 } else {
 980                         cmd->resp[0] = mci_readl(host, RESP0);
 981                         cmd->resp[1] = 0;
 982                         cmd->resp[2] = 0;
 983                         cmd->resp[3] = 0;
 984                 }
 985         }
 986
 987         if (status & SDMMC_INT_RTO)
 988                 cmd->error = -ETIMEDOUT;
 989         else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
 990                 cmd->error = -EILSEQ;
 991         else if (status & SDMMC_INT_RESP_ERR)
 992                 cmd->error = -EIO;
 993         else
 994                 cmd->error = 0;
 995
 996         if (cmd->error) {
 997                 /* newer ip versions need a delay between retries */
 998                 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
 999                         mdelay(20);
1000
1001                 if (cmd->data) {
1002                         dw_mci_stop_dma(host);
1003                         host->data = NULL;
1004                 }
1005         }
1006 }
1007
1008 static void dw_mci_tasklet_func(unsigned long priv)
1009 {
1010         struct dw_mci *host = (struct dw_mci *)priv;
1011         struct mmc_data *data;
1012         struct mmc_command *cmd;
1013         enum dw_mci_state state;
1014         enum dw_mci_state prev_state;
1015         u32 status, ctrl;
1016
1017         spin_lock(&host->lock);
1018
1019         state = host->state;
1020         data = host->data;
1021
1022         do {
1023                 prev_state = state;
1024
1025                 switch (state) {
1026                 case STATE_IDLE:
1027                         break;
1028
1029                 case STATE_SENDING_CMD:
1030                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1031                                                 &host->pending_events))
1032                                 break;
1033
1034                         cmd = host->cmd;
1035                         host->cmd = NULL;
1036                         set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
1037                         dw_mci_command_complete(host, cmd);
1038                         if (cmd == host->mrq->sbc && !cmd->error) {
1039                                 prev_state = state = STATE_SENDING_CMD;
1040                                 __dw_mci_start_request(host, host->cur_slot,
1041                                                        host->mrq->cmd);
1042                                 goto unlock;
1043                         }
1044
1045                         if (!host->mrq->data || cmd->error) {
1046                                 dw_mci_request_end(host, host->mrq);
1047                                 goto unlock;
1048                         }
1049
1050                         prev_state = state = STATE_SENDING_DATA;
1051                         /* fall through */
1052
1053                 case STATE_SENDING_DATA:
1054                         if (test_and_clear_bit(EVENT_DATA_ERROR,
1055                                                &host->pending_events)) {
1056                                 dw_mci_stop_dma(host);
1057                                 if (data->stop)
1058                                         send_stop_cmd(host, data);
1059                                 state = STATE_DATA_ERROR;
1060                                 break;
1061                         }
1062
1063                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1064                                                 &host->pending_events))
1065                                 break;
1066
1067                         set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
1068                         prev_state = state = STATE_DATA_BUSY;
1069                         /* fall through */
1070
1071                 case STATE_DATA_BUSY:
1072                         if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
1073                                                 &host->pending_events))
1074                                 break;
1075
1076                         host->data = NULL;
1077                         set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
1078                         status = host->data_status;
1079
1080                         if (status & DW_MCI_DATA_ERROR_FLAGS) {
1081                                 if (status & SDMMC_INT_DTO) {
1082                                         data->error = -ETIMEDOUT;
1083                                 } else if (status & SDMMC_INT_DCRC) {
1084                                         data->error = -EILSEQ;
1085                                 } else if (status & SDMMC_INT_EBE &&
1086                                            host->dir_status ==
1087                                                         DW_MCI_SEND_STATUS) {
1088                                         /*
1089                                          * No data CRC status was returned.
1090                                          * The number of bytes transferred will
1091                                          * be exaggerated in PIO mode.
1092                                          */
1093                                         data->bytes_xfered = 0;
1094                                         data->error = -ETIMEDOUT;
1095                                 } else {
1096                                         dev_err(host->dev,
1097                                                 "data FIFO error "
1098                                                 "(status=%08x)\n",
1099                                                 status);
1100                                         data->error = -EIO;
1101                                 }
1102                                 /*
1103                                  * After an error, there may be data lingering
1104                                  * in the FIFO, so reset it - doing so
1105                                  * generates a block interrupt, hence setting
1106                                  * the scatter-gather pointer to NULL.
1107                                  */
1108                                 sg_miter_stop(&host->sg_miter);
1109                                 host->sg = NULL;
1110                                 ctrl = mci_readl(host, CTRL);
1111                                 ctrl |= SDMMC_CTRL_FIFO_RESET;
1112                                 mci_writel(host, CTRL, ctrl);
1113                         } else {
1114                                 data->bytes_xfered = data->blocks * data->blksz;
1115                                 data->error = 0;
1116                         }
1117
1118                         if (!data->stop) {
1119                                 dw_mci_request_end(host, host->mrq);
1120                                 goto unlock;
1121                         }
1122
1123                         if (host->mrq->sbc && !data->error) {
1124                                 data->stop->error = 0;
1125                                 dw_mci_request_end(host, host->mrq);
1126                                 goto unlock;
1127                         }
1128
1129                         prev_state = state = STATE_SENDING_STOP;
1130                         if (!data->error)
1131                                 send_stop_cmd(host, data);
1132                         /* fall through */
1133
1134                 case STATE_SENDING_STOP:
1135                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1136                                                 &host->pending_events))
1137                                 break;
1138
1139                         host->cmd = NULL;
1140                         dw_mci_command_complete(host, host->mrq->stop);
1141                         dw_mci_request_end(host, host->mrq);
1142                         goto unlock;
1143
1144                 case STATE_DATA_ERROR:
1145                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1146                                                 &host->pending_events))
1147                                 break;
1148
1149                         state = STATE_DATA_BUSY;
1150                         break;
1151                 }
1152         } while (state != prev_state);
1153
1154         host->state = state;
1155 unlock:
1156         spin_unlock(&host->lock);
1157
1158 }
1159
1160 /* push final bytes to part_buf, only use during push */
1161 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
1162 {
1163         memcpy((void *)&host->part_buf, buf, cnt);
1164         host->part_buf_count = cnt;
1165 }
1166
1167 /* append bytes to part_buf, only use during push */
1168 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
1169 {
1170         cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
1171         memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
1172         host->part_buf_count += cnt;
1173         return cnt;
1174 }
1175
1176 /* pull first bytes from part_buf, only use during pull */
1177 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
1178 {
1179         cnt = min(cnt, (int)host->part_buf_count);
1180         if (cnt) {
1181                 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
1182                        cnt);
1183                 host->part_buf_count -= cnt;
1184                 host->part_buf_start += cnt;
1185         }
1186         return cnt;
1187 }
1188
1189 /* pull final bytes from the part_buf, assuming it's just been filled */
1190 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
1191 {
1192         memcpy(buf, &host->part_buf, cnt);
1193         host->part_buf_start = cnt;
1194         host->part_buf_count = (1 << host->data_shift) - cnt;
1195 }
1196
1197 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
1198 {
1199         /* try and push anything in the part_buf */
1200         if (unlikely(host->part_buf_count)) {
1201                 int len = dw_mci_push_part_bytes(host, buf, cnt);
1202                 buf += len;
1203                 cnt -= len;
1204                 if (!sg_next(host->sg) || host->part_buf_count == 2) {
1205                         mci_writew(host, DATA(host->data_offset),
1206                                         host->part_buf16);
1207                         host->part_buf_count = 0;
1208                 }
1209         }
1210 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1211         if (unlikely((unsigned long)buf & 0x1)) {
1212                 while (cnt >= 2) {
1213                         u16 aligned_buf[64];
1214                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
1215                         int items = len >> 1;
1216                         int i;
1217                         /* memcpy from input buffer into aligned buffer */
1218                         memcpy(aligned_buf, buf, len);
1219                         buf += len;
1220                         cnt -= len;
1221                         /* push data from aligned buffer into fifo */
1222                         for (i = 0; i < items; ++i)
1223                                 mci_writew(host, DATA(host->data_offset),
1224                                                 aligned_buf[i]);
1225                 }
1226         } else
1227 #endif
1228         {
1229                 u16 *pdata = buf;
1230                 for (; cnt >= 2; cnt -= 2)
1231                         mci_writew(host, DATA(host->data_offset), *pdata++);
1232                 buf = pdata;
1233         }
1234         /* put anything remaining in the part_buf */
1235         if (cnt) {
1236                 dw_mci_set_part_bytes(host, buf, cnt);
1237                 if (!sg_next(host->sg))
1238                         mci_writew(host, DATA(host->data_offset),
1239                                         host->part_buf16);
1240         }
1241 }
1242
1243 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
1244 {
1245 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1246         if (unlikely((unsigned long)buf & 0x1)) {
1247                 while (cnt >= 2) {
1248                         /* pull data from fifo into aligned buffer */
1249                         u16 aligned_buf[64];
1250                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
1251                         int items = len >> 1;
1252                         int i;
1253                         for (i = 0; i < items; ++i)
1254                                 aligned_buf[i] = mci_readw(host,
1255                                                 DATA(host->data_offset));
1256                         /* memcpy from aligned buffer into output buffer */
1257                         memcpy(buf, aligned_buf, len);
1258                         buf += len;
1259                         cnt -= len;
1260                 }
1261         } else
1262 #endif
1263         {
1264                 u16 *pdata = buf;
1265                 for (; cnt >= 2; cnt -= 2)
1266                         *pdata++ = mci_readw(host, DATA(host->data_offset));
1267                 buf = pdata;
1268         }
1269         if (cnt) {
1270                 host->part_buf16 = mci_readw(host, DATA(host->data_offset));
1271                 dw_mci_pull_final_bytes(host, buf, cnt);
1272         }
1273 }
1274
1275 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
1276 {
1277         /* try and push anything in the part_buf */
1278         if (unlikely(host->part_buf_count)) {
1279                 int len = dw_mci_push_part_bytes(host, buf, cnt);
1280                 buf += len;
1281                 cnt -= len;
1282                 if (!sg_next(host->sg) || host->part_buf_count == 4) {
1283                         mci_writel(host, DATA(host->data_offset),
1284                                         host->part_buf32);
1285                         host->part_buf_count = 0;
1286                 }
1287         }
1288 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1289         if (unlikely((unsigned long)buf & 0x3)) {
1290                 while (cnt >= 4) {
1291                         u32 aligned_buf[32];
1292                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
1293                         int items = len >> 2;
1294                         int i;
1295                         /* memcpy from input buffer into aligned buffer */
1296                         memcpy(aligned_buf, buf, len);
1297                         buf += len;
1298                         cnt -= len;
1299                         /* push data from aligned buffer into fifo */
1300                         for (i = 0; i < items; ++i)
1301                                 mci_writel(host, DATA(host->data_offset),
1302                                                 aligned_buf[i]);
1303                 }
1304         } else
1305 #endif
1306         {
1307                 u32 *pdata = buf;
1308                 for (; cnt >= 4; cnt -= 4)
1309                         mci_writel(host, DATA(host->data_offset), *pdata++);
1310                 buf = pdata;
1311         }
1312         /* put anything remaining in the part_buf */
1313         if (cnt) {
1314                 dw_mci_set_part_bytes(host, buf, cnt);
1315                 if (!sg_next(host->sg))
1316                         mci_writel(host, DATA(host->data_offset),
1317                                                 host->part_buf32);
1318         }
1319 }
1320
1321 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
1322 {
1323 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1324         if (unlikely((unsigned long)buf & 0x3)) {
1325                 while (cnt >= 4) {
1326                         /* pull data from fifo into aligned buffer */
1327                         u32 aligned_buf[32];
1328                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
1329                         int items = len >> 2;
1330                         int i;
1331                         for (i = 0; i < items; ++i)
1332                                 aligned_buf[i] = mci_readl(host,
1333                                                 DATA(host->data_offset));
1334                         /* memcpy from aligned buffer into output buffer */
1335                         memcpy(buf, aligned_buf, len);
1336                         buf += len;
1337                         cnt -= len;
1338                 }
1339         } else
1340 #endif
1341         {
1342                 u32 *pdata = buf;
1343                 for (; cnt >= 4; cnt -= 4)
1344                         *pdata++ = mci_readl(host, DATA(host->data_offset));
1345                 buf = pdata;
1346         }
1347         if (cnt) {
1348                 host->part_buf32 = mci_readl(host, DATA(host->data_offset));
1349                 dw_mci_pull_final_bytes(host, buf, cnt);
1350         }
1351 }
1352
1353 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
1354 {
1355         /* try and push anything in the part_buf */
1356         if (unlikely(host->part_buf_count)) {
1357                 int len = dw_mci_push_part_bytes(host, buf, cnt);
1358                 buf += len;
1359                 cnt -= len;
1360                 if (!sg_next(host->sg) || host->part_buf_count == 8) {
1361                         mci_writew(host, DATA(host->data_offset),
1362                                         host->part_buf);
1363                         host->part_buf_count = 0;
1364                 }
1365         }
1366 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1367         if (unlikely((unsigned long)buf & 0x7)) {
1368                 while (cnt >= 8) {
1369                         u64 aligned_buf[16];
1370                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
1371                         int items = len >> 3;
1372                         int i;
1373                         /* memcpy from input buffer into aligned buffer */
1374                         memcpy(aligned_buf, buf, len);
1375                         buf += len;
1376                         cnt -= len;
1377                         /* push data from aligned buffer into fifo */
1378                         for (i = 0; i < items; ++i)
1379                                 mci_writeq(host, DATA(host->data_offset),
1380                                                 aligned_buf[i]);
1381                 }
1382         } else
1383 #endif
1384         {
1385                 u64 *pdata = buf;
1386                 for (; cnt >= 8; cnt -= 8)
1387                         mci_writeq(host, DATA(host->data_offset), *pdata++);
1388                 buf = pdata;
1389         }
1390         /* put anything remaining in the part_buf */
1391         if (cnt) {
1392                 dw_mci_set_part_bytes(host, buf, cnt);
1393                 if (!sg_next(host->sg))
1394                         mci_writeq(host, DATA(host->data_offset),
1395                                         host->part_buf);
1396         }
1397 }
1398
1399 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
1400 {
1401 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1402         if (unlikely((unsigned long)buf & 0x7)) {
1403                 while (cnt >= 8) {
1404                         /* pull data from fifo into aligned buffer */
1405                         u64 aligned_buf[16];
1406                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
1407                         int items = len >> 3;
1408                         int i;
1409                         for (i = 0; i < items; ++i)
1410                                 aligned_buf[i] = mci_readq(host,
1411                                                 DATA(host->data_offset));
1412                         /* memcpy from aligned buffer into output buffer */
1413                         memcpy(buf, aligned_buf, len);
1414                         buf += len;
1415                         cnt -= len;
1416                 }
1417         } else
1418 #endif
1419         {
1420                 u64 *pdata = buf;
1421                 for (; cnt >= 8; cnt -= 8)
1422                         *pdata++ = mci_readq(host, DATA(host->data_offset));
1423                 buf = pdata;
1424         }
1425         if (cnt) {
1426                 host->part_buf = mci_readq(host, DATA(host->data_offset));
1427                 dw_mci_pull_final_bytes(host, buf, cnt);
1428         }
1429 }
1430
1431 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
1432 {
1433         int len;
1434
1435         /* get remaining partial bytes */
1436         len = dw_mci_pull_part_bytes(host, buf, cnt);
1437         if (unlikely(len == cnt))
1438                 return;
1439         buf += len;
1440         cnt -= len;
1441
1442         /* get the rest of the data */
1443         host->pull_data(host, buf, cnt);
1444 }
1445
1446 static void dw_mci_read_data_pio(struct dw_mci *host)
1447 {
1448         struct sg_mapping_iter *sg_miter = &host->sg_miter;
1449         void *buf;
1450         unsigned int offset;
1451         struct mmc_data *data = host->data;
1452         int shift = host->data_shift;
1453         u32 status;
1454         unsigned int nbytes = 0, len;
1455         unsigned int remain, fcnt;
1456
1457         do {
1458                 if (!sg_miter_next(sg_miter))
1459                         goto done;
1460
1461                 host->sg = sg_miter->__sg;
1462                 buf = sg_miter->addr;
1463                 remain = sg_miter->length;
1464                 offset = 0;
1465
1466                 do {
1467                         fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
1468                                         << shift) + host->part_buf_count;
1469                         len = min(remain, fcnt);
1470                         if (!len)
1471                                 break;
1472                         dw_mci_pull_data(host, (void *)(buf + offset), len);
1473                         offset += len;
1474                         nbytes += len;
1475                         remain -= len;
1476                 } while (remain);
1477
1478                 sg_miter->consumed = offset;
1479                 status = mci_readl(host, MINTSTS);
1480                 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
1481         } while (status & SDMMC_INT_RXDR); /*if the RXDR is ready read again*/
1482         data->bytes_xfered += nbytes;
1483
1484         if (!remain) {
1485                 if (!sg_miter_next(sg_miter))
1486                         goto done;
1487                 sg_miter->consumed = 0;
1488         }
1489         sg_miter_stop(sg_miter);
1490         return;
1491
1492 done:
1493         data->bytes_xfered += nbytes;
1494         sg_miter_stop(sg_miter);
1495         host->sg = NULL;
1496         smp_wmb();
1497         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1498 }
1499
1500 static void dw_mci_write_data_pio(struct dw_mci *host)
1501 {
1502         struct sg_mapping_iter *sg_miter = &host->sg_miter;
1503         void *buf;
1504         unsigned int offset;
1505         struct mmc_data *data = host->data;
1506         int shift = host->data_shift;
1507         u32 status;
1508         unsigned int nbytes = 0, len;
1509         unsigned int fifo_depth = host->fifo_depth;
1510         unsigned int remain, fcnt;
1511
1512         do {
1513                 if (!sg_miter_next(sg_miter))
1514                         goto done;
1515
1516                 host->sg = sg_miter->__sg;
1517                 buf = sg_miter->addr;
1518                 remain = sg_miter->length;
1519                 offset = 0;
1520
1521                 do {
1522                         fcnt = ((fifo_depth -
1523                                  SDMMC_GET_FCNT(mci_readl(host, STATUS)))
1524                                         << shift) - host->part_buf_count;
1525                         len = min(remain, fcnt);
1526                         if (!len)
1527                                 break;
1528                         host->push_data(host, (void *)(buf + offset), len);
1529                         offset += len;
1530                         nbytes += len;
1531                         remain -= len;
1532                 } while (remain);
1533
1534                 sg_miter->consumed = offset;
1535                 status = mci_readl(host, MINTSTS);
1536                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
1537         } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
1538         data->bytes_xfered += nbytes;
1539
1540         if (!remain) {
1541                 if (!sg_miter_next(sg_miter))
1542                         goto done;
1543                 sg_miter->consumed = 0;
1544         }
1545         sg_miter_stop(sg_miter);
1546         return;
1547
1548 done:
1549         data->bytes_xfered += nbytes;
1550         sg_miter_stop(sg_miter);
1551         host->sg = NULL;
1552         smp_wmb();
1553         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1554 }
1555
1556 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
1557 {
1558         if (!host->cmd_status)
1559                 host->cmd_status = status;
1560
1561         smp_wmb();
1562
1563         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1564         tasklet_schedule(&host->tasklet);
1565 }
1566
1567 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
1568 {
1569         struct dw_mci *host = dev_id;
1570         u32 pending;
1571         unsigned int pass_count = 0;
1572         int i;
1573
1574         do {
1575                 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
1576
1577                 /*
1578                  * DTO fix - version 2.10a and below, and only if internal DMA
1579                  * is configured.
1580                  */
1581                 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
1582                         if (!pending &&
1583                             ((mci_readl(host, STATUS) >> 17) & 0x1fff))
1584                                 pending |= SDMMC_INT_DATA_OVER;
1585                 }
1586
1587                 if (!pending)
1588                         break;
1589
1590                 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
1591                         mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
1592                         host->cmd_status = pending;
1593                         smp_wmb();
1594                         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1595                 }
1596
1597                 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
1598                         /* if there is an error report DATA_ERROR */
1599                         mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
1600                         host->data_status = pending;
1601                         smp_wmb();
1602                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
1603                         tasklet_schedule(&host->tasklet);
1604                 }
1605
1606                 if (pending & SDMMC_INT_DATA_OVER) {
1607                         mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
1608                         if (!host->data_status)
1609                                 host->data_status = pending;
1610                         smp_wmb();
1611                         if (host->dir_status == DW_MCI_RECV_STATUS) {
1612                                 if (host->sg != NULL)
1613                                         dw_mci_read_data_pio(host);
1614                         }
1615                         set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
1616                         tasklet_schedule(&host->tasklet);
1617                 }
1618
1619                 if (pending & SDMMC_INT_RXDR) {
1620                         mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
1621                         if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
1622                                 dw_mci_read_data_pio(host);
1623                 }
1624
1625                 if (pending & SDMMC_INT_TXDR) {
1626                         mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
1627                         if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
1628                                 dw_mci_write_data_pio(host);
1629                 }
1630
1631                 if (pending & SDMMC_INT_CMD_DONE) {
1632                         mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
1633                         dw_mci_cmd_interrupt(host, pending);
1634                 }
1635
1636                 if (pending & SDMMC_INT_CD) {
1637                         mci_writel(host, RINTSTS, SDMMC_INT_CD);
1638                         queue_work(host->card_workqueue, &host->card_work);
1639                 }
1640
1641                 /* Handle SDIO Interrupts */
1642                 for (i = 0; i < host->num_slots; i++) {
1643                         struct dw_mci_slot *slot = host->slot[i];
1644                         if (pending & SDMMC_INT_SDIO(i)) {
1645                                 mci_writel(host, RINTSTS, SDMMC_INT_SDIO(i));
1646                                 mmc_signal_sdio_irq(slot->mmc);
1647                         }
1648                 }
1649
1650         } while (pass_count++ < 5);
1651
1652 #ifdef CONFIG_MMC_DW_IDMAC
1653         /* Handle DMA interrupts */
1654         pending = mci_readl(host, IDSTS);
1655         if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
1656                 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI);
1657                 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
1658                 host->dma_ops->complete(host);
1659         }
1660 #endif
1661
1662         return IRQ_HANDLED;
1663 }
1664
1665 static void dw_mci_work_routine_card(struct work_struct *work)
1666 {
1667         struct dw_mci *host = container_of(work, struct dw_mci, card_work);
1668         int i;
1669
1670         for (i = 0; i < host->num_slots; i++) {
1671                 struct dw_mci_slot *slot = host->slot[i];
1672                 struct mmc_host *mmc = slot->mmc;
1673                 struct mmc_request *mrq;
1674                 int present;
1675                 u32 ctrl;
1676
1677                 present = dw_mci_get_cd(mmc);
1678                 while (present != slot->last_detect_state) {
1679                         dev_dbg(&slot->mmc->class_dev, "card %s\n",
1680                                 present ? "inserted" : "removed");
1681
1682                         /* Power up slot (before spin_lock, may sleep) */
1683                         if (present != 0 && host->pdata->setpower)
1684                                 host->pdata->setpower(slot->id, mmc->ocr_avail);
1685
1686                         spin_lock_bh(&host->lock);
1687
1688                         /* Card change detected */
1689                         slot->last_detect_state = present;
1690
1691                         /* Mark card as present if applicable */
1692                         if (present != 0)
1693                                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1694
1695                         /* Clean up queue if present */
1696                         mrq = slot->mrq;
1697                         if (mrq) {
1698                                 if (mrq == host->mrq) {
1699                                         host->data = NULL;
1700                                         host->cmd = NULL;
1701
1702                                         switch (host->state) {
1703                                         case STATE_IDLE:
1704                                                 break;
1705                                         case STATE_SENDING_CMD:
1706                                                 mrq->cmd->error = -ENOMEDIUM;
1707                                                 if (!mrq->data)
1708                                                         break;
1709                                                 /* fall through */
1710                                         case STATE_SENDING_DATA:
1711                                                 mrq->data->error = -ENOMEDIUM;
1712                                                 dw_mci_stop_dma(host);
1713                                                 break;
1714                                         case STATE_DATA_BUSY:
1715                                         case STATE_DATA_ERROR:
1716                                                 if (mrq->data->error == -EINPROGRESS)
1717                                                         mrq->data->error = -ENOMEDIUM;
1718                                                 if (!mrq->stop)
1719                                                         break;
1720                                                 /* fall through */
1721                                         case STATE_SENDING_STOP:
1722                                                 mrq->stop->error = -ENOMEDIUM;
1723                                                 break;
1724                                         }
1725
1726                                         dw_mci_request_end(host, mrq);
1727                                 } else {
1728                                         list_del(&slot->queue_node);
1729                                         mrq->cmd->error = -ENOMEDIUM;
1730                                         if (mrq->data)
1731                                                 mrq->data->error = -ENOMEDIUM;
1732                                         if (mrq->stop)
1733                                                 mrq->stop->error = -ENOMEDIUM;
1734
1735                                         spin_unlock(&host->lock);
1736                                         mmc_request_done(slot->mmc, mrq);
1737                                         spin_lock(&host->lock);
1738                                 }
1739                         }
1740
1741                         /* Power down slot */
1742                         if (present == 0) {
1743                                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1744
1745                                 /*
1746                                  * Clear down the FIFO - doing so generates a
1747                                  * block interrupt, hence setting the
1748                                  * scatter-gather pointer to NULL.
1749                                  */
1750                                 sg_miter_stop(&host->sg_miter);
1751                                 host->sg = NULL;
1752
1753                                 ctrl = mci_readl(host, CTRL);
1754                                 ctrl |= SDMMC_CTRL_FIFO_RESET;
1755                                 mci_writel(host, CTRL, ctrl);
1756
1757 #ifdef CONFIG_MMC_DW_IDMAC
1758                                 ctrl = mci_readl(host, BMOD);
1759                                 /* Software reset of DMA */
1760                                 ctrl |= SDMMC_IDMAC_SWRESET;
1761                                 mci_writel(host, BMOD, ctrl);
1762 #endif
1763
1764                         }
1765
1766                         spin_unlock_bh(&host->lock);
1767
1768                         /* Power down slot (after spin_unlock, may sleep) */
1769                         if (present == 0 && host->pdata->setpower)
1770                                 host->pdata->setpower(slot->id, 0);
1771
1772                         present = dw_mci_get_cd(mmc);
1773                 }
1774
1775                 mmc_detect_change(slot->mmc,
1776                         msecs_to_jiffies(host->pdata->detect_delay_ms));
1777         }
1778 }
1779
1780 #ifdef CONFIG_OF
1781 /* given a slot id, find out the device node representing that slot */
1782 static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
1783 {
1784         struct device_node *np;
1785         const __be32 *addr;
1786         int len;
1787
1788         if (!dev || !dev->of_node)
1789                 return NULL;
1790
1791         for_each_child_of_node(dev->of_node, np) {
1792                 addr = of_get_property(np, "reg", &len);
1793                 if (!addr || (len < sizeof(int)))
1794                         continue;
1795                 if (be32_to_cpup(addr) == slot)
1796                         return np;
1797         }
1798         return NULL;
1799 }
1800
1801 /* find out bus-width for a given slot */
1802 static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot)
1803 {
1804         struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
1805         u32 bus_wd = 1;
1806
1807         if (!np)
1808                 return 1;
1809
1810         if (of_property_read_u32(np, "bus-width", &bus_wd))
1811                 dev_err(dev, "bus-width property not found, assuming width"
1812                                " as 1\n");
1813         return bus_wd;
1814 }
1815 #else /* CONFIG_OF */
1816 static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot)
1817 {
1818         return 1;
1819 }
1820 static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
1821 {
1822         return NULL;
1823 }
1824 #endif /* CONFIG_OF */
1825
1826 static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
1827 {
1828         struct mmc_host *mmc;
1829         struct dw_mci_slot *slot;
1830         int ctrl_id, ret;
1831         u8 bus_width;
1832
1833         mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
1834         if (!mmc)
1835                 return -ENOMEM;
1836
1837         slot = mmc_priv(mmc);
1838         slot->id = id;
1839         slot->mmc = mmc;
1840         slot->host = host;
1841         host->slot[id] = slot;
1842
1843         mmc->ops = &dw_mci_ops;
1844         mmc->f_min = DIV_ROUND_UP(host->bus_hz, 510);
1845         mmc->f_max = host->bus_hz;
1846
1847         if (host->pdata->get_ocr)
1848                 mmc->ocr_avail = host->pdata->get_ocr(id);
1849         else
1850                 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1851
1852         /*
1853          * Start with slot power disabled, it will be enabled when a card
1854          * is detected.
1855          */
1856         if (host->pdata->setpower)
1857                 host->pdata->setpower(id, 0);
1858
1859         if (host->pdata->caps)
1860                 mmc->caps = host->pdata->caps;
1861
1862         if (host->dev->of_node) {
1863                 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
1864                 if (ctrl_id < 0)
1865                         ctrl_id = 0;
1866         } else {
1867                 ctrl_id = to_platform_device(host->dev)->id;
1868         }
1869         if (host->drv_data && host->drv_data->caps)
1870                 mmc->caps |= host->drv_data->caps[ctrl_id];
1871
1872         if (host->pdata->caps2)
1873                 mmc->caps2 = host->pdata->caps2;
1874
1875         if (host->pdata->get_bus_wd)
1876                 bus_width = host->pdata->get_bus_wd(slot->id);
1877         else if (host->dev->of_node)
1878                 bus_width = dw_mci_of_get_bus_wd(host->dev, slot->id);
1879         else
1880                 bus_width = 1;
1881
1882         if (host->drv_data->setup_bus) {
1883                 struct device_node *slot_np;
1884                 slot_np = dw_mci_of_find_slot_node(host->dev, slot->id);
1885                 ret = host->drv_data->setup_bus(host, slot_np, bus_width);
1886                 if (ret)
1887                         goto err_setup_bus;
1888         }
1889
1890         switch (bus_width) {
1891         case 8:
1892                 mmc->caps |= MMC_CAP_8_BIT_DATA;
1893         case 4:
1894                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1895         }
1896
1897         if (host->pdata->quirks & DW_MCI_QUIRK_HIGHSPEED)
1898                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
1899
1900         if (mmc->caps2 & MMC_CAP2_POWEROFF_NOTIFY)
1901                 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_SHORT;
1902         else
1903                 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_NONE;
1904
1905         if (host->pdata->blk_settings) {
1906                 mmc->max_segs = host->pdata->blk_settings->max_segs;
1907                 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
1908                 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
1909                 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
1910                 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
1911         } else {
1912                 /* Useful defaults if platform data is unset. */
1913 #ifdef CONFIG_MMC_DW_IDMAC
1914                 mmc->max_segs = host->ring_size;
1915                 mmc->max_blk_size = 65536;
1916                 mmc->max_blk_count = host->ring_size;
1917                 mmc->max_seg_size = 0x1000;
1918                 mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count;
1919 #else
1920                 mmc->max_segs = 64;
1921                 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
1922                 mmc->max_blk_count = 512;
1923                 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1924                 mmc->max_seg_size = mmc->max_req_size;
1925 #endif /* CONFIG_MMC_DW_IDMAC */
1926         }
1927
1928         host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
1929         if (IS_ERR(host->vmmc)) {
1930                 pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
1931                 host->vmmc = NULL;
1932         } else
1933                 regulator_enable(host->vmmc);
1934
1935         if (dw_mci_get_cd(mmc))
1936                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1937         else
1938                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1939
1940         mmc_add_host(mmc);
1941
1942 #if defined(CONFIG_DEBUG_FS)
1943         dw_mci_init_debugfs(slot);
1944 #endif
1945
1946         /* Card initially undetected */
1947         slot->last_detect_state = 0;
1948
1949         /*
1950          * Card may have been plugged in prior to boot so we
1951          * need to run the detect tasklet
1952          */
1953         queue_work(host->card_workqueue, &host->card_work);
1954
1955         return 0;
1956
1957 err_setup_bus:
1958         mmc_free_host(mmc);
1959         return -EINVAL;
1960 }
1961
1962 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
1963 {
1964         /* Shutdown detect IRQ */
1965         if (slot->host->pdata->exit)
1966                 slot->host->pdata->exit(id);
1967
1968         /* Debugfs stuff is cleaned up by mmc core */
1969         mmc_remove_host(slot->mmc);
1970         slot->host->slot[id] = NULL;
1971         mmc_free_host(slot->mmc);
1972 }
1973
1974 static void dw_mci_init_dma(struct dw_mci *host)
1975 {
1976         /* Alloc memory for sg translation */
1977         host->sg_cpu = dma_alloc_coherent(host->dev, PAGE_SIZE,
1978                                           &host->sg_dma, GFP_KERNEL);
1979         if (!host->sg_cpu) {
1980                 dev_err(host->dev, "%s: could not alloc DMA memory\n",
1981                         __func__);
1982                 goto no_dma;
1983         }
1984
1985         /* Determine which DMA interface to use */
1986 #ifdef CONFIG_MMC_DW_IDMAC
1987         host->dma_ops = &dw_mci_idmac_ops;
1988 #endif
1989
1990         if (!host->dma_ops)
1991                 goto no_dma;
1992
1993         if (host->dma_ops->init && host->dma_ops->start &&
1994             host->dma_ops->stop && host->dma_ops->cleanup) {
1995                 if (host->dma_ops->init(host)) {
1996                         dev_err(host->dev, "%s: Unable to initialize "
1997                                 "DMA Controller.\n", __func__);
1998                         goto no_dma;
1999                 }
2000         } else {
2001                 dev_err(host->dev, "DMA initialization not found.\n");
2002                 goto no_dma;
2003         }
2004
2005         host->use_dma = 1;
2006         return;
2007
2008 no_dma:
2009         dev_info(host->dev, "Using PIO mode.\n");
2010         host->use_dma = 0;
2011         return;
2012 }
2013
2014 static bool mci_wait_reset(struct device *dev, struct dw_mci *host)
2015 {
2016         unsigned long timeout = jiffies + msecs_to_jiffies(500);
2017         unsigned int ctrl;
2018
2019         mci_writel(host, CTRL, (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
2020                                 SDMMC_CTRL_DMA_RESET));
2021
2022         /* wait till resets clear */
2023         do {
2024                 ctrl = mci_readl(host, CTRL);
2025                 if (!(ctrl & (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
2026                               SDMMC_CTRL_DMA_RESET)))
2027                         return true;
2028         } while (time_before(jiffies, timeout));
2029
2030         dev_err(dev, "Timeout resetting block (ctrl %#x)\n", ctrl);
2031
2032         return false;
2033 }
2034
2035 #ifdef CONFIG_OF
2036 static struct dw_mci_of_quirks {
2037         char *quirk;
2038         int id;
2039 } of_quirks[] = {
2040         {
2041                 .quirk  = "supports-highspeed",
2042                 .id     = DW_MCI_QUIRK_HIGHSPEED,
2043         }, {
2044                 .quirk  = "broken-cd",
2045                 .id     = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
2046         },
2047 };
2048
2049 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2050 {
2051         struct dw_mci_board *pdata;
2052         struct device *dev = host->dev;
2053         struct device_node *np = dev->of_node;
2054         int idx, ret;
2055
2056         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2057         if (!pdata) {
2058                 dev_err(dev, "could not allocate memory for pdata\n");
2059                 return ERR_PTR(-ENOMEM);
2060         }
2061
2062         /* find out number of slots supported */
2063         if (of_property_read_u32(dev->of_node, "num-slots",
2064                                 &pdata->num_slots)) {
2065                 dev_info(dev, "num-slots property not found, "
2066                                 "assuming 1 slot is available\n");
2067                 pdata->num_slots = 1;
2068         }
2069
2070         /* get quirks */
2071         for (idx = 0; idx < ARRAY_SIZE(of_quirks); idx++)
2072                 if (of_get_property(np, of_quirks[idx].quirk, NULL))
2073                         pdata->quirks |= of_quirks[idx].id;
2074
2075         if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
2076                 dev_info(dev, "fifo-depth property not found, using "
2077                                 "value of FIFOTH register as default\n");
2078
2079         of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
2080
2081         if (host->drv_data->parse_dt) {
2082                 ret = host->drv_data->parse_dt(host);
2083                 if (ret)
2084                         return ERR_PTR(ret);
2085         }
2086
2087         return pdata;
2088 }
2089
2090 #else /* CONFIG_OF */
2091 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2092 {
2093         return ERR_PTR(-EINVAL);
2094 }
2095 #endif /* CONFIG_OF */
2096
2097 int dw_mci_probe(struct dw_mci *host)
2098 {
2099         int width, i, ret = 0;
2100         u32 fifo_size;
2101         int init_slots = 0;
2102
2103         if (!host->pdata) {
2104                 host->pdata = dw_mci_parse_dt(host);
2105                 if (IS_ERR(host->pdata)) {
2106                         dev_err(host->dev, "platform data not available\n");
2107                         return -EINVAL;
2108                 }
2109         }
2110
2111         if (!host->pdata->select_slot && host->pdata->num_slots > 1) {
2112                 dev_err(host->dev,
2113                         "Platform data must supply select_slot function\n");
2114                 return -ENODEV;
2115         }
2116
2117         host->biu_clk = clk_get(host->dev, "biu");
2118         if (IS_ERR(host->biu_clk)) {
2119                 dev_dbg(host->dev, "biu clock not available\n");
2120         } else {
2121                 ret = clk_prepare_enable(host->biu_clk);
2122                 if (ret) {
2123                         dev_err(host->dev, "failed to enable biu clock\n");
2124                         clk_put(host->biu_clk);
2125                         return ret;
2126                 }
2127         }
2128
2129         host->ciu_clk = clk_get(host->dev, "ciu");
2130         if (IS_ERR(host->ciu_clk)) {
2131                 dev_dbg(host->dev, "ciu clock not available\n");
2132         } else {
2133                 ret = clk_prepare_enable(host->ciu_clk);
2134                 if (ret) {
2135                         dev_err(host->dev, "failed to enable ciu clock\n");
2136                         clk_put(host->ciu_clk);
2137                         goto err_clk_biu;
2138                 }
2139         }
2140
2141         if (IS_ERR(host->ciu_clk))
2142                 host->bus_hz = host->pdata->bus_hz;
2143         else
2144                 host->bus_hz = clk_get_rate(host->ciu_clk);
2145
2146         if (host->drv_data->setup_clock) {
2147                 ret = host->drv_data->setup_clock(host);
2148                 if (ret) {
2149                         dev_err(host->dev,
2150                                 "implementation specific clock setup failed\n");
2151                         goto err_clk_ciu;
2152                 }
2153         }
2154
2155         if (!host->bus_hz) {
2156                 dev_err(host->dev,
2157                         "Platform data must supply bus speed\n");
2158                 ret = -ENODEV;
2159                 goto err_clk_ciu;
2160         }
2161
2162         host->quirks = host->pdata->quirks;
2163
2164         spin_lock_init(&host->lock);
2165         INIT_LIST_HEAD(&host->queue);
2166
2167         /*
2168          * Get the host data width - this assumes that HCON has been set with
2169          * the correct values.
2170          */
2171         i = (mci_readl(host, HCON) >> 7) & 0x7;
2172         if (!i) {
2173                 host->push_data = dw_mci_push_data16;
2174                 host->pull_data = dw_mci_pull_data16;
2175                 width = 16;
2176                 host->data_shift = 1;
2177         } else if (i == 2) {
2178                 host->push_data = dw_mci_push_data64;
2179                 host->pull_data = dw_mci_pull_data64;
2180                 width = 64;
2181                 host->data_shift = 3;
2182         } else {
2183                 /* Check for a reserved value, and warn if it is */
2184                 WARN((i != 1),
2185                      "HCON reports a reserved host data width!\n"
2186                      "Defaulting to 32-bit access.\n");
2187                 host->push_data = dw_mci_push_data32;
2188                 host->pull_data = dw_mci_pull_data32;
2189                 width = 32;
2190                 host->data_shift = 2;
2191         }
2192
2193         /* Reset all blocks */
2194         if (!mci_wait_reset(host->dev, host))
2195                 return -ENODEV;
2196
2197         host->dma_ops = host->pdata->dma_ops;
2198         dw_mci_init_dma(host);
2199
2200         /* Clear the interrupts for the host controller */
2201         mci_writel(host, RINTSTS, 0xFFFFFFFF);
2202         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
2203
2204         /* Put in max timeout */
2205         mci_writel(host, TMOUT, 0xFFFFFFFF);
2206
2207         /*
2208          * FIFO threshold settings  RxMark  = fifo_size / 2 - 1,
2209          *                          Tx Mark = fifo_size / 2 DMA Size = 8
2210          */
2211         if (!host->pdata->fifo_depth) {
2212                 /*
2213                  * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
2214                  * have been overwritten by the bootloader, just like we're
2215                  * about to do, so if you know the value for your hardware, you
2216                  * should put it in the platform data.
2217                  */
2218                 fifo_size = mci_readl(host, FIFOTH);
2219                 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
2220         } else {
2221                 fifo_size = host->pdata->fifo_depth;
2222         }
2223         host->fifo_depth = fifo_size;
2224         host->fifoth_val = ((0x2 << 28) | ((fifo_size/2 - 1) << 16) |
2225                         ((fifo_size/2) << 0));
2226         mci_writel(host, FIFOTH, host->fifoth_val);
2227
2228         /* disable clock to CIU */
2229         mci_writel(host, CLKENA, 0);
2230         mci_writel(host, CLKSRC, 0);
2231
2232         tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
2233         host->card_workqueue = alloc_workqueue("dw-mci-card",
2234                         WQ_MEM_RECLAIM | WQ_NON_REENTRANT, 1);
2235         if (!host->card_workqueue)
2236                 goto err_dmaunmap;
2237         INIT_WORK(&host->card_work, dw_mci_work_routine_card);
2238         ret = request_irq(host->irq, dw_mci_interrupt, host->irq_flags, "dw-mci", host);
2239         if (ret)
2240                 goto err_workqueue;
2241
2242         if (host->pdata->num_slots)
2243                 host->num_slots = host->pdata->num_slots;
2244         else
2245                 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
2246
2247         /* We need at least one slot to succeed */
2248         for (i = 0; i < host->num_slots; i++) {
2249                 ret = dw_mci_init_slot(host, i);
2250                 if (ret)
2251                         dev_dbg(host->dev, "slot %d init failed\n", i);
2252                 else
2253                         init_slots++;
2254         }
2255
2256         if (init_slots) {
2257                 dev_info(host->dev, "%d slots initialized\n", init_slots);
2258         } else {
2259                 dev_dbg(host->dev, "attempted to initialize %d slots, "
2260                                         "but failed on all\n", host->num_slots);
2261                 goto err_init_slot;
2262         }
2263
2264         /*
2265          * In 2.40a spec, Data offset is changed.
2266          * Need to check the version-id and set data-offset for DATA register.
2267          */
2268         host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
2269         dev_info(host->dev, "Version ID is %04x\n", host->verid);
2270
2271         if (host->verid < DW_MMC_240A)
2272                 host->data_offset = DATA_OFFSET;
2273         else
2274                 host->data_offset = DATA_240A_OFFSET;
2275
2276         /*
2277          * Enable interrupts for command done, data over, data empty, card det,
2278          * receive ready and error such as transmit, receive timeout, crc error
2279          */
2280         mci_writel(host, RINTSTS, 0xFFFFFFFF);
2281         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2282                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2283                    DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
2284         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
2285
2286         dev_info(host->dev, "DW MMC controller at irq %d, "
2287                  "%d bit host data width, "
2288                  "%u deep fifo\n",
2289                  host->irq, width, fifo_size);
2290         if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
2291                 dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n");
2292
2293         return 0;
2294
2295 err_init_slot:
2296         free_irq(host->irq, host);
2297
2298 err_workqueue:
2299         destroy_workqueue(host->card_workqueue);
2300
2301 err_dmaunmap:
2302         if (host->use_dma && host->dma_ops->exit)
2303                 host->dma_ops->exit(host);
2304         dma_free_coherent(host->dev, PAGE_SIZE,
2305                           host->sg_cpu, host->sg_dma);
2306
2307         if (host->vmmc) {
2308                 regulator_disable(host->vmmc);
2309                 regulator_put(host->vmmc);
2310         }
2311
2312 err_clk_ciu:
2313         if (!IS_ERR(host->ciu_clk)) {
2314                 clk_disable_unprepare(host->ciu_clk);
2315                 clk_put(host->ciu_clk);
2316         }
2317 err_clk_biu:
2318         if (!IS_ERR(host->biu_clk)) {
2319                 clk_disable_unprepare(host->biu_clk);
2320                 clk_put(host->biu_clk);
2321         }
2322         return ret;
2323 }
2324 EXPORT_SYMBOL(dw_mci_probe);
2325
2326 void dw_mci_remove(struct dw_mci *host)
2327 {
2328         int i;
2329
2330         mci_writel(host, RINTSTS, 0xFFFFFFFF);
2331         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
2332
2333         for (i = 0; i < host->num_slots; i++) {
2334                 dev_dbg(host->dev, "remove slot %d\n", i);
2335                 if (host->slot[i])
2336                         dw_mci_cleanup_slot(host->slot[i], i);
2337         }
2338
2339         /* disable clock to CIU */
2340         mci_writel(host, CLKENA, 0);
2341         mci_writel(host, CLKSRC, 0);
2342
2343         free_irq(host->irq, host);
2344         destroy_workqueue(host->card_workqueue);
2345         dma_free_coherent(host->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
2346
2347         if (host->use_dma && host->dma_ops->exit)
2348                 host->dma_ops->exit(host);
2349
2350         if (host->vmmc) {
2351                 regulator_disable(host->vmmc);
2352                 regulator_put(host->vmmc);
2353         }
2354
2355         if (!IS_ERR(host->ciu_clk))
2356                 clk_disable_unprepare(host->ciu_clk);
2357         if (!IS_ERR(host->biu_clk))
2358                 clk_disable_unprepare(host->biu_clk);
2359         clk_put(host->ciu_clk);
2360         clk_put(host->biu_clk);
2361 }
2362 EXPORT_SYMBOL(dw_mci_remove);
2363
2364
2365
2366 #ifdef CONFIG_PM_SLEEP
2367 /*
2368  * TODO: we should probably disable the clock to the card in the suspend path.
2369  */
2370 int dw_mci_suspend(struct dw_mci *host)
2371 {
2372         int i, ret = 0;
2373
2374         for (i = 0; i < host->num_slots; i++) {
2375                 struct dw_mci_slot *slot = host->slot[i];
2376                 if (!slot)
2377                         continue;
2378                 ret = mmc_suspend_host(slot->mmc);
2379                 if (ret < 0) {
2380                         while (--i >= 0) {
2381                                 slot = host->slot[i];
2382                                 if (slot)
2383                                         mmc_resume_host(host->slot[i]->mmc);
2384                         }
2385                         return ret;
2386                 }
2387         }
2388
2389         if (host->vmmc)
2390                 regulator_disable(host->vmmc);
2391
2392         return 0;
2393 }
2394 EXPORT_SYMBOL(dw_mci_suspend);
2395
2396 int dw_mci_resume(struct dw_mci *host)
2397 {
2398         int i, ret;
2399
2400         if (host->vmmc)
2401                 regulator_enable(host->vmmc);
2402
2403         if (!mci_wait_reset(host->dev, host)) {
2404                 ret = -ENODEV;
2405                 return ret;
2406         }
2407
2408         if (host->use_dma && host->dma_ops->init)
2409                 host->dma_ops->init(host);
2410
2411         /* Restore the old value at FIFOTH register */
2412         mci_writel(host, FIFOTH, host->fifoth_val);
2413
2414         mci_writel(host, RINTSTS, 0xFFFFFFFF);
2415         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2416                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2417                    DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
2418         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
2419
2420         for (i = 0; i < host->num_slots; i++) {
2421                 struct dw_mci_slot *slot = host->slot[i];
2422                 if (!slot)
2423                         continue;
2424                 ret = mmc_resume_host(host->slot[i]->mmc);
2425                 if (ret < 0)
2426                         return ret;
2427         }
2428         return 0;
2429 }
2430 EXPORT_SYMBOL(dw_mci_resume);
2431 #endif /* CONFIG_PM_SLEEP */
2432
2433 static int __init dw_mci_init(void)
2434 {
2435         printk(KERN_INFO "Synopsys Designware Multimedia Card Interface Driver");
2436         return 0;
2437 }
2438
2439 static void __exit dw_mci_exit(void)
2440 {
2441 }
2442
2443 module_init(dw_mci_init);
2444 module_exit(dw_mci_exit);
2445
2446 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
2447 MODULE_AUTHOR("NXP Semiconductor VietNam");
2448 MODULE_AUTHOR("Imagination Technologies Ltd");
2449 MODULE_LICENSE("GPL v2");