2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/blkdev.h>
15 #include <linux/clk.h>
16 #include <linux/debugfs.h>
17 #include <linux/device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/ioport.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/seq_file.h>
26 #include <linux/slab.h>
27 #include <linux/stat.h>
28 #include <linux/delay.h>
29 #include <linux/irq.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/host.h>
32 #include <linux/mmc/mmc.h>
33 #include <linux/mmc/sd.h>
34 #include <linux/mmc/sdio.h>
35 #include <linux/mmc/dw_mmc.h>
36 #include <linux/bitops.h>
37 #include <linux/regulator/consumer.h>
39 #include <linux/of_gpio.h>
40 #include <linux/mmc/slot-gpio.h>
44 /* Common flag combinations */
45 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
46 SDMMC_INT_HTO | SDMMC_INT_SBE | \
47 SDMMC_INT_EBE | SDMMC_INT_HLE)
48 #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
49 SDMMC_INT_RESP_ERR | SDMMC_INT_HLE)
50 #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
51 DW_MCI_CMD_ERROR_FLAGS)
52 #define DW_MCI_SEND_STATUS 1
53 #define DW_MCI_RECV_STATUS 2
54 #define DW_MCI_DMA_THRESHOLD 16
56 #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */
57 #define DW_MCI_FREQ_MIN 400000 /* unit: HZ */
59 #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
60 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
61 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
64 struct idmac_desc_64addr {
65 u32 des0; /* Control Descriptor */
67 u32 des1; /* Reserved */
69 u32 des2; /*Buffer sizes */
70 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
71 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
72 ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
74 u32 des3; /* Reserved */
76 u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/
77 u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/
79 u32 des6; /* Lower 32-bits of Next Descriptor Address */
80 u32 des7; /* Upper 32-bits of Next Descriptor Address */
84 __le32 des0; /* Control Descriptor */
85 #define IDMAC_DES0_DIC BIT(1)
86 #define IDMAC_DES0_LD BIT(2)
87 #define IDMAC_DES0_FD BIT(3)
88 #define IDMAC_DES0_CH BIT(4)
89 #define IDMAC_DES0_ER BIT(5)
90 #define IDMAC_DES0_CES BIT(30)
91 #define IDMAC_DES0_OWN BIT(31)
93 __le32 des1; /* Buffer sizes */
94 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
95 ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff)))
97 __le32 des2; /* buffer 1 physical address */
99 __le32 des3; /* buffer 2 physical address */
102 /* Each descriptor can transfer up to 4KB of data in chained mode */
103 #define DW_MCI_DESC_DATA_LENGTH 0x1000
105 static bool dw_mci_reset(struct dw_mci *host);
106 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
107 static int dw_mci_card_busy(struct mmc_host *mmc);
108 static int dw_mci_get_cd(struct mmc_host *mmc);
110 #if defined(CONFIG_DEBUG_FS)
111 static int dw_mci_req_show(struct seq_file *s, void *v)
113 struct dw_mci_slot *slot = s->private;
114 struct mmc_request *mrq;
115 struct mmc_command *cmd;
116 struct mmc_command *stop;
117 struct mmc_data *data;
119 /* Make sure we get a consistent snapshot */
120 spin_lock_bh(&slot->host->lock);
130 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
131 cmd->opcode, cmd->arg, cmd->flags,
132 cmd->resp[0], cmd->resp[1], cmd->resp[2],
133 cmd->resp[2], cmd->error);
135 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
136 data->bytes_xfered, data->blocks,
137 data->blksz, data->flags, data->error);
140 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
141 stop->opcode, stop->arg, stop->flags,
142 stop->resp[0], stop->resp[1], stop->resp[2],
143 stop->resp[2], stop->error);
146 spin_unlock_bh(&slot->host->lock);
151 static int dw_mci_req_open(struct inode *inode, struct file *file)
153 return single_open(file, dw_mci_req_show, inode->i_private);
156 static const struct file_operations dw_mci_req_fops = {
157 .owner = THIS_MODULE,
158 .open = dw_mci_req_open,
161 .release = single_release,
164 static int dw_mci_regs_show(struct seq_file *s, void *v)
166 seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
167 seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
168 seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
169 seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
170 seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
171 seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
176 static int dw_mci_regs_open(struct inode *inode, struct file *file)
178 return single_open(file, dw_mci_regs_show, inode->i_private);
181 static const struct file_operations dw_mci_regs_fops = {
182 .owner = THIS_MODULE,
183 .open = dw_mci_regs_open,
186 .release = single_release,
189 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
191 struct mmc_host *mmc = slot->mmc;
192 struct dw_mci *host = slot->host;
196 root = mmc->debugfs_root;
200 node = debugfs_create_file("regs", S_IRUSR, root, host,
205 node = debugfs_create_file("req", S_IRUSR, root, slot,
210 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
214 node = debugfs_create_x32("pending_events", S_IRUSR, root,
215 (u32 *)&host->pending_events);
219 node = debugfs_create_x32("completed_events", S_IRUSR, root,
220 (u32 *)&host->completed_events);
227 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
229 #endif /* defined(CONFIG_DEBUG_FS) */
231 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg);
233 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
235 struct mmc_data *data;
236 struct dw_mci_slot *slot = mmc_priv(mmc);
237 struct dw_mci *host = slot->host;
240 cmd->error = -EINPROGRESS;
243 if (cmd->opcode == MMC_STOP_TRANSMISSION ||
244 cmd->opcode == MMC_GO_IDLE_STATE ||
245 cmd->opcode == MMC_GO_INACTIVE_STATE ||
246 (cmd->opcode == SD_IO_RW_DIRECT &&
247 ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
248 cmdr |= SDMMC_CMD_STOP;
249 else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
250 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
252 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
255 /* Special bit makes CMD11 not die */
256 cmdr |= SDMMC_CMD_VOLT_SWITCH;
258 /* Change state to continue to handle CMD11 weirdness */
259 WARN_ON(slot->host->state != STATE_SENDING_CMD);
260 slot->host->state = STATE_SENDING_CMD11;
263 * We need to disable low power mode (automatic clock stop)
264 * while doing voltage switch so we don't confuse the card,
265 * since stopping the clock is a specific part of the UHS
266 * voltage change dance.
268 * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
269 * unconditionally turned back on in dw_mci_setup_bus() if it's
270 * ever called with a non-zero clock. That shouldn't happen
271 * until the voltage change is all done.
273 clk_en_a = mci_readl(host, CLKENA);
274 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
275 mci_writel(host, CLKENA, clk_en_a);
276 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
277 SDMMC_CMD_PRV_DAT_WAIT, 0);
280 if (cmd->flags & MMC_RSP_PRESENT) {
281 /* We expect a response, so set this bit */
282 cmdr |= SDMMC_CMD_RESP_EXP;
283 if (cmd->flags & MMC_RSP_136)
284 cmdr |= SDMMC_CMD_RESP_LONG;
287 if (cmd->flags & MMC_RSP_CRC)
288 cmdr |= SDMMC_CMD_RESP_CRC;
292 cmdr |= SDMMC_CMD_DAT_EXP;
293 if (data->flags & MMC_DATA_WRITE)
294 cmdr |= SDMMC_CMD_DAT_WR;
297 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags))
298 cmdr |= SDMMC_CMD_USE_HOLD_REG;
303 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
305 struct mmc_command *stop;
311 stop = &host->stop_abort;
313 memset(stop, 0, sizeof(struct mmc_command));
315 if (cmdr == MMC_READ_SINGLE_BLOCK ||
316 cmdr == MMC_READ_MULTIPLE_BLOCK ||
317 cmdr == MMC_WRITE_BLOCK ||
318 cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
319 cmdr == MMC_SEND_TUNING_BLOCK ||
320 cmdr == MMC_SEND_TUNING_BLOCK_HS200) {
321 stop->opcode = MMC_STOP_TRANSMISSION;
323 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
324 } else if (cmdr == SD_IO_RW_EXTENDED) {
325 stop->opcode = SD_IO_RW_DIRECT;
326 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
327 ((cmd->arg >> 28) & 0x7);
328 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
333 cmdr = stop->opcode | SDMMC_CMD_STOP |
334 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
339 static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
341 unsigned long timeout = jiffies + msecs_to_jiffies(500);
344 * Databook says that before issuing a new data transfer command
345 * we need to check to see if the card is busy. Data transfer commands
346 * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
348 * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
351 if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) &&
352 !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) {
353 while (mci_readl(host, STATUS) & SDMMC_STATUS_BUSY) {
354 if (time_after(jiffies, timeout)) {
355 /* Command will fail; we'll pass error then */
356 dev_err(host->dev, "Busy; trying anyway\n");
364 static void dw_mci_start_command(struct dw_mci *host,
365 struct mmc_command *cmd, u32 cmd_flags)
369 "start command: ARGR=0x%08x CMDR=0x%08x\n",
370 cmd->arg, cmd_flags);
372 mci_writel(host, CMDARG, cmd->arg);
373 wmb(); /* drain writebuffer */
374 dw_mci_wait_while_busy(host, cmd_flags);
376 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
379 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
381 struct mmc_command *stop = data->stop ? data->stop : &host->stop_abort;
383 dw_mci_start_command(host, stop, host->stop_cmdr);
386 /* DMA interface functions */
387 static void dw_mci_stop_dma(struct dw_mci *host)
389 if (host->using_dma) {
390 host->dma_ops->stop(host);
391 host->dma_ops->cleanup(host);
394 /* Data transfer was stopped by the interrupt handler */
395 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
398 static int dw_mci_get_dma_dir(struct mmc_data *data)
400 if (data->flags & MMC_DATA_WRITE)
401 return DMA_TO_DEVICE;
403 return DMA_FROM_DEVICE;
406 static void dw_mci_dma_cleanup(struct dw_mci *host)
408 struct mmc_data *data = host->data;
411 if (!data->host_cookie)
412 dma_unmap_sg(host->dev,
415 dw_mci_get_dma_dir(data));
418 static void dw_mci_idmac_reset(struct dw_mci *host)
420 u32 bmod = mci_readl(host, BMOD);
421 /* Software reset of DMA */
422 bmod |= SDMMC_IDMAC_SWRESET;
423 mci_writel(host, BMOD, bmod);
426 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
430 /* Disable and reset the IDMAC interface */
431 temp = mci_readl(host, CTRL);
432 temp &= ~SDMMC_CTRL_USE_IDMAC;
433 temp |= SDMMC_CTRL_DMA_RESET;
434 mci_writel(host, CTRL, temp);
436 /* Stop the IDMAC running */
437 temp = mci_readl(host, BMOD);
438 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
439 temp |= SDMMC_IDMAC_SWRESET;
440 mci_writel(host, BMOD, temp);
443 static void dw_mci_dmac_complete_dma(void *arg)
445 struct dw_mci *host = arg;
446 struct mmc_data *data = host->data;
448 dev_vdbg(host->dev, "DMA complete\n");
450 if ((host->use_dma == TRANS_MODE_EDMAC) &&
451 data && (data->flags & MMC_DATA_READ))
452 /* Invalidate cache after read */
453 dma_sync_sg_for_cpu(mmc_dev(host->cur_slot->mmc),
458 host->dma_ops->cleanup(host);
461 * If the card was removed, data will be NULL. No point in trying to
462 * send the stop command or waiting for NBUSY in this case.
465 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
466 tasklet_schedule(&host->tasklet);
470 static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
473 unsigned int desc_len;
476 if (host->dma_64bit_address == 1) {
477 struct idmac_desc_64addr *desc_first, *desc_last, *desc;
479 desc_first = desc_last = desc = host->sg_cpu;
481 for (i = 0; i < sg_len; i++) {
482 unsigned int length = sg_dma_len(&data->sg[i]);
484 u64 mem_addr = sg_dma_address(&data->sg[i]);
486 for ( ; length ; desc++) {
487 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
488 length : DW_MCI_DESC_DATA_LENGTH;
493 * Set the OWN bit and disable interrupts
494 * for this descriptor
496 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
500 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len);
502 /* Physical address to DMA to/from */
503 desc->des4 = mem_addr & 0xffffffff;
504 desc->des5 = mem_addr >> 32;
506 /* Update physical address for the next desc */
507 mem_addr += desc_len;
509 /* Save pointer to the last descriptor */
514 /* Set first descriptor */
515 desc_first->des0 |= IDMAC_DES0_FD;
517 /* Set last descriptor */
518 desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
519 desc_last->des0 |= IDMAC_DES0_LD;
522 struct idmac_desc *desc_first, *desc_last, *desc;
524 desc_first = desc_last = desc = host->sg_cpu;
526 for (i = 0; i < sg_len; i++) {
527 unsigned int length = sg_dma_len(&data->sg[i]);
529 u32 mem_addr = sg_dma_address(&data->sg[i]);
531 for ( ; length ; desc++) {
532 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
533 length : DW_MCI_DESC_DATA_LENGTH;
538 * Set the OWN bit and disable interrupts
539 * for this descriptor
541 desc->des0 = cpu_to_le32(IDMAC_DES0_OWN |
546 IDMAC_SET_BUFFER1_SIZE(desc, desc_len);
548 /* Physical address to DMA to/from */
549 desc->des2 = cpu_to_le32(mem_addr);
551 /* Update physical address for the next desc */
552 mem_addr += desc_len;
554 /* Save pointer to the last descriptor */
559 /* Set first descriptor */
560 desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD);
562 /* Set last descriptor */
563 desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH |
565 desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD);
568 wmb(); /* drain writebuffer */
571 static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
575 dw_mci_translate_sglist(host, host->data, sg_len);
577 /* Make sure to reset DMA in case we did PIO before this */
578 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
579 dw_mci_idmac_reset(host);
581 /* Select IDMAC interface */
582 temp = mci_readl(host, CTRL);
583 temp |= SDMMC_CTRL_USE_IDMAC;
584 mci_writel(host, CTRL, temp);
586 /* drain writebuffer */
589 /* Enable the IDMAC */
590 temp = mci_readl(host, BMOD);
591 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
592 mci_writel(host, BMOD, temp);
594 /* Start it running */
595 mci_writel(host, PLDMND, 1);
600 static int dw_mci_idmac_init(struct dw_mci *host)
604 if (host->dma_64bit_address == 1) {
605 struct idmac_desc_64addr *p;
606 /* Number of descriptors in the ring buffer */
607 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc_64addr);
609 /* Forward link the descriptor list */
610 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
612 p->des6 = (host->sg_dma +
613 (sizeof(struct idmac_desc_64addr) *
614 (i + 1))) & 0xffffffff;
616 p->des7 = (u64)(host->sg_dma +
617 (sizeof(struct idmac_desc_64addr) *
619 /* Initialize reserved and buffer size fields to "0" */
625 /* Set the last descriptor as the end-of-ring descriptor */
626 p->des6 = host->sg_dma & 0xffffffff;
627 p->des7 = (u64)host->sg_dma >> 32;
628 p->des0 = IDMAC_DES0_ER;
631 struct idmac_desc *p;
632 /* Number of descriptors in the ring buffer */
633 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
635 /* Forward link the descriptor list */
636 for (i = 0, p = host->sg_cpu;
637 i < host->ring_size - 1;
639 p->des3 = cpu_to_le32(host->sg_dma +
640 (sizeof(struct idmac_desc) * (i + 1)));
644 /* Set the last descriptor as the end-of-ring descriptor */
645 p->des3 = cpu_to_le32(host->sg_dma);
646 p->des0 = cpu_to_le32(IDMAC_DES0_ER);
649 dw_mci_idmac_reset(host);
651 if (host->dma_64bit_address == 1) {
652 /* Mask out interrupts - get Tx & Rx complete only */
653 mci_writel(host, IDSTS64, IDMAC_INT_CLR);
654 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
655 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
657 /* Set the descriptor base address */
658 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
659 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
662 /* Mask out interrupts - get Tx & Rx complete only */
663 mci_writel(host, IDSTS, IDMAC_INT_CLR);
664 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
665 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
667 /* Set the descriptor base address */
668 mci_writel(host, DBADDR, host->sg_dma);
674 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
675 .init = dw_mci_idmac_init,
676 .start = dw_mci_idmac_start_dma,
677 .stop = dw_mci_idmac_stop_dma,
678 .complete = dw_mci_dmac_complete_dma,
679 .cleanup = dw_mci_dma_cleanup,
682 static void dw_mci_edmac_stop_dma(struct dw_mci *host)
684 dmaengine_terminate_async(host->dms->ch);
687 static int dw_mci_edmac_start_dma(struct dw_mci *host,
690 struct dma_slave_config cfg;
691 struct dma_async_tx_descriptor *desc = NULL;
692 struct scatterlist *sgl = host->data->sg;
693 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
694 u32 sg_elems = host->data->sg_len;
696 u32 fifo_offset = host->fifo_reg - host->regs;
699 /* Set external dma config: burst size, burst width */
700 cfg.dst_addr = host->phy_regs + fifo_offset;
701 cfg.src_addr = cfg.dst_addr;
702 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
703 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
705 /* Match burst msize with external dma config */
706 fifoth_val = mci_readl(host, FIFOTH);
707 cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7];
708 cfg.src_maxburst = cfg.dst_maxburst;
710 if (host->data->flags & MMC_DATA_WRITE)
711 cfg.direction = DMA_MEM_TO_DEV;
713 cfg.direction = DMA_DEV_TO_MEM;
715 ret = dmaengine_slave_config(host->dms->ch, &cfg);
717 dev_err(host->dev, "Failed to config edmac.\n");
721 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl,
722 sg_len, cfg.direction,
723 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
725 dev_err(host->dev, "Can't prepare slave sg.\n");
729 /* Set dw_mci_dmac_complete_dma as callback */
730 desc->callback = dw_mci_dmac_complete_dma;
731 desc->callback_param = (void *)host;
732 dmaengine_submit(desc);
734 /* Flush cache before write */
735 if (host->data->flags & MMC_DATA_WRITE)
736 dma_sync_sg_for_device(mmc_dev(host->cur_slot->mmc), sgl,
737 sg_elems, DMA_TO_DEVICE);
739 dma_async_issue_pending(host->dms->ch);
744 static int dw_mci_edmac_init(struct dw_mci *host)
746 /* Request external dma channel */
747 host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
751 host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx");
752 if (!host->dms->ch) {
753 dev_err(host->dev, "Failed to get external DMA channel.\n");
762 static void dw_mci_edmac_exit(struct dw_mci *host)
766 dma_release_channel(host->dms->ch);
767 host->dms->ch = NULL;
774 static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
775 .init = dw_mci_edmac_init,
776 .exit = dw_mci_edmac_exit,
777 .start = dw_mci_edmac_start_dma,
778 .stop = dw_mci_edmac_stop_dma,
779 .complete = dw_mci_dmac_complete_dma,
780 .cleanup = dw_mci_dma_cleanup,
783 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
784 struct mmc_data *data,
787 struct scatterlist *sg;
788 unsigned int i, sg_len;
790 if (!next && data->host_cookie)
791 return data->host_cookie;
794 * We don't do DMA on "complex" transfers, i.e. with
795 * non-word-aligned buffers or lengths. Also, we don't bother
796 * with all the DMA setup overhead for short transfers.
798 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
804 for_each_sg(data->sg, sg, data->sg_len, i) {
805 if (sg->offset & 3 || sg->length & 3)
809 sg_len = dma_map_sg(host->dev,
812 dw_mci_get_dma_dir(data));
817 data->host_cookie = sg_len;
822 static void dw_mci_pre_req(struct mmc_host *mmc,
823 struct mmc_request *mrq,
826 struct dw_mci_slot *slot = mmc_priv(mmc);
827 struct mmc_data *data = mrq->data;
829 if (!slot->host->use_dma || !data)
832 if (data->host_cookie) {
833 data->host_cookie = 0;
837 if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
838 data->host_cookie = 0;
841 static void dw_mci_post_req(struct mmc_host *mmc,
842 struct mmc_request *mrq,
845 struct dw_mci_slot *slot = mmc_priv(mmc);
846 struct mmc_data *data = mrq->data;
848 if (!slot->host->use_dma || !data)
851 if (data->host_cookie)
852 dma_unmap_sg(slot->host->dev,
855 dw_mci_get_dma_dir(data));
856 data->host_cookie = 0;
859 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
861 unsigned int blksz = data->blksz;
862 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
863 u32 fifo_width = 1 << host->data_shift;
864 u32 blksz_depth = blksz / fifo_width, fifoth_val;
865 u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
866 int idx = ARRAY_SIZE(mszs) - 1;
868 /* pio should ship this scenario */
872 tx_wmark = (host->fifo_depth) / 2;
873 tx_wmark_invers = host->fifo_depth - tx_wmark;
877 * if blksz is not a multiple of the FIFO width
879 if (blksz % fifo_width) {
886 if (!((blksz_depth % mszs[idx]) ||
887 (tx_wmark_invers % mszs[idx]))) {
889 rx_wmark = mszs[idx] - 1;
894 * If idx is '0', it won't be tried
895 * Thus, initial values are uesed
898 fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
899 mci_writel(host, FIFOTH, fifoth_val);
902 static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data)
904 unsigned int blksz = data->blksz;
905 u32 blksz_depth, fifo_depth;
908 WARN_ON(!(data->flags & MMC_DATA_READ));
911 * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
912 * in the FIFO region, so we really shouldn't access it).
914 if (host->verid < DW_MMC_240A)
917 if (host->timing != MMC_TIMING_MMC_HS200 &&
918 host->timing != MMC_TIMING_MMC_HS400 &&
919 host->timing != MMC_TIMING_UHS_SDR104)
922 blksz_depth = blksz / (1 << host->data_shift);
923 fifo_depth = host->fifo_depth;
925 if (blksz_depth > fifo_depth)
929 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
930 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz
931 * Currently just choose blksz.
934 mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1));
938 mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0));
941 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
943 unsigned long irqflags;
949 /* If we don't have a channel, we can't do DMA */
953 sg_len = dw_mci_pre_dma_transfer(host, data, 0);
955 host->dma_ops->stop(host);
961 if (host->use_dma == TRANS_MODE_IDMAC)
963 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
964 (unsigned long)host->sg_cpu,
965 (unsigned long)host->sg_dma,
969 * Decide the MSIZE and RX/TX Watermark.
970 * If current block size is same with previous size,
971 * no need to update fifoth.
973 if (host->prev_blksz != data->blksz)
974 dw_mci_adjust_fifoth(host, data);
976 /* Enable the DMA interface */
977 temp = mci_readl(host, CTRL);
978 temp |= SDMMC_CTRL_DMA_ENABLE;
979 mci_writel(host, CTRL, temp);
981 /* Disable RX/TX IRQs, let DMA handle it */
982 spin_lock_irqsave(&host->irq_lock, irqflags);
983 temp = mci_readl(host, INTMASK);
984 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
985 mci_writel(host, INTMASK, temp);
986 spin_unlock_irqrestore(&host->irq_lock, irqflags);
988 if (host->dma_ops->start(host, sg_len)) {
989 /* We can't do DMA */
990 dev_err(host->dev, "%s: failed to start DMA.\n", __func__);
997 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
999 unsigned long irqflags;
1000 int flags = SG_MITER_ATOMIC;
1003 data->error = -EINPROGRESS;
1005 WARN_ON(host->data);
1009 if (data->flags & MMC_DATA_READ) {
1010 host->dir_status = DW_MCI_RECV_STATUS;
1011 dw_mci_ctrl_rd_thld(host, data);
1013 host->dir_status = DW_MCI_SEND_STATUS;
1016 if (dw_mci_submit_data_dma(host, data)) {
1017 if (host->data->flags & MMC_DATA_READ)
1018 flags |= SG_MITER_TO_SG;
1020 flags |= SG_MITER_FROM_SG;
1022 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1023 host->sg = data->sg;
1024 host->part_buf_start = 0;
1025 host->part_buf_count = 0;
1027 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
1029 spin_lock_irqsave(&host->irq_lock, irqflags);
1030 temp = mci_readl(host, INTMASK);
1031 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
1032 mci_writel(host, INTMASK, temp);
1033 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1035 temp = mci_readl(host, CTRL);
1036 temp &= ~SDMMC_CTRL_DMA_ENABLE;
1037 mci_writel(host, CTRL, temp);
1040 * Use the initial fifoth_val for PIO mode.
1041 * If next issued data may be transfered by DMA mode,
1042 * prev_blksz should be invalidated.
1044 mci_writel(host, FIFOTH, host->fifoth_val);
1045 host->prev_blksz = 0;
1048 * Keep the current block size.
1049 * It will be used to decide whether to update
1050 * fifoth register next time.
1052 host->prev_blksz = data->blksz;
1056 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
1058 struct dw_mci *host = slot->host;
1059 unsigned long timeout = jiffies + msecs_to_jiffies(500);
1060 unsigned int cmd_status = 0;
1062 mci_writel(host, CMDARG, arg);
1063 wmb(); /* drain writebuffer */
1064 dw_mci_wait_while_busy(host, cmd);
1065 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
1067 while (time_before(jiffies, timeout)) {
1068 cmd_status = mci_readl(host, CMD);
1069 if (!(cmd_status & SDMMC_CMD_START))
1072 dev_err(&slot->mmc->class_dev,
1073 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
1074 cmd, arg, cmd_status);
1077 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
1079 struct dw_mci *host = slot->host;
1080 unsigned int clock = slot->clock;
1083 u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
1085 /* We must continue to set bit 28 in CMD until the change is complete */
1086 if (host->state == STATE_WAITING_CMD11_DONE)
1087 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
1090 mci_writel(host, CLKENA, 0);
1091 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1092 } else if (clock != host->current_speed || force_clkinit) {
1093 div = host->bus_hz / clock;
1094 if (host->bus_hz % clock && host->bus_hz > clock)
1096 * move the + 1 after the divide to prevent
1097 * over-clocking the card.
1101 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
1103 if ((clock << div) != slot->__clk_old || force_clkinit)
1104 dev_info(&slot->mmc->class_dev,
1105 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1106 slot->id, host->bus_hz, clock,
1107 div ? ((host->bus_hz / div) >> 1) :
1111 mci_writel(host, CLKENA, 0);
1112 mci_writel(host, CLKSRC, 0);
1115 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1117 /* set clock to desired speed */
1118 mci_writel(host, CLKDIV, div);
1121 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1123 /* enable clock; only low power if no SDIO */
1124 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
1125 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
1126 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1127 mci_writel(host, CLKENA, clk_en_a);
1130 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1132 /* keep the clock with reflecting clock dividor */
1133 slot->__clk_old = clock << div;
1136 host->current_speed = clock;
1138 /* Set the current slot bus width */
1139 mci_writel(host, CTYPE, (slot->ctype << slot->id));
1142 static void __dw_mci_start_request(struct dw_mci *host,
1143 struct dw_mci_slot *slot,
1144 struct mmc_command *cmd)
1146 struct mmc_request *mrq;
1147 struct mmc_data *data;
1152 host->cur_slot = slot;
1155 host->pending_events = 0;
1156 host->completed_events = 0;
1157 host->cmd_status = 0;
1158 host->data_status = 0;
1159 host->dir_status = 0;
1163 mci_writel(host, TMOUT, 0xFFFFFFFF);
1164 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1165 mci_writel(host, BLKSIZ, data->blksz);
1168 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1170 /* this is the first command, send the initialization clock */
1171 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1172 cmdflags |= SDMMC_CMD_INIT;
1175 dw_mci_submit_data(host, data);
1176 wmb(); /* drain writebuffer */
1179 dw_mci_start_command(host, cmd, cmdflags);
1181 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
1182 unsigned long irqflags;
1185 * Databook says to fail after 2ms w/ no response, but evidence
1186 * shows that sometimes the cmd11 interrupt takes over 130ms.
1187 * We'll set to 500ms, plus an extra jiffy just in case jiffies
1188 * is just about to roll over.
1190 * We do this whole thing under spinlock and only if the
1191 * command hasn't already completed (indicating the the irq
1192 * already ran so we don't want the timeout).
1194 spin_lock_irqsave(&host->irq_lock, irqflags);
1195 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1196 mod_timer(&host->cmd11_timer,
1197 jiffies + msecs_to_jiffies(500) + 1);
1198 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1202 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
1204 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
1207 static void dw_mci_start_request(struct dw_mci *host,
1208 struct dw_mci_slot *slot)
1210 struct mmc_request *mrq = slot->mrq;
1211 struct mmc_command *cmd;
1213 cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1214 __dw_mci_start_request(host, slot, cmd);
1217 /* must be called with host->lock held */
1218 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1219 struct mmc_request *mrq)
1221 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1226 if (host->state == STATE_WAITING_CMD11_DONE) {
1227 dev_warn(&slot->mmc->class_dev,
1228 "Voltage change didn't complete\n");
1230 * this case isn't expected to happen, so we can
1231 * either crash here or just try to continue on
1232 * in the closest possible state
1234 host->state = STATE_IDLE;
1237 if (host->state == STATE_IDLE) {
1238 host->state = STATE_SENDING_CMD;
1239 dw_mci_start_request(host, slot);
1241 list_add_tail(&slot->queue_node, &host->queue);
1245 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1247 struct dw_mci_slot *slot = mmc_priv(mmc);
1248 struct dw_mci *host = slot->host;
1253 * The check for card presence and queueing of the request must be
1254 * atomic, otherwise the card could be removed in between and the
1255 * request wouldn't fail until another card was inserted.
1258 if (!dw_mci_get_cd(mmc)) {
1259 mrq->cmd->error = -ENOMEDIUM;
1260 mmc_request_done(mmc, mrq);
1264 spin_lock_bh(&host->lock);
1266 dw_mci_queue_request(host, slot, mrq);
1268 spin_unlock_bh(&host->lock);
1271 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1273 struct dw_mci_slot *slot = mmc_priv(mmc);
1274 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1278 switch (ios->bus_width) {
1279 case MMC_BUS_WIDTH_4:
1280 slot->ctype = SDMMC_CTYPE_4BIT;
1282 case MMC_BUS_WIDTH_8:
1283 slot->ctype = SDMMC_CTYPE_8BIT;
1286 /* set default 1 bit mode */
1287 slot->ctype = SDMMC_CTYPE_1BIT;
1290 regs = mci_readl(slot->host, UHS_REG);
1293 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
1294 ios->timing == MMC_TIMING_UHS_DDR50 ||
1295 ios->timing == MMC_TIMING_MMC_HS400)
1296 regs |= ((0x1 << slot->id) << 16);
1298 regs &= ~((0x1 << slot->id) << 16);
1300 mci_writel(slot->host, UHS_REG, regs);
1301 slot->host->timing = ios->timing;
1304 * Use mirror of ios->clock to prevent race with mmc
1305 * core ios update when finding the minimum.
1307 slot->clock = ios->clock;
1309 if (drv_data && drv_data->set_ios)
1310 drv_data->set_ios(slot->host, ios);
1312 switch (ios->power_mode) {
1314 if (!IS_ERR(mmc->supply.vmmc)) {
1315 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1318 dev_err(slot->host->dev,
1319 "failed to enable vmmc regulator\n");
1320 /*return, if failed turn on vmmc*/
1324 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1325 regs = mci_readl(slot->host, PWREN);
1326 regs |= (1 << slot->id);
1327 mci_writel(slot->host, PWREN, regs);
1330 if (!slot->host->vqmmc_enabled) {
1331 if (!IS_ERR(mmc->supply.vqmmc)) {
1332 ret = regulator_enable(mmc->supply.vqmmc);
1334 dev_err(slot->host->dev,
1335 "failed to enable vqmmc\n");
1337 slot->host->vqmmc_enabled = true;
1340 /* Keep track so we don't reset again */
1341 slot->host->vqmmc_enabled = true;
1344 /* Reset our state machine after powering on */
1345 dw_mci_ctrl_reset(slot->host,
1346 SDMMC_CTRL_ALL_RESET_FLAGS);
1349 /* Adjust clock / bus width after power is up */
1350 dw_mci_setup_bus(slot, false);
1354 /* Turn clock off before power goes down */
1355 dw_mci_setup_bus(slot, false);
1357 if (!IS_ERR(mmc->supply.vmmc))
1358 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1360 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
1361 regulator_disable(mmc->supply.vqmmc);
1362 slot->host->vqmmc_enabled = false;
1364 regs = mci_readl(slot->host, PWREN);
1365 regs &= ~(1 << slot->id);
1366 mci_writel(slot->host, PWREN, regs);
1372 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1373 slot->host->state = STATE_IDLE;
1376 static int dw_mci_card_busy(struct mmc_host *mmc)
1378 struct dw_mci_slot *slot = mmc_priv(mmc);
1382 * Check the busy bit which is low when DAT[3:0]
1383 * (the data lines) are 0000
1385 status = mci_readl(slot->host, STATUS);
1387 return !!(status & SDMMC_STATUS_BUSY);
1390 static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1392 struct dw_mci_slot *slot = mmc_priv(mmc);
1393 struct dw_mci *host = slot->host;
1394 const struct dw_mci_drv_data *drv_data = host->drv_data;
1396 u32 v18 = SDMMC_UHS_18V << slot->id;
1399 if (drv_data && drv_data->switch_voltage)
1400 return drv_data->switch_voltage(mmc, ios);
1403 * Program the voltage. Note that some instances of dw_mmc may use
1404 * the UHS_REG for this. For other instances (like exynos) the UHS_REG
1405 * does no harm but you need to set the regulator directly. Try both.
1407 uhs = mci_readl(host, UHS_REG);
1408 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1413 if (!IS_ERR(mmc->supply.vqmmc)) {
1414 ret = mmc_regulator_set_vqmmc(mmc, ios);
1417 dev_dbg(&mmc->class_dev,
1418 "Regulator set error %d - %s V\n",
1419 ret, uhs & v18 ? "1.8" : "3.3");
1423 mci_writel(host, UHS_REG, uhs);
1428 static int dw_mci_get_ro(struct mmc_host *mmc)
1431 struct dw_mci_slot *slot = mmc_priv(mmc);
1432 int gpio_ro = mmc_gpio_get_ro(mmc);
1434 /* Use platform get_ro function, else try on board write protect */
1436 read_only = gpio_ro;
1439 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1441 dev_dbg(&mmc->class_dev, "card is %s\n",
1442 read_only ? "read-only" : "read-write");
1447 static int dw_mci_get_cd(struct mmc_host *mmc)
1450 struct dw_mci_slot *slot = mmc_priv(mmc);
1451 struct dw_mci *host = slot->host;
1452 int gpio_cd = mmc_gpio_get_cd(mmc);
1454 /* Use platform get_cd function, else try onboard card detect */
1455 if ((mmc->caps & MMC_CAP_NEEDS_POLL) || !mmc_card_is_removable(mmc))
1457 else if (gpio_cd >= 0)
1460 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
1463 spin_lock_bh(&host->lock);
1465 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1466 dev_dbg(&mmc->class_dev, "card is present\n");
1468 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1469 dev_dbg(&mmc->class_dev, "card is not present\n");
1471 spin_unlock_bh(&host->lock);
1476 static void dw_mci_hw_reset(struct mmc_host *mmc)
1478 struct dw_mci_slot *slot = mmc_priv(mmc);
1479 struct dw_mci *host = slot->host;
1482 if (host->use_dma == TRANS_MODE_IDMAC)
1483 dw_mci_idmac_reset(host);
1485 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET |
1486 SDMMC_CTRL_FIFO_RESET))
1490 * According to eMMC spec, card reset procedure:
1491 * tRstW >= 1us: RST_n pulse width
1492 * tRSCA >= 200us: RST_n to Command time
1493 * tRSTH >= 1us: RST_n high period
1495 reset = mci_readl(host, RST_N);
1496 reset &= ~(SDMMC_RST_HWACTIVE << slot->id);
1497 mci_writel(host, RST_N, reset);
1499 reset |= SDMMC_RST_HWACTIVE << slot->id;
1500 mci_writel(host, RST_N, reset);
1501 usleep_range(200, 300);
1504 static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card)
1506 struct dw_mci_slot *slot = mmc_priv(mmc);
1507 struct dw_mci *host = slot->host;
1510 * Low power mode will stop the card clock when idle. According to the
1511 * description of the CLKENA register we should disable low power mode
1512 * for SDIO cards if we need SDIO interrupts to work.
1514 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1515 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1519 clk_en_a_old = mci_readl(host, CLKENA);
1521 if (card->type == MMC_TYPE_SDIO ||
1522 card->type == MMC_TYPE_SD_COMBO) {
1523 set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1524 clk_en_a = clk_en_a_old & ~clken_low_pwr;
1526 clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1527 clk_en_a = clk_en_a_old | clken_low_pwr;
1530 if (clk_en_a != clk_en_a_old) {
1531 mci_writel(host, CLKENA, clk_en_a);
1532 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1533 SDMMC_CMD_PRV_DAT_WAIT, 0);
1538 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1540 struct dw_mci_slot *slot = mmc_priv(mmc);
1541 struct dw_mci *host = slot->host;
1542 unsigned long irqflags;
1545 spin_lock_irqsave(&host->irq_lock, irqflags);
1547 /* Enable/disable Slot Specific SDIO interrupt */
1548 int_mask = mci_readl(host, INTMASK);
1550 int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
1552 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
1553 mci_writel(host, INTMASK, int_mask);
1555 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1558 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1560 struct dw_mci_slot *slot = mmc_priv(mmc);
1561 struct dw_mci *host = slot->host;
1562 const struct dw_mci_drv_data *drv_data = host->drv_data;
1565 if (drv_data && drv_data->execute_tuning)
1566 err = drv_data->execute_tuning(slot, opcode);
1570 static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc,
1571 struct mmc_ios *ios)
1573 struct dw_mci_slot *slot = mmc_priv(mmc);
1574 struct dw_mci *host = slot->host;
1575 const struct dw_mci_drv_data *drv_data = host->drv_data;
1577 if (drv_data && drv_data->prepare_hs400_tuning)
1578 return drv_data->prepare_hs400_tuning(host, ios);
1583 static const struct mmc_host_ops dw_mci_ops = {
1584 .request = dw_mci_request,
1585 .pre_req = dw_mci_pre_req,
1586 .post_req = dw_mci_post_req,
1587 .set_ios = dw_mci_set_ios,
1588 .get_ro = dw_mci_get_ro,
1589 .get_cd = dw_mci_get_cd,
1590 .hw_reset = dw_mci_hw_reset,
1591 .enable_sdio_irq = dw_mci_enable_sdio_irq,
1592 .execute_tuning = dw_mci_execute_tuning,
1593 .card_busy = dw_mci_card_busy,
1594 .start_signal_voltage_switch = dw_mci_switch_voltage,
1595 .init_card = dw_mci_init_card,
1596 .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning,
1599 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1600 __releases(&host->lock)
1601 __acquires(&host->lock)
1603 struct dw_mci_slot *slot;
1604 struct mmc_host *prev_mmc = host->cur_slot->mmc;
1606 WARN_ON(host->cmd || host->data);
1608 host->cur_slot->mrq = NULL;
1610 if (!list_empty(&host->queue)) {
1611 slot = list_entry(host->queue.next,
1612 struct dw_mci_slot, queue_node);
1613 list_del(&slot->queue_node);
1614 dev_vdbg(host->dev, "list not empty: %s is next\n",
1615 mmc_hostname(slot->mmc));
1616 host->state = STATE_SENDING_CMD;
1617 dw_mci_start_request(host, slot);
1619 dev_vdbg(host->dev, "list empty\n");
1621 if (host->state == STATE_SENDING_CMD11)
1622 host->state = STATE_WAITING_CMD11_DONE;
1624 host->state = STATE_IDLE;
1627 spin_unlock(&host->lock);
1628 mmc_request_done(prev_mmc, mrq);
1629 spin_lock(&host->lock);
1632 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
1634 u32 status = host->cmd_status;
1636 host->cmd_status = 0;
1638 /* Read the response from the card (up to 16 bytes) */
1639 if (cmd->flags & MMC_RSP_PRESENT) {
1640 if (cmd->flags & MMC_RSP_136) {
1641 cmd->resp[3] = mci_readl(host, RESP0);
1642 cmd->resp[2] = mci_readl(host, RESP1);
1643 cmd->resp[1] = mci_readl(host, RESP2);
1644 cmd->resp[0] = mci_readl(host, RESP3);
1646 cmd->resp[0] = mci_readl(host, RESP0);
1653 if (status & SDMMC_INT_RTO)
1654 cmd->error = -ETIMEDOUT;
1655 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1656 cmd->error = -EILSEQ;
1657 else if (status & SDMMC_INT_RESP_ERR)
1665 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1667 u32 status = host->data_status;
1669 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1670 if (status & SDMMC_INT_DRTO) {
1671 data->error = -ETIMEDOUT;
1672 } else if (status & SDMMC_INT_DCRC) {
1673 data->error = -EILSEQ;
1674 } else if (status & SDMMC_INT_EBE) {
1675 if (host->dir_status ==
1676 DW_MCI_SEND_STATUS) {
1678 * No data CRC status was returned.
1679 * The number of bytes transferred
1680 * will be exaggerated in PIO mode.
1682 data->bytes_xfered = 0;
1683 data->error = -ETIMEDOUT;
1684 } else if (host->dir_status ==
1685 DW_MCI_RECV_STATUS) {
1689 /* SDMMC_INT_SBE is included */
1693 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
1696 * After an error, there may be data lingering
1701 data->bytes_xfered = data->blocks * data->blksz;
1708 static void dw_mci_set_drto(struct dw_mci *host)
1710 unsigned int drto_clks;
1711 unsigned int drto_ms;
1713 drto_clks = mci_readl(host, TMOUT) >> 8;
1714 drto_ms = DIV_ROUND_UP(drto_clks, host->bus_hz / 1000);
1716 /* add a bit spare time */
1719 mod_timer(&host->dto_timer, jiffies + msecs_to_jiffies(drto_ms));
1722 static void dw_mci_tasklet_func(unsigned long priv)
1724 struct dw_mci *host = (struct dw_mci *)priv;
1725 struct mmc_data *data;
1726 struct mmc_command *cmd;
1727 struct mmc_request *mrq;
1728 enum dw_mci_state state;
1729 enum dw_mci_state prev_state;
1732 spin_lock(&host->lock);
1734 state = host->state;
1743 case STATE_WAITING_CMD11_DONE:
1746 case STATE_SENDING_CMD11:
1747 case STATE_SENDING_CMD:
1748 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1749 &host->pending_events))
1754 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
1755 err = dw_mci_command_complete(host, cmd);
1756 if (cmd == mrq->sbc && !err) {
1757 prev_state = state = STATE_SENDING_CMD;
1758 __dw_mci_start_request(host, host->cur_slot,
1763 if (cmd->data && err) {
1765 * During UHS tuning sequence, sending the stop
1766 * command after the response CRC error would
1767 * throw the system into a confused state
1768 * causing all future tuning phases to report
1771 * In such case controller will move into a data
1772 * transfer state after a response error or
1773 * response CRC error. Let's let that finish
1774 * before trying to send a stop, so we'll go to
1775 * STATE_SENDING_DATA.
1777 * Although letting the data transfer take place
1778 * will waste a bit of time (we already know
1779 * the command was bad), it can't cause any
1780 * errors since it's possible it would have
1781 * taken place anyway if this tasklet got
1782 * delayed. Allowing the transfer to take place
1783 * avoids races and keeps things simple.
1785 if ((err != -ETIMEDOUT) &&
1786 (cmd->opcode == MMC_SEND_TUNING_BLOCK)) {
1787 state = STATE_SENDING_DATA;
1791 dw_mci_stop_dma(host);
1792 send_stop_abort(host, data);
1793 state = STATE_SENDING_STOP;
1797 if (!cmd->data || err) {
1798 dw_mci_request_end(host, mrq);
1802 prev_state = state = STATE_SENDING_DATA;
1805 case STATE_SENDING_DATA:
1807 * We could get a data error and never a transfer
1808 * complete so we'd better check for it here.
1810 * Note that we don't really care if we also got a
1811 * transfer complete; stopping the DMA and sending an
1814 if (test_and_clear_bit(EVENT_DATA_ERROR,
1815 &host->pending_events)) {
1816 dw_mci_stop_dma(host);
1818 !(host->data_status & (SDMMC_INT_DRTO |
1820 send_stop_abort(host, data);
1821 state = STATE_DATA_ERROR;
1825 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1826 &host->pending_events)) {
1828 * If all data-related interrupts don't come
1829 * within the given time in reading data state.
1831 if ((host->quirks & DW_MCI_QUIRK_BROKEN_DTO) &&
1832 (host->dir_status == DW_MCI_RECV_STATUS))
1833 dw_mci_set_drto(host);
1837 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
1840 * Handle an EVENT_DATA_ERROR that might have shown up
1841 * before the transfer completed. This might not have
1842 * been caught by the check above because the interrupt
1843 * could have gone off between the previous check and
1844 * the check for transfer complete.
1846 * Technically this ought not be needed assuming we
1847 * get a DATA_COMPLETE eventually (we'll notice the
1848 * error and end the request), but it shouldn't hurt.
1850 * This has the advantage of sending the stop command.
1852 if (test_and_clear_bit(EVENT_DATA_ERROR,
1853 &host->pending_events)) {
1854 dw_mci_stop_dma(host);
1856 !(host->data_status & (SDMMC_INT_DRTO |
1858 send_stop_abort(host, data);
1859 state = STATE_DATA_ERROR;
1862 prev_state = state = STATE_DATA_BUSY;
1866 case STATE_DATA_BUSY:
1867 if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
1868 &host->pending_events)) {
1870 * If data error interrupt comes but data over
1871 * interrupt doesn't come within the given time.
1872 * in reading data state.
1874 if ((host->quirks & DW_MCI_QUIRK_BROKEN_DTO) &&
1875 (host->dir_status == DW_MCI_RECV_STATUS))
1876 dw_mci_set_drto(host);
1881 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
1882 err = dw_mci_data_complete(host, data);
1885 if (!data->stop || mrq->sbc) {
1886 if (mrq->sbc && data->stop)
1887 data->stop->error = 0;
1888 dw_mci_request_end(host, mrq);
1892 /* stop command for open-ended transfer*/
1894 send_stop_abort(host, data);
1897 * If we don't have a command complete now we'll
1898 * never get one since we just reset everything;
1899 * better end the request.
1901 * If we do have a command complete we'll fall
1902 * through to the SENDING_STOP command and
1903 * everything will be peachy keen.
1905 if (!test_bit(EVENT_CMD_COMPLETE,
1906 &host->pending_events)) {
1908 dw_mci_request_end(host, mrq);
1914 * If err has non-zero,
1915 * stop-abort command has been already issued.
1917 prev_state = state = STATE_SENDING_STOP;
1921 case STATE_SENDING_STOP:
1922 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1923 &host->pending_events))
1926 /* CMD error in data command */
1927 if (mrq->cmd->error && mrq->data)
1934 dw_mci_command_complete(host, mrq->stop);
1936 host->cmd_status = 0;
1938 dw_mci_request_end(host, mrq);
1941 case STATE_DATA_ERROR:
1942 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1943 &host->pending_events))
1946 state = STATE_DATA_BUSY;
1949 } while (state != prev_state);
1951 host->state = state;
1953 spin_unlock(&host->lock);
1957 /* push final bytes to part_buf, only use during push */
1958 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
1960 memcpy((void *)&host->part_buf, buf, cnt);
1961 host->part_buf_count = cnt;
1964 /* append bytes to part_buf, only use during push */
1965 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
1967 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
1968 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
1969 host->part_buf_count += cnt;
1973 /* pull first bytes from part_buf, only use during pull */
1974 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
1976 cnt = min_t(int, cnt, host->part_buf_count);
1978 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
1980 host->part_buf_count -= cnt;
1981 host->part_buf_start += cnt;
1986 /* pull final bytes from the part_buf, assuming it's just been filled */
1987 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
1989 memcpy(buf, &host->part_buf, cnt);
1990 host->part_buf_start = cnt;
1991 host->part_buf_count = (1 << host->data_shift) - cnt;
1994 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
1996 struct mmc_data *data = host->data;
1999 /* try and push anything in the part_buf */
2000 if (unlikely(host->part_buf_count)) {
2001 int len = dw_mci_push_part_bytes(host, buf, cnt);
2005 if (host->part_buf_count == 2) {
2006 mci_fifo_writew(host->fifo_reg, host->part_buf16);
2007 host->part_buf_count = 0;
2010 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2011 if (unlikely((unsigned long)buf & 0x1)) {
2013 u16 aligned_buf[64];
2014 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2015 int items = len >> 1;
2017 /* memcpy from input buffer into aligned buffer */
2018 memcpy(aligned_buf, buf, len);
2021 /* push data from aligned buffer into fifo */
2022 for (i = 0; i < items; ++i)
2023 mci_fifo_writew(host->fifo_reg, aligned_buf[i]);
2030 for (; cnt >= 2; cnt -= 2)
2031 mci_fifo_writew(host->fifo_reg, *pdata++);
2034 /* put anything remaining in the part_buf */
2036 dw_mci_set_part_bytes(host, buf, cnt);
2037 /* Push data if we have reached the expected data length */
2038 if ((data->bytes_xfered + init_cnt) ==
2039 (data->blksz * data->blocks))
2040 mci_fifo_writew(host->fifo_reg, host->part_buf16);
2044 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2046 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2047 if (unlikely((unsigned long)buf & 0x1)) {
2049 /* pull data from fifo into aligned buffer */
2050 u16 aligned_buf[64];
2051 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2052 int items = len >> 1;
2055 for (i = 0; i < items; ++i)
2056 aligned_buf[i] = mci_fifo_readw(host->fifo_reg);
2057 /* memcpy from aligned buffer into output buffer */
2058 memcpy(buf, aligned_buf, len);
2067 for (; cnt >= 2; cnt -= 2)
2068 *pdata++ = mci_fifo_readw(host->fifo_reg);
2072 host->part_buf16 = mci_fifo_readw(host->fifo_reg);
2073 dw_mci_pull_final_bytes(host, buf, cnt);
2077 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2079 struct mmc_data *data = host->data;
2082 /* try and push anything in the part_buf */
2083 if (unlikely(host->part_buf_count)) {
2084 int len = dw_mci_push_part_bytes(host, buf, cnt);
2088 if (host->part_buf_count == 4) {
2089 mci_fifo_writel(host->fifo_reg, host->part_buf32);
2090 host->part_buf_count = 0;
2093 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2094 if (unlikely((unsigned long)buf & 0x3)) {
2096 u32 aligned_buf[32];
2097 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2098 int items = len >> 2;
2100 /* memcpy from input buffer into aligned buffer */
2101 memcpy(aligned_buf, buf, len);
2104 /* push data from aligned buffer into fifo */
2105 for (i = 0; i < items; ++i)
2106 mci_fifo_writel(host->fifo_reg, aligned_buf[i]);
2113 for (; cnt >= 4; cnt -= 4)
2114 mci_fifo_writel(host->fifo_reg, *pdata++);
2117 /* put anything remaining in the part_buf */
2119 dw_mci_set_part_bytes(host, buf, cnt);
2120 /* Push data if we have reached the expected data length */
2121 if ((data->bytes_xfered + init_cnt) ==
2122 (data->blksz * data->blocks))
2123 mci_fifo_writel(host->fifo_reg, host->part_buf32);
2127 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2129 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2130 if (unlikely((unsigned long)buf & 0x3)) {
2132 /* pull data from fifo into aligned buffer */
2133 u32 aligned_buf[32];
2134 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2135 int items = len >> 2;
2138 for (i = 0; i < items; ++i)
2139 aligned_buf[i] = mci_fifo_readl(host->fifo_reg);
2140 /* memcpy from aligned buffer into output buffer */
2141 memcpy(buf, aligned_buf, len);
2150 for (; cnt >= 4; cnt -= 4)
2151 *pdata++ = mci_fifo_readl(host->fifo_reg);
2155 host->part_buf32 = mci_fifo_readl(host->fifo_reg);
2156 dw_mci_pull_final_bytes(host, buf, cnt);
2160 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2162 struct mmc_data *data = host->data;
2165 /* try and push anything in the part_buf */
2166 if (unlikely(host->part_buf_count)) {
2167 int len = dw_mci_push_part_bytes(host, buf, cnt);
2172 if (host->part_buf_count == 8) {
2173 mci_fifo_writeq(host->fifo_reg, host->part_buf);
2174 host->part_buf_count = 0;
2177 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2178 if (unlikely((unsigned long)buf & 0x7)) {
2180 u64 aligned_buf[16];
2181 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2182 int items = len >> 3;
2184 /* memcpy from input buffer into aligned buffer */
2185 memcpy(aligned_buf, buf, len);
2188 /* push data from aligned buffer into fifo */
2189 for (i = 0; i < items; ++i)
2190 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]);
2197 for (; cnt >= 8; cnt -= 8)
2198 mci_fifo_writeq(host->fifo_reg, *pdata++);
2201 /* put anything remaining in the part_buf */
2203 dw_mci_set_part_bytes(host, buf, cnt);
2204 /* Push data if we have reached the expected data length */
2205 if ((data->bytes_xfered + init_cnt) ==
2206 (data->blksz * data->blocks))
2207 mci_fifo_writeq(host->fifo_reg, host->part_buf);
2211 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2213 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2214 if (unlikely((unsigned long)buf & 0x7)) {
2216 /* pull data from fifo into aligned buffer */
2217 u64 aligned_buf[16];
2218 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2219 int items = len >> 3;
2222 for (i = 0; i < items; ++i)
2223 aligned_buf[i] = mci_fifo_readq(host->fifo_reg);
2225 /* memcpy from aligned buffer into output buffer */
2226 memcpy(buf, aligned_buf, len);
2235 for (; cnt >= 8; cnt -= 8)
2236 *pdata++ = mci_fifo_readq(host->fifo_reg);
2240 host->part_buf = mci_fifo_readq(host->fifo_reg);
2241 dw_mci_pull_final_bytes(host, buf, cnt);
2245 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2249 /* get remaining partial bytes */
2250 len = dw_mci_pull_part_bytes(host, buf, cnt);
2251 if (unlikely(len == cnt))
2256 /* get the rest of the data */
2257 host->pull_data(host, buf, cnt);
2260 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
2262 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2264 unsigned int offset;
2265 struct mmc_data *data = host->data;
2266 int shift = host->data_shift;
2269 unsigned int remain, fcnt;
2272 if (!sg_miter_next(sg_miter))
2275 host->sg = sg_miter->piter.sg;
2276 buf = sg_miter->addr;
2277 remain = sg_miter->length;
2281 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2282 << shift) + host->part_buf_count;
2283 len = min(remain, fcnt);
2286 dw_mci_pull_data(host, (void *)(buf + offset), len);
2287 data->bytes_xfered += len;
2292 sg_miter->consumed = offset;
2293 status = mci_readl(host, MINTSTS);
2294 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2295 /* if the RXDR is ready read again */
2296 } while ((status & SDMMC_INT_RXDR) ||
2297 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
2300 if (!sg_miter_next(sg_miter))
2302 sg_miter->consumed = 0;
2304 sg_miter_stop(sg_miter);
2308 sg_miter_stop(sg_miter);
2310 smp_wmb(); /* drain writebuffer */
2311 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2314 static void dw_mci_write_data_pio(struct dw_mci *host)
2316 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2318 unsigned int offset;
2319 struct mmc_data *data = host->data;
2320 int shift = host->data_shift;
2323 unsigned int fifo_depth = host->fifo_depth;
2324 unsigned int remain, fcnt;
2327 if (!sg_miter_next(sg_miter))
2330 host->sg = sg_miter->piter.sg;
2331 buf = sg_miter->addr;
2332 remain = sg_miter->length;
2336 fcnt = ((fifo_depth -
2337 SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2338 << shift) - host->part_buf_count;
2339 len = min(remain, fcnt);
2342 host->push_data(host, (void *)(buf + offset), len);
2343 data->bytes_xfered += len;
2348 sg_miter->consumed = offset;
2349 status = mci_readl(host, MINTSTS);
2350 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2351 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
2354 if (!sg_miter_next(sg_miter))
2356 sg_miter->consumed = 0;
2358 sg_miter_stop(sg_miter);
2362 sg_miter_stop(sg_miter);
2364 smp_wmb(); /* drain writebuffer */
2365 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2368 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2370 if (!host->cmd_status)
2371 host->cmd_status = status;
2373 smp_wmb(); /* drain writebuffer */
2375 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2376 tasklet_schedule(&host->tasklet);
2379 static void dw_mci_handle_cd(struct dw_mci *host)
2383 for (i = 0; i < host->num_slots; i++) {
2384 struct dw_mci_slot *slot = host->slot[i];
2389 if (slot->mmc->ops->card_event)
2390 slot->mmc->ops->card_event(slot->mmc);
2391 mmc_detect_change(slot->mmc,
2392 msecs_to_jiffies(host->pdata->detect_delay_ms));
2396 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2398 struct dw_mci *host = dev_id;
2402 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2405 /* Check volt switch first, since it can look like an error */
2406 if ((host->state == STATE_SENDING_CMD11) &&
2407 (pending & SDMMC_INT_VOLT_SWITCH)) {
2408 unsigned long irqflags;
2410 mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
2411 pending &= ~SDMMC_INT_VOLT_SWITCH;
2414 * Hold the lock; we know cmd11_timer can't be kicked
2415 * off after the lock is released, so safe to delete.
2417 spin_lock_irqsave(&host->irq_lock, irqflags);
2418 dw_mci_cmd_interrupt(host, pending);
2419 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2421 del_timer(&host->cmd11_timer);
2424 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2425 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
2426 host->cmd_status = pending;
2427 smp_wmb(); /* drain writebuffer */
2428 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2431 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2432 /* if there is an error report DATA_ERROR */
2433 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2434 host->data_status = pending;
2435 smp_wmb(); /* drain writebuffer */
2436 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2437 tasklet_schedule(&host->tasklet);
2440 if (pending & SDMMC_INT_DATA_OVER) {
2441 if (host->quirks & DW_MCI_QUIRK_BROKEN_DTO)
2442 del_timer(&host->dto_timer);
2444 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2445 if (!host->data_status)
2446 host->data_status = pending;
2447 smp_wmb(); /* drain writebuffer */
2448 if (host->dir_status == DW_MCI_RECV_STATUS) {
2449 if (host->sg != NULL)
2450 dw_mci_read_data_pio(host, true);
2452 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2453 tasklet_schedule(&host->tasklet);
2456 if (pending & SDMMC_INT_RXDR) {
2457 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2458 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2459 dw_mci_read_data_pio(host, false);
2462 if (pending & SDMMC_INT_TXDR) {
2463 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2464 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2465 dw_mci_write_data_pio(host);
2468 if (pending & SDMMC_INT_CMD_DONE) {
2469 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2470 dw_mci_cmd_interrupt(host, pending);
2473 if (pending & SDMMC_INT_CD) {
2474 mci_writel(host, RINTSTS, SDMMC_INT_CD);
2475 dw_mci_handle_cd(host);
2478 /* Handle SDIO Interrupts */
2479 for (i = 0; i < host->num_slots; i++) {
2480 struct dw_mci_slot *slot = host->slot[i];
2485 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
2486 mci_writel(host, RINTSTS,
2487 SDMMC_INT_SDIO(slot->sdio_id));
2488 mmc_signal_sdio_irq(slot->mmc);
2494 if (host->use_dma != TRANS_MODE_IDMAC)
2497 /* Handle IDMA interrupts */
2498 if (host->dma_64bit_address == 1) {
2499 pending = mci_readl(host, IDSTS64);
2500 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2501 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2502 SDMMC_IDMAC_INT_RI);
2503 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
2504 host->dma_ops->complete((void *)host);
2507 pending = mci_readl(host, IDSTS);
2508 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2509 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2510 SDMMC_IDMAC_INT_RI);
2511 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
2512 host->dma_ops->complete((void *)host);
2520 /* given a slot, find out the device node representing that slot */
2521 static struct device_node *dw_mci_of_find_slot_node(struct dw_mci_slot *slot)
2523 struct device *dev = slot->mmc->parent;
2524 struct device_node *np;
2528 if (!dev || !dev->of_node)
2531 for_each_child_of_node(dev->of_node, np) {
2532 addr = of_get_property(np, "reg", &len);
2533 if (!addr || (len < sizeof(int)))
2535 if (be32_to_cpup(addr) == slot->id)
2541 static void dw_mci_slot_of_parse(struct dw_mci_slot *slot)
2543 struct device_node *np = dw_mci_of_find_slot_node(slot);
2548 if (of_property_read_bool(np, "disable-wp")) {
2549 slot->mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT;
2550 dev_warn(slot->mmc->parent,
2551 "Slot quirk 'disable-wp' is deprecated\n");
2554 #else /* CONFIG_OF */
2555 static void dw_mci_slot_of_parse(struct dw_mci_slot *slot)
2558 #endif /* CONFIG_OF */
2560 static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
2562 struct mmc_host *mmc;
2563 struct dw_mci_slot *slot;
2564 const struct dw_mci_drv_data *drv_data = host->drv_data;
2568 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
2572 slot = mmc_priv(mmc);
2574 slot->sdio_id = host->sdio_id0 + id;
2577 host->slot[id] = slot;
2579 mmc->ops = &dw_mci_ops;
2580 if (of_property_read_u32_array(host->dev->of_node,
2581 "clock-freq-min-max", freq, 2)) {
2582 mmc->f_min = DW_MCI_FREQ_MIN;
2583 mmc->f_max = DW_MCI_FREQ_MAX;
2585 mmc->f_min = freq[0];
2586 mmc->f_max = freq[1];
2589 /*if there are external regulators, get them*/
2590 ret = mmc_regulator_get_supply(mmc);
2591 if (ret == -EPROBE_DEFER)
2592 goto err_host_allocated;
2594 if (!mmc->ocr_avail)
2595 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2597 if (host->pdata->caps)
2598 mmc->caps = host->pdata->caps;
2600 if (host->pdata->pm_caps)
2601 mmc->pm_caps = host->pdata->pm_caps;
2603 if (host->dev->of_node) {
2604 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2608 ctrl_id = to_platform_device(host->dev)->id;
2610 if (drv_data && drv_data->caps)
2611 mmc->caps |= drv_data->caps[ctrl_id];
2613 if (host->pdata->caps2)
2614 mmc->caps2 = host->pdata->caps2;
2616 dw_mci_slot_of_parse(slot);
2618 ret = mmc_of_parse(mmc);
2620 goto err_host_allocated;
2622 /* Useful defaults if platform data is unset. */
2623 if (host->use_dma == TRANS_MODE_IDMAC) {
2624 mmc->max_segs = host->ring_size;
2625 mmc->max_blk_size = 65535;
2626 mmc->max_seg_size = 0x1000;
2627 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2628 mmc->max_blk_count = mmc->max_req_size / 512;
2629 } else if (host->use_dma == TRANS_MODE_EDMAC) {
2631 mmc->max_blk_size = 65535;
2632 mmc->max_blk_count = 65535;
2634 mmc->max_blk_size * mmc->max_blk_count;
2635 mmc->max_seg_size = mmc->max_req_size;
2637 /* TRANS_MODE_PIO */
2639 mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */
2640 mmc->max_blk_count = 512;
2641 mmc->max_req_size = mmc->max_blk_size *
2643 mmc->max_seg_size = mmc->max_req_size;
2648 ret = mmc_add_host(mmc);
2650 goto err_host_allocated;
2652 #if defined(CONFIG_DEBUG_FS)
2653 dw_mci_init_debugfs(slot);
2663 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
2665 /* Debugfs stuff is cleaned up by mmc core */
2666 mmc_remove_host(slot->mmc);
2667 slot->host->slot[id] = NULL;
2668 mmc_free_host(slot->mmc);
2671 static void dw_mci_init_dma(struct dw_mci *host)
2674 struct device *dev = host->dev;
2675 struct device_node *np = dev->of_node;
2678 * Check tansfer mode from HCON[17:16]
2679 * Clear the ambiguous description of dw_mmc databook:
2680 * 2b'00: No DMA Interface -> Actually means using Internal DMA block
2681 * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block
2682 * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block
2683 * 2b'11: Non DW DMA Interface -> pio only
2684 * Compared to DesignWare DMA Interface, Generic DMA Interface has a
2685 * simpler request/acknowledge handshake mechanism and both of them
2686 * are regarded as external dma master for dw_mmc.
2688 host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
2689 if (host->use_dma == DMA_INTERFACE_IDMA) {
2690 host->use_dma = TRANS_MODE_IDMAC;
2691 } else if (host->use_dma == DMA_INTERFACE_DWDMA ||
2692 host->use_dma == DMA_INTERFACE_GDMA) {
2693 host->use_dma = TRANS_MODE_EDMAC;
2698 /* Determine which DMA interface to use */
2699 if (host->use_dma == TRANS_MODE_IDMAC) {
2701 * Check ADDR_CONFIG bit in HCON to find
2702 * IDMAC address bus width
2704 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
2706 if (addr_config == 1) {
2707 /* host supports IDMAC in 64-bit address mode */
2708 host->dma_64bit_address = 1;
2710 "IDMAC supports 64-bit address mode.\n");
2711 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
2712 dma_set_coherent_mask(host->dev,
2715 /* host supports IDMAC in 32-bit address mode */
2716 host->dma_64bit_address = 0;
2718 "IDMAC supports 32-bit address mode.\n");
2721 /* Alloc memory for sg translation */
2722 host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE,
2723 &host->sg_dma, GFP_KERNEL);
2724 if (!host->sg_cpu) {
2726 "%s: could not alloc DMA memory\n",
2731 host->dma_ops = &dw_mci_idmac_ops;
2732 dev_info(host->dev, "Using internal DMA controller.\n");
2734 /* TRANS_MODE_EDMAC: check dma bindings again */
2735 if ((of_property_count_strings(np, "dma-names") < 0) ||
2736 (!of_find_property(np, "dmas", NULL))) {
2739 host->dma_ops = &dw_mci_edmac_ops;
2740 dev_info(host->dev, "Using external DMA controller.\n");
2743 if (host->dma_ops->init && host->dma_ops->start &&
2744 host->dma_ops->stop && host->dma_ops->cleanup) {
2745 if (host->dma_ops->init(host)) {
2746 dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n",
2751 dev_err(host->dev, "DMA initialization not found.\n");
2758 dev_info(host->dev, "Using PIO mode.\n");
2759 host->use_dma = TRANS_MODE_PIO;
2762 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
2764 unsigned long timeout = jiffies + msecs_to_jiffies(500);
2767 ctrl = mci_readl(host, CTRL);
2769 mci_writel(host, CTRL, ctrl);
2771 /* wait till resets clear */
2773 ctrl = mci_readl(host, CTRL);
2774 if (!(ctrl & reset))
2776 } while (time_before(jiffies, timeout));
2779 "Timeout resetting block (ctrl reset %#x)\n",
2785 static bool dw_mci_reset(struct dw_mci *host)
2787 u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
2791 * Reseting generates a block interrupt, hence setting
2792 * the scatter-gather pointer to NULL.
2795 sg_miter_stop(&host->sg_miter);
2800 flags |= SDMMC_CTRL_DMA_RESET;
2802 if (dw_mci_ctrl_reset(host, flags)) {
2804 * In all cases we clear the RAWINTS register to clear any
2807 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2809 /* if using dma we wait for dma_req to clear */
2810 if (host->use_dma) {
2811 unsigned long timeout = jiffies + msecs_to_jiffies(500);
2815 status = mci_readl(host, STATUS);
2816 if (!(status & SDMMC_STATUS_DMA_REQ))
2819 } while (time_before(jiffies, timeout));
2821 if (status & SDMMC_STATUS_DMA_REQ) {
2823 "%s: Timeout waiting for dma_req to clear during reset\n",
2828 /* when using DMA next we reset the fifo again */
2829 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
2833 /* if the controller reset bit did clear, then set clock regs */
2834 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
2836 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
2842 if (host->use_dma == TRANS_MODE_IDMAC)
2843 /* It is also recommended that we reset and reprogram idmac */
2844 dw_mci_idmac_reset(host);
2849 /* After a CTRL reset we need to have CIU set clock registers */
2850 mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0);
2855 static void dw_mci_cmd11_timer(unsigned long arg)
2857 struct dw_mci *host = (struct dw_mci *)arg;
2859 if (host->state != STATE_SENDING_CMD11) {
2860 dev_warn(host->dev, "Unexpected CMD11 timeout\n");
2864 host->cmd_status = SDMMC_INT_RTO;
2865 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2866 tasklet_schedule(&host->tasklet);
2869 static void dw_mci_dto_timer(unsigned long arg)
2871 struct dw_mci *host = (struct dw_mci *)arg;
2873 switch (host->state) {
2874 case STATE_SENDING_DATA:
2875 case STATE_DATA_BUSY:
2877 * If DTO interrupt does NOT come in sending data state,
2878 * we should notify the driver to terminate current transfer
2879 * and report a data timeout to the core.
2881 host->data_status = SDMMC_INT_DRTO;
2882 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2883 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2884 tasklet_schedule(&host->tasklet);
2892 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2894 struct dw_mci_board *pdata;
2895 struct device *dev = host->dev;
2896 struct device_node *np = dev->of_node;
2897 const struct dw_mci_drv_data *drv_data = host->drv_data;
2899 u32 clock_frequency;
2901 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2903 return ERR_PTR(-ENOMEM);
2905 /* find out number of slots supported */
2906 of_property_read_u32(np, "num-slots", &pdata->num_slots);
2908 if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
2910 "fifo-depth property not found, using value of FIFOTH register as default\n");
2912 of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
2914 if (!of_property_read_u32(np, "clock-frequency", &clock_frequency))
2915 pdata->bus_hz = clock_frequency;
2917 if (drv_data && drv_data->parse_dt) {
2918 ret = drv_data->parse_dt(host);
2920 return ERR_PTR(ret);
2923 if (of_find_property(np, "supports-highspeed", NULL)) {
2924 dev_info(dev, "supports-highspeed property is deprecated.\n");
2925 pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2931 #else /* CONFIG_OF */
2932 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2934 return ERR_PTR(-EINVAL);
2936 #endif /* CONFIG_OF */
2938 static void dw_mci_enable_cd(struct dw_mci *host)
2940 unsigned long irqflags;
2943 struct dw_mci_slot *slot;
2946 * No need for CD if all slots have a non-error GPIO
2947 * as well as broken card detection is found.
2949 for (i = 0; i < host->num_slots; i++) {
2950 slot = host->slot[i];
2951 if (slot->mmc->caps & MMC_CAP_NEEDS_POLL)
2954 if (mmc_gpio_get_cd(slot->mmc) < 0)
2957 if (i == host->num_slots)
2960 spin_lock_irqsave(&host->irq_lock, irqflags);
2961 temp = mci_readl(host, INTMASK);
2962 temp |= SDMMC_INT_CD;
2963 mci_writel(host, INTMASK, temp);
2964 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2967 int dw_mci_probe(struct dw_mci *host)
2969 const struct dw_mci_drv_data *drv_data = host->drv_data;
2970 int width, i, ret = 0;
2975 host->pdata = dw_mci_parse_dt(host);
2976 if (IS_ERR(host->pdata)) {
2977 dev_err(host->dev, "platform data not available\n");
2982 host->biu_clk = devm_clk_get(host->dev, "biu");
2983 if (IS_ERR(host->biu_clk)) {
2984 dev_dbg(host->dev, "biu clock not available\n");
2986 ret = clk_prepare_enable(host->biu_clk);
2988 dev_err(host->dev, "failed to enable biu clock\n");
2993 host->ciu_clk = devm_clk_get(host->dev, "ciu");
2994 if (IS_ERR(host->ciu_clk)) {
2995 dev_dbg(host->dev, "ciu clock not available\n");
2996 host->bus_hz = host->pdata->bus_hz;
2998 ret = clk_prepare_enable(host->ciu_clk);
3000 dev_err(host->dev, "failed to enable ciu clock\n");
3004 if (host->pdata->bus_hz) {
3005 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
3008 "Unable to set bus rate to %uHz\n",
3009 host->pdata->bus_hz);
3011 host->bus_hz = clk_get_rate(host->ciu_clk);
3014 if (!host->bus_hz) {
3016 "Platform data must supply bus speed\n");
3021 if (drv_data && drv_data->init) {
3022 ret = drv_data->init(host);
3025 "implementation specific init failed\n");
3030 setup_timer(&host->cmd11_timer,
3031 dw_mci_cmd11_timer, (unsigned long)host);
3033 host->quirks = host->pdata->quirks;
3035 if (host->quirks & DW_MCI_QUIRK_BROKEN_DTO)
3036 setup_timer(&host->dto_timer,
3037 dw_mci_dto_timer, (unsigned long)host);
3039 spin_lock_init(&host->lock);
3040 spin_lock_init(&host->irq_lock);
3041 INIT_LIST_HEAD(&host->queue);
3044 * Get the host data width - this assumes that HCON has been set with
3045 * the correct values.
3047 i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));
3049 host->push_data = dw_mci_push_data16;
3050 host->pull_data = dw_mci_pull_data16;
3052 host->data_shift = 1;
3053 } else if (i == 2) {
3054 host->push_data = dw_mci_push_data64;
3055 host->pull_data = dw_mci_pull_data64;
3057 host->data_shift = 3;
3059 /* Check for a reserved value, and warn if it is */
3061 "HCON reports a reserved host data width!\n"
3062 "Defaulting to 32-bit access.\n");
3063 host->push_data = dw_mci_push_data32;
3064 host->pull_data = dw_mci_pull_data32;
3066 host->data_shift = 2;
3069 /* Reset all blocks */
3070 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3075 host->dma_ops = host->pdata->dma_ops;
3076 dw_mci_init_dma(host);
3078 /* Clear the interrupts for the host controller */
3079 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3080 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3082 /* Put in max timeout */
3083 mci_writel(host, TMOUT, 0xFFFFFFFF);
3086 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
3087 * Tx Mark = fifo_size / 2 DMA Size = 8
3089 if (!host->pdata->fifo_depth) {
3091 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
3092 * have been overwritten by the bootloader, just like we're
3093 * about to do, so if you know the value for your hardware, you
3094 * should put it in the platform data.
3096 fifo_size = mci_readl(host, FIFOTH);
3097 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
3099 fifo_size = host->pdata->fifo_depth;
3101 host->fifo_depth = fifo_size;
3103 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
3104 mci_writel(host, FIFOTH, host->fifoth_val);
3106 /* disable clock to CIU */
3107 mci_writel(host, CLKENA, 0);
3108 mci_writel(host, CLKSRC, 0);
3111 * In 2.40a spec, Data offset is changed.
3112 * Need to check the version-id and set data-offset for DATA register.
3114 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
3115 dev_info(host->dev, "Version ID is %04x\n", host->verid);
3117 if (host->verid < DW_MMC_240A)
3118 host->fifo_reg = host->regs + DATA_OFFSET;
3120 host->fifo_reg = host->regs + DATA_240A_OFFSET;
3122 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
3123 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
3124 host->irq_flags, "dw-mci", host);
3128 if (host->pdata->num_slots)
3129 host->num_slots = host->pdata->num_slots;
3131 host->num_slots = 1;
3133 if (host->num_slots < 1 ||
3134 host->num_slots > SDMMC_GET_SLOT_NUM(mci_readl(host, HCON))) {
3136 "Platform data must supply correct num_slots.\n");
3142 * Enable interrupts for command done, data over, data empty,
3143 * receive ready and error such as transmit, receive timeout, crc error
3145 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3146 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3147 DW_MCI_ERROR_FLAGS);
3148 /* Enable mci interrupt */
3149 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3152 "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n",
3153 host->irq, width, fifo_size);
3155 /* We need at least one slot to succeed */
3156 for (i = 0; i < host->num_slots; i++) {
3157 ret = dw_mci_init_slot(host, i);
3159 dev_dbg(host->dev, "slot %d init failed\n", i);
3165 dev_info(host->dev, "%d slots initialized\n", init_slots);
3168 "attempted to initialize %d slots, but failed on all\n",
3173 /* Now that slots are all setup, we can enable card detect */
3174 dw_mci_enable_cd(host);
3179 if (host->use_dma && host->dma_ops->exit)
3180 host->dma_ops->exit(host);
3183 if (!IS_ERR(host->ciu_clk))
3184 clk_disable_unprepare(host->ciu_clk);
3187 if (!IS_ERR(host->biu_clk))
3188 clk_disable_unprepare(host->biu_clk);
3192 EXPORT_SYMBOL(dw_mci_probe);
3194 void dw_mci_remove(struct dw_mci *host)
3198 for (i = 0; i < host->num_slots; i++) {
3199 dev_dbg(host->dev, "remove slot %d\n", i);
3201 dw_mci_cleanup_slot(host->slot[i], i);
3204 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3205 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3207 /* disable clock to CIU */
3208 mci_writel(host, CLKENA, 0);
3209 mci_writel(host, CLKSRC, 0);
3211 if (host->use_dma && host->dma_ops->exit)
3212 host->dma_ops->exit(host);
3214 if (!IS_ERR(host->ciu_clk))
3215 clk_disable_unprepare(host->ciu_clk);
3217 if (!IS_ERR(host->biu_clk))
3218 clk_disable_unprepare(host->biu_clk);
3220 EXPORT_SYMBOL(dw_mci_remove);
3224 #ifdef CONFIG_PM_SLEEP
3226 * TODO: we should probably disable the clock to the card in the suspend path.
3228 int dw_mci_suspend(struct dw_mci *host)
3230 if (host->use_dma && host->dma_ops->exit)
3231 host->dma_ops->exit(host);
3235 EXPORT_SYMBOL(dw_mci_suspend);
3237 int dw_mci_resume(struct dw_mci *host)
3241 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3246 if (host->use_dma && host->dma_ops->init)
3247 host->dma_ops->init(host);
3250 * Restore the initial value at FIFOTH register
3251 * And Invalidate the prev_blksz with zero
3253 mci_writel(host, FIFOTH, host->fifoth_val);
3254 host->prev_blksz = 0;
3256 /* Put in max timeout */
3257 mci_writel(host, TMOUT, 0xFFFFFFFF);
3259 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3260 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3261 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3262 DW_MCI_ERROR_FLAGS);
3263 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3265 for (i = 0; i < host->num_slots; i++) {
3266 struct dw_mci_slot *slot = host->slot[i];
3270 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
3271 dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
3272 dw_mci_setup_bus(slot, true);
3276 /* Now that slots are all setup, we can enable card detect */
3277 dw_mci_enable_cd(host);
3281 EXPORT_SYMBOL(dw_mci_resume);
3282 #endif /* CONFIG_PM_SLEEP */
3284 static int __init dw_mci_init(void)
3286 pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
3290 static void __exit dw_mci_exit(void)
3294 module_init(dw_mci_init);
3295 module_exit(dw_mci_exit);
3297 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
3298 MODULE_AUTHOR("NXP Semiconductor VietNam");
3299 MODULE_AUTHOR("Imagination Technologies Ltd");
3300 MODULE_LICENSE("GPL v2");