1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Synopsys DesignWare Multimedia Card Interface driver
4 * (Based on NXP driver for lpc 31xx)
6 * Copyright (C) 2009 NXP Semiconductors
7 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
10 #include <linux/blkdev.h>
11 #include <linux/clk.h>
12 #include <linux/debugfs.h>
13 #include <linux/device.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/err.h>
16 #include <linux/init.h>
17 #include <linux/interrupt.h>
18 #include <linux/iopoll.h>
19 #include <linux/ioport.h>
20 #include <linux/ktime.h>
21 #include <linux/module.h>
22 #include <linux/platform_device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/prandom.h>
25 #include <linux/seq_file.h>
26 #include <linux/slab.h>
27 #include <linux/stat.h>
28 #include <linux/delay.h>
29 #include <linux/irq.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/host.h>
32 #include <linux/mmc/mmc.h>
33 #include <linux/mmc/sd.h>
34 #include <linux/mmc/sdio.h>
35 #include <linux/bitops.h>
36 #include <linux/regulator/consumer.h>
38 #include <linux/of_gpio.h>
39 #include <linux/mmc/slot-gpio.h>
43 /* Common flag combinations */
44 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
45 SDMMC_INT_HTO | SDMMC_INT_SBE | \
46 SDMMC_INT_EBE | SDMMC_INT_HLE)
47 #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
48 SDMMC_INT_RESP_ERR | SDMMC_INT_HLE)
49 #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
50 DW_MCI_CMD_ERROR_FLAGS)
51 #define DW_MCI_SEND_STATUS 1
52 #define DW_MCI_RECV_STATUS 2
53 #define DW_MCI_DMA_THRESHOLD 16
55 #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */
56 #define DW_MCI_FREQ_MIN 100000 /* unit: HZ */
58 #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
59 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
60 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
63 #define DESC_RING_BUF_SZ PAGE_SIZE
65 struct idmac_desc_64addr {
66 u32 des0; /* Control Descriptor */
67 #define IDMAC_OWN_CLR64(x) \
68 !((x) & cpu_to_le32(IDMAC_DES0_OWN))
70 u32 des1; /* Reserved */
72 u32 des2; /*Buffer sizes */
73 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
74 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
75 ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
77 u32 des3; /* Reserved */
79 u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/
80 u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/
82 u32 des6; /* Lower 32-bits of Next Descriptor Address */
83 u32 des7; /* Upper 32-bits of Next Descriptor Address */
87 __le32 des0; /* Control Descriptor */
88 #define IDMAC_DES0_DIC BIT(1)
89 #define IDMAC_DES0_LD BIT(2)
90 #define IDMAC_DES0_FD BIT(3)
91 #define IDMAC_DES0_CH BIT(4)
92 #define IDMAC_DES0_ER BIT(5)
93 #define IDMAC_DES0_CES BIT(30)
94 #define IDMAC_DES0_OWN BIT(31)
96 __le32 des1; /* Buffer sizes */
97 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
98 ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff)))
100 __le32 des2; /* buffer 1 physical address */
102 __le32 des3; /* buffer 2 physical address */
105 /* Each descriptor can transfer up to 4KB of data in chained mode */
106 #define DW_MCI_DESC_DATA_LENGTH 0x1000
108 #if defined(CONFIG_DEBUG_FS)
109 static int dw_mci_req_show(struct seq_file *s, void *v)
111 struct dw_mci_slot *slot = s->private;
112 struct mmc_request *mrq;
113 struct mmc_command *cmd;
114 struct mmc_command *stop;
115 struct mmc_data *data;
117 /* Make sure we get a consistent snapshot */
118 spin_lock_bh(&slot->host->lock);
128 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
129 cmd->opcode, cmd->arg, cmd->flags,
130 cmd->resp[0], cmd->resp[1], cmd->resp[2],
131 cmd->resp[2], cmd->error);
133 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
134 data->bytes_xfered, data->blocks,
135 data->blksz, data->flags, data->error);
138 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
139 stop->opcode, stop->arg, stop->flags,
140 stop->resp[0], stop->resp[1], stop->resp[2],
141 stop->resp[2], stop->error);
144 spin_unlock_bh(&slot->host->lock);
148 DEFINE_SHOW_ATTRIBUTE(dw_mci_req);
150 static int dw_mci_regs_show(struct seq_file *s, void *v)
152 struct dw_mci *host = s->private;
154 pm_runtime_get_sync(host->dev);
156 seq_printf(s, "STATUS:\t0x%08x\n", mci_readl(host, STATUS));
157 seq_printf(s, "RINTSTS:\t0x%08x\n", mci_readl(host, RINTSTS));
158 seq_printf(s, "CMD:\t0x%08x\n", mci_readl(host, CMD));
159 seq_printf(s, "CTRL:\t0x%08x\n", mci_readl(host, CTRL));
160 seq_printf(s, "INTMASK:\t0x%08x\n", mci_readl(host, INTMASK));
161 seq_printf(s, "CLKENA:\t0x%08x\n", mci_readl(host, CLKENA));
163 pm_runtime_put_autosuspend(host->dev);
167 DEFINE_SHOW_ATTRIBUTE(dw_mci_regs);
169 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
171 struct mmc_host *mmc = slot->mmc;
172 struct dw_mci *host = slot->host;
175 root = mmc->debugfs_root;
179 debugfs_create_file("regs", S_IRUSR, root, host, &dw_mci_regs_fops);
180 debugfs_create_file("req", S_IRUSR, root, slot, &dw_mci_req_fops);
181 debugfs_create_u32("state", S_IRUSR, root, &host->state);
182 debugfs_create_xul("pending_events", S_IRUSR, root,
183 &host->pending_events);
184 debugfs_create_xul("completed_events", S_IRUSR, root,
185 &host->completed_events);
186 #ifdef CONFIG_FAULT_INJECTION
187 fault_create_debugfs_attr("fail_data_crc", root, &host->fail_data_crc);
190 #endif /* defined(CONFIG_DEBUG_FS) */
192 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
196 ctrl = mci_readl(host, CTRL);
198 mci_writel(host, CTRL, ctrl);
200 /* wait till resets clear */
201 if (readl_poll_timeout_atomic(host->regs + SDMMC_CTRL, ctrl,
203 1, 500 * USEC_PER_MSEC)) {
205 "Timeout resetting block (ctrl reset %#x)\n",
213 static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
218 * Databook says that before issuing a new data transfer command
219 * we need to check to see if the card is busy. Data transfer commands
220 * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
222 * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
225 if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) &&
226 !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) {
227 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
229 !(status & SDMMC_STATUS_BUSY),
230 10, 500 * USEC_PER_MSEC))
231 dev_err(host->dev, "Busy; trying anyway\n");
235 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
237 struct dw_mci *host = slot->host;
238 unsigned int cmd_status = 0;
240 mci_writel(host, CMDARG, arg);
241 wmb(); /* drain writebuffer */
242 dw_mci_wait_while_busy(host, cmd);
243 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
245 if (readl_poll_timeout_atomic(host->regs + SDMMC_CMD, cmd_status,
246 !(cmd_status & SDMMC_CMD_START),
247 1, 500 * USEC_PER_MSEC))
248 dev_err(&slot->mmc->class_dev,
249 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
250 cmd, arg, cmd_status);
253 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
255 struct dw_mci_slot *slot = mmc_priv(mmc);
256 struct dw_mci *host = slot->host;
259 cmd->error = -EINPROGRESS;
262 if (cmd->opcode == MMC_STOP_TRANSMISSION ||
263 cmd->opcode == MMC_GO_IDLE_STATE ||
264 cmd->opcode == MMC_GO_INACTIVE_STATE ||
265 (cmd->opcode == SD_IO_RW_DIRECT &&
266 ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
267 cmdr |= SDMMC_CMD_STOP;
268 else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
269 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
271 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
274 /* Special bit makes CMD11 not die */
275 cmdr |= SDMMC_CMD_VOLT_SWITCH;
277 /* Change state to continue to handle CMD11 weirdness */
278 WARN_ON(slot->host->state != STATE_SENDING_CMD);
279 slot->host->state = STATE_SENDING_CMD11;
282 * We need to disable low power mode (automatic clock stop)
283 * while doing voltage switch so we don't confuse the card,
284 * since stopping the clock is a specific part of the UHS
285 * voltage change dance.
287 * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
288 * unconditionally turned back on in dw_mci_setup_bus() if it's
289 * ever called with a non-zero clock. That shouldn't happen
290 * until the voltage change is all done.
292 clk_en_a = mci_readl(host, CLKENA);
293 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
294 mci_writel(host, CLKENA, clk_en_a);
295 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
296 SDMMC_CMD_PRV_DAT_WAIT, 0);
299 if (cmd->flags & MMC_RSP_PRESENT) {
300 /* We expect a response, so set this bit */
301 cmdr |= SDMMC_CMD_RESP_EXP;
302 if (cmd->flags & MMC_RSP_136)
303 cmdr |= SDMMC_CMD_RESP_LONG;
306 if (cmd->flags & MMC_RSP_CRC)
307 cmdr |= SDMMC_CMD_RESP_CRC;
310 cmdr |= SDMMC_CMD_DAT_EXP;
311 if (cmd->data->flags & MMC_DATA_WRITE)
312 cmdr |= SDMMC_CMD_DAT_WR;
315 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags))
316 cmdr |= SDMMC_CMD_USE_HOLD_REG;
321 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
323 struct mmc_command *stop;
329 stop = &host->stop_abort;
331 memset(stop, 0, sizeof(struct mmc_command));
333 if (cmdr == MMC_READ_SINGLE_BLOCK ||
334 cmdr == MMC_READ_MULTIPLE_BLOCK ||
335 cmdr == MMC_WRITE_BLOCK ||
336 cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
337 cmdr == MMC_SEND_TUNING_BLOCK ||
338 cmdr == MMC_SEND_TUNING_BLOCK_HS200) {
339 stop->opcode = MMC_STOP_TRANSMISSION;
341 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
342 } else if (cmdr == SD_IO_RW_EXTENDED) {
343 stop->opcode = SD_IO_RW_DIRECT;
344 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
345 ((cmd->arg >> 28) & 0x7);
346 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
351 cmdr = stop->opcode | SDMMC_CMD_STOP |
352 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
354 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &host->slot->flags))
355 cmdr |= SDMMC_CMD_USE_HOLD_REG;
360 static inline void dw_mci_set_cto(struct dw_mci *host)
362 unsigned int cto_clks;
363 unsigned int cto_div;
365 unsigned long irqflags;
367 cto_clks = mci_readl(host, TMOUT) & 0xff;
368 cto_div = (mci_readl(host, CLKDIV) & 0xff) * 2;
372 cto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * cto_clks * cto_div,
375 /* add a bit spare time */
379 * The durations we're working with are fairly short so we have to be
380 * extra careful about synchronization here. Specifically in hardware a
381 * command timeout is _at most_ 5.1 ms, so that means we expect an
382 * interrupt (either command done or timeout) to come rather quickly
383 * after the mci_writel. ...but just in case we have a long interrupt
384 * latency let's add a bit of paranoia.
386 * In general we'll assume that at least an interrupt will be asserted
387 * in hardware by the time the cto_timer runs. ...and if it hasn't
388 * been asserted in hardware by that time then we'll assume it'll never
391 spin_lock_irqsave(&host->irq_lock, irqflags);
392 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
393 mod_timer(&host->cto_timer,
394 jiffies + msecs_to_jiffies(cto_ms) + 1);
395 spin_unlock_irqrestore(&host->irq_lock, irqflags);
398 static void dw_mci_start_command(struct dw_mci *host,
399 struct mmc_command *cmd, u32 cmd_flags)
403 "start command: ARGR=0x%08x CMDR=0x%08x\n",
404 cmd->arg, cmd_flags);
406 mci_writel(host, CMDARG, cmd->arg);
407 wmb(); /* drain writebuffer */
408 dw_mci_wait_while_busy(host, cmd_flags);
410 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
412 /* response expected command only */
413 if (cmd_flags & SDMMC_CMD_RESP_EXP)
414 dw_mci_set_cto(host);
417 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
419 struct mmc_command *stop = &host->stop_abort;
421 dw_mci_start_command(host, stop, host->stop_cmdr);
424 /* DMA interface functions */
425 static void dw_mci_stop_dma(struct dw_mci *host)
427 if (host->using_dma) {
428 host->dma_ops->stop(host);
429 host->dma_ops->cleanup(host);
432 /* Data transfer was stopped by the interrupt handler */
433 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
436 static void dw_mci_dma_cleanup(struct dw_mci *host)
438 struct mmc_data *data = host->data;
440 if (data && data->host_cookie == COOKIE_MAPPED) {
441 dma_unmap_sg(host->dev,
444 mmc_get_dma_dir(data));
445 data->host_cookie = COOKIE_UNMAPPED;
449 static void dw_mci_idmac_reset(struct dw_mci *host)
451 u32 bmod = mci_readl(host, BMOD);
452 /* Software reset of DMA */
453 bmod |= SDMMC_IDMAC_SWRESET;
454 mci_writel(host, BMOD, bmod);
457 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
461 /* Disable and reset the IDMAC interface */
462 temp = mci_readl(host, CTRL);
463 temp &= ~SDMMC_CTRL_USE_IDMAC;
464 temp |= SDMMC_CTRL_DMA_RESET;
465 mci_writel(host, CTRL, temp);
467 /* Stop the IDMAC running */
468 temp = mci_readl(host, BMOD);
469 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
470 temp |= SDMMC_IDMAC_SWRESET;
471 mci_writel(host, BMOD, temp);
474 static void dw_mci_dmac_complete_dma(void *arg)
476 struct dw_mci *host = arg;
477 struct mmc_data *data = host->data;
479 dev_vdbg(host->dev, "DMA complete\n");
481 if ((host->use_dma == TRANS_MODE_EDMAC) &&
482 data && (data->flags & MMC_DATA_READ))
483 /* Invalidate cache after read */
484 dma_sync_sg_for_cpu(mmc_dev(host->slot->mmc),
489 host->dma_ops->cleanup(host);
492 * If the card was removed, data will be NULL. No point in trying to
493 * send the stop command or waiting for NBUSY in this case.
496 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
497 tasklet_schedule(&host->tasklet);
501 static int dw_mci_idmac_init(struct dw_mci *host)
505 if (host->dma_64bit_address == 1) {
506 struct idmac_desc_64addr *p;
507 /* Number of descriptors in the ring buffer */
509 DESC_RING_BUF_SZ / sizeof(struct idmac_desc_64addr);
511 /* Forward link the descriptor list */
512 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
514 p->des6 = (host->sg_dma +
515 (sizeof(struct idmac_desc_64addr) *
516 (i + 1))) & 0xffffffff;
518 p->des7 = (u64)(host->sg_dma +
519 (sizeof(struct idmac_desc_64addr) *
521 /* Initialize reserved and buffer size fields to "0" */
528 /* Set the last descriptor as the end-of-ring descriptor */
529 p->des6 = host->sg_dma & 0xffffffff;
530 p->des7 = (u64)host->sg_dma >> 32;
531 p->des0 = IDMAC_DES0_ER;
534 struct idmac_desc *p;
535 /* Number of descriptors in the ring buffer */
537 DESC_RING_BUF_SZ / sizeof(struct idmac_desc);
539 /* Forward link the descriptor list */
540 for (i = 0, p = host->sg_cpu;
541 i < host->ring_size - 1;
543 p->des3 = cpu_to_le32(host->sg_dma +
544 (sizeof(struct idmac_desc) * (i + 1)));
549 /* Set the last descriptor as the end-of-ring descriptor */
550 p->des3 = cpu_to_le32(host->sg_dma);
551 p->des0 = cpu_to_le32(IDMAC_DES0_ER);
554 dw_mci_idmac_reset(host);
556 if (host->dma_64bit_address == 1) {
557 /* Mask out interrupts - get Tx & Rx complete only */
558 mci_writel(host, IDSTS64, IDMAC_INT_CLR);
559 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
560 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
562 /* Set the descriptor base address */
563 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
564 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
567 /* Mask out interrupts - get Tx & Rx complete only */
568 mci_writel(host, IDSTS, IDMAC_INT_CLR);
569 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
570 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
572 /* Set the descriptor base address */
573 mci_writel(host, DBADDR, host->sg_dma);
579 static inline int dw_mci_prepare_desc64(struct dw_mci *host,
580 struct mmc_data *data,
583 unsigned int desc_len;
584 struct idmac_desc_64addr *desc_first, *desc_last, *desc;
588 desc_first = desc_last = desc = host->sg_cpu;
590 for (i = 0; i < sg_len; i++) {
591 unsigned int length = sg_dma_len(&data->sg[i]);
593 u64 mem_addr = sg_dma_address(&data->sg[i]);
595 for ( ; length ; desc++) {
596 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
597 length : DW_MCI_DESC_DATA_LENGTH;
602 * Wait for the former clear OWN bit operation
603 * of IDMAC to make sure that this descriptor
604 * isn't still owned by IDMAC as IDMAC's write
605 * ops and CPU's read ops are asynchronous.
607 if (readl_poll_timeout_atomic(&desc->des0, val,
608 !(val & IDMAC_DES0_OWN),
609 10, 100 * USEC_PER_MSEC))
613 * Set the OWN bit and disable interrupts
614 * for this descriptor
616 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
620 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len);
622 /* Physical address to DMA to/from */
623 desc->des4 = mem_addr & 0xffffffff;
624 desc->des5 = mem_addr >> 32;
626 /* Update physical address for the next desc */
627 mem_addr += desc_len;
629 /* Save pointer to the last descriptor */
634 /* Set first descriptor */
635 desc_first->des0 |= IDMAC_DES0_FD;
637 /* Set last descriptor */
638 desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
639 desc_last->des0 |= IDMAC_DES0_LD;
643 /* restore the descriptor chain as it's polluted */
644 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
645 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
646 dw_mci_idmac_init(host);
651 static inline int dw_mci_prepare_desc32(struct dw_mci *host,
652 struct mmc_data *data,
655 unsigned int desc_len;
656 struct idmac_desc *desc_first, *desc_last, *desc;
660 desc_first = desc_last = desc = host->sg_cpu;
662 for (i = 0; i < sg_len; i++) {
663 unsigned int length = sg_dma_len(&data->sg[i]);
665 u32 mem_addr = sg_dma_address(&data->sg[i]);
667 for ( ; length ; desc++) {
668 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
669 length : DW_MCI_DESC_DATA_LENGTH;
674 * Wait for the former clear OWN bit operation
675 * of IDMAC to make sure that this descriptor
676 * isn't still owned by IDMAC as IDMAC's write
677 * ops and CPU's read ops are asynchronous.
679 if (readl_poll_timeout_atomic(&desc->des0, val,
680 IDMAC_OWN_CLR64(val),
682 100 * USEC_PER_MSEC))
686 * Set the OWN bit and disable interrupts
687 * for this descriptor
689 desc->des0 = cpu_to_le32(IDMAC_DES0_OWN |
694 IDMAC_SET_BUFFER1_SIZE(desc, desc_len);
696 /* Physical address to DMA to/from */
697 desc->des2 = cpu_to_le32(mem_addr);
699 /* Update physical address for the next desc */
700 mem_addr += desc_len;
702 /* Save pointer to the last descriptor */
707 /* Set first descriptor */
708 desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD);
710 /* Set last descriptor */
711 desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH |
713 desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD);
717 /* restore the descriptor chain as it's polluted */
718 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
719 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
720 dw_mci_idmac_init(host);
724 static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
729 if (host->dma_64bit_address == 1)
730 ret = dw_mci_prepare_desc64(host, host->data, sg_len);
732 ret = dw_mci_prepare_desc32(host, host->data, sg_len);
737 /* drain writebuffer */
740 /* Make sure to reset DMA in case we did PIO before this */
741 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
742 dw_mci_idmac_reset(host);
744 /* Select IDMAC interface */
745 temp = mci_readl(host, CTRL);
746 temp |= SDMMC_CTRL_USE_IDMAC;
747 mci_writel(host, CTRL, temp);
749 /* drain writebuffer */
752 /* Enable the IDMAC */
753 temp = mci_readl(host, BMOD);
754 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
755 mci_writel(host, BMOD, temp);
757 /* Start it running */
758 mci_writel(host, PLDMND, 1);
764 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
765 .init = dw_mci_idmac_init,
766 .start = dw_mci_idmac_start_dma,
767 .stop = dw_mci_idmac_stop_dma,
768 .complete = dw_mci_dmac_complete_dma,
769 .cleanup = dw_mci_dma_cleanup,
772 static void dw_mci_edmac_stop_dma(struct dw_mci *host)
774 dmaengine_terminate_async(host->dms->ch);
777 static int dw_mci_edmac_start_dma(struct dw_mci *host,
780 struct dma_slave_config cfg;
781 struct dma_async_tx_descriptor *desc = NULL;
782 struct scatterlist *sgl = host->data->sg;
783 static const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
784 u32 sg_elems = host->data->sg_len;
786 u32 fifo_offset = host->fifo_reg - host->regs;
789 /* Set external dma config: burst size, burst width */
790 memset(&cfg, 0, sizeof(cfg));
791 cfg.dst_addr = host->phy_regs + fifo_offset;
792 cfg.src_addr = cfg.dst_addr;
793 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
794 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
796 /* Match burst msize with external dma config */
797 fifoth_val = mci_readl(host, FIFOTH);
798 cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7];
799 cfg.src_maxburst = cfg.dst_maxburst;
801 if (host->data->flags & MMC_DATA_WRITE)
802 cfg.direction = DMA_MEM_TO_DEV;
804 cfg.direction = DMA_DEV_TO_MEM;
806 ret = dmaengine_slave_config(host->dms->ch, &cfg);
808 dev_err(host->dev, "Failed to config edmac.\n");
812 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl,
813 sg_len, cfg.direction,
814 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
816 dev_err(host->dev, "Can't prepare slave sg.\n");
820 /* Set dw_mci_dmac_complete_dma as callback */
821 desc->callback = dw_mci_dmac_complete_dma;
822 desc->callback_param = (void *)host;
823 dmaengine_submit(desc);
825 /* Flush cache before write */
826 if (host->data->flags & MMC_DATA_WRITE)
827 dma_sync_sg_for_device(mmc_dev(host->slot->mmc), sgl,
828 sg_elems, DMA_TO_DEVICE);
830 dma_async_issue_pending(host->dms->ch);
835 static int dw_mci_edmac_init(struct dw_mci *host)
837 /* Request external dma channel */
838 host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
842 host->dms->ch = dma_request_chan(host->dev, "rx-tx");
843 if (IS_ERR(host->dms->ch)) {
844 int ret = PTR_ERR(host->dms->ch);
846 dev_err(host->dev, "Failed to get external DMA channel.\n");
855 static void dw_mci_edmac_exit(struct dw_mci *host)
859 dma_release_channel(host->dms->ch);
860 host->dms->ch = NULL;
867 static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
868 .init = dw_mci_edmac_init,
869 .exit = dw_mci_edmac_exit,
870 .start = dw_mci_edmac_start_dma,
871 .stop = dw_mci_edmac_stop_dma,
872 .complete = dw_mci_dmac_complete_dma,
873 .cleanup = dw_mci_dma_cleanup,
876 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
877 struct mmc_data *data,
880 struct scatterlist *sg;
881 unsigned int i, sg_len;
883 if (data->host_cookie == COOKIE_PRE_MAPPED)
887 * We don't do DMA on "complex" transfers, i.e. with
888 * non-word-aligned buffers or lengths. Also, we don't bother
889 * with all the DMA setup overhead for short transfers.
891 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
897 for_each_sg(data->sg, sg, data->sg_len, i) {
898 if (sg->offset & 3 || sg->length & 3)
902 sg_len = dma_map_sg(host->dev,
905 mmc_get_dma_dir(data));
909 data->host_cookie = cookie;
914 static void dw_mci_pre_req(struct mmc_host *mmc,
915 struct mmc_request *mrq)
917 struct dw_mci_slot *slot = mmc_priv(mmc);
918 struct mmc_data *data = mrq->data;
920 if (!slot->host->use_dma || !data)
923 /* This data might be unmapped at this time */
924 data->host_cookie = COOKIE_UNMAPPED;
926 if (dw_mci_pre_dma_transfer(slot->host, mrq->data,
927 COOKIE_PRE_MAPPED) < 0)
928 data->host_cookie = COOKIE_UNMAPPED;
931 static void dw_mci_post_req(struct mmc_host *mmc,
932 struct mmc_request *mrq,
935 struct dw_mci_slot *slot = mmc_priv(mmc);
936 struct mmc_data *data = mrq->data;
938 if (!slot->host->use_dma || !data)
941 if (data->host_cookie != COOKIE_UNMAPPED)
942 dma_unmap_sg(slot->host->dev,
945 mmc_get_dma_dir(data));
946 data->host_cookie = COOKIE_UNMAPPED;
949 static int dw_mci_get_cd(struct mmc_host *mmc)
952 struct dw_mci_slot *slot = mmc_priv(mmc);
953 struct dw_mci *host = slot->host;
954 int gpio_cd = mmc_gpio_get_cd(mmc);
956 /* Use platform get_cd function, else try onboard card detect */
957 if (((mmc->caps & MMC_CAP_NEEDS_POLL)
958 || !mmc_card_is_removable(mmc))) {
961 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
962 if (mmc->caps & MMC_CAP_NEEDS_POLL) {
963 dev_info(&mmc->class_dev,
964 "card is polling.\n");
966 dev_info(&mmc->class_dev,
967 "card is non-removable.\n");
969 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
973 } else if (gpio_cd >= 0)
976 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
979 spin_lock_bh(&host->lock);
980 if (present && !test_and_set_bit(DW_MMC_CARD_PRESENT, &slot->flags))
981 dev_dbg(&mmc->class_dev, "card is present\n");
983 !test_and_clear_bit(DW_MMC_CARD_PRESENT, &slot->flags))
984 dev_dbg(&mmc->class_dev, "card is not present\n");
985 spin_unlock_bh(&host->lock);
990 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
992 unsigned int blksz = data->blksz;
993 static const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
994 u32 fifo_width = 1 << host->data_shift;
995 u32 blksz_depth = blksz / fifo_width, fifoth_val;
996 u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
997 int idx = ARRAY_SIZE(mszs) - 1;
999 /* pio should ship this scenario */
1003 tx_wmark = (host->fifo_depth) / 2;
1004 tx_wmark_invers = host->fifo_depth - tx_wmark;
1008 * if blksz is not a multiple of the FIFO width
1010 if (blksz % fifo_width)
1014 if (!((blksz_depth % mszs[idx]) ||
1015 (tx_wmark_invers % mszs[idx]))) {
1017 rx_wmark = mszs[idx] - 1;
1020 } while (--idx > 0);
1022 * If idx is '0', it won't be tried
1023 * Thus, initial values are uesed
1026 fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
1027 mci_writel(host, FIFOTH, fifoth_val);
1030 static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data)
1032 unsigned int blksz = data->blksz;
1033 u32 blksz_depth, fifo_depth;
1038 * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
1039 * in the FIFO region, so we really shouldn't access it).
1041 if (host->verid < DW_MMC_240A ||
1042 (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE))
1046 * Card write Threshold is introduced since 2.80a
1047 * It's used when HS400 mode is enabled.
1049 if (data->flags & MMC_DATA_WRITE &&
1050 host->timing != MMC_TIMING_MMC_HS400)
1053 if (data->flags & MMC_DATA_WRITE)
1054 enable = SDMMC_CARD_WR_THR_EN;
1056 enable = SDMMC_CARD_RD_THR_EN;
1058 if (host->timing != MMC_TIMING_MMC_HS200 &&
1059 host->timing != MMC_TIMING_UHS_SDR104 &&
1060 host->timing != MMC_TIMING_MMC_HS400)
1063 blksz_depth = blksz / (1 << host->data_shift);
1064 fifo_depth = host->fifo_depth;
1066 if (blksz_depth > fifo_depth)
1070 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
1071 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz
1072 * Currently just choose blksz.
1075 mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable));
1079 mci_writel(host, CDTHRCTL, 0);
1082 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
1084 unsigned long irqflags;
1088 host->using_dma = 0;
1090 /* If we don't have a channel, we can't do DMA */
1094 sg_len = dw_mci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1096 host->dma_ops->stop(host);
1100 host->using_dma = 1;
1102 if (host->use_dma == TRANS_MODE_IDMAC)
1104 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
1105 (unsigned long)host->sg_cpu,
1106 (unsigned long)host->sg_dma,
1110 * Decide the MSIZE and RX/TX Watermark.
1111 * If current block size is same with previous size,
1112 * no need to update fifoth.
1114 if (host->prev_blksz != data->blksz)
1115 dw_mci_adjust_fifoth(host, data);
1117 /* Enable the DMA interface */
1118 temp = mci_readl(host, CTRL);
1119 temp |= SDMMC_CTRL_DMA_ENABLE;
1120 mci_writel(host, CTRL, temp);
1122 /* Disable RX/TX IRQs, let DMA handle it */
1123 spin_lock_irqsave(&host->irq_lock, irqflags);
1124 temp = mci_readl(host, INTMASK);
1125 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
1126 mci_writel(host, INTMASK, temp);
1127 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1129 if (host->dma_ops->start(host, sg_len)) {
1130 host->dma_ops->stop(host);
1131 /* We can't do DMA, try PIO for this one */
1133 "%s: fall back to PIO mode for current transfer\n",
1141 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
1143 unsigned long irqflags;
1144 int flags = SG_MITER_ATOMIC;
1147 data->error = -EINPROGRESS;
1149 WARN_ON(host->data);
1153 if (data->flags & MMC_DATA_READ)
1154 host->dir_status = DW_MCI_RECV_STATUS;
1156 host->dir_status = DW_MCI_SEND_STATUS;
1158 dw_mci_ctrl_thld(host, data);
1160 if (dw_mci_submit_data_dma(host, data)) {
1161 if (host->data->flags & MMC_DATA_READ)
1162 flags |= SG_MITER_TO_SG;
1164 flags |= SG_MITER_FROM_SG;
1166 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1167 host->sg = data->sg;
1168 host->part_buf_start = 0;
1169 host->part_buf_count = 0;
1171 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
1173 spin_lock_irqsave(&host->irq_lock, irqflags);
1174 temp = mci_readl(host, INTMASK);
1175 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
1176 mci_writel(host, INTMASK, temp);
1177 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1179 temp = mci_readl(host, CTRL);
1180 temp &= ~SDMMC_CTRL_DMA_ENABLE;
1181 mci_writel(host, CTRL, temp);
1184 * Use the initial fifoth_val for PIO mode. If wm_algined
1185 * is set, we set watermark same as data size.
1186 * If next issued data may be transfered by DMA mode,
1187 * prev_blksz should be invalidated.
1189 if (host->wm_aligned)
1190 dw_mci_adjust_fifoth(host, data);
1192 mci_writel(host, FIFOTH, host->fifoth_val);
1193 host->prev_blksz = 0;
1196 * Keep the current block size.
1197 * It will be used to decide whether to update
1198 * fifoth register next time.
1200 host->prev_blksz = data->blksz;
1204 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
1206 struct dw_mci *host = slot->host;
1207 unsigned int clock = slot->clock;
1210 u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
1212 /* We must continue to set bit 28 in CMD until the change is complete */
1213 if (host->state == STATE_WAITING_CMD11_DONE)
1214 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
1216 slot->mmc->actual_clock = 0;
1219 mci_writel(host, CLKENA, 0);
1220 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1221 } else if (clock != host->current_speed || force_clkinit) {
1222 div = host->bus_hz / clock;
1223 if (host->bus_hz % clock && host->bus_hz > clock)
1225 * move the + 1 after the divide to prevent
1226 * over-clocking the card.
1230 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
1232 if ((clock != slot->__clk_old &&
1233 !test_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags)) ||
1235 /* Silent the verbose log if calling from PM context */
1237 dev_info(&slot->mmc->class_dev,
1238 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1239 slot->id, host->bus_hz, clock,
1240 div ? ((host->bus_hz / div) >> 1) :
1244 * If card is polling, display the message only
1245 * one time at boot time.
1247 if (slot->mmc->caps & MMC_CAP_NEEDS_POLL &&
1248 slot->mmc->f_min == clock)
1249 set_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags);
1253 mci_writel(host, CLKENA, 0);
1254 mci_writel(host, CLKSRC, 0);
1257 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1259 /* set clock to desired speed */
1260 mci_writel(host, CLKDIV, div);
1263 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1265 /* enable clock; only low power if no SDIO */
1266 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
1267 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
1268 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1269 mci_writel(host, CLKENA, clk_en_a);
1272 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1274 /* keep the last clock value that was requested from core */
1275 slot->__clk_old = clock;
1276 slot->mmc->actual_clock = div ? ((host->bus_hz / div) >> 1) :
1280 host->current_speed = clock;
1282 /* Set the current slot bus width */
1283 mci_writel(host, CTYPE, (slot->ctype << slot->id));
1286 static void __dw_mci_start_request(struct dw_mci *host,
1287 struct dw_mci_slot *slot,
1288 struct mmc_command *cmd)
1290 struct mmc_request *mrq;
1291 struct mmc_data *data;
1298 host->pending_events = 0;
1299 host->completed_events = 0;
1300 host->cmd_status = 0;
1301 host->data_status = 0;
1302 host->dir_status = 0;
1306 mci_writel(host, TMOUT, 0xFFFFFFFF);
1307 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1308 mci_writel(host, BLKSIZ, data->blksz);
1311 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1313 /* this is the first command, send the initialization clock */
1314 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1315 cmdflags |= SDMMC_CMD_INIT;
1318 dw_mci_submit_data(host, data);
1319 wmb(); /* drain writebuffer */
1322 dw_mci_start_command(host, cmd, cmdflags);
1324 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
1325 unsigned long irqflags;
1328 * Databook says to fail after 2ms w/ no response, but evidence
1329 * shows that sometimes the cmd11 interrupt takes over 130ms.
1330 * We'll set to 500ms, plus an extra jiffy just in case jiffies
1331 * is just about to roll over.
1333 * We do this whole thing under spinlock and only if the
1334 * command hasn't already completed (indicating the the irq
1335 * already ran so we don't want the timeout).
1337 spin_lock_irqsave(&host->irq_lock, irqflags);
1338 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1339 mod_timer(&host->cmd11_timer,
1340 jiffies + msecs_to_jiffies(500) + 1);
1341 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1344 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
1347 static void dw_mci_start_request(struct dw_mci *host,
1348 struct dw_mci_slot *slot)
1350 struct mmc_request *mrq = slot->mrq;
1351 struct mmc_command *cmd;
1353 cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1354 __dw_mci_start_request(host, slot, cmd);
1357 /* must be called with host->lock held */
1358 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1359 struct mmc_request *mrq)
1361 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1366 if (host->state == STATE_WAITING_CMD11_DONE) {
1367 dev_warn(&slot->mmc->class_dev,
1368 "Voltage change didn't complete\n");
1370 * this case isn't expected to happen, so we can
1371 * either crash here or just try to continue on
1372 * in the closest possible state
1374 host->state = STATE_IDLE;
1377 if (host->state == STATE_IDLE) {
1378 host->state = STATE_SENDING_CMD;
1379 dw_mci_start_request(host, slot);
1381 list_add_tail(&slot->queue_node, &host->queue);
1385 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1387 struct dw_mci_slot *slot = mmc_priv(mmc);
1388 struct dw_mci *host = slot->host;
1393 * The check for card presence and queueing of the request must be
1394 * atomic, otherwise the card could be removed in between and the
1395 * request wouldn't fail until another card was inserted.
1398 if (!dw_mci_get_cd(mmc)) {
1399 mrq->cmd->error = -ENOMEDIUM;
1400 mmc_request_done(mmc, mrq);
1404 spin_lock_bh(&host->lock);
1406 dw_mci_queue_request(host, slot, mrq);
1408 spin_unlock_bh(&host->lock);
1411 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1413 struct dw_mci_slot *slot = mmc_priv(mmc);
1414 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1418 switch (ios->bus_width) {
1419 case MMC_BUS_WIDTH_4:
1420 slot->ctype = SDMMC_CTYPE_4BIT;
1422 case MMC_BUS_WIDTH_8:
1423 slot->ctype = SDMMC_CTYPE_8BIT;
1426 /* set default 1 bit mode */
1427 slot->ctype = SDMMC_CTYPE_1BIT;
1430 regs = mci_readl(slot->host, UHS_REG);
1433 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
1434 ios->timing == MMC_TIMING_UHS_DDR50 ||
1435 ios->timing == MMC_TIMING_MMC_HS400)
1436 regs |= ((0x1 << slot->id) << 16);
1438 regs &= ~((0x1 << slot->id) << 16);
1440 mci_writel(slot->host, UHS_REG, regs);
1441 slot->host->timing = ios->timing;
1444 * Use mirror of ios->clock to prevent race with mmc
1445 * core ios update when finding the minimum.
1447 slot->clock = ios->clock;
1449 if (drv_data && drv_data->set_ios)
1450 drv_data->set_ios(slot->host, ios);
1452 switch (ios->power_mode) {
1454 if (!IS_ERR(mmc->supply.vmmc)) {
1455 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1458 dev_err(slot->host->dev,
1459 "failed to enable vmmc regulator\n");
1460 /*return, if failed turn on vmmc*/
1464 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1465 regs = mci_readl(slot->host, PWREN);
1466 regs |= (1 << slot->id);
1467 mci_writel(slot->host, PWREN, regs);
1470 if (!slot->host->vqmmc_enabled) {
1471 if (!IS_ERR(mmc->supply.vqmmc)) {
1472 ret = regulator_enable(mmc->supply.vqmmc);
1474 dev_err(slot->host->dev,
1475 "failed to enable vqmmc\n");
1477 slot->host->vqmmc_enabled = true;
1480 /* Keep track so we don't reset again */
1481 slot->host->vqmmc_enabled = true;
1484 /* Reset our state machine after powering on */
1485 dw_mci_ctrl_reset(slot->host,
1486 SDMMC_CTRL_ALL_RESET_FLAGS);
1489 /* Adjust clock / bus width after power is up */
1490 dw_mci_setup_bus(slot, false);
1494 /* Turn clock off before power goes down */
1495 dw_mci_setup_bus(slot, false);
1497 if (!IS_ERR(mmc->supply.vmmc))
1498 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1500 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
1501 regulator_disable(mmc->supply.vqmmc);
1502 slot->host->vqmmc_enabled = false;
1504 regs = mci_readl(slot->host, PWREN);
1505 regs &= ~(1 << slot->id);
1506 mci_writel(slot->host, PWREN, regs);
1512 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1513 slot->host->state = STATE_IDLE;
1516 static int dw_mci_card_busy(struct mmc_host *mmc)
1518 struct dw_mci_slot *slot = mmc_priv(mmc);
1522 * Check the busy bit which is low when DAT[3:0]
1523 * (the data lines) are 0000
1525 status = mci_readl(slot->host, STATUS);
1527 return !!(status & SDMMC_STATUS_BUSY);
1530 static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1532 struct dw_mci_slot *slot = mmc_priv(mmc);
1533 struct dw_mci *host = slot->host;
1534 const struct dw_mci_drv_data *drv_data = host->drv_data;
1536 u32 v18 = SDMMC_UHS_18V << slot->id;
1539 if (drv_data && drv_data->switch_voltage)
1540 return drv_data->switch_voltage(mmc, ios);
1543 * Program the voltage. Note that some instances of dw_mmc may use
1544 * the UHS_REG for this. For other instances (like exynos) the UHS_REG
1545 * does no harm but you need to set the regulator directly. Try both.
1547 uhs = mci_readl(host, UHS_REG);
1548 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1553 if (!IS_ERR(mmc->supply.vqmmc)) {
1554 ret = mmc_regulator_set_vqmmc(mmc, ios);
1556 dev_dbg(&mmc->class_dev,
1557 "Regulator set error %d - %s V\n",
1558 ret, uhs & v18 ? "1.8" : "3.3");
1562 mci_writel(host, UHS_REG, uhs);
1567 static int dw_mci_get_ro(struct mmc_host *mmc)
1570 struct dw_mci_slot *slot = mmc_priv(mmc);
1571 int gpio_ro = mmc_gpio_get_ro(mmc);
1573 /* Use platform get_ro function, else try on board write protect */
1575 read_only = gpio_ro;
1578 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1580 dev_dbg(&mmc->class_dev, "card is %s\n",
1581 read_only ? "read-only" : "read-write");
1586 static void dw_mci_hw_reset(struct mmc_host *mmc)
1588 struct dw_mci_slot *slot = mmc_priv(mmc);
1589 struct dw_mci *host = slot->host;
1592 if (host->use_dma == TRANS_MODE_IDMAC)
1593 dw_mci_idmac_reset(host);
1595 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET |
1596 SDMMC_CTRL_FIFO_RESET))
1600 * According to eMMC spec, card reset procedure:
1601 * tRstW >= 1us: RST_n pulse width
1602 * tRSCA >= 200us: RST_n to Command time
1603 * tRSTH >= 1us: RST_n high period
1605 reset = mci_readl(host, RST_N);
1606 reset &= ~(SDMMC_RST_HWACTIVE << slot->id);
1607 mci_writel(host, RST_N, reset);
1609 reset |= SDMMC_RST_HWACTIVE << slot->id;
1610 mci_writel(host, RST_N, reset);
1611 usleep_range(200, 300);
1614 static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card)
1616 struct dw_mci_slot *slot = mmc_priv(mmc);
1617 struct dw_mci *host = slot->host;
1620 * Low power mode will stop the card clock when idle. According to the
1621 * description of the CLKENA register we should disable low power mode
1622 * for SDIO cards if we need SDIO interrupts to work.
1624 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1625 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1629 clk_en_a_old = mci_readl(host, CLKENA);
1631 if (card->type == MMC_TYPE_SDIO ||
1632 card->type == MMC_TYPE_SD_COMBO) {
1633 set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1634 clk_en_a = clk_en_a_old & ~clken_low_pwr;
1636 clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1637 clk_en_a = clk_en_a_old | clken_low_pwr;
1640 if (clk_en_a != clk_en_a_old) {
1641 mci_writel(host, CLKENA, clk_en_a);
1642 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1643 SDMMC_CMD_PRV_DAT_WAIT, 0);
1648 static void __dw_mci_enable_sdio_irq(struct dw_mci_slot *slot, int enb)
1650 struct dw_mci *host = slot->host;
1651 unsigned long irqflags;
1654 spin_lock_irqsave(&host->irq_lock, irqflags);
1656 /* Enable/disable Slot Specific SDIO interrupt */
1657 int_mask = mci_readl(host, INTMASK);
1659 int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
1661 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
1662 mci_writel(host, INTMASK, int_mask);
1664 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1667 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1669 struct dw_mci_slot *slot = mmc_priv(mmc);
1670 struct dw_mci *host = slot->host;
1672 __dw_mci_enable_sdio_irq(slot, enb);
1674 /* Avoid runtime suspending the device when SDIO IRQ is enabled */
1676 pm_runtime_get_noresume(host->dev);
1678 pm_runtime_put_noidle(host->dev);
1681 static void dw_mci_ack_sdio_irq(struct mmc_host *mmc)
1683 struct dw_mci_slot *slot = mmc_priv(mmc);
1685 __dw_mci_enable_sdio_irq(slot, 1);
1688 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1690 struct dw_mci_slot *slot = mmc_priv(mmc);
1691 struct dw_mci *host = slot->host;
1692 const struct dw_mci_drv_data *drv_data = host->drv_data;
1695 if (drv_data && drv_data->execute_tuning)
1696 err = drv_data->execute_tuning(slot, opcode);
1700 static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc,
1701 struct mmc_ios *ios)
1703 struct dw_mci_slot *slot = mmc_priv(mmc);
1704 struct dw_mci *host = slot->host;
1705 const struct dw_mci_drv_data *drv_data = host->drv_data;
1707 if (drv_data && drv_data->prepare_hs400_tuning)
1708 return drv_data->prepare_hs400_tuning(host, ios);
1713 static bool dw_mci_reset(struct dw_mci *host)
1715 u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
1720 * Resetting generates a block interrupt, hence setting
1721 * the scatter-gather pointer to NULL.
1724 sg_miter_stop(&host->sg_miter);
1729 flags |= SDMMC_CTRL_DMA_RESET;
1731 if (dw_mci_ctrl_reset(host, flags)) {
1733 * In all cases we clear the RAWINTS
1734 * register to clear any interrupts.
1736 mci_writel(host, RINTSTS, 0xFFFFFFFF);
1738 if (!host->use_dma) {
1743 /* Wait for dma_req to be cleared */
1744 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
1746 !(status & SDMMC_STATUS_DMA_REQ),
1747 1, 500 * USEC_PER_MSEC)) {
1749 "%s: Timeout waiting for dma_req to be cleared\n",
1754 /* when using DMA next we reset the fifo again */
1755 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
1758 /* if the controller reset bit did clear, then set clock regs */
1759 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
1761 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
1767 if (host->use_dma == TRANS_MODE_IDMAC)
1768 /* It is also required that we reinit idmac */
1769 dw_mci_idmac_init(host);
1774 /* After a CTRL reset we need to have CIU set clock registers */
1775 mci_send_cmd(host->slot, SDMMC_CMD_UPD_CLK, 0);
1780 static const struct mmc_host_ops dw_mci_ops = {
1781 .request = dw_mci_request,
1782 .pre_req = dw_mci_pre_req,
1783 .post_req = dw_mci_post_req,
1784 .set_ios = dw_mci_set_ios,
1785 .get_ro = dw_mci_get_ro,
1786 .get_cd = dw_mci_get_cd,
1787 .hw_reset = dw_mci_hw_reset,
1788 .enable_sdio_irq = dw_mci_enable_sdio_irq,
1789 .ack_sdio_irq = dw_mci_ack_sdio_irq,
1790 .execute_tuning = dw_mci_execute_tuning,
1791 .card_busy = dw_mci_card_busy,
1792 .start_signal_voltage_switch = dw_mci_switch_voltage,
1793 .init_card = dw_mci_init_card,
1794 .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning,
1797 #ifdef CONFIG_FAULT_INJECTION
1798 static enum hrtimer_restart dw_mci_fault_timer(struct hrtimer *t)
1800 struct dw_mci *host = container_of(t, struct dw_mci, fault_timer);
1801 unsigned long flags;
1803 spin_lock_irqsave(&host->irq_lock, flags);
1805 if (!host->data_status)
1806 host->data_status = SDMMC_INT_DCRC;
1807 set_bit(EVENT_DATA_ERROR, &host->pending_events);
1808 tasklet_schedule(&host->tasklet);
1810 spin_unlock_irqrestore(&host->irq_lock, flags);
1812 return HRTIMER_NORESTART;
1815 static void dw_mci_start_fault_timer(struct dw_mci *host)
1817 struct mmc_data *data = host->data;
1819 if (!data || data->blocks <= 1)
1822 if (!should_fail(&host->fail_data_crc, 1))
1826 * Try to inject the error at random points during the data transfer.
1828 hrtimer_start(&host->fault_timer,
1829 ms_to_ktime(prandom_u32() % 25),
1833 static void dw_mci_stop_fault_timer(struct dw_mci *host)
1835 hrtimer_cancel(&host->fault_timer);
1838 static void dw_mci_init_fault(struct dw_mci *host)
1840 host->fail_data_crc = (struct fault_attr) FAULT_ATTR_INITIALIZER;
1842 hrtimer_init(&host->fault_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1843 host->fault_timer.function = dw_mci_fault_timer;
1846 static void dw_mci_init_fault(struct dw_mci *host)
1850 static void dw_mci_start_fault_timer(struct dw_mci *host)
1854 static void dw_mci_stop_fault_timer(struct dw_mci *host)
1859 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1860 __releases(&host->lock)
1861 __acquires(&host->lock)
1863 struct dw_mci_slot *slot;
1864 struct mmc_host *prev_mmc = host->slot->mmc;
1866 WARN_ON(host->cmd || host->data);
1868 host->slot->mrq = NULL;
1870 if (!list_empty(&host->queue)) {
1871 slot = list_entry(host->queue.next,
1872 struct dw_mci_slot, queue_node);
1873 list_del(&slot->queue_node);
1874 dev_vdbg(host->dev, "list not empty: %s is next\n",
1875 mmc_hostname(slot->mmc));
1876 host->state = STATE_SENDING_CMD;
1877 dw_mci_start_request(host, slot);
1879 dev_vdbg(host->dev, "list empty\n");
1881 if (host->state == STATE_SENDING_CMD11)
1882 host->state = STATE_WAITING_CMD11_DONE;
1884 host->state = STATE_IDLE;
1887 spin_unlock(&host->lock);
1888 mmc_request_done(prev_mmc, mrq);
1889 spin_lock(&host->lock);
1892 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
1894 u32 status = host->cmd_status;
1896 host->cmd_status = 0;
1898 /* Read the response from the card (up to 16 bytes) */
1899 if (cmd->flags & MMC_RSP_PRESENT) {
1900 if (cmd->flags & MMC_RSP_136) {
1901 cmd->resp[3] = mci_readl(host, RESP0);
1902 cmd->resp[2] = mci_readl(host, RESP1);
1903 cmd->resp[1] = mci_readl(host, RESP2);
1904 cmd->resp[0] = mci_readl(host, RESP3);
1906 cmd->resp[0] = mci_readl(host, RESP0);
1913 if (status & SDMMC_INT_RTO)
1914 cmd->error = -ETIMEDOUT;
1915 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1916 cmd->error = -EILSEQ;
1917 else if (status & SDMMC_INT_RESP_ERR)
1925 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1927 u32 status = host->data_status;
1929 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1930 if (status & SDMMC_INT_DRTO) {
1931 data->error = -ETIMEDOUT;
1932 } else if (status & SDMMC_INT_DCRC) {
1933 data->error = -EILSEQ;
1934 } else if (status & SDMMC_INT_EBE) {
1935 if (host->dir_status ==
1936 DW_MCI_SEND_STATUS) {
1938 * No data CRC status was returned.
1939 * The number of bytes transferred
1940 * will be exaggerated in PIO mode.
1942 data->bytes_xfered = 0;
1943 data->error = -ETIMEDOUT;
1944 } else if (host->dir_status ==
1945 DW_MCI_RECV_STATUS) {
1946 data->error = -EILSEQ;
1949 /* SDMMC_INT_SBE is included */
1950 data->error = -EILSEQ;
1953 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
1956 * After an error, there may be data lingering
1961 data->bytes_xfered = data->blocks * data->blksz;
1968 static void dw_mci_set_drto(struct dw_mci *host)
1970 unsigned int drto_clks;
1971 unsigned int drto_div;
1972 unsigned int drto_ms;
1973 unsigned long irqflags;
1975 drto_clks = mci_readl(host, TMOUT) >> 8;
1976 drto_div = (mci_readl(host, CLKDIV) & 0xff) * 2;
1980 drto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * drto_clks * drto_div,
1983 /* add a bit spare time */
1986 spin_lock_irqsave(&host->irq_lock, irqflags);
1987 if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events))
1988 mod_timer(&host->dto_timer,
1989 jiffies + msecs_to_jiffies(drto_ms));
1990 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1993 static bool dw_mci_clear_pending_cmd_complete(struct dw_mci *host)
1995 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1999 * Really be certain that the timer has stopped. This is a bit of
2000 * paranoia and could only really happen if we had really bad
2001 * interrupt latency and the interrupt routine and timeout were
2002 * running concurrently so that the del_timer() in the interrupt
2003 * handler couldn't run.
2005 WARN_ON(del_timer_sync(&host->cto_timer));
2006 clear_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2011 static bool dw_mci_clear_pending_data_complete(struct dw_mci *host)
2013 if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events))
2016 /* Extra paranoia just like dw_mci_clear_pending_cmd_complete() */
2017 WARN_ON(del_timer_sync(&host->dto_timer));
2018 clear_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2023 static void dw_mci_tasklet_func(struct tasklet_struct *t)
2025 struct dw_mci *host = from_tasklet(host, t, tasklet);
2026 struct mmc_data *data;
2027 struct mmc_command *cmd;
2028 struct mmc_request *mrq;
2029 enum dw_mci_state state;
2030 enum dw_mci_state prev_state;
2033 spin_lock(&host->lock);
2035 state = host->state;
2044 case STATE_WAITING_CMD11_DONE:
2047 case STATE_SENDING_CMD11:
2048 case STATE_SENDING_CMD:
2049 if (!dw_mci_clear_pending_cmd_complete(host))
2054 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
2055 err = dw_mci_command_complete(host, cmd);
2056 if (cmd == mrq->sbc && !err) {
2057 __dw_mci_start_request(host, host->slot,
2062 if (cmd->data && err) {
2064 * During UHS tuning sequence, sending the stop
2065 * command after the response CRC error would
2066 * throw the system into a confused state
2067 * causing all future tuning phases to report
2070 * In such case controller will move into a data
2071 * transfer state after a response error or
2072 * response CRC error. Let's let that finish
2073 * before trying to send a stop, so we'll go to
2074 * STATE_SENDING_DATA.
2076 * Although letting the data transfer take place
2077 * will waste a bit of time (we already know
2078 * the command was bad), it can't cause any
2079 * errors since it's possible it would have
2080 * taken place anyway if this tasklet got
2081 * delayed. Allowing the transfer to take place
2082 * avoids races and keeps things simple.
2084 if (err != -ETIMEDOUT) {
2085 state = STATE_SENDING_DATA;
2089 send_stop_abort(host, data);
2090 dw_mci_stop_dma(host);
2091 state = STATE_SENDING_STOP;
2095 if (!cmd->data || err) {
2096 dw_mci_request_end(host, mrq);
2100 prev_state = state = STATE_SENDING_DATA;
2103 case STATE_SENDING_DATA:
2105 * We could get a data error and never a transfer
2106 * complete so we'd better check for it here.
2108 * Note that we don't really care if we also got a
2109 * transfer complete; stopping the DMA and sending an
2112 if (test_and_clear_bit(EVENT_DATA_ERROR,
2113 &host->pending_events)) {
2114 if (!(host->data_status & (SDMMC_INT_DRTO |
2116 send_stop_abort(host, data);
2117 dw_mci_stop_dma(host);
2118 state = STATE_DATA_ERROR;
2122 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2123 &host->pending_events)) {
2125 * If all data-related interrupts don't come
2126 * within the given time in reading data state.
2128 if (host->dir_status == DW_MCI_RECV_STATUS)
2129 dw_mci_set_drto(host);
2133 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
2136 * Handle an EVENT_DATA_ERROR that might have shown up
2137 * before the transfer completed. This might not have
2138 * been caught by the check above because the interrupt
2139 * could have gone off between the previous check and
2140 * the check for transfer complete.
2142 * Technically this ought not be needed assuming we
2143 * get a DATA_COMPLETE eventually (we'll notice the
2144 * error and end the request), but it shouldn't hurt.
2146 * This has the advantage of sending the stop command.
2148 if (test_and_clear_bit(EVENT_DATA_ERROR,
2149 &host->pending_events)) {
2150 if (!(host->data_status & (SDMMC_INT_DRTO |
2152 send_stop_abort(host, data);
2153 dw_mci_stop_dma(host);
2154 state = STATE_DATA_ERROR;
2157 prev_state = state = STATE_DATA_BUSY;
2161 case STATE_DATA_BUSY:
2162 if (!dw_mci_clear_pending_data_complete(host)) {
2164 * If data error interrupt comes but data over
2165 * interrupt doesn't come within the given time.
2166 * in reading data state.
2168 if (host->dir_status == DW_MCI_RECV_STATUS)
2169 dw_mci_set_drto(host);
2173 dw_mci_stop_fault_timer(host);
2175 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
2176 err = dw_mci_data_complete(host, data);
2179 if (!data->stop || mrq->sbc) {
2180 if (mrq->sbc && data->stop)
2181 data->stop->error = 0;
2182 dw_mci_request_end(host, mrq);
2186 /* stop command for open-ended transfer*/
2188 send_stop_abort(host, data);
2191 * If we don't have a command complete now we'll
2192 * never get one since we just reset everything;
2193 * better end the request.
2195 * If we do have a command complete we'll fall
2196 * through to the SENDING_STOP command and
2197 * everything will be peachy keen.
2199 if (!test_bit(EVENT_CMD_COMPLETE,
2200 &host->pending_events)) {
2202 dw_mci_request_end(host, mrq);
2208 * If err has non-zero,
2209 * stop-abort command has been already issued.
2211 prev_state = state = STATE_SENDING_STOP;
2215 case STATE_SENDING_STOP:
2216 if (!dw_mci_clear_pending_cmd_complete(host))
2219 /* CMD error in data command */
2220 if (mrq->cmd->error && mrq->data)
2223 dw_mci_stop_fault_timer(host);
2227 if (!mrq->sbc && mrq->stop)
2228 dw_mci_command_complete(host, mrq->stop);
2230 host->cmd_status = 0;
2232 dw_mci_request_end(host, mrq);
2235 case STATE_DATA_ERROR:
2236 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2237 &host->pending_events))
2240 state = STATE_DATA_BUSY;
2243 } while (state != prev_state);
2245 host->state = state;
2247 spin_unlock(&host->lock);
2251 /* push final bytes to part_buf, only use during push */
2252 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
2254 memcpy((void *)&host->part_buf, buf, cnt);
2255 host->part_buf_count = cnt;
2258 /* append bytes to part_buf, only use during push */
2259 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
2261 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
2262 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
2263 host->part_buf_count += cnt;
2267 /* pull first bytes from part_buf, only use during pull */
2268 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
2270 cnt = min_t(int, cnt, host->part_buf_count);
2272 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
2274 host->part_buf_count -= cnt;
2275 host->part_buf_start += cnt;
2280 /* pull final bytes from the part_buf, assuming it's just been filled */
2281 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
2283 memcpy(buf, &host->part_buf, cnt);
2284 host->part_buf_start = cnt;
2285 host->part_buf_count = (1 << host->data_shift) - cnt;
2288 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
2290 struct mmc_data *data = host->data;
2293 /* try and push anything in the part_buf */
2294 if (unlikely(host->part_buf_count)) {
2295 int len = dw_mci_push_part_bytes(host, buf, cnt);
2299 if (host->part_buf_count == 2) {
2300 mci_fifo_writew(host->fifo_reg, host->part_buf16);
2301 host->part_buf_count = 0;
2304 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2305 if (unlikely((unsigned long)buf & 0x1)) {
2307 u16 aligned_buf[64];
2308 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2309 int items = len >> 1;
2311 /* memcpy from input buffer into aligned buffer */
2312 memcpy(aligned_buf, buf, len);
2315 /* push data from aligned buffer into fifo */
2316 for (i = 0; i < items; ++i)
2317 mci_fifo_writew(host->fifo_reg, aligned_buf[i]);
2324 for (; cnt >= 2; cnt -= 2)
2325 mci_fifo_writew(host->fifo_reg, *pdata++);
2328 /* put anything remaining in the part_buf */
2330 dw_mci_set_part_bytes(host, buf, cnt);
2331 /* Push data if we have reached the expected data length */
2332 if ((data->bytes_xfered + init_cnt) ==
2333 (data->blksz * data->blocks))
2334 mci_fifo_writew(host->fifo_reg, host->part_buf16);
2338 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2340 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2341 if (unlikely((unsigned long)buf & 0x1)) {
2343 /* pull data from fifo into aligned buffer */
2344 u16 aligned_buf[64];
2345 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2346 int items = len >> 1;
2349 for (i = 0; i < items; ++i)
2350 aligned_buf[i] = mci_fifo_readw(host->fifo_reg);
2351 /* memcpy from aligned buffer into output buffer */
2352 memcpy(buf, aligned_buf, len);
2361 for (; cnt >= 2; cnt -= 2)
2362 *pdata++ = mci_fifo_readw(host->fifo_reg);
2366 host->part_buf16 = mci_fifo_readw(host->fifo_reg);
2367 dw_mci_pull_final_bytes(host, buf, cnt);
2371 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2373 struct mmc_data *data = host->data;
2376 /* try and push anything in the part_buf */
2377 if (unlikely(host->part_buf_count)) {
2378 int len = dw_mci_push_part_bytes(host, buf, cnt);
2382 if (host->part_buf_count == 4) {
2383 mci_fifo_writel(host->fifo_reg, host->part_buf32);
2384 host->part_buf_count = 0;
2387 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2388 if (unlikely((unsigned long)buf & 0x3)) {
2390 u32 aligned_buf[32];
2391 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2392 int items = len >> 2;
2394 /* memcpy from input buffer into aligned buffer */
2395 memcpy(aligned_buf, buf, len);
2398 /* push data from aligned buffer into fifo */
2399 for (i = 0; i < items; ++i)
2400 mci_fifo_writel(host->fifo_reg, aligned_buf[i]);
2407 for (; cnt >= 4; cnt -= 4)
2408 mci_fifo_writel(host->fifo_reg, *pdata++);
2411 /* put anything remaining in the part_buf */
2413 dw_mci_set_part_bytes(host, buf, cnt);
2414 /* Push data if we have reached the expected data length */
2415 if ((data->bytes_xfered + init_cnt) ==
2416 (data->blksz * data->blocks))
2417 mci_fifo_writel(host->fifo_reg, host->part_buf32);
2421 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2423 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2424 if (unlikely((unsigned long)buf & 0x3)) {
2426 /* pull data from fifo into aligned buffer */
2427 u32 aligned_buf[32];
2428 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2429 int items = len >> 2;
2432 for (i = 0; i < items; ++i)
2433 aligned_buf[i] = mci_fifo_readl(host->fifo_reg);
2434 /* memcpy from aligned buffer into output buffer */
2435 memcpy(buf, aligned_buf, len);
2444 for (; cnt >= 4; cnt -= 4)
2445 *pdata++ = mci_fifo_readl(host->fifo_reg);
2449 host->part_buf32 = mci_fifo_readl(host->fifo_reg);
2450 dw_mci_pull_final_bytes(host, buf, cnt);
2454 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2456 struct mmc_data *data = host->data;
2459 /* try and push anything in the part_buf */
2460 if (unlikely(host->part_buf_count)) {
2461 int len = dw_mci_push_part_bytes(host, buf, cnt);
2466 if (host->part_buf_count == 8) {
2467 mci_fifo_writeq(host->fifo_reg, host->part_buf);
2468 host->part_buf_count = 0;
2471 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2472 if (unlikely((unsigned long)buf & 0x7)) {
2474 u64 aligned_buf[16];
2475 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2476 int items = len >> 3;
2478 /* memcpy from input buffer into aligned buffer */
2479 memcpy(aligned_buf, buf, len);
2482 /* push data from aligned buffer into fifo */
2483 for (i = 0; i < items; ++i)
2484 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]);
2491 for (; cnt >= 8; cnt -= 8)
2492 mci_fifo_writeq(host->fifo_reg, *pdata++);
2495 /* put anything remaining in the part_buf */
2497 dw_mci_set_part_bytes(host, buf, cnt);
2498 /* Push data if we have reached the expected data length */
2499 if ((data->bytes_xfered + init_cnt) ==
2500 (data->blksz * data->blocks))
2501 mci_fifo_writeq(host->fifo_reg, host->part_buf);
2505 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2507 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2508 if (unlikely((unsigned long)buf & 0x7)) {
2510 /* pull data from fifo into aligned buffer */
2511 u64 aligned_buf[16];
2512 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2513 int items = len >> 3;
2516 for (i = 0; i < items; ++i)
2517 aligned_buf[i] = mci_fifo_readq(host->fifo_reg);
2519 /* memcpy from aligned buffer into output buffer */
2520 memcpy(buf, aligned_buf, len);
2529 for (; cnt >= 8; cnt -= 8)
2530 *pdata++ = mci_fifo_readq(host->fifo_reg);
2534 host->part_buf = mci_fifo_readq(host->fifo_reg);
2535 dw_mci_pull_final_bytes(host, buf, cnt);
2539 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2543 /* get remaining partial bytes */
2544 len = dw_mci_pull_part_bytes(host, buf, cnt);
2545 if (unlikely(len == cnt))
2550 /* get the rest of the data */
2551 host->pull_data(host, buf, cnt);
2554 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
2556 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2558 unsigned int offset;
2559 struct mmc_data *data = host->data;
2560 int shift = host->data_shift;
2563 unsigned int remain, fcnt;
2566 if (!sg_miter_next(sg_miter))
2569 host->sg = sg_miter->piter.sg;
2570 buf = sg_miter->addr;
2571 remain = sg_miter->length;
2575 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2576 << shift) + host->part_buf_count;
2577 len = min(remain, fcnt);
2580 dw_mci_pull_data(host, (void *)(buf + offset), len);
2581 data->bytes_xfered += len;
2586 sg_miter->consumed = offset;
2587 status = mci_readl(host, MINTSTS);
2588 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2589 /* if the RXDR is ready read again */
2590 } while ((status & SDMMC_INT_RXDR) ||
2591 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
2594 if (!sg_miter_next(sg_miter))
2596 sg_miter->consumed = 0;
2598 sg_miter_stop(sg_miter);
2602 sg_miter_stop(sg_miter);
2604 smp_wmb(); /* drain writebuffer */
2605 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2608 static void dw_mci_write_data_pio(struct dw_mci *host)
2610 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2612 unsigned int offset;
2613 struct mmc_data *data = host->data;
2614 int shift = host->data_shift;
2617 unsigned int fifo_depth = host->fifo_depth;
2618 unsigned int remain, fcnt;
2621 if (!sg_miter_next(sg_miter))
2624 host->sg = sg_miter->piter.sg;
2625 buf = sg_miter->addr;
2626 remain = sg_miter->length;
2630 fcnt = ((fifo_depth -
2631 SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2632 << shift) - host->part_buf_count;
2633 len = min(remain, fcnt);
2636 host->push_data(host, (void *)(buf + offset), len);
2637 data->bytes_xfered += len;
2642 sg_miter->consumed = offset;
2643 status = mci_readl(host, MINTSTS);
2644 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2645 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
2648 if (!sg_miter_next(sg_miter))
2650 sg_miter->consumed = 0;
2652 sg_miter_stop(sg_miter);
2656 sg_miter_stop(sg_miter);
2658 smp_wmb(); /* drain writebuffer */
2659 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2662 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2664 del_timer(&host->cto_timer);
2666 if (!host->cmd_status)
2667 host->cmd_status = status;
2669 smp_wmb(); /* drain writebuffer */
2671 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2672 tasklet_schedule(&host->tasklet);
2674 dw_mci_start_fault_timer(host);
2677 static void dw_mci_handle_cd(struct dw_mci *host)
2679 struct dw_mci_slot *slot = host->slot;
2681 mmc_detect_change(slot->mmc,
2682 msecs_to_jiffies(host->pdata->detect_delay_ms));
2685 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2687 struct dw_mci *host = dev_id;
2689 struct dw_mci_slot *slot = host->slot;
2691 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2694 /* Check volt switch first, since it can look like an error */
2695 if ((host->state == STATE_SENDING_CMD11) &&
2696 (pending & SDMMC_INT_VOLT_SWITCH)) {
2697 mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
2698 pending &= ~SDMMC_INT_VOLT_SWITCH;
2701 * Hold the lock; we know cmd11_timer can't be kicked
2702 * off after the lock is released, so safe to delete.
2704 spin_lock(&host->irq_lock);
2705 dw_mci_cmd_interrupt(host, pending);
2706 spin_unlock(&host->irq_lock);
2708 del_timer(&host->cmd11_timer);
2711 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2712 spin_lock(&host->irq_lock);
2714 del_timer(&host->cto_timer);
2715 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
2716 host->cmd_status = pending;
2717 smp_wmb(); /* drain writebuffer */
2718 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2720 spin_unlock(&host->irq_lock);
2723 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2724 /* if there is an error report DATA_ERROR */
2725 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2726 host->data_status = pending;
2727 smp_wmb(); /* drain writebuffer */
2728 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2729 tasklet_schedule(&host->tasklet);
2732 if (pending & SDMMC_INT_DATA_OVER) {
2733 spin_lock(&host->irq_lock);
2735 del_timer(&host->dto_timer);
2737 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2738 if (!host->data_status)
2739 host->data_status = pending;
2740 smp_wmb(); /* drain writebuffer */
2741 if (host->dir_status == DW_MCI_RECV_STATUS) {
2742 if (host->sg != NULL)
2743 dw_mci_read_data_pio(host, true);
2745 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2746 tasklet_schedule(&host->tasklet);
2748 spin_unlock(&host->irq_lock);
2751 if (pending & SDMMC_INT_RXDR) {
2752 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2753 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2754 dw_mci_read_data_pio(host, false);
2757 if (pending & SDMMC_INT_TXDR) {
2758 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2759 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2760 dw_mci_write_data_pio(host);
2763 if (pending & SDMMC_INT_CMD_DONE) {
2764 spin_lock(&host->irq_lock);
2766 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2767 dw_mci_cmd_interrupt(host, pending);
2769 spin_unlock(&host->irq_lock);
2772 if (pending & SDMMC_INT_CD) {
2773 mci_writel(host, RINTSTS, SDMMC_INT_CD);
2774 dw_mci_handle_cd(host);
2777 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
2778 mci_writel(host, RINTSTS,
2779 SDMMC_INT_SDIO(slot->sdio_id));
2780 __dw_mci_enable_sdio_irq(slot, 0);
2781 sdio_signal_irq(slot->mmc);
2786 if (host->use_dma != TRANS_MODE_IDMAC)
2789 /* Handle IDMA interrupts */
2790 if (host->dma_64bit_address == 1) {
2791 pending = mci_readl(host, IDSTS64);
2792 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2793 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2794 SDMMC_IDMAC_INT_RI);
2795 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
2796 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2797 host->dma_ops->complete((void *)host);
2800 pending = mci_readl(host, IDSTS);
2801 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2802 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2803 SDMMC_IDMAC_INT_RI);
2804 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
2805 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2806 host->dma_ops->complete((void *)host);
2813 static int dw_mci_init_slot_caps(struct dw_mci_slot *slot)
2815 struct dw_mci *host = slot->host;
2816 const struct dw_mci_drv_data *drv_data = host->drv_data;
2817 struct mmc_host *mmc = slot->mmc;
2820 if (host->pdata->caps)
2821 mmc->caps = host->pdata->caps;
2823 if (host->pdata->pm_caps)
2824 mmc->pm_caps = host->pdata->pm_caps;
2826 if (host->dev->of_node) {
2827 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2831 ctrl_id = to_platform_device(host->dev)->id;
2834 if (drv_data && drv_data->caps) {
2835 if (ctrl_id >= drv_data->num_caps) {
2836 dev_err(host->dev, "invalid controller id %d\n",
2840 mmc->caps |= drv_data->caps[ctrl_id];
2843 if (host->pdata->caps2)
2844 mmc->caps2 = host->pdata->caps2;
2846 mmc->f_min = DW_MCI_FREQ_MIN;
2848 mmc->f_max = DW_MCI_FREQ_MAX;
2850 /* Process SDIO IRQs through the sdio_irq_work. */
2851 if (mmc->caps & MMC_CAP_SDIO_IRQ)
2852 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
2857 static int dw_mci_init_slot(struct dw_mci *host)
2859 struct mmc_host *mmc;
2860 struct dw_mci_slot *slot;
2863 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
2867 slot = mmc_priv(mmc);
2869 slot->sdio_id = host->sdio_id0 + slot->id;
2874 mmc->ops = &dw_mci_ops;
2876 /*if there are external regulators, get them*/
2877 ret = mmc_regulator_get_supply(mmc);
2879 goto err_host_allocated;
2881 if (!mmc->ocr_avail)
2882 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2884 ret = mmc_of_parse(mmc);
2886 goto err_host_allocated;
2888 ret = dw_mci_init_slot_caps(slot);
2890 goto err_host_allocated;
2892 /* Useful defaults if platform data is unset. */
2893 if (host->use_dma == TRANS_MODE_IDMAC) {
2894 mmc->max_segs = host->ring_size;
2895 mmc->max_blk_size = 65535;
2896 mmc->max_seg_size = 0x1000;
2897 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2898 mmc->max_blk_count = mmc->max_req_size / 512;
2899 } else if (host->use_dma == TRANS_MODE_EDMAC) {
2901 mmc->max_blk_size = 65535;
2902 mmc->max_blk_count = 65535;
2904 mmc->max_blk_size * mmc->max_blk_count;
2905 mmc->max_seg_size = mmc->max_req_size;
2907 /* TRANS_MODE_PIO */
2909 mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */
2910 mmc->max_blk_count = 512;
2911 mmc->max_req_size = mmc->max_blk_size *
2913 mmc->max_seg_size = mmc->max_req_size;
2918 ret = mmc_add_host(mmc);
2920 goto err_host_allocated;
2922 #if defined(CONFIG_DEBUG_FS)
2923 dw_mci_init_debugfs(slot);
2933 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot)
2935 /* Debugfs stuff is cleaned up by mmc core */
2936 mmc_remove_host(slot->mmc);
2937 slot->host->slot = NULL;
2938 mmc_free_host(slot->mmc);
2941 static void dw_mci_init_dma(struct dw_mci *host)
2944 struct device *dev = host->dev;
2947 * Check tansfer mode from HCON[17:16]
2948 * Clear the ambiguous description of dw_mmc databook:
2949 * 2b'00: No DMA Interface -> Actually means using Internal DMA block
2950 * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block
2951 * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block
2952 * 2b'11: Non DW DMA Interface -> pio only
2953 * Compared to DesignWare DMA Interface, Generic DMA Interface has a
2954 * simpler request/acknowledge handshake mechanism and both of them
2955 * are regarded as external dma master for dw_mmc.
2957 host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
2958 if (host->use_dma == DMA_INTERFACE_IDMA) {
2959 host->use_dma = TRANS_MODE_IDMAC;
2960 } else if (host->use_dma == DMA_INTERFACE_DWDMA ||
2961 host->use_dma == DMA_INTERFACE_GDMA) {
2962 host->use_dma = TRANS_MODE_EDMAC;
2967 /* Determine which DMA interface to use */
2968 if (host->use_dma == TRANS_MODE_IDMAC) {
2970 * Check ADDR_CONFIG bit in HCON to find
2971 * IDMAC address bus width
2973 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
2975 if (addr_config == 1) {
2976 /* host supports IDMAC in 64-bit address mode */
2977 host->dma_64bit_address = 1;
2979 "IDMAC supports 64-bit address mode.\n");
2980 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
2981 dma_set_coherent_mask(host->dev,
2984 /* host supports IDMAC in 32-bit address mode */
2985 host->dma_64bit_address = 0;
2987 "IDMAC supports 32-bit address mode.\n");
2990 /* Alloc memory for sg translation */
2991 host->sg_cpu = dmam_alloc_coherent(host->dev,
2993 &host->sg_dma, GFP_KERNEL);
2994 if (!host->sg_cpu) {
2996 "%s: could not alloc DMA memory\n",
3001 host->dma_ops = &dw_mci_idmac_ops;
3002 dev_info(host->dev, "Using internal DMA controller.\n");
3004 /* TRANS_MODE_EDMAC: check dma bindings again */
3005 if ((device_property_read_string_array(dev, "dma-names",
3007 !device_property_present(dev, "dmas")) {
3010 host->dma_ops = &dw_mci_edmac_ops;
3011 dev_info(host->dev, "Using external DMA controller.\n");
3014 if (host->dma_ops->init && host->dma_ops->start &&
3015 host->dma_ops->stop && host->dma_ops->cleanup) {
3016 if (host->dma_ops->init(host)) {
3017 dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n",
3022 dev_err(host->dev, "DMA initialization not found.\n");
3029 dev_info(host->dev, "Using PIO mode.\n");
3030 host->use_dma = TRANS_MODE_PIO;
3033 static void dw_mci_cmd11_timer(struct timer_list *t)
3035 struct dw_mci *host = from_timer(host, t, cmd11_timer);
3037 if (host->state != STATE_SENDING_CMD11) {
3038 dev_warn(host->dev, "Unexpected CMD11 timeout\n");
3042 host->cmd_status = SDMMC_INT_RTO;
3043 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
3044 tasklet_schedule(&host->tasklet);
3047 static void dw_mci_cto_timer(struct timer_list *t)
3049 struct dw_mci *host = from_timer(host, t, cto_timer);
3050 unsigned long irqflags;
3053 spin_lock_irqsave(&host->irq_lock, irqflags);
3056 * If somehow we have very bad interrupt latency it's remotely possible
3057 * that the timer could fire while the interrupt is still pending or
3058 * while the interrupt is midway through running. Let's be paranoid
3059 * and detect those two cases. Note that this is paranoia is somewhat
3060 * justified because in this function we don't actually cancel the
3061 * pending command in the controller--we just assume it will never come.
3063 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
3064 if (pending & (DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_CMD_DONE)) {
3065 /* The interrupt should fire; no need to act but we can warn */
3066 dev_warn(host->dev, "Unexpected interrupt latency\n");
3069 if (test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) {
3070 /* Presumably interrupt handler couldn't delete the timer */
3071 dev_warn(host->dev, "CTO timeout when already completed\n");
3076 * Continued paranoia to make sure we're in the state we expect.
3077 * This paranoia isn't really justified but it seems good to be safe.
3079 switch (host->state) {
3080 case STATE_SENDING_CMD11:
3081 case STATE_SENDING_CMD:
3082 case STATE_SENDING_STOP:
3084 * If CMD_DONE interrupt does NOT come in sending command
3085 * state, we should notify the driver to terminate current
3086 * transfer and report a command timeout to the core.
3088 host->cmd_status = SDMMC_INT_RTO;
3089 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
3090 tasklet_schedule(&host->tasklet);
3093 dev_warn(host->dev, "Unexpected command timeout, state %d\n",
3099 spin_unlock_irqrestore(&host->irq_lock, irqflags);
3102 static void dw_mci_dto_timer(struct timer_list *t)
3104 struct dw_mci *host = from_timer(host, t, dto_timer);
3105 unsigned long irqflags;
3108 spin_lock_irqsave(&host->irq_lock, irqflags);
3111 * The DTO timer is much longer than the CTO timer, so it's even less
3112 * likely that we'll these cases, but it pays to be paranoid.
3114 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
3115 if (pending & SDMMC_INT_DATA_OVER) {
3116 /* The interrupt should fire; no need to act but we can warn */
3117 dev_warn(host->dev, "Unexpected data interrupt latency\n");
3120 if (test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) {
3121 /* Presumably interrupt handler couldn't delete the timer */
3122 dev_warn(host->dev, "DTO timeout when already completed\n");
3127 * Continued paranoia to make sure we're in the state we expect.
3128 * This paranoia isn't really justified but it seems good to be safe.
3130 switch (host->state) {
3131 case STATE_SENDING_DATA:
3132 case STATE_DATA_BUSY:
3134 * If DTO interrupt does NOT come in sending data state,
3135 * we should notify the driver to terminate current transfer
3136 * and report a data timeout to the core.
3138 host->data_status = SDMMC_INT_DRTO;
3139 set_bit(EVENT_DATA_ERROR, &host->pending_events);
3140 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
3141 tasklet_schedule(&host->tasklet);
3144 dev_warn(host->dev, "Unexpected data timeout, state %d\n",
3150 spin_unlock_irqrestore(&host->irq_lock, irqflags);
3154 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3156 struct dw_mci_board *pdata;
3157 struct device *dev = host->dev;
3158 const struct dw_mci_drv_data *drv_data = host->drv_data;
3160 u32 clock_frequency;
3162 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3164 return ERR_PTR(-ENOMEM);
3166 /* find reset controller when exist */
3167 pdata->rstc = devm_reset_control_get_optional_exclusive(dev, "reset");
3168 if (IS_ERR(pdata->rstc))
3169 return ERR_CAST(pdata->rstc);
3171 if (device_property_read_u32(dev, "fifo-depth", &pdata->fifo_depth))
3173 "fifo-depth property not found, using value of FIFOTH register as default\n");
3175 device_property_read_u32(dev, "card-detect-delay",
3176 &pdata->detect_delay_ms);
3178 device_property_read_u32(dev, "data-addr", &host->data_addr_override);
3180 if (device_property_present(dev, "fifo-watermark-aligned"))
3181 host->wm_aligned = true;
3183 if (!device_property_read_u32(dev, "clock-frequency", &clock_frequency))
3184 pdata->bus_hz = clock_frequency;
3186 if (drv_data && drv_data->parse_dt) {
3187 ret = drv_data->parse_dt(host);
3189 return ERR_PTR(ret);
3195 #else /* CONFIG_OF */
3196 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3198 return ERR_PTR(-EINVAL);
3200 #endif /* CONFIG_OF */
3202 static void dw_mci_enable_cd(struct dw_mci *host)
3204 unsigned long irqflags;
3208 * No need for CD if all slots have a non-error GPIO
3209 * as well as broken card detection is found.
3211 if (host->slot->mmc->caps & MMC_CAP_NEEDS_POLL)
3214 if (mmc_gpio_get_cd(host->slot->mmc) < 0) {
3215 spin_lock_irqsave(&host->irq_lock, irqflags);
3216 temp = mci_readl(host, INTMASK);
3217 temp |= SDMMC_INT_CD;
3218 mci_writel(host, INTMASK, temp);
3219 spin_unlock_irqrestore(&host->irq_lock, irqflags);
3223 int dw_mci_probe(struct dw_mci *host)
3225 const struct dw_mci_drv_data *drv_data = host->drv_data;
3226 int width, i, ret = 0;
3230 host->pdata = dw_mci_parse_dt(host);
3231 if (IS_ERR(host->pdata))
3232 return dev_err_probe(host->dev, PTR_ERR(host->pdata),
3233 "platform data not available\n");
3236 host->biu_clk = devm_clk_get(host->dev, "biu");
3237 if (IS_ERR(host->biu_clk)) {
3238 dev_dbg(host->dev, "biu clock not available\n");
3240 ret = clk_prepare_enable(host->biu_clk);
3242 dev_err(host->dev, "failed to enable biu clock\n");
3247 host->ciu_clk = devm_clk_get(host->dev, "ciu");
3248 if (IS_ERR(host->ciu_clk)) {
3249 dev_dbg(host->dev, "ciu clock not available\n");
3250 host->bus_hz = host->pdata->bus_hz;
3252 ret = clk_prepare_enable(host->ciu_clk);
3254 dev_err(host->dev, "failed to enable ciu clock\n");
3258 if (host->pdata->bus_hz) {
3259 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
3262 "Unable to set bus rate to %uHz\n",
3263 host->pdata->bus_hz);
3265 host->bus_hz = clk_get_rate(host->ciu_clk);
3268 if (!host->bus_hz) {
3270 "Platform data must supply bus speed\n");
3275 if (host->pdata->rstc) {
3276 reset_control_assert(host->pdata->rstc);
3277 usleep_range(10, 50);
3278 reset_control_deassert(host->pdata->rstc);
3281 if (drv_data && drv_data->init) {
3282 ret = drv_data->init(host);
3285 "implementation specific init failed\n");
3290 timer_setup(&host->cmd11_timer, dw_mci_cmd11_timer, 0);
3291 timer_setup(&host->cto_timer, dw_mci_cto_timer, 0);
3292 timer_setup(&host->dto_timer, dw_mci_dto_timer, 0);
3294 spin_lock_init(&host->lock);
3295 spin_lock_init(&host->irq_lock);
3296 INIT_LIST_HEAD(&host->queue);
3298 dw_mci_init_fault(host);
3301 * Get the host data width - this assumes that HCON has been set with
3302 * the correct values.
3304 i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));
3306 host->push_data = dw_mci_push_data16;
3307 host->pull_data = dw_mci_pull_data16;
3309 host->data_shift = 1;
3310 } else if (i == 2) {
3311 host->push_data = dw_mci_push_data64;
3312 host->pull_data = dw_mci_pull_data64;
3314 host->data_shift = 3;
3316 /* Check for a reserved value, and warn if it is */
3318 "HCON reports a reserved host data width!\n"
3319 "Defaulting to 32-bit access.\n");
3320 host->push_data = dw_mci_push_data32;
3321 host->pull_data = dw_mci_pull_data32;
3323 host->data_shift = 2;
3326 /* Reset all blocks */
3327 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3332 host->dma_ops = host->pdata->dma_ops;
3333 dw_mci_init_dma(host);
3335 /* Clear the interrupts for the host controller */
3336 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3337 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3339 /* Put in max timeout */
3340 mci_writel(host, TMOUT, 0xFFFFFFFF);
3343 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
3344 * Tx Mark = fifo_size / 2 DMA Size = 8
3346 if (!host->pdata->fifo_depth) {
3348 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
3349 * have been overwritten by the bootloader, just like we're
3350 * about to do, so if you know the value for your hardware, you
3351 * should put it in the platform data.
3353 fifo_size = mci_readl(host, FIFOTH);
3354 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
3356 fifo_size = host->pdata->fifo_depth;
3358 host->fifo_depth = fifo_size;
3360 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
3361 mci_writel(host, FIFOTH, host->fifoth_val);
3363 /* disable clock to CIU */
3364 mci_writel(host, CLKENA, 0);
3365 mci_writel(host, CLKSRC, 0);
3368 * In 2.40a spec, Data offset is changed.
3369 * Need to check the version-id and set data-offset for DATA register.
3371 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
3372 dev_info(host->dev, "Version ID is %04x\n", host->verid);
3374 if (host->data_addr_override)
3375 host->fifo_reg = host->regs + host->data_addr_override;
3376 else if (host->verid < DW_MMC_240A)
3377 host->fifo_reg = host->regs + DATA_OFFSET;
3379 host->fifo_reg = host->regs + DATA_240A_OFFSET;
3381 tasklet_setup(&host->tasklet, dw_mci_tasklet_func);
3382 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
3383 host->irq_flags, "dw-mci", host);
3388 * Enable interrupts for command done, data over, data empty,
3389 * receive ready and error such as transmit, receive timeout, crc error
3391 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3392 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3393 DW_MCI_ERROR_FLAGS);
3394 /* Enable mci interrupt */
3395 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3398 "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n",
3399 host->irq, width, fifo_size);
3401 /* We need at least one slot to succeed */
3402 ret = dw_mci_init_slot(host);
3404 dev_dbg(host->dev, "slot %d init failed\n", i);
3408 /* Now that slots are all setup, we can enable card detect */
3409 dw_mci_enable_cd(host);
3414 if (host->use_dma && host->dma_ops->exit)
3415 host->dma_ops->exit(host);
3417 reset_control_assert(host->pdata->rstc);
3420 clk_disable_unprepare(host->ciu_clk);
3423 clk_disable_unprepare(host->biu_clk);
3427 EXPORT_SYMBOL(dw_mci_probe);
3429 void dw_mci_remove(struct dw_mci *host)
3431 dev_dbg(host->dev, "remove slot\n");
3433 dw_mci_cleanup_slot(host->slot);
3435 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3436 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3438 /* disable clock to CIU */
3439 mci_writel(host, CLKENA, 0);
3440 mci_writel(host, CLKSRC, 0);
3442 if (host->use_dma && host->dma_ops->exit)
3443 host->dma_ops->exit(host);
3445 reset_control_assert(host->pdata->rstc);
3447 clk_disable_unprepare(host->ciu_clk);
3448 clk_disable_unprepare(host->biu_clk);
3450 EXPORT_SYMBOL(dw_mci_remove);
3455 int dw_mci_runtime_suspend(struct device *dev)
3457 struct dw_mci *host = dev_get_drvdata(dev);
3459 if (host->use_dma && host->dma_ops->exit)
3460 host->dma_ops->exit(host);
3462 clk_disable_unprepare(host->ciu_clk);
3465 (mmc_can_gpio_cd(host->slot->mmc) ||
3466 !mmc_card_is_removable(host->slot->mmc)))
3467 clk_disable_unprepare(host->biu_clk);
3471 EXPORT_SYMBOL(dw_mci_runtime_suspend);
3473 int dw_mci_runtime_resume(struct device *dev)
3476 struct dw_mci *host = dev_get_drvdata(dev);
3479 (mmc_can_gpio_cd(host->slot->mmc) ||
3480 !mmc_card_is_removable(host->slot->mmc))) {
3481 ret = clk_prepare_enable(host->biu_clk);
3486 ret = clk_prepare_enable(host->ciu_clk);
3490 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3491 clk_disable_unprepare(host->ciu_clk);
3496 if (host->use_dma && host->dma_ops->init)
3497 host->dma_ops->init(host);
3500 * Restore the initial value at FIFOTH register
3501 * And Invalidate the prev_blksz with zero
3503 mci_writel(host, FIFOTH, host->fifoth_val);
3504 host->prev_blksz = 0;
3506 /* Put in max timeout */
3507 mci_writel(host, TMOUT, 0xFFFFFFFF);
3509 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3510 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3511 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3512 DW_MCI_ERROR_FLAGS);
3513 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3516 if (host->slot->mmc->pm_flags & MMC_PM_KEEP_POWER)
3517 dw_mci_set_ios(host->slot->mmc, &host->slot->mmc->ios);
3519 /* Force setup bus to guarantee available clock output */
3520 dw_mci_setup_bus(host->slot, true);
3522 /* Re-enable SDIO interrupts. */
3523 if (sdio_irq_claimed(host->slot->mmc))
3524 __dw_mci_enable_sdio_irq(host->slot, 1);
3526 /* Now that slots are all setup, we can enable card detect */
3527 dw_mci_enable_cd(host);
3533 (mmc_can_gpio_cd(host->slot->mmc) ||
3534 !mmc_card_is_removable(host->slot->mmc)))
3535 clk_disable_unprepare(host->biu_clk);
3539 EXPORT_SYMBOL(dw_mci_runtime_resume);
3540 #endif /* CONFIG_PM */
3542 static int __init dw_mci_init(void)
3544 pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
3548 static void __exit dw_mci_exit(void)
3552 module_init(dw_mci_init);
3553 module_exit(dw_mci_exit);
3555 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
3556 MODULE_AUTHOR("NXP Semiconductor VietNam");
3557 MODULE_AUTHOR("Imagination Technologies Ltd");
3558 MODULE_LICENSE("GPL v2");