2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/blkdev.h>
15 #include <linux/clk.h>
16 #include <linux/debugfs.h>
17 #include <linux/device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/ioport.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/seq_file.h>
26 #include <linux/slab.h>
27 #include <linux/stat.h>
28 #include <linux/delay.h>
29 #include <linux/irq.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/host.h>
32 #include <linux/mmc/mmc.h>
33 #include <linux/mmc/sd.h>
34 #include <linux/mmc/sdio.h>
35 #include <linux/mmc/dw_mmc.h>
36 #include <linux/bitops.h>
37 #include <linux/regulator/consumer.h>
39 #include <linux/of_gpio.h>
40 #include <linux/mmc/slot-gpio.h>
44 /* Common flag combinations */
45 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
46 SDMMC_INT_HTO | SDMMC_INT_SBE | \
47 SDMMC_INT_EBE | SDMMC_INT_HLE)
48 #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
49 SDMMC_INT_RESP_ERR | SDMMC_INT_HLE)
50 #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
51 DW_MCI_CMD_ERROR_FLAGS)
52 #define DW_MCI_SEND_STATUS 1
53 #define DW_MCI_RECV_STATUS 2
54 #define DW_MCI_DMA_THRESHOLD 16
56 #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */
57 #define DW_MCI_FREQ_MIN 100000 /* unit: HZ */
59 #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
60 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
61 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
64 #define DESC_RING_BUF_SZ PAGE_SIZE
66 struct idmac_desc_64addr {
67 u32 des0; /* Control Descriptor */
69 u32 des1; /* Reserved */
71 u32 des2; /*Buffer sizes */
72 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
73 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
74 ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
76 u32 des3; /* Reserved */
78 u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/
79 u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/
81 u32 des6; /* Lower 32-bits of Next Descriptor Address */
82 u32 des7; /* Upper 32-bits of Next Descriptor Address */
86 __le32 des0; /* Control Descriptor */
87 #define IDMAC_DES0_DIC BIT(1)
88 #define IDMAC_DES0_LD BIT(2)
89 #define IDMAC_DES0_FD BIT(3)
90 #define IDMAC_DES0_CH BIT(4)
91 #define IDMAC_DES0_ER BIT(5)
92 #define IDMAC_DES0_CES BIT(30)
93 #define IDMAC_DES0_OWN BIT(31)
95 __le32 des1; /* Buffer sizes */
96 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
97 ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff)))
99 __le32 des2; /* buffer 1 physical address */
101 __le32 des3; /* buffer 2 physical address */
104 /* Each descriptor can transfer up to 4KB of data in chained mode */
105 #define DW_MCI_DESC_DATA_LENGTH 0x1000
107 static bool dw_mci_reset(struct dw_mci *host);
108 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
109 static int dw_mci_card_busy(struct mmc_host *mmc);
110 static int dw_mci_get_cd(struct mmc_host *mmc);
112 #if defined(CONFIG_DEBUG_FS)
113 static int dw_mci_req_show(struct seq_file *s, void *v)
115 struct dw_mci_slot *slot = s->private;
116 struct mmc_request *mrq;
117 struct mmc_command *cmd;
118 struct mmc_command *stop;
119 struct mmc_data *data;
121 /* Make sure we get a consistent snapshot */
122 spin_lock_bh(&slot->host->lock);
132 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
133 cmd->opcode, cmd->arg, cmd->flags,
134 cmd->resp[0], cmd->resp[1], cmd->resp[2],
135 cmd->resp[2], cmd->error);
137 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
138 data->bytes_xfered, data->blocks,
139 data->blksz, data->flags, data->error);
142 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
143 stop->opcode, stop->arg, stop->flags,
144 stop->resp[0], stop->resp[1], stop->resp[2],
145 stop->resp[2], stop->error);
148 spin_unlock_bh(&slot->host->lock);
153 static int dw_mci_req_open(struct inode *inode, struct file *file)
155 return single_open(file, dw_mci_req_show, inode->i_private);
158 static const struct file_operations dw_mci_req_fops = {
159 .owner = THIS_MODULE,
160 .open = dw_mci_req_open,
163 .release = single_release,
166 static int dw_mci_regs_show(struct seq_file *s, void *v)
168 struct dw_mci *host = s->private;
170 seq_printf(s, "STATUS:\t0x%08x\n", mci_readl(host, STATUS));
171 seq_printf(s, "RINTSTS:\t0x%08x\n", mci_readl(host, RINTSTS));
172 seq_printf(s, "CMD:\t0x%08x\n", mci_readl(host, CMD));
173 seq_printf(s, "CTRL:\t0x%08x\n", mci_readl(host, CTRL));
174 seq_printf(s, "INTMASK:\t0x%08x\n", mci_readl(host, INTMASK));
175 seq_printf(s, "CLKENA:\t0x%08x\n", mci_readl(host, CLKENA));
180 static int dw_mci_regs_open(struct inode *inode, struct file *file)
182 return single_open(file, dw_mci_regs_show, inode->i_private);
185 static const struct file_operations dw_mci_regs_fops = {
186 .owner = THIS_MODULE,
187 .open = dw_mci_regs_open,
190 .release = single_release,
193 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
195 struct mmc_host *mmc = slot->mmc;
196 struct dw_mci *host = slot->host;
200 root = mmc->debugfs_root;
204 node = debugfs_create_file("regs", S_IRUSR, root, host,
209 node = debugfs_create_file("req", S_IRUSR, root, slot,
214 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
218 node = debugfs_create_x32("pending_events", S_IRUSR, root,
219 (u32 *)&host->pending_events);
223 node = debugfs_create_x32("completed_events", S_IRUSR, root,
224 (u32 *)&host->completed_events);
231 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
233 #endif /* defined(CONFIG_DEBUG_FS) */
235 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg);
237 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
239 struct mmc_data *data;
240 struct dw_mci_slot *slot = mmc_priv(mmc);
241 struct dw_mci *host = slot->host;
244 cmd->error = -EINPROGRESS;
247 if (cmd->opcode == MMC_STOP_TRANSMISSION ||
248 cmd->opcode == MMC_GO_IDLE_STATE ||
249 cmd->opcode == MMC_GO_INACTIVE_STATE ||
250 (cmd->opcode == SD_IO_RW_DIRECT &&
251 ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
252 cmdr |= SDMMC_CMD_STOP;
253 else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
254 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
256 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
259 /* Special bit makes CMD11 not die */
260 cmdr |= SDMMC_CMD_VOLT_SWITCH;
262 /* Change state to continue to handle CMD11 weirdness */
263 WARN_ON(slot->host->state != STATE_SENDING_CMD);
264 slot->host->state = STATE_SENDING_CMD11;
267 * We need to disable low power mode (automatic clock stop)
268 * while doing voltage switch so we don't confuse the card,
269 * since stopping the clock is a specific part of the UHS
270 * voltage change dance.
272 * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
273 * unconditionally turned back on in dw_mci_setup_bus() if it's
274 * ever called with a non-zero clock. That shouldn't happen
275 * until the voltage change is all done.
277 clk_en_a = mci_readl(host, CLKENA);
278 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
279 mci_writel(host, CLKENA, clk_en_a);
280 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
281 SDMMC_CMD_PRV_DAT_WAIT, 0);
284 if (cmd->flags & MMC_RSP_PRESENT) {
285 /* We expect a response, so set this bit */
286 cmdr |= SDMMC_CMD_RESP_EXP;
287 if (cmd->flags & MMC_RSP_136)
288 cmdr |= SDMMC_CMD_RESP_LONG;
291 if (cmd->flags & MMC_RSP_CRC)
292 cmdr |= SDMMC_CMD_RESP_CRC;
296 cmdr |= SDMMC_CMD_DAT_EXP;
297 if (data->flags & MMC_DATA_WRITE)
298 cmdr |= SDMMC_CMD_DAT_WR;
301 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags))
302 cmdr |= SDMMC_CMD_USE_HOLD_REG;
307 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
309 struct mmc_command *stop;
315 stop = &host->stop_abort;
317 memset(stop, 0, sizeof(struct mmc_command));
319 if (cmdr == MMC_READ_SINGLE_BLOCK ||
320 cmdr == MMC_READ_MULTIPLE_BLOCK ||
321 cmdr == MMC_WRITE_BLOCK ||
322 cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
323 cmdr == MMC_SEND_TUNING_BLOCK ||
324 cmdr == MMC_SEND_TUNING_BLOCK_HS200) {
325 stop->opcode = MMC_STOP_TRANSMISSION;
327 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
328 } else if (cmdr == SD_IO_RW_EXTENDED) {
329 stop->opcode = SD_IO_RW_DIRECT;
330 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
331 ((cmd->arg >> 28) & 0x7);
332 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
337 cmdr = stop->opcode | SDMMC_CMD_STOP |
338 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
340 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &host->cur_slot->flags))
341 cmdr |= SDMMC_CMD_USE_HOLD_REG;
346 static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
348 unsigned long timeout = jiffies + msecs_to_jiffies(500);
351 * Databook says that before issuing a new data transfer command
352 * we need to check to see if the card is busy. Data transfer commands
353 * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
355 * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
358 if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) &&
359 !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) {
360 while (mci_readl(host, STATUS) & SDMMC_STATUS_BUSY) {
361 if (time_after(jiffies, timeout)) {
362 /* Command will fail; we'll pass error then */
363 dev_err(host->dev, "Busy; trying anyway\n");
371 static void dw_mci_start_command(struct dw_mci *host,
372 struct mmc_command *cmd, u32 cmd_flags)
376 "start command: ARGR=0x%08x CMDR=0x%08x\n",
377 cmd->arg, cmd_flags);
379 mci_writel(host, CMDARG, cmd->arg);
380 wmb(); /* drain writebuffer */
381 dw_mci_wait_while_busy(host, cmd_flags);
383 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
386 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
388 struct mmc_command *stop = &host->stop_abort;
390 dw_mci_start_command(host, stop, host->stop_cmdr);
393 /* DMA interface functions */
394 static void dw_mci_stop_dma(struct dw_mci *host)
396 if (host->using_dma) {
397 host->dma_ops->stop(host);
398 host->dma_ops->cleanup(host);
401 /* Data transfer was stopped by the interrupt handler */
402 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
405 static int dw_mci_get_dma_dir(struct mmc_data *data)
407 if (data->flags & MMC_DATA_WRITE)
408 return DMA_TO_DEVICE;
410 return DMA_FROM_DEVICE;
413 static void dw_mci_dma_cleanup(struct dw_mci *host)
415 struct mmc_data *data = host->data;
417 if (data && data->host_cookie == COOKIE_MAPPED) {
418 dma_unmap_sg(host->dev,
421 dw_mci_get_dma_dir(data));
422 data->host_cookie = COOKIE_UNMAPPED;
426 static void dw_mci_idmac_reset(struct dw_mci *host)
428 u32 bmod = mci_readl(host, BMOD);
429 /* Software reset of DMA */
430 bmod |= SDMMC_IDMAC_SWRESET;
431 mci_writel(host, BMOD, bmod);
434 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
438 /* Disable and reset the IDMAC interface */
439 temp = mci_readl(host, CTRL);
440 temp &= ~SDMMC_CTRL_USE_IDMAC;
441 temp |= SDMMC_CTRL_DMA_RESET;
442 mci_writel(host, CTRL, temp);
444 /* Stop the IDMAC running */
445 temp = mci_readl(host, BMOD);
446 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
447 temp |= SDMMC_IDMAC_SWRESET;
448 mci_writel(host, BMOD, temp);
451 static void dw_mci_dmac_complete_dma(void *arg)
453 struct dw_mci *host = arg;
454 struct mmc_data *data = host->data;
456 dev_vdbg(host->dev, "DMA complete\n");
458 if ((host->use_dma == TRANS_MODE_EDMAC) &&
459 data && (data->flags & MMC_DATA_READ))
460 /* Invalidate cache after read */
461 dma_sync_sg_for_cpu(mmc_dev(host->cur_slot->mmc),
466 host->dma_ops->cleanup(host);
469 * If the card was removed, data will be NULL. No point in trying to
470 * send the stop command or waiting for NBUSY in this case.
473 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
474 tasklet_schedule(&host->tasklet);
478 static int dw_mci_idmac_init(struct dw_mci *host)
482 if (host->dma_64bit_address == 1) {
483 struct idmac_desc_64addr *p;
484 /* Number of descriptors in the ring buffer */
486 DESC_RING_BUF_SZ / sizeof(struct idmac_desc_64addr);
488 /* Forward link the descriptor list */
489 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
491 p->des6 = (host->sg_dma +
492 (sizeof(struct idmac_desc_64addr) *
493 (i + 1))) & 0xffffffff;
495 p->des7 = (u64)(host->sg_dma +
496 (sizeof(struct idmac_desc_64addr) *
498 /* Initialize reserved and buffer size fields to "0" */
504 /* Set the last descriptor as the end-of-ring descriptor */
505 p->des6 = host->sg_dma & 0xffffffff;
506 p->des7 = (u64)host->sg_dma >> 32;
507 p->des0 = IDMAC_DES0_ER;
510 struct idmac_desc *p;
511 /* Number of descriptors in the ring buffer */
513 DESC_RING_BUF_SZ / sizeof(struct idmac_desc);
515 /* Forward link the descriptor list */
516 for (i = 0, p = host->sg_cpu;
517 i < host->ring_size - 1;
519 p->des3 = cpu_to_le32(host->sg_dma +
520 (sizeof(struct idmac_desc) * (i + 1)));
524 /* Set the last descriptor as the end-of-ring descriptor */
525 p->des3 = cpu_to_le32(host->sg_dma);
526 p->des0 = cpu_to_le32(IDMAC_DES0_ER);
529 dw_mci_idmac_reset(host);
531 if (host->dma_64bit_address == 1) {
532 /* Mask out interrupts - get Tx & Rx complete only */
533 mci_writel(host, IDSTS64, IDMAC_INT_CLR);
534 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
535 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
537 /* Set the descriptor base address */
538 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
539 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
542 /* Mask out interrupts - get Tx & Rx complete only */
543 mci_writel(host, IDSTS, IDMAC_INT_CLR);
544 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
545 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
547 /* Set the descriptor base address */
548 mci_writel(host, DBADDR, host->sg_dma);
554 static inline int dw_mci_prepare_desc64(struct dw_mci *host,
555 struct mmc_data *data,
558 unsigned int desc_len;
559 struct idmac_desc_64addr *desc_first, *desc_last, *desc;
560 unsigned long timeout;
563 desc_first = desc_last = desc = host->sg_cpu;
565 for (i = 0; i < sg_len; i++) {
566 unsigned int length = sg_dma_len(&data->sg[i]);
568 u64 mem_addr = sg_dma_address(&data->sg[i]);
570 for ( ; length ; desc++) {
571 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
572 length : DW_MCI_DESC_DATA_LENGTH;
577 * Wait for the former clear OWN bit operation
578 * of IDMAC to make sure that this descriptor
579 * isn't still owned by IDMAC as IDMAC's write
580 * ops and CPU's read ops are asynchronous.
582 timeout = jiffies + msecs_to_jiffies(100);
583 while (readl(&desc->des0) & IDMAC_DES0_OWN) {
584 if (time_after(jiffies, timeout))
590 * Set the OWN bit and disable interrupts
591 * for this descriptor
593 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
597 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len);
599 /* Physical address to DMA to/from */
600 desc->des4 = mem_addr & 0xffffffff;
601 desc->des5 = mem_addr >> 32;
603 /* Update physical address for the next desc */
604 mem_addr += desc_len;
606 /* Save pointer to the last descriptor */
611 /* Set first descriptor */
612 desc_first->des0 |= IDMAC_DES0_FD;
614 /* Set last descriptor */
615 desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
616 desc_last->des0 |= IDMAC_DES0_LD;
620 /* restore the descriptor chain as it's polluted */
621 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
622 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
623 dw_mci_idmac_init(host);
628 static inline int dw_mci_prepare_desc32(struct dw_mci *host,
629 struct mmc_data *data,
632 unsigned int desc_len;
633 struct idmac_desc *desc_first, *desc_last, *desc;
634 unsigned long timeout;
637 desc_first = desc_last = desc = host->sg_cpu;
639 for (i = 0; i < sg_len; i++) {
640 unsigned int length = sg_dma_len(&data->sg[i]);
642 u32 mem_addr = sg_dma_address(&data->sg[i]);
644 for ( ; length ; desc++) {
645 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
646 length : DW_MCI_DESC_DATA_LENGTH;
651 * Wait for the former clear OWN bit operation
652 * of IDMAC to make sure that this descriptor
653 * isn't still owned by IDMAC as IDMAC's write
654 * ops and CPU's read ops are asynchronous.
656 timeout = jiffies + msecs_to_jiffies(100);
657 while (readl(&desc->des0) &
658 cpu_to_le32(IDMAC_DES0_OWN)) {
659 if (time_after(jiffies, timeout))
665 * Set the OWN bit and disable interrupts
666 * for this descriptor
668 desc->des0 = cpu_to_le32(IDMAC_DES0_OWN |
673 IDMAC_SET_BUFFER1_SIZE(desc, desc_len);
675 /* Physical address to DMA to/from */
676 desc->des2 = cpu_to_le32(mem_addr);
678 /* Update physical address for the next desc */
679 mem_addr += desc_len;
681 /* Save pointer to the last descriptor */
686 /* Set first descriptor */
687 desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD);
689 /* Set last descriptor */
690 desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH |
692 desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD);
696 /* restore the descriptor chain as it's polluted */
697 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
698 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
699 dw_mci_idmac_init(host);
703 static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
708 if (host->dma_64bit_address == 1)
709 ret = dw_mci_prepare_desc64(host, host->data, sg_len);
711 ret = dw_mci_prepare_desc32(host, host->data, sg_len);
716 /* drain writebuffer */
719 /* Make sure to reset DMA in case we did PIO before this */
720 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
721 dw_mci_idmac_reset(host);
723 /* Select IDMAC interface */
724 temp = mci_readl(host, CTRL);
725 temp |= SDMMC_CTRL_USE_IDMAC;
726 mci_writel(host, CTRL, temp);
728 /* drain writebuffer */
731 /* Enable the IDMAC */
732 temp = mci_readl(host, BMOD);
733 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
734 mci_writel(host, BMOD, temp);
736 /* Start it running */
737 mci_writel(host, PLDMND, 1);
743 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
744 .init = dw_mci_idmac_init,
745 .start = dw_mci_idmac_start_dma,
746 .stop = dw_mci_idmac_stop_dma,
747 .complete = dw_mci_dmac_complete_dma,
748 .cleanup = dw_mci_dma_cleanup,
751 static void dw_mci_edmac_stop_dma(struct dw_mci *host)
753 dmaengine_terminate_async(host->dms->ch);
756 static int dw_mci_edmac_start_dma(struct dw_mci *host,
759 struct dma_slave_config cfg;
760 struct dma_async_tx_descriptor *desc = NULL;
761 struct scatterlist *sgl = host->data->sg;
762 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
763 u32 sg_elems = host->data->sg_len;
765 u32 fifo_offset = host->fifo_reg - host->regs;
768 /* Set external dma config: burst size, burst width */
769 cfg.dst_addr = host->phy_regs + fifo_offset;
770 cfg.src_addr = cfg.dst_addr;
771 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
772 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
774 /* Match burst msize with external dma config */
775 fifoth_val = mci_readl(host, FIFOTH);
776 cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7];
777 cfg.src_maxburst = cfg.dst_maxburst;
779 if (host->data->flags & MMC_DATA_WRITE)
780 cfg.direction = DMA_MEM_TO_DEV;
782 cfg.direction = DMA_DEV_TO_MEM;
784 ret = dmaengine_slave_config(host->dms->ch, &cfg);
786 dev_err(host->dev, "Failed to config edmac.\n");
790 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl,
791 sg_len, cfg.direction,
792 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
794 dev_err(host->dev, "Can't prepare slave sg.\n");
798 /* Set dw_mci_dmac_complete_dma as callback */
799 desc->callback = dw_mci_dmac_complete_dma;
800 desc->callback_param = (void *)host;
801 dmaengine_submit(desc);
803 /* Flush cache before write */
804 if (host->data->flags & MMC_DATA_WRITE)
805 dma_sync_sg_for_device(mmc_dev(host->cur_slot->mmc), sgl,
806 sg_elems, DMA_TO_DEVICE);
808 dma_async_issue_pending(host->dms->ch);
813 static int dw_mci_edmac_init(struct dw_mci *host)
815 /* Request external dma channel */
816 host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
820 host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx");
821 if (!host->dms->ch) {
822 dev_err(host->dev, "Failed to get external DMA channel.\n");
831 static void dw_mci_edmac_exit(struct dw_mci *host)
835 dma_release_channel(host->dms->ch);
836 host->dms->ch = NULL;
843 static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
844 .init = dw_mci_edmac_init,
845 .exit = dw_mci_edmac_exit,
846 .start = dw_mci_edmac_start_dma,
847 .stop = dw_mci_edmac_stop_dma,
848 .complete = dw_mci_dmac_complete_dma,
849 .cleanup = dw_mci_dma_cleanup,
852 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
853 struct mmc_data *data,
856 struct scatterlist *sg;
857 unsigned int i, sg_len;
859 if (data->host_cookie == COOKIE_PRE_MAPPED)
863 * We don't do DMA on "complex" transfers, i.e. with
864 * non-word-aligned buffers or lengths. Also, we don't bother
865 * with all the DMA setup overhead for short transfers.
867 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
873 for_each_sg(data->sg, sg, data->sg_len, i) {
874 if (sg->offset & 3 || sg->length & 3)
878 sg_len = dma_map_sg(host->dev,
881 dw_mci_get_dma_dir(data));
885 data->host_cookie = cookie;
890 static void dw_mci_pre_req(struct mmc_host *mmc,
891 struct mmc_request *mrq,
894 struct dw_mci_slot *slot = mmc_priv(mmc);
895 struct mmc_data *data = mrq->data;
897 if (!slot->host->use_dma || !data)
900 /* This data might be unmapped at this time */
901 data->host_cookie = COOKIE_UNMAPPED;
903 if (dw_mci_pre_dma_transfer(slot->host, mrq->data,
904 COOKIE_PRE_MAPPED) < 0)
905 data->host_cookie = COOKIE_UNMAPPED;
908 static void dw_mci_post_req(struct mmc_host *mmc,
909 struct mmc_request *mrq,
912 struct dw_mci_slot *slot = mmc_priv(mmc);
913 struct mmc_data *data = mrq->data;
915 if (!slot->host->use_dma || !data)
918 if (data->host_cookie != COOKIE_UNMAPPED)
919 dma_unmap_sg(slot->host->dev,
922 dw_mci_get_dma_dir(data));
923 data->host_cookie = COOKIE_UNMAPPED;
926 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
928 unsigned int blksz = data->blksz;
929 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
930 u32 fifo_width = 1 << host->data_shift;
931 u32 blksz_depth = blksz / fifo_width, fifoth_val;
932 u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
933 int idx = ARRAY_SIZE(mszs) - 1;
935 /* pio should ship this scenario */
939 tx_wmark = (host->fifo_depth) / 2;
940 tx_wmark_invers = host->fifo_depth - tx_wmark;
944 * if blksz is not a multiple of the FIFO width
946 if (blksz % fifo_width)
950 if (!((blksz_depth % mszs[idx]) ||
951 (tx_wmark_invers % mszs[idx]))) {
953 rx_wmark = mszs[idx] - 1;
958 * If idx is '0', it won't be tried
959 * Thus, initial values are uesed
962 fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
963 mci_writel(host, FIFOTH, fifoth_val);
966 static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data)
968 unsigned int blksz = data->blksz;
969 u32 blksz_depth, fifo_depth;
974 * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
975 * in the FIFO region, so we really shouldn't access it).
977 if (host->verid < DW_MMC_240A ||
978 (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE))
982 * Card write Threshold is introduced since 2.80a
983 * It's used when HS400 mode is enabled.
985 if (data->flags & MMC_DATA_WRITE &&
986 !(host->timing != MMC_TIMING_MMC_HS400))
989 if (data->flags & MMC_DATA_WRITE)
990 enable = SDMMC_CARD_WR_THR_EN;
992 enable = SDMMC_CARD_RD_THR_EN;
994 if (host->timing != MMC_TIMING_MMC_HS200 &&
995 host->timing != MMC_TIMING_UHS_SDR104)
998 blksz_depth = blksz / (1 << host->data_shift);
999 fifo_depth = host->fifo_depth;
1001 if (blksz_depth > fifo_depth)
1005 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
1006 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz
1007 * Currently just choose blksz.
1010 mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable));
1014 mci_writel(host, CDTHRCTL, 0);
1017 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
1019 unsigned long irqflags;
1023 host->using_dma = 0;
1025 /* If we don't have a channel, we can't do DMA */
1029 sg_len = dw_mci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1031 host->dma_ops->stop(host);
1035 host->using_dma = 1;
1037 if (host->use_dma == TRANS_MODE_IDMAC)
1039 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
1040 (unsigned long)host->sg_cpu,
1041 (unsigned long)host->sg_dma,
1045 * Decide the MSIZE and RX/TX Watermark.
1046 * If current block size is same with previous size,
1047 * no need to update fifoth.
1049 if (host->prev_blksz != data->blksz)
1050 dw_mci_adjust_fifoth(host, data);
1052 /* Enable the DMA interface */
1053 temp = mci_readl(host, CTRL);
1054 temp |= SDMMC_CTRL_DMA_ENABLE;
1055 mci_writel(host, CTRL, temp);
1057 /* Disable RX/TX IRQs, let DMA handle it */
1058 spin_lock_irqsave(&host->irq_lock, irqflags);
1059 temp = mci_readl(host, INTMASK);
1060 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
1061 mci_writel(host, INTMASK, temp);
1062 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1064 if (host->dma_ops->start(host, sg_len)) {
1065 host->dma_ops->stop(host);
1066 /* We can't do DMA, try PIO for this one */
1068 "%s: fall back to PIO mode for current transfer\n",
1076 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
1078 unsigned long irqflags;
1079 int flags = SG_MITER_ATOMIC;
1082 data->error = -EINPROGRESS;
1084 WARN_ON(host->data);
1088 if (data->flags & MMC_DATA_READ)
1089 host->dir_status = DW_MCI_RECV_STATUS;
1091 host->dir_status = DW_MCI_SEND_STATUS;
1093 dw_mci_ctrl_thld(host, data);
1095 if (dw_mci_submit_data_dma(host, data)) {
1096 if (host->data->flags & MMC_DATA_READ)
1097 flags |= SG_MITER_TO_SG;
1099 flags |= SG_MITER_FROM_SG;
1101 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1102 host->sg = data->sg;
1103 host->part_buf_start = 0;
1104 host->part_buf_count = 0;
1106 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
1108 spin_lock_irqsave(&host->irq_lock, irqflags);
1109 temp = mci_readl(host, INTMASK);
1110 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
1111 mci_writel(host, INTMASK, temp);
1112 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1114 temp = mci_readl(host, CTRL);
1115 temp &= ~SDMMC_CTRL_DMA_ENABLE;
1116 mci_writel(host, CTRL, temp);
1119 * Use the initial fifoth_val for PIO mode.
1120 * If next issued data may be transfered by DMA mode,
1121 * prev_blksz should be invalidated.
1123 mci_writel(host, FIFOTH, host->fifoth_val);
1124 host->prev_blksz = 0;
1127 * Keep the current block size.
1128 * It will be used to decide whether to update
1129 * fifoth register next time.
1131 host->prev_blksz = data->blksz;
1135 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
1137 struct dw_mci *host = slot->host;
1138 unsigned long timeout = jiffies + msecs_to_jiffies(500);
1139 unsigned int cmd_status = 0;
1141 mci_writel(host, CMDARG, arg);
1142 wmb(); /* drain writebuffer */
1143 dw_mci_wait_while_busy(host, cmd);
1144 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
1146 while (time_before(jiffies, timeout)) {
1147 cmd_status = mci_readl(host, CMD);
1148 if (!(cmd_status & SDMMC_CMD_START))
1151 dev_err(&slot->mmc->class_dev,
1152 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
1153 cmd, arg, cmd_status);
1156 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
1158 struct dw_mci *host = slot->host;
1159 unsigned int clock = slot->clock;
1162 u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
1164 /* We must continue to set bit 28 in CMD until the change is complete */
1165 if (host->state == STATE_WAITING_CMD11_DONE)
1166 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
1169 mci_writel(host, CLKENA, 0);
1170 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1171 } else if (clock != host->current_speed || force_clkinit) {
1172 div = host->bus_hz / clock;
1173 if (host->bus_hz % clock && host->bus_hz > clock)
1175 * move the + 1 after the divide to prevent
1176 * over-clocking the card.
1180 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
1182 if (clock != slot->__clk_old || force_clkinit)
1183 dev_info(&slot->mmc->class_dev,
1184 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1185 slot->id, host->bus_hz, clock,
1186 div ? ((host->bus_hz / div) >> 1) :
1190 mci_writel(host, CLKENA, 0);
1191 mci_writel(host, CLKSRC, 0);
1194 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1196 /* set clock to desired speed */
1197 mci_writel(host, CLKDIV, div);
1200 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1202 /* enable clock; only low power if no SDIO */
1203 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
1204 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
1205 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1206 mci_writel(host, CLKENA, clk_en_a);
1209 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1211 /* keep the last clock value that was requested from core */
1212 slot->__clk_old = clock;
1215 host->current_speed = clock;
1217 /* Set the current slot bus width */
1218 mci_writel(host, CTYPE, (slot->ctype << slot->id));
1221 static void __dw_mci_start_request(struct dw_mci *host,
1222 struct dw_mci_slot *slot,
1223 struct mmc_command *cmd)
1225 struct mmc_request *mrq;
1226 struct mmc_data *data;
1231 host->cur_slot = slot;
1234 host->pending_events = 0;
1235 host->completed_events = 0;
1236 host->cmd_status = 0;
1237 host->data_status = 0;
1238 host->dir_status = 0;
1242 mci_writel(host, TMOUT, 0xFFFFFFFF);
1243 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1244 mci_writel(host, BLKSIZ, data->blksz);
1247 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1249 /* this is the first command, send the initialization clock */
1250 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1251 cmdflags |= SDMMC_CMD_INIT;
1254 dw_mci_submit_data(host, data);
1255 wmb(); /* drain writebuffer */
1258 dw_mci_start_command(host, cmd, cmdflags);
1260 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
1261 unsigned long irqflags;
1264 * Databook says to fail after 2ms w/ no response, but evidence
1265 * shows that sometimes the cmd11 interrupt takes over 130ms.
1266 * We'll set to 500ms, plus an extra jiffy just in case jiffies
1267 * is just about to roll over.
1269 * We do this whole thing under spinlock and only if the
1270 * command hasn't already completed (indicating the the irq
1271 * already ran so we don't want the timeout).
1273 spin_lock_irqsave(&host->irq_lock, irqflags);
1274 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1275 mod_timer(&host->cmd11_timer,
1276 jiffies + msecs_to_jiffies(500) + 1);
1277 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1280 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
1283 static void dw_mci_start_request(struct dw_mci *host,
1284 struct dw_mci_slot *slot)
1286 struct mmc_request *mrq = slot->mrq;
1287 struct mmc_command *cmd;
1289 cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1290 __dw_mci_start_request(host, slot, cmd);
1293 /* must be called with host->lock held */
1294 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1295 struct mmc_request *mrq)
1297 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1302 if (host->state == STATE_WAITING_CMD11_DONE) {
1303 dev_warn(&slot->mmc->class_dev,
1304 "Voltage change didn't complete\n");
1306 * this case isn't expected to happen, so we can
1307 * either crash here or just try to continue on
1308 * in the closest possible state
1310 host->state = STATE_IDLE;
1313 if (host->state == STATE_IDLE) {
1314 host->state = STATE_SENDING_CMD;
1315 dw_mci_start_request(host, slot);
1317 list_add_tail(&slot->queue_node, &host->queue);
1321 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1323 struct dw_mci_slot *slot = mmc_priv(mmc);
1324 struct dw_mci *host = slot->host;
1329 * The check for card presence and queueing of the request must be
1330 * atomic, otherwise the card could be removed in between and the
1331 * request wouldn't fail until another card was inserted.
1334 if (!dw_mci_get_cd(mmc)) {
1335 mrq->cmd->error = -ENOMEDIUM;
1336 mmc_request_done(mmc, mrq);
1340 spin_lock_bh(&host->lock);
1342 dw_mci_queue_request(host, slot, mrq);
1344 spin_unlock_bh(&host->lock);
1347 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1349 struct dw_mci_slot *slot = mmc_priv(mmc);
1350 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1354 switch (ios->bus_width) {
1355 case MMC_BUS_WIDTH_4:
1356 slot->ctype = SDMMC_CTYPE_4BIT;
1358 case MMC_BUS_WIDTH_8:
1359 slot->ctype = SDMMC_CTYPE_8BIT;
1362 /* set default 1 bit mode */
1363 slot->ctype = SDMMC_CTYPE_1BIT;
1366 regs = mci_readl(slot->host, UHS_REG);
1369 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
1370 ios->timing == MMC_TIMING_UHS_DDR50 ||
1371 ios->timing == MMC_TIMING_MMC_HS400)
1372 regs |= ((0x1 << slot->id) << 16);
1374 regs &= ~((0x1 << slot->id) << 16);
1376 mci_writel(slot->host, UHS_REG, regs);
1377 slot->host->timing = ios->timing;
1380 * Use mirror of ios->clock to prevent race with mmc
1381 * core ios update when finding the minimum.
1383 slot->clock = ios->clock;
1385 if (drv_data && drv_data->set_ios)
1386 drv_data->set_ios(slot->host, ios);
1388 switch (ios->power_mode) {
1390 if (!IS_ERR(mmc->supply.vmmc)) {
1391 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1394 dev_err(slot->host->dev,
1395 "failed to enable vmmc regulator\n");
1396 /*return, if failed turn on vmmc*/
1400 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1401 regs = mci_readl(slot->host, PWREN);
1402 regs |= (1 << slot->id);
1403 mci_writel(slot->host, PWREN, regs);
1406 if (!slot->host->vqmmc_enabled) {
1407 if (!IS_ERR(mmc->supply.vqmmc)) {
1408 ret = regulator_enable(mmc->supply.vqmmc);
1410 dev_err(slot->host->dev,
1411 "failed to enable vqmmc\n");
1413 slot->host->vqmmc_enabled = true;
1416 /* Keep track so we don't reset again */
1417 slot->host->vqmmc_enabled = true;
1420 /* Reset our state machine after powering on */
1421 dw_mci_ctrl_reset(slot->host,
1422 SDMMC_CTRL_ALL_RESET_FLAGS);
1425 /* Adjust clock / bus width after power is up */
1426 dw_mci_setup_bus(slot, false);
1430 /* Turn clock off before power goes down */
1431 dw_mci_setup_bus(slot, false);
1433 if (!IS_ERR(mmc->supply.vmmc))
1434 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1436 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
1437 regulator_disable(mmc->supply.vqmmc);
1438 slot->host->vqmmc_enabled = false;
1440 regs = mci_readl(slot->host, PWREN);
1441 regs &= ~(1 << slot->id);
1442 mci_writel(slot->host, PWREN, regs);
1448 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1449 slot->host->state = STATE_IDLE;
1452 static int dw_mci_card_busy(struct mmc_host *mmc)
1454 struct dw_mci_slot *slot = mmc_priv(mmc);
1458 * Check the busy bit which is low when DAT[3:0]
1459 * (the data lines) are 0000
1461 status = mci_readl(slot->host, STATUS);
1463 return !!(status & SDMMC_STATUS_BUSY);
1466 static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1468 struct dw_mci_slot *slot = mmc_priv(mmc);
1469 struct dw_mci *host = slot->host;
1470 const struct dw_mci_drv_data *drv_data = host->drv_data;
1472 u32 v18 = SDMMC_UHS_18V << slot->id;
1475 if (drv_data && drv_data->switch_voltage)
1476 return drv_data->switch_voltage(mmc, ios);
1479 * Program the voltage. Note that some instances of dw_mmc may use
1480 * the UHS_REG for this. For other instances (like exynos) the UHS_REG
1481 * does no harm but you need to set the regulator directly. Try both.
1483 uhs = mci_readl(host, UHS_REG);
1484 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1489 if (!IS_ERR(mmc->supply.vqmmc)) {
1490 ret = mmc_regulator_set_vqmmc(mmc, ios);
1493 dev_dbg(&mmc->class_dev,
1494 "Regulator set error %d - %s V\n",
1495 ret, uhs & v18 ? "1.8" : "3.3");
1499 mci_writel(host, UHS_REG, uhs);
1504 static int dw_mci_get_ro(struct mmc_host *mmc)
1507 struct dw_mci_slot *slot = mmc_priv(mmc);
1508 int gpio_ro = mmc_gpio_get_ro(mmc);
1510 /* Use platform get_ro function, else try on board write protect */
1512 read_only = gpio_ro;
1515 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1517 dev_dbg(&mmc->class_dev, "card is %s\n",
1518 read_only ? "read-only" : "read-write");
1523 static int dw_mci_get_cd(struct mmc_host *mmc)
1526 struct dw_mci_slot *slot = mmc_priv(mmc);
1527 struct dw_mci *host = slot->host;
1528 int gpio_cd = mmc_gpio_get_cd(mmc);
1530 /* Use platform get_cd function, else try onboard card detect */
1531 if ((mmc->caps & MMC_CAP_NEEDS_POLL) || !mmc_card_is_removable(mmc))
1533 else if (gpio_cd >= 0)
1536 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
1539 spin_lock_bh(&host->lock);
1540 if (present && !test_and_set_bit(DW_MMC_CARD_PRESENT, &slot->flags))
1541 dev_dbg(&mmc->class_dev, "card is present\n");
1542 else if (!test_and_clear_bit(DW_MMC_CARD_PRESENT, &slot->flags))
1543 dev_dbg(&mmc->class_dev, "card is not present\n");
1544 spin_unlock_bh(&host->lock);
1549 static void dw_mci_hw_reset(struct mmc_host *mmc)
1551 struct dw_mci_slot *slot = mmc_priv(mmc);
1552 struct dw_mci *host = slot->host;
1555 if (host->use_dma == TRANS_MODE_IDMAC)
1556 dw_mci_idmac_reset(host);
1558 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET |
1559 SDMMC_CTRL_FIFO_RESET))
1563 * According to eMMC spec, card reset procedure:
1564 * tRstW >= 1us: RST_n pulse width
1565 * tRSCA >= 200us: RST_n to Command time
1566 * tRSTH >= 1us: RST_n high period
1568 reset = mci_readl(host, RST_N);
1569 reset &= ~(SDMMC_RST_HWACTIVE << slot->id);
1570 mci_writel(host, RST_N, reset);
1572 reset |= SDMMC_RST_HWACTIVE << slot->id;
1573 mci_writel(host, RST_N, reset);
1574 usleep_range(200, 300);
1577 static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card)
1579 struct dw_mci_slot *slot = mmc_priv(mmc);
1580 struct dw_mci *host = slot->host;
1583 * Low power mode will stop the card clock when idle. According to the
1584 * description of the CLKENA register we should disable low power mode
1585 * for SDIO cards if we need SDIO interrupts to work.
1587 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1588 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1592 clk_en_a_old = mci_readl(host, CLKENA);
1594 if (card->type == MMC_TYPE_SDIO ||
1595 card->type == MMC_TYPE_SD_COMBO) {
1596 set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1597 clk_en_a = clk_en_a_old & ~clken_low_pwr;
1599 clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1600 clk_en_a = clk_en_a_old | clken_low_pwr;
1603 if (clk_en_a != clk_en_a_old) {
1604 mci_writel(host, CLKENA, clk_en_a);
1605 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1606 SDMMC_CMD_PRV_DAT_WAIT, 0);
1611 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1613 struct dw_mci_slot *slot = mmc_priv(mmc);
1614 struct dw_mci *host = slot->host;
1615 unsigned long irqflags;
1618 spin_lock_irqsave(&host->irq_lock, irqflags);
1620 /* Enable/disable Slot Specific SDIO interrupt */
1621 int_mask = mci_readl(host, INTMASK);
1623 int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
1625 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
1626 mci_writel(host, INTMASK, int_mask);
1628 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1631 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1633 struct dw_mci_slot *slot = mmc_priv(mmc);
1634 struct dw_mci *host = slot->host;
1635 const struct dw_mci_drv_data *drv_data = host->drv_data;
1638 if (drv_data && drv_data->execute_tuning)
1639 err = drv_data->execute_tuning(slot, opcode);
1643 static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc,
1644 struct mmc_ios *ios)
1646 struct dw_mci_slot *slot = mmc_priv(mmc);
1647 struct dw_mci *host = slot->host;
1648 const struct dw_mci_drv_data *drv_data = host->drv_data;
1650 if (drv_data && drv_data->prepare_hs400_tuning)
1651 return drv_data->prepare_hs400_tuning(host, ios);
1656 static const struct mmc_host_ops dw_mci_ops = {
1657 .request = dw_mci_request,
1658 .pre_req = dw_mci_pre_req,
1659 .post_req = dw_mci_post_req,
1660 .set_ios = dw_mci_set_ios,
1661 .get_ro = dw_mci_get_ro,
1662 .get_cd = dw_mci_get_cd,
1663 .hw_reset = dw_mci_hw_reset,
1664 .enable_sdio_irq = dw_mci_enable_sdio_irq,
1665 .execute_tuning = dw_mci_execute_tuning,
1666 .card_busy = dw_mci_card_busy,
1667 .start_signal_voltage_switch = dw_mci_switch_voltage,
1668 .init_card = dw_mci_init_card,
1669 .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning,
1672 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1673 __releases(&host->lock)
1674 __acquires(&host->lock)
1676 struct dw_mci_slot *slot;
1677 struct mmc_host *prev_mmc = host->cur_slot->mmc;
1679 WARN_ON(host->cmd || host->data);
1681 host->cur_slot->mrq = NULL;
1683 if (!list_empty(&host->queue)) {
1684 slot = list_entry(host->queue.next,
1685 struct dw_mci_slot, queue_node);
1686 list_del(&slot->queue_node);
1687 dev_vdbg(host->dev, "list not empty: %s is next\n",
1688 mmc_hostname(slot->mmc));
1689 host->state = STATE_SENDING_CMD;
1690 dw_mci_start_request(host, slot);
1692 dev_vdbg(host->dev, "list empty\n");
1694 if (host->state == STATE_SENDING_CMD11)
1695 host->state = STATE_WAITING_CMD11_DONE;
1697 host->state = STATE_IDLE;
1700 spin_unlock(&host->lock);
1701 mmc_request_done(prev_mmc, mrq);
1702 spin_lock(&host->lock);
1705 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
1707 u32 status = host->cmd_status;
1709 host->cmd_status = 0;
1711 /* Read the response from the card (up to 16 bytes) */
1712 if (cmd->flags & MMC_RSP_PRESENT) {
1713 if (cmd->flags & MMC_RSP_136) {
1714 cmd->resp[3] = mci_readl(host, RESP0);
1715 cmd->resp[2] = mci_readl(host, RESP1);
1716 cmd->resp[1] = mci_readl(host, RESP2);
1717 cmd->resp[0] = mci_readl(host, RESP3);
1719 cmd->resp[0] = mci_readl(host, RESP0);
1726 if (status & SDMMC_INT_RTO)
1727 cmd->error = -ETIMEDOUT;
1728 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1729 cmd->error = -EILSEQ;
1730 else if (status & SDMMC_INT_RESP_ERR)
1738 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1740 u32 status = host->data_status;
1742 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1743 if (status & SDMMC_INT_DRTO) {
1744 data->error = -ETIMEDOUT;
1745 } else if (status & SDMMC_INT_DCRC) {
1746 data->error = -EILSEQ;
1747 } else if (status & SDMMC_INT_EBE) {
1748 if (host->dir_status ==
1749 DW_MCI_SEND_STATUS) {
1751 * No data CRC status was returned.
1752 * The number of bytes transferred
1753 * will be exaggerated in PIO mode.
1755 data->bytes_xfered = 0;
1756 data->error = -ETIMEDOUT;
1757 } else if (host->dir_status ==
1758 DW_MCI_RECV_STATUS) {
1759 data->error = -EILSEQ;
1762 /* SDMMC_INT_SBE is included */
1763 data->error = -EILSEQ;
1766 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
1769 * After an error, there may be data lingering
1774 data->bytes_xfered = data->blocks * data->blksz;
1781 static void dw_mci_set_drto(struct dw_mci *host)
1783 unsigned int drto_clks;
1784 unsigned int drto_ms;
1786 drto_clks = mci_readl(host, TMOUT) >> 8;
1787 drto_ms = DIV_ROUND_UP(drto_clks, host->bus_hz / 1000);
1789 /* add a bit spare time */
1792 mod_timer(&host->dto_timer, jiffies + msecs_to_jiffies(drto_ms));
1795 static void dw_mci_tasklet_func(unsigned long priv)
1797 struct dw_mci *host = (struct dw_mci *)priv;
1798 struct mmc_data *data;
1799 struct mmc_command *cmd;
1800 struct mmc_request *mrq;
1801 enum dw_mci_state state;
1802 enum dw_mci_state prev_state;
1805 spin_lock(&host->lock);
1807 state = host->state;
1816 case STATE_WAITING_CMD11_DONE:
1819 case STATE_SENDING_CMD11:
1820 case STATE_SENDING_CMD:
1821 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1822 &host->pending_events))
1827 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
1828 err = dw_mci_command_complete(host, cmd);
1829 if (cmd == mrq->sbc && !err) {
1830 prev_state = state = STATE_SENDING_CMD;
1831 __dw_mci_start_request(host, host->cur_slot,
1836 if (cmd->data && err) {
1838 * During UHS tuning sequence, sending the stop
1839 * command after the response CRC error would
1840 * throw the system into a confused state
1841 * causing all future tuning phases to report
1844 * In such case controller will move into a data
1845 * transfer state after a response error or
1846 * response CRC error. Let's let that finish
1847 * before trying to send a stop, so we'll go to
1848 * STATE_SENDING_DATA.
1850 * Although letting the data transfer take place
1851 * will waste a bit of time (we already know
1852 * the command was bad), it can't cause any
1853 * errors since it's possible it would have
1854 * taken place anyway if this tasklet got
1855 * delayed. Allowing the transfer to take place
1856 * avoids races and keeps things simple.
1858 if ((err != -ETIMEDOUT) &&
1859 (cmd->opcode == MMC_SEND_TUNING_BLOCK)) {
1860 state = STATE_SENDING_DATA;
1864 dw_mci_stop_dma(host);
1865 send_stop_abort(host, data);
1866 state = STATE_SENDING_STOP;
1870 if (!cmd->data || err) {
1871 dw_mci_request_end(host, mrq);
1875 prev_state = state = STATE_SENDING_DATA;
1878 case STATE_SENDING_DATA:
1880 * We could get a data error and never a transfer
1881 * complete so we'd better check for it here.
1883 * Note that we don't really care if we also got a
1884 * transfer complete; stopping the DMA and sending an
1887 if (test_and_clear_bit(EVENT_DATA_ERROR,
1888 &host->pending_events)) {
1889 dw_mci_stop_dma(host);
1890 if (!(host->data_status & (SDMMC_INT_DRTO |
1892 send_stop_abort(host, data);
1893 state = STATE_DATA_ERROR;
1897 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1898 &host->pending_events)) {
1900 * If all data-related interrupts don't come
1901 * within the given time in reading data state.
1903 if (host->dir_status == DW_MCI_RECV_STATUS)
1904 dw_mci_set_drto(host);
1908 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
1911 * Handle an EVENT_DATA_ERROR that might have shown up
1912 * before the transfer completed. This might not have
1913 * been caught by the check above because the interrupt
1914 * could have gone off between the previous check and
1915 * the check for transfer complete.
1917 * Technically this ought not be needed assuming we
1918 * get a DATA_COMPLETE eventually (we'll notice the
1919 * error and end the request), but it shouldn't hurt.
1921 * This has the advantage of sending the stop command.
1923 if (test_and_clear_bit(EVENT_DATA_ERROR,
1924 &host->pending_events)) {
1925 dw_mci_stop_dma(host);
1926 if (!(host->data_status & (SDMMC_INT_DRTO |
1928 send_stop_abort(host, data);
1929 state = STATE_DATA_ERROR;
1932 prev_state = state = STATE_DATA_BUSY;
1936 case STATE_DATA_BUSY:
1937 if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
1938 &host->pending_events)) {
1940 * If data error interrupt comes but data over
1941 * interrupt doesn't come within the given time.
1942 * in reading data state.
1944 if (host->dir_status == DW_MCI_RECV_STATUS)
1945 dw_mci_set_drto(host);
1950 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
1951 err = dw_mci_data_complete(host, data);
1954 if (!data->stop || mrq->sbc) {
1955 if (mrq->sbc && data->stop)
1956 data->stop->error = 0;
1957 dw_mci_request_end(host, mrq);
1961 /* stop command for open-ended transfer*/
1963 send_stop_abort(host, data);
1966 * If we don't have a command complete now we'll
1967 * never get one since we just reset everything;
1968 * better end the request.
1970 * If we do have a command complete we'll fall
1971 * through to the SENDING_STOP command and
1972 * everything will be peachy keen.
1974 if (!test_bit(EVENT_CMD_COMPLETE,
1975 &host->pending_events)) {
1977 dw_mci_request_end(host, mrq);
1983 * If err has non-zero,
1984 * stop-abort command has been already issued.
1986 prev_state = state = STATE_SENDING_STOP;
1990 case STATE_SENDING_STOP:
1991 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1992 &host->pending_events))
1995 /* CMD error in data command */
1996 if (mrq->cmd->error && mrq->data)
2002 if (!mrq->sbc && mrq->stop)
2003 dw_mci_command_complete(host, mrq->stop);
2005 host->cmd_status = 0;
2007 dw_mci_request_end(host, mrq);
2010 case STATE_DATA_ERROR:
2011 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2012 &host->pending_events))
2015 state = STATE_DATA_BUSY;
2018 } while (state != prev_state);
2020 host->state = state;
2022 spin_unlock(&host->lock);
2026 /* push final bytes to part_buf, only use during push */
2027 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
2029 memcpy((void *)&host->part_buf, buf, cnt);
2030 host->part_buf_count = cnt;
2033 /* append bytes to part_buf, only use during push */
2034 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
2036 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
2037 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
2038 host->part_buf_count += cnt;
2042 /* pull first bytes from part_buf, only use during pull */
2043 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
2045 cnt = min_t(int, cnt, host->part_buf_count);
2047 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
2049 host->part_buf_count -= cnt;
2050 host->part_buf_start += cnt;
2055 /* pull final bytes from the part_buf, assuming it's just been filled */
2056 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
2058 memcpy(buf, &host->part_buf, cnt);
2059 host->part_buf_start = cnt;
2060 host->part_buf_count = (1 << host->data_shift) - cnt;
2063 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
2065 struct mmc_data *data = host->data;
2068 /* try and push anything in the part_buf */
2069 if (unlikely(host->part_buf_count)) {
2070 int len = dw_mci_push_part_bytes(host, buf, cnt);
2074 if (host->part_buf_count == 2) {
2075 mci_fifo_writew(host->fifo_reg, host->part_buf16);
2076 host->part_buf_count = 0;
2079 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2080 if (unlikely((unsigned long)buf & 0x1)) {
2082 u16 aligned_buf[64];
2083 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2084 int items = len >> 1;
2086 /* memcpy from input buffer into aligned buffer */
2087 memcpy(aligned_buf, buf, len);
2090 /* push data from aligned buffer into fifo */
2091 for (i = 0; i < items; ++i)
2092 mci_fifo_writew(host->fifo_reg, aligned_buf[i]);
2099 for (; cnt >= 2; cnt -= 2)
2100 mci_fifo_writew(host->fifo_reg, *pdata++);
2103 /* put anything remaining in the part_buf */
2105 dw_mci_set_part_bytes(host, buf, cnt);
2106 /* Push data if we have reached the expected data length */
2107 if ((data->bytes_xfered + init_cnt) ==
2108 (data->blksz * data->blocks))
2109 mci_fifo_writew(host->fifo_reg, host->part_buf16);
2113 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2115 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2116 if (unlikely((unsigned long)buf & 0x1)) {
2118 /* pull data from fifo into aligned buffer */
2119 u16 aligned_buf[64];
2120 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2121 int items = len >> 1;
2124 for (i = 0; i < items; ++i)
2125 aligned_buf[i] = mci_fifo_readw(host->fifo_reg);
2126 /* memcpy from aligned buffer into output buffer */
2127 memcpy(buf, aligned_buf, len);
2136 for (; cnt >= 2; cnt -= 2)
2137 *pdata++ = mci_fifo_readw(host->fifo_reg);
2141 host->part_buf16 = mci_fifo_readw(host->fifo_reg);
2142 dw_mci_pull_final_bytes(host, buf, cnt);
2146 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2148 struct mmc_data *data = host->data;
2151 /* try and push anything in the part_buf */
2152 if (unlikely(host->part_buf_count)) {
2153 int len = dw_mci_push_part_bytes(host, buf, cnt);
2157 if (host->part_buf_count == 4) {
2158 mci_fifo_writel(host->fifo_reg, host->part_buf32);
2159 host->part_buf_count = 0;
2162 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2163 if (unlikely((unsigned long)buf & 0x3)) {
2165 u32 aligned_buf[32];
2166 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2167 int items = len >> 2;
2169 /* memcpy from input buffer into aligned buffer */
2170 memcpy(aligned_buf, buf, len);
2173 /* push data from aligned buffer into fifo */
2174 for (i = 0; i < items; ++i)
2175 mci_fifo_writel(host->fifo_reg, aligned_buf[i]);
2182 for (; cnt >= 4; cnt -= 4)
2183 mci_fifo_writel(host->fifo_reg, *pdata++);
2186 /* put anything remaining in the part_buf */
2188 dw_mci_set_part_bytes(host, buf, cnt);
2189 /* Push data if we have reached the expected data length */
2190 if ((data->bytes_xfered + init_cnt) ==
2191 (data->blksz * data->blocks))
2192 mci_fifo_writel(host->fifo_reg, host->part_buf32);
2196 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2198 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2199 if (unlikely((unsigned long)buf & 0x3)) {
2201 /* pull data from fifo into aligned buffer */
2202 u32 aligned_buf[32];
2203 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2204 int items = len >> 2;
2207 for (i = 0; i < items; ++i)
2208 aligned_buf[i] = mci_fifo_readl(host->fifo_reg);
2209 /* memcpy from aligned buffer into output buffer */
2210 memcpy(buf, aligned_buf, len);
2219 for (; cnt >= 4; cnt -= 4)
2220 *pdata++ = mci_fifo_readl(host->fifo_reg);
2224 host->part_buf32 = mci_fifo_readl(host->fifo_reg);
2225 dw_mci_pull_final_bytes(host, buf, cnt);
2229 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2231 struct mmc_data *data = host->data;
2234 /* try and push anything in the part_buf */
2235 if (unlikely(host->part_buf_count)) {
2236 int len = dw_mci_push_part_bytes(host, buf, cnt);
2241 if (host->part_buf_count == 8) {
2242 mci_fifo_writeq(host->fifo_reg, host->part_buf);
2243 host->part_buf_count = 0;
2246 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2247 if (unlikely((unsigned long)buf & 0x7)) {
2249 u64 aligned_buf[16];
2250 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2251 int items = len >> 3;
2253 /* memcpy from input buffer into aligned buffer */
2254 memcpy(aligned_buf, buf, len);
2257 /* push data from aligned buffer into fifo */
2258 for (i = 0; i < items; ++i)
2259 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]);
2266 for (; cnt >= 8; cnt -= 8)
2267 mci_fifo_writeq(host->fifo_reg, *pdata++);
2270 /* put anything remaining in the part_buf */
2272 dw_mci_set_part_bytes(host, buf, cnt);
2273 /* Push data if we have reached the expected data length */
2274 if ((data->bytes_xfered + init_cnt) ==
2275 (data->blksz * data->blocks))
2276 mci_fifo_writeq(host->fifo_reg, host->part_buf);
2280 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2282 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2283 if (unlikely((unsigned long)buf & 0x7)) {
2285 /* pull data from fifo into aligned buffer */
2286 u64 aligned_buf[16];
2287 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2288 int items = len >> 3;
2291 for (i = 0; i < items; ++i)
2292 aligned_buf[i] = mci_fifo_readq(host->fifo_reg);
2294 /* memcpy from aligned buffer into output buffer */
2295 memcpy(buf, aligned_buf, len);
2304 for (; cnt >= 8; cnt -= 8)
2305 *pdata++ = mci_fifo_readq(host->fifo_reg);
2309 host->part_buf = mci_fifo_readq(host->fifo_reg);
2310 dw_mci_pull_final_bytes(host, buf, cnt);
2314 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2318 /* get remaining partial bytes */
2319 len = dw_mci_pull_part_bytes(host, buf, cnt);
2320 if (unlikely(len == cnt))
2325 /* get the rest of the data */
2326 host->pull_data(host, buf, cnt);
2329 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
2331 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2333 unsigned int offset;
2334 struct mmc_data *data = host->data;
2335 int shift = host->data_shift;
2338 unsigned int remain, fcnt;
2341 if (!sg_miter_next(sg_miter))
2344 host->sg = sg_miter->piter.sg;
2345 buf = sg_miter->addr;
2346 remain = sg_miter->length;
2350 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2351 << shift) + host->part_buf_count;
2352 len = min(remain, fcnt);
2355 dw_mci_pull_data(host, (void *)(buf + offset), len);
2356 data->bytes_xfered += len;
2361 sg_miter->consumed = offset;
2362 status = mci_readl(host, MINTSTS);
2363 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2364 /* if the RXDR is ready read again */
2365 } while ((status & SDMMC_INT_RXDR) ||
2366 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
2369 if (!sg_miter_next(sg_miter))
2371 sg_miter->consumed = 0;
2373 sg_miter_stop(sg_miter);
2377 sg_miter_stop(sg_miter);
2379 smp_wmb(); /* drain writebuffer */
2380 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2383 static void dw_mci_write_data_pio(struct dw_mci *host)
2385 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2387 unsigned int offset;
2388 struct mmc_data *data = host->data;
2389 int shift = host->data_shift;
2392 unsigned int fifo_depth = host->fifo_depth;
2393 unsigned int remain, fcnt;
2396 if (!sg_miter_next(sg_miter))
2399 host->sg = sg_miter->piter.sg;
2400 buf = sg_miter->addr;
2401 remain = sg_miter->length;
2405 fcnt = ((fifo_depth -
2406 SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2407 << shift) - host->part_buf_count;
2408 len = min(remain, fcnt);
2411 host->push_data(host, (void *)(buf + offset), len);
2412 data->bytes_xfered += len;
2417 sg_miter->consumed = offset;
2418 status = mci_readl(host, MINTSTS);
2419 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2420 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
2423 if (!sg_miter_next(sg_miter))
2425 sg_miter->consumed = 0;
2427 sg_miter_stop(sg_miter);
2431 sg_miter_stop(sg_miter);
2433 smp_wmb(); /* drain writebuffer */
2434 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2437 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2439 if (!host->cmd_status)
2440 host->cmd_status = status;
2442 smp_wmb(); /* drain writebuffer */
2444 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2445 tasklet_schedule(&host->tasklet);
2448 static void dw_mci_handle_cd(struct dw_mci *host)
2452 for (i = 0; i < host->num_slots; i++) {
2453 struct dw_mci_slot *slot = host->slot[i];
2458 if (slot->mmc->ops->card_event)
2459 slot->mmc->ops->card_event(slot->mmc);
2460 mmc_detect_change(slot->mmc,
2461 msecs_to_jiffies(host->pdata->detect_delay_ms));
2465 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2467 struct dw_mci *host = dev_id;
2471 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2474 /* Check volt switch first, since it can look like an error */
2475 if ((host->state == STATE_SENDING_CMD11) &&
2476 (pending & SDMMC_INT_VOLT_SWITCH)) {
2477 unsigned long irqflags;
2479 mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
2480 pending &= ~SDMMC_INT_VOLT_SWITCH;
2483 * Hold the lock; we know cmd11_timer can't be kicked
2484 * off after the lock is released, so safe to delete.
2486 spin_lock_irqsave(&host->irq_lock, irqflags);
2487 dw_mci_cmd_interrupt(host, pending);
2488 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2490 del_timer(&host->cmd11_timer);
2493 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2494 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
2495 host->cmd_status = pending;
2496 smp_wmb(); /* drain writebuffer */
2497 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2500 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2501 /* if there is an error report DATA_ERROR */
2502 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2503 host->data_status = pending;
2504 smp_wmb(); /* drain writebuffer */
2505 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2506 tasklet_schedule(&host->tasklet);
2509 if (pending & SDMMC_INT_DATA_OVER) {
2510 del_timer(&host->dto_timer);
2512 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2513 if (!host->data_status)
2514 host->data_status = pending;
2515 smp_wmb(); /* drain writebuffer */
2516 if (host->dir_status == DW_MCI_RECV_STATUS) {
2517 if (host->sg != NULL)
2518 dw_mci_read_data_pio(host, true);
2520 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2521 tasklet_schedule(&host->tasklet);
2524 if (pending & SDMMC_INT_RXDR) {
2525 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2526 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2527 dw_mci_read_data_pio(host, false);
2530 if (pending & SDMMC_INT_TXDR) {
2531 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2532 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2533 dw_mci_write_data_pio(host);
2536 if (pending & SDMMC_INT_CMD_DONE) {
2537 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2538 dw_mci_cmd_interrupt(host, pending);
2541 if (pending & SDMMC_INT_CD) {
2542 mci_writel(host, RINTSTS, SDMMC_INT_CD);
2543 dw_mci_handle_cd(host);
2546 /* Handle SDIO Interrupts */
2547 for (i = 0; i < host->num_slots; i++) {
2548 struct dw_mci_slot *slot = host->slot[i];
2553 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
2554 mci_writel(host, RINTSTS,
2555 SDMMC_INT_SDIO(slot->sdio_id));
2556 mmc_signal_sdio_irq(slot->mmc);
2562 if (host->use_dma != TRANS_MODE_IDMAC)
2565 /* Handle IDMA interrupts */
2566 if (host->dma_64bit_address == 1) {
2567 pending = mci_readl(host, IDSTS64);
2568 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2569 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2570 SDMMC_IDMAC_INT_RI);
2571 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
2572 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2573 host->dma_ops->complete((void *)host);
2576 pending = mci_readl(host, IDSTS);
2577 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2578 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2579 SDMMC_IDMAC_INT_RI);
2580 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
2581 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2582 host->dma_ops->complete((void *)host);
2589 static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
2591 struct mmc_host *mmc;
2592 struct dw_mci_slot *slot;
2593 const struct dw_mci_drv_data *drv_data = host->drv_data;
2597 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
2601 slot = mmc_priv(mmc);
2603 slot->sdio_id = host->sdio_id0 + id;
2606 host->slot[id] = slot;
2608 mmc->ops = &dw_mci_ops;
2609 if (of_property_read_u32_array(host->dev->of_node,
2610 "clock-freq-min-max", freq, 2)) {
2611 mmc->f_min = DW_MCI_FREQ_MIN;
2612 mmc->f_max = DW_MCI_FREQ_MAX;
2614 mmc->f_min = freq[0];
2615 mmc->f_max = freq[1];
2618 /*if there are external regulators, get them*/
2619 ret = mmc_regulator_get_supply(mmc);
2620 if (ret == -EPROBE_DEFER)
2621 goto err_host_allocated;
2623 if (!mmc->ocr_avail)
2624 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2626 if (host->pdata->caps)
2627 mmc->caps = host->pdata->caps;
2630 * Support MMC_CAP_ERASE by default.
2631 * It needs to use trim/discard/erase commands.
2633 mmc->caps |= MMC_CAP_ERASE;
2635 if (host->pdata->pm_caps)
2636 mmc->pm_caps = host->pdata->pm_caps;
2638 if (host->dev->of_node) {
2639 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2643 ctrl_id = to_platform_device(host->dev)->id;
2645 if (drv_data && drv_data->caps)
2646 mmc->caps |= drv_data->caps[ctrl_id];
2648 if (host->pdata->caps2)
2649 mmc->caps2 = host->pdata->caps2;
2651 ret = mmc_of_parse(mmc);
2653 goto err_host_allocated;
2655 /* Useful defaults if platform data is unset. */
2656 if (host->use_dma == TRANS_MODE_IDMAC) {
2657 mmc->max_segs = host->ring_size;
2658 mmc->max_blk_size = 65535;
2659 mmc->max_seg_size = 0x1000;
2660 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2661 mmc->max_blk_count = mmc->max_req_size / 512;
2662 } else if (host->use_dma == TRANS_MODE_EDMAC) {
2664 mmc->max_blk_size = 65535;
2665 mmc->max_blk_count = 65535;
2667 mmc->max_blk_size * mmc->max_blk_count;
2668 mmc->max_seg_size = mmc->max_req_size;
2670 /* TRANS_MODE_PIO */
2672 mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */
2673 mmc->max_blk_count = 512;
2674 mmc->max_req_size = mmc->max_blk_size *
2676 mmc->max_seg_size = mmc->max_req_size;
2681 ret = mmc_add_host(mmc);
2683 goto err_host_allocated;
2685 #if defined(CONFIG_DEBUG_FS)
2686 dw_mci_init_debugfs(slot);
2696 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
2698 /* Debugfs stuff is cleaned up by mmc core */
2699 mmc_remove_host(slot->mmc);
2700 slot->host->slot[id] = NULL;
2701 mmc_free_host(slot->mmc);
2704 static void dw_mci_init_dma(struct dw_mci *host)
2707 struct device *dev = host->dev;
2708 struct device_node *np = dev->of_node;
2711 * Check tansfer mode from HCON[17:16]
2712 * Clear the ambiguous description of dw_mmc databook:
2713 * 2b'00: No DMA Interface -> Actually means using Internal DMA block
2714 * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block
2715 * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block
2716 * 2b'11: Non DW DMA Interface -> pio only
2717 * Compared to DesignWare DMA Interface, Generic DMA Interface has a
2718 * simpler request/acknowledge handshake mechanism and both of them
2719 * are regarded as external dma master for dw_mmc.
2721 host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
2722 if (host->use_dma == DMA_INTERFACE_IDMA) {
2723 host->use_dma = TRANS_MODE_IDMAC;
2724 } else if (host->use_dma == DMA_INTERFACE_DWDMA ||
2725 host->use_dma == DMA_INTERFACE_GDMA) {
2726 host->use_dma = TRANS_MODE_EDMAC;
2731 /* Determine which DMA interface to use */
2732 if (host->use_dma == TRANS_MODE_IDMAC) {
2734 * Check ADDR_CONFIG bit in HCON to find
2735 * IDMAC address bus width
2737 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
2739 if (addr_config == 1) {
2740 /* host supports IDMAC in 64-bit address mode */
2741 host->dma_64bit_address = 1;
2743 "IDMAC supports 64-bit address mode.\n");
2744 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
2745 dma_set_coherent_mask(host->dev,
2748 /* host supports IDMAC in 32-bit address mode */
2749 host->dma_64bit_address = 0;
2751 "IDMAC supports 32-bit address mode.\n");
2754 /* Alloc memory for sg translation */
2755 host->sg_cpu = dmam_alloc_coherent(host->dev,
2757 &host->sg_dma, GFP_KERNEL);
2758 if (!host->sg_cpu) {
2760 "%s: could not alloc DMA memory\n",
2765 host->dma_ops = &dw_mci_idmac_ops;
2766 dev_info(host->dev, "Using internal DMA controller.\n");
2768 /* TRANS_MODE_EDMAC: check dma bindings again */
2769 if ((of_property_count_strings(np, "dma-names") < 0) ||
2770 (!of_find_property(np, "dmas", NULL))) {
2773 host->dma_ops = &dw_mci_edmac_ops;
2774 dev_info(host->dev, "Using external DMA controller.\n");
2777 if (host->dma_ops->init && host->dma_ops->start &&
2778 host->dma_ops->stop && host->dma_ops->cleanup) {
2779 if (host->dma_ops->init(host)) {
2780 dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n",
2785 dev_err(host->dev, "DMA initialization not found.\n");
2792 dev_info(host->dev, "Using PIO mode.\n");
2793 host->use_dma = TRANS_MODE_PIO;
2796 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
2798 unsigned long timeout = jiffies + msecs_to_jiffies(500);
2801 ctrl = mci_readl(host, CTRL);
2803 mci_writel(host, CTRL, ctrl);
2805 /* wait till resets clear */
2807 ctrl = mci_readl(host, CTRL);
2808 if (!(ctrl & reset))
2810 } while (time_before(jiffies, timeout));
2813 "Timeout resetting block (ctrl reset %#x)\n",
2819 static bool dw_mci_reset(struct dw_mci *host)
2821 u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
2825 * Reseting generates a block interrupt, hence setting
2826 * the scatter-gather pointer to NULL.
2829 sg_miter_stop(&host->sg_miter);
2834 flags |= SDMMC_CTRL_DMA_RESET;
2836 if (dw_mci_ctrl_reset(host, flags)) {
2838 * In all cases we clear the RAWINTS register to clear any
2841 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2843 /* if using dma we wait for dma_req to clear */
2844 if (host->use_dma) {
2845 unsigned long timeout = jiffies + msecs_to_jiffies(500);
2849 status = mci_readl(host, STATUS);
2850 if (!(status & SDMMC_STATUS_DMA_REQ))
2853 } while (time_before(jiffies, timeout));
2855 if (status & SDMMC_STATUS_DMA_REQ) {
2857 "%s: Timeout waiting for dma_req to clear during reset\n",
2862 /* when using DMA next we reset the fifo again */
2863 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
2867 /* if the controller reset bit did clear, then set clock regs */
2868 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
2870 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
2876 if (host->use_dma == TRANS_MODE_IDMAC)
2877 /* It is also recommended that we reset and reprogram idmac */
2878 dw_mci_idmac_reset(host);
2883 /* After a CTRL reset we need to have CIU set clock registers */
2884 mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0);
2889 static void dw_mci_cmd11_timer(unsigned long arg)
2891 struct dw_mci *host = (struct dw_mci *)arg;
2893 if (host->state != STATE_SENDING_CMD11) {
2894 dev_warn(host->dev, "Unexpected CMD11 timeout\n");
2898 host->cmd_status = SDMMC_INT_RTO;
2899 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2900 tasklet_schedule(&host->tasklet);
2903 static void dw_mci_dto_timer(unsigned long arg)
2905 struct dw_mci *host = (struct dw_mci *)arg;
2907 switch (host->state) {
2908 case STATE_SENDING_DATA:
2909 case STATE_DATA_BUSY:
2911 * If DTO interrupt does NOT come in sending data state,
2912 * we should notify the driver to terminate current transfer
2913 * and report a data timeout to the core.
2915 host->data_status = SDMMC_INT_DRTO;
2916 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2917 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2918 tasklet_schedule(&host->tasklet);
2926 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2928 struct dw_mci_board *pdata;
2929 struct device *dev = host->dev;
2930 struct device_node *np = dev->of_node;
2931 const struct dw_mci_drv_data *drv_data = host->drv_data;
2933 u32 clock_frequency;
2935 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2937 return ERR_PTR(-ENOMEM);
2939 /* find reset controller when exist */
2940 pdata->rstc = devm_reset_control_get_optional(dev, "reset");
2941 if (IS_ERR(pdata->rstc)) {
2942 if (PTR_ERR(pdata->rstc) == -EPROBE_DEFER)
2943 return ERR_PTR(-EPROBE_DEFER);
2946 /* find out number of slots supported */
2947 of_property_read_u32(np, "num-slots", &pdata->num_slots);
2949 if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
2951 "fifo-depth property not found, using value of FIFOTH register as default\n");
2953 of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
2955 if (!of_property_read_u32(np, "clock-frequency", &clock_frequency))
2956 pdata->bus_hz = clock_frequency;
2958 if (drv_data && drv_data->parse_dt) {
2959 ret = drv_data->parse_dt(host);
2961 return ERR_PTR(ret);
2967 #else /* CONFIG_OF */
2968 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2970 return ERR_PTR(-EINVAL);
2972 #endif /* CONFIG_OF */
2974 static void dw_mci_enable_cd(struct dw_mci *host)
2976 unsigned long irqflags;
2979 struct dw_mci_slot *slot;
2982 * No need for CD if all slots have a non-error GPIO
2983 * as well as broken card detection is found.
2985 for (i = 0; i < host->num_slots; i++) {
2986 slot = host->slot[i];
2987 if (slot->mmc->caps & MMC_CAP_NEEDS_POLL)
2990 if (mmc_gpio_get_cd(slot->mmc) < 0)
2993 if (i == host->num_slots)
2996 spin_lock_irqsave(&host->irq_lock, irqflags);
2997 temp = mci_readl(host, INTMASK);
2998 temp |= SDMMC_INT_CD;
2999 mci_writel(host, INTMASK, temp);
3000 spin_unlock_irqrestore(&host->irq_lock, irqflags);
3003 int dw_mci_probe(struct dw_mci *host)
3005 const struct dw_mci_drv_data *drv_data = host->drv_data;
3006 int width, i, ret = 0;
3011 host->pdata = dw_mci_parse_dt(host);
3012 if (PTR_ERR(host->pdata) == -EPROBE_DEFER) {
3013 return -EPROBE_DEFER;
3014 } else if (IS_ERR(host->pdata)) {
3015 dev_err(host->dev, "platform data not available\n");
3020 host->biu_clk = devm_clk_get(host->dev, "biu");
3021 if (IS_ERR(host->biu_clk)) {
3022 dev_dbg(host->dev, "biu clock not available\n");
3024 ret = clk_prepare_enable(host->biu_clk);
3026 dev_err(host->dev, "failed to enable biu clock\n");
3031 host->ciu_clk = devm_clk_get(host->dev, "ciu");
3032 if (IS_ERR(host->ciu_clk)) {
3033 dev_dbg(host->dev, "ciu clock not available\n");
3034 host->bus_hz = host->pdata->bus_hz;
3036 ret = clk_prepare_enable(host->ciu_clk);
3038 dev_err(host->dev, "failed to enable ciu clock\n");
3042 if (host->pdata->bus_hz) {
3043 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
3046 "Unable to set bus rate to %uHz\n",
3047 host->pdata->bus_hz);
3049 host->bus_hz = clk_get_rate(host->ciu_clk);
3052 if (!host->bus_hz) {
3054 "Platform data must supply bus speed\n");
3059 if (drv_data && drv_data->init) {
3060 ret = drv_data->init(host);
3063 "implementation specific init failed\n");
3068 if (!IS_ERR(host->pdata->rstc)) {
3069 reset_control_assert(host->pdata->rstc);
3070 usleep_range(10, 50);
3071 reset_control_deassert(host->pdata->rstc);
3074 setup_timer(&host->cmd11_timer,
3075 dw_mci_cmd11_timer, (unsigned long)host);
3077 setup_timer(&host->dto_timer,
3078 dw_mci_dto_timer, (unsigned long)host);
3080 spin_lock_init(&host->lock);
3081 spin_lock_init(&host->irq_lock);
3082 INIT_LIST_HEAD(&host->queue);
3085 * Get the host data width - this assumes that HCON has been set with
3086 * the correct values.
3088 i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));
3090 host->push_data = dw_mci_push_data16;
3091 host->pull_data = dw_mci_pull_data16;
3093 host->data_shift = 1;
3094 } else if (i == 2) {
3095 host->push_data = dw_mci_push_data64;
3096 host->pull_data = dw_mci_pull_data64;
3098 host->data_shift = 3;
3100 /* Check for a reserved value, and warn if it is */
3102 "HCON reports a reserved host data width!\n"
3103 "Defaulting to 32-bit access.\n");
3104 host->push_data = dw_mci_push_data32;
3105 host->pull_data = dw_mci_pull_data32;
3107 host->data_shift = 2;
3110 /* Reset all blocks */
3111 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3116 host->dma_ops = host->pdata->dma_ops;
3117 dw_mci_init_dma(host);
3119 /* Clear the interrupts for the host controller */
3120 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3121 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3123 /* Put in max timeout */
3124 mci_writel(host, TMOUT, 0xFFFFFFFF);
3127 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
3128 * Tx Mark = fifo_size / 2 DMA Size = 8
3130 if (!host->pdata->fifo_depth) {
3132 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
3133 * have been overwritten by the bootloader, just like we're
3134 * about to do, so if you know the value for your hardware, you
3135 * should put it in the platform data.
3137 fifo_size = mci_readl(host, FIFOTH);
3138 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
3140 fifo_size = host->pdata->fifo_depth;
3142 host->fifo_depth = fifo_size;
3144 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
3145 mci_writel(host, FIFOTH, host->fifoth_val);
3147 /* disable clock to CIU */
3148 mci_writel(host, CLKENA, 0);
3149 mci_writel(host, CLKSRC, 0);
3152 * In 2.40a spec, Data offset is changed.
3153 * Need to check the version-id and set data-offset for DATA register.
3155 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
3156 dev_info(host->dev, "Version ID is %04x\n", host->verid);
3158 if (host->verid < DW_MMC_240A)
3159 host->fifo_reg = host->regs + DATA_OFFSET;
3161 host->fifo_reg = host->regs + DATA_240A_OFFSET;
3163 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
3164 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
3165 host->irq_flags, "dw-mci", host);
3169 if (host->pdata->num_slots)
3170 host->num_slots = host->pdata->num_slots;
3172 host->num_slots = 1;
3174 if (host->num_slots < 1 ||
3175 host->num_slots > SDMMC_GET_SLOT_NUM(mci_readl(host, HCON))) {
3177 "Platform data must supply correct num_slots.\n");
3183 * Enable interrupts for command done, data over, data empty,
3184 * receive ready and error such as transmit, receive timeout, crc error
3186 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3187 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3188 DW_MCI_ERROR_FLAGS);
3189 /* Enable mci interrupt */
3190 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3193 "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n",
3194 host->irq, width, fifo_size);
3196 /* We need at least one slot to succeed */
3197 for (i = 0; i < host->num_slots; i++) {
3198 ret = dw_mci_init_slot(host, i);
3200 dev_dbg(host->dev, "slot %d init failed\n", i);
3206 dev_info(host->dev, "%d slots initialized\n", init_slots);
3209 "attempted to initialize %d slots, but failed on all\n",
3214 /* Now that slots are all setup, we can enable card detect */
3215 dw_mci_enable_cd(host);
3220 if (host->use_dma && host->dma_ops->exit)
3221 host->dma_ops->exit(host);
3223 if (!IS_ERR(host->pdata->rstc))
3224 reset_control_assert(host->pdata->rstc);
3227 clk_disable_unprepare(host->ciu_clk);
3230 clk_disable_unprepare(host->biu_clk);
3234 EXPORT_SYMBOL(dw_mci_probe);
3236 void dw_mci_remove(struct dw_mci *host)
3240 for (i = 0; i < host->num_slots; i++) {
3241 dev_dbg(host->dev, "remove slot %d\n", i);
3243 dw_mci_cleanup_slot(host->slot[i], i);
3246 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3247 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3249 /* disable clock to CIU */
3250 mci_writel(host, CLKENA, 0);
3251 mci_writel(host, CLKSRC, 0);
3253 if (host->use_dma && host->dma_ops->exit)
3254 host->dma_ops->exit(host);
3256 if (!IS_ERR(host->pdata->rstc))
3257 reset_control_assert(host->pdata->rstc);
3259 clk_disable_unprepare(host->ciu_clk);
3260 clk_disable_unprepare(host->biu_clk);
3262 EXPORT_SYMBOL(dw_mci_remove);
3267 int dw_mci_runtime_suspend(struct device *dev)
3269 struct dw_mci *host = dev_get_drvdata(dev);
3271 if (host->use_dma && host->dma_ops->exit)
3272 host->dma_ops->exit(host);
3274 clk_disable_unprepare(host->ciu_clk);
3276 if (host->cur_slot &&
3277 (mmc_can_gpio_cd(host->cur_slot->mmc) ||
3278 !mmc_card_is_removable(host->cur_slot->mmc)))
3279 clk_disable_unprepare(host->biu_clk);
3283 EXPORT_SYMBOL(dw_mci_runtime_suspend);
3285 int dw_mci_runtime_resume(struct device *dev)
3288 struct dw_mci *host = dev_get_drvdata(dev);
3290 if (host->cur_slot &&
3291 (mmc_can_gpio_cd(host->cur_slot->mmc) ||
3292 !mmc_card_is_removable(host->cur_slot->mmc))) {
3293 ret = clk_prepare_enable(host->biu_clk);
3298 ret = clk_prepare_enable(host->ciu_clk);
3302 if (host->use_dma && host->dma_ops->init)
3303 host->dma_ops->init(host);
3306 * Restore the initial value at FIFOTH register
3307 * And Invalidate the prev_blksz with zero
3309 mci_writel(host, FIFOTH, host->fifoth_val);
3310 host->prev_blksz = 0;
3312 /* Put in max timeout */
3313 mci_writel(host, TMOUT, 0xFFFFFFFF);
3315 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3316 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3317 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3318 DW_MCI_ERROR_FLAGS);
3319 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3321 for (i = 0; i < host->num_slots; i++) {
3322 struct dw_mci_slot *slot = host->slot[i];
3326 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
3327 dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
3328 dw_mci_setup_bus(slot, true);
3332 /* Now that slots are all setup, we can enable card detect */
3333 dw_mci_enable_cd(host);
3337 EXPORT_SYMBOL(dw_mci_runtime_resume);
3338 #endif /* CONFIG_PM */
3340 static int __init dw_mci_init(void)
3342 pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
3346 static void __exit dw_mci_exit(void)
3350 module_init(dw_mci_init);
3351 module_exit(dw_mci_exit);
3353 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
3354 MODULE_AUTHOR("NXP Semiconductor VietNam");
3355 MODULE_AUTHOR("Imagination Technologies Ltd");
3356 MODULE_LICENSE("GPL v2");