drivers/mmc/host/dw_mmc.c

   1 /*
   2  * Synopsys DesignWare Multimedia Card Interface driver
   3  *  (Based on NXP driver for lpc 31xx)
   4  *
   5  * Copyright (C) 2009 NXP Semiconductors
   6  * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/blkdev.h>
  15 #include <linux/clk.h>
  16 #include <linux/debugfs.h>
  17 #include <linux/device.h>
  18 #include <linux/dma-mapping.h>
  19 #include <linux/err.h>
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/iopoll.h>
  23 #include <linux/ioport.h>
  24 #include <linux/module.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/seq_file.h>
  28 #include <linux/slab.h>
  29 #include <linux/stat.h>
  30 #include <linux/delay.h>
  31 #include <linux/irq.h>
  32 #include <linux/mmc/card.h>
  33 #include <linux/mmc/host.h>
  34 #include <linux/mmc/mmc.h>
  35 #include <linux/mmc/sd.h>
  36 #include <linux/mmc/sdio.h>
  37 #include <linux/bitops.h>
  38 #include <linux/regulator/consumer.h>
  39 #include <linux/of.h>
  40 #include <linux/of_gpio.h>
  41 #include <linux/mmc/slot-gpio.h>
  42
  43 #include "dw_mmc.h"
  44
  45 /* Common flag combinations */
  46 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
  47                                  SDMMC_INT_HTO | SDMMC_INT_SBE  | \
  48                                  SDMMC_INT_EBE | SDMMC_INT_HLE)
  49 #define DW_MCI_CMD_ERROR_FLAGS  (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
  50                                  SDMMC_INT_RESP_ERR | SDMMC_INT_HLE)
  51 #define DW_MCI_ERROR_FLAGS      (DW_MCI_DATA_ERROR_FLAGS | \
  52                                  DW_MCI_CMD_ERROR_FLAGS)
  53 #define DW_MCI_SEND_STATUS      1
  54 #define DW_MCI_RECV_STATUS      2
  55 #define DW_MCI_DMA_THRESHOLD    16
  56
  57 #define DW_MCI_FREQ_MAX 200000000       /* unit: HZ */
  58 #define DW_MCI_FREQ_MIN 100000          /* unit: HZ */
  59
  60 #define IDMAC_INT_CLR           (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
  61                                  SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
  62                                  SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
  63                                  SDMMC_IDMAC_INT_TI)
  64
  65 #define DESC_RING_BUF_SZ        PAGE_SIZE
  66
  67 struct idmac_desc_64addr {
  68         u32             des0;   /* Control Descriptor */
  69 #define IDMAC_OWN_CLR64(x) \
  70         !((x) & cpu_to_le32(IDMAC_DES0_OWN))
  71
  72         u32             des1;   /* Reserved */
  73
  74         u32             des2;   /*Buffer sizes */
  75 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
  76         ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
  77          ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
  78
  79         u32             des3;   /* Reserved */
  80
  81         u32             des4;   /* Lower 32-bits of Buffer Address Pointer 1*/
  82         u32             des5;   /* Upper 32-bits of Buffer Address Pointer 1*/
  83
  84         u32             des6;   /* Lower 32-bits of Next Descriptor Address */
  85         u32             des7;   /* Upper 32-bits of Next Descriptor Address */
  86 };
  87
  88 struct idmac_desc {
  89         __le32          des0;   /* Control Descriptor */
  90 #define IDMAC_DES0_DIC  BIT(1)
  91 #define IDMAC_DES0_LD   BIT(2)
  92 #define IDMAC_DES0_FD   BIT(3)
  93 #define IDMAC_DES0_CH   BIT(4)
  94 #define IDMAC_DES0_ER   BIT(5)
  95 #define IDMAC_DES0_CES  BIT(30)
  96 #define IDMAC_DES0_OWN  BIT(31)
  97
  98         __le32          des1;   /* Buffer sizes */
  99 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
 100         ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff)))
 101
 102         __le32          des2;   /* buffer 1 physical address */
 103
 104         __le32          des3;   /* buffer 2 physical address */
 105 };
 106
 107 /* Each descriptor can transfer up to 4KB of data in chained mode */
 108 #define DW_MCI_DESC_DATA_LENGTH 0x1000
 109
 110 #if defined(CONFIG_DEBUG_FS)
 111 static int dw_mci_req_show(struct seq_file *s, void *v)
 112 {
 113         struct dw_mci_slot *slot = s->private;
 114         struct mmc_request *mrq;
 115         struct mmc_command *cmd;
 116         struct mmc_command *stop;
 117         struct mmc_data *data;
 118
 119         /* Make sure we get a consistent snapshot */
 120         spin_lock_bh(&slot->host->lock);
 121         mrq = slot->mrq;
 122
 123         if (mrq) {
 124                 cmd = mrq->cmd;
 125                 data = mrq->data;
 126                 stop = mrq->stop;
 127
 128                 if (cmd)
 129                         seq_printf(s,
 130                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 131                                    cmd->opcode, cmd->arg, cmd->flags,
 132                                    cmd->resp[0], cmd->resp[1], cmd->resp[2],
 133                                    cmd->resp[2], cmd->error);
 134                 if (data)
 135                         seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
 136                                    data->bytes_xfered, data->blocks,
 137                                    data->blksz, data->flags, data->error);
 138                 if (stop)
 139                         seq_printf(s,
 140                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 141                                    stop->opcode, stop->arg, stop->flags,
 142                                    stop->resp[0], stop->resp[1], stop->resp[2],
 143                                    stop->resp[2], stop->error);
 144         }
 145
 146         spin_unlock_bh(&slot->host->lock);
 147
 148         return 0;
 149 }
 150
 151 static int dw_mci_req_open(struct inode *inode, struct file *file)
 152 {
 153         return single_open(file, dw_mci_req_show, inode->i_private);
 154 }
 155
 156 static const struct file_operations dw_mci_req_fops = {
 157         .owner          = THIS_MODULE,
 158         .open           = dw_mci_req_open,
 159         .read           = seq_read,
 160         .llseek         = seq_lseek,
 161         .release        = single_release,
 162 };
 163
 164 static int dw_mci_regs_show(struct seq_file *s, void *v)
 165 {
 166         struct dw_mci *host = s->private;
 167
 168         seq_printf(s, "STATUS:\t0x%08x\n", mci_readl(host, STATUS));
 169         seq_printf(s, "RINTSTS:\t0x%08x\n", mci_readl(host, RINTSTS));
 170         seq_printf(s, "CMD:\t0x%08x\n", mci_readl(host, CMD));
 171         seq_printf(s, "CTRL:\t0x%08x\n", mci_readl(host, CTRL));
 172         seq_printf(s, "INTMASK:\t0x%08x\n", mci_readl(host, INTMASK));
 173         seq_printf(s, "CLKENA:\t0x%08x\n", mci_readl(host, CLKENA));
 174
 175         return 0;
 176 }
 177
 178 static int dw_mci_regs_open(struct inode *inode, struct file *file)
 179 {
 180         return single_open(file, dw_mci_regs_show, inode->i_private);
 181 }
 182
 183 static const struct file_operations dw_mci_regs_fops = {
 184         .owner          = THIS_MODULE,
 185         .open           = dw_mci_regs_open,
 186         .read           = seq_read,
 187         .llseek         = seq_lseek,
 188         .release        = single_release,
 189 };
 190
 191 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
 192 {
 193         struct mmc_host *mmc = slot->mmc;
 194         struct dw_mci *host = slot->host;
 195         struct dentry *root;
 196         struct dentry *node;
 197
 198         root = mmc->debugfs_root;
 199         if (!root)
 200                 return;
 201
 202         node = debugfs_create_file("regs", S_IRUSR, root, host,
 203                                    &dw_mci_regs_fops);
 204         if (!node)
 205                 goto err;
 206
 207         node = debugfs_create_file("req", S_IRUSR, root, slot,
 208                                    &dw_mci_req_fops);
 209         if (!node)
 210                 goto err;
 211
 212         node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
 213         if (!node)
 214                 goto err;
 215
 216         node = debugfs_create_x32("pending_events", S_IRUSR, root,
 217                                   (u32 *)&host->pending_events);
 218         if (!node)
 219                 goto err;
 220
 221         node = debugfs_create_x32("completed_events", S_IRUSR, root,
 222                                   (u32 *)&host->completed_events);
 223         if (!node)
 224                 goto err;
 225
 226         return;
 227
 228 err:
 229         dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
 230 }
 231 #endif /* defined(CONFIG_DEBUG_FS) */
 232
 233 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
 234 {
 235         u32 ctrl;
 236
 237         ctrl = mci_readl(host, CTRL);
 238         ctrl |= reset;
 239         mci_writel(host, CTRL, ctrl);
 240
 241         /* wait till resets clear */
 242         if (readl_poll_timeout_atomic(host->regs + SDMMC_CTRL, ctrl,
 243                                       !(ctrl & reset),
 244                                       1, 500 * USEC_PER_MSEC)) {
 245                 dev_err(host->dev,
 246                         "Timeout resetting block (ctrl reset %#x)\n",
 247                         ctrl & reset);
 248                 return false;
 249         }
 250
 251         return true;
 252 }
 253
 254 static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
 255 {
 256         u32 status;
 257
 258         /*
 259          * Databook says that before issuing a new data transfer command
 260          * we need to check to see if the card is busy.  Data transfer commands
 261          * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
 262          *
 263          * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
 264          * expected.
 265          */
 266         if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) &&
 267             !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) {
 268                 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
 269                                               status,
 270                                               !(status & SDMMC_STATUS_BUSY),
 271                                               10, 500 * USEC_PER_MSEC))
 272                         dev_err(host->dev, "Busy; trying anyway\n");
 273         }
 274 }
 275
 276 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
 277 {
 278         struct dw_mci *host = slot->host;
 279         unsigned int cmd_status = 0;
 280
 281         mci_writel(host, CMDARG, arg);
 282         wmb(); /* drain writebuffer */
 283         dw_mci_wait_while_busy(host, cmd);
 284         mci_writel(host, CMD, SDMMC_CMD_START | cmd);
 285
 286         if (readl_poll_timeout_atomic(host->regs + SDMMC_CMD, cmd_status,
 287                                       !(cmd_status & SDMMC_CMD_START),
 288                                       1, 500 * USEC_PER_MSEC))
 289                 dev_err(&slot->mmc->class_dev,
 290                         "Timeout sending command (cmd %#x arg %#x status %#x)\n",
 291                         cmd, arg, cmd_status);
 292 }
 293
 294 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
 295 {
 296         struct dw_mci_slot *slot = mmc_priv(mmc);
 297         struct dw_mci *host = slot->host;
 298         u32 cmdr;
 299
 300         cmd->error = -EINPROGRESS;
 301         cmdr = cmd->opcode;
 302
 303         if (cmd->opcode == MMC_STOP_TRANSMISSION ||
 304             cmd->opcode == MMC_GO_IDLE_STATE ||
 305             cmd->opcode == MMC_GO_INACTIVE_STATE ||
 306             (cmd->opcode == SD_IO_RW_DIRECT &&
 307              ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
 308                 cmdr |= SDMMC_CMD_STOP;
 309         else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
 310                 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
 311
 312         if (cmd->opcode == SD_SWITCH_VOLTAGE) {
 313                 u32 clk_en_a;
 314
 315                 /* Special bit makes CMD11 not die */
 316                 cmdr |= SDMMC_CMD_VOLT_SWITCH;
 317
 318                 /* Change state to continue to handle CMD11 weirdness */
 319                 WARN_ON(slot->host->state != STATE_SENDING_CMD);
 320                 slot->host->state = STATE_SENDING_CMD11;
 321
 322                 /*
 323                  * We need to disable low power mode (automatic clock stop)
 324                  * while doing voltage switch so we don't confuse the card,
 325                  * since stopping the clock is a specific part of the UHS
 326                  * voltage change dance.
 327                  *
 328                  * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
 329                  * unconditionally turned back on in dw_mci_setup_bus() if it's
 330                  * ever called with a non-zero clock.  That shouldn't happen
 331                  * until the voltage change is all done.
 332                  */
 333                 clk_en_a = mci_readl(host, CLKENA);
 334                 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
 335                 mci_writel(host, CLKENA, clk_en_a);
 336                 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
 337                              SDMMC_CMD_PRV_DAT_WAIT, 0);
 338         }
 339
 340         if (cmd->flags & MMC_RSP_PRESENT) {
 341                 /* We expect a response, so set this bit */
 342                 cmdr |= SDMMC_CMD_RESP_EXP;
 343                 if (cmd->flags & MMC_RSP_136)
 344                         cmdr |= SDMMC_CMD_RESP_LONG;
 345         }
 346
 347         if (cmd->flags & MMC_RSP_CRC)
 348                 cmdr |= SDMMC_CMD_RESP_CRC;
 349
 350         if (cmd->data) {
 351                 cmdr |= SDMMC_CMD_DAT_EXP;
 352                 if (cmd->data->flags & MMC_DATA_WRITE)
 353                         cmdr |= SDMMC_CMD_DAT_WR;
 354         }
 355
 356         if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags))
 357                 cmdr |= SDMMC_CMD_USE_HOLD_REG;
 358
 359         return cmdr;
 360 }
 361
 362 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
 363 {
 364         struct mmc_command *stop;
 365         u32 cmdr;
 366
 367         if (!cmd->data)
 368                 return 0;
 369
 370         stop = &host->stop_abort;
 371         cmdr = cmd->opcode;
 372         memset(stop, 0, sizeof(struct mmc_command));
 373
 374         if (cmdr == MMC_READ_SINGLE_BLOCK ||
 375             cmdr == MMC_READ_MULTIPLE_BLOCK ||
 376             cmdr == MMC_WRITE_BLOCK ||
 377             cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
 378             cmdr == MMC_SEND_TUNING_BLOCK ||
 379             cmdr == MMC_SEND_TUNING_BLOCK_HS200) {
 380                 stop->opcode = MMC_STOP_TRANSMISSION;
 381                 stop->arg = 0;
 382                 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
 383         } else if (cmdr == SD_IO_RW_EXTENDED) {
 384                 stop->opcode = SD_IO_RW_DIRECT;
 385                 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
 386                              ((cmd->arg >> 28) & 0x7);
 387                 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
 388         } else {
 389                 return 0;
 390         }
 391
 392         cmdr = stop->opcode | SDMMC_CMD_STOP |
 393                 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
 394
 395         if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &host->cur_slot->flags))
 396                 cmdr |= SDMMC_CMD_USE_HOLD_REG;
 397
 398         return cmdr;
 399 }
 400
 401 static void dw_mci_start_command(struct dw_mci *host,
 402                                  struct mmc_command *cmd, u32 cmd_flags)
 403 {
 404         host->cmd = cmd;
 405         dev_vdbg(host->dev,
 406                  "start command: ARGR=0x%08x CMDR=0x%08x\n",
 407                  cmd->arg, cmd_flags);
 408
 409         mci_writel(host, CMDARG, cmd->arg);
 410         wmb(); /* drain writebuffer */
 411         dw_mci_wait_while_busy(host, cmd_flags);
 412
 413         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
 414 }
 415
 416 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
 417 {
 418         struct mmc_command *stop = &host->stop_abort;
 419
 420         dw_mci_start_command(host, stop, host->stop_cmdr);
 421 }
 422
 423 /* DMA interface functions */
 424 static void dw_mci_stop_dma(struct dw_mci *host)
 425 {
 426         if (host->using_dma) {
 427                 host->dma_ops->stop(host);
 428                 host->dma_ops->cleanup(host);
 429         }
 430
 431         /* Data transfer was stopped by the interrupt handler */
 432         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 433 }
 434
 435 static void dw_mci_dma_cleanup(struct dw_mci *host)
 436 {
 437         struct mmc_data *data = host->data;
 438
 439         if (data && data->host_cookie == COOKIE_MAPPED) {
 440                 dma_unmap_sg(host->dev,
 441                              data->sg,
 442                              data->sg_len,
 443                              mmc_get_dma_dir(data));
 444                 data->host_cookie = COOKIE_UNMAPPED;
 445         }
 446 }
 447
 448 static void dw_mci_idmac_reset(struct dw_mci *host)
 449 {
 450         u32 bmod = mci_readl(host, BMOD);
 451         /* Software reset of DMA */
 452         bmod |= SDMMC_IDMAC_SWRESET;
 453         mci_writel(host, BMOD, bmod);
 454 }
 455
 456 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
 457 {
 458         u32 temp;
 459
 460         /* Disable and reset the IDMAC interface */
 461         temp = mci_readl(host, CTRL);
 462         temp &= ~SDMMC_CTRL_USE_IDMAC;
 463         temp |= SDMMC_CTRL_DMA_RESET;
 464         mci_writel(host, CTRL, temp);
 465
 466         /* Stop the IDMAC running */
 467         temp = mci_readl(host, BMOD);
 468         temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
 469         temp |= SDMMC_IDMAC_SWRESET;
 470         mci_writel(host, BMOD, temp);
 471 }
 472
 473 static void dw_mci_dmac_complete_dma(void *arg)
 474 {
 475         struct dw_mci *host = arg;
 476         struct mmc_data *data = host->data;
 477
 478         dev_vdbg(host->dev, "DMA complete\n");
 479
 480         if ((host->use_dma == TRANS_MODE_EDMAC) &&
 481             data && (data->flags & MMC_DATA_READ))
 482                 /* Invalidate cache after read */
 483                 dma_sync_sg_for_cpu(mmc_dev(host->cur_slot->mmc),
 484                                     data->sg,
 485                                     data->sg_len,
 486                                     DMA_FROM_DEVICE);
 487
 488         host->dma_ops->cleanup(host);
 489
 490         /*
 491          * If the card was removed, data will be NULL. No point in trying to
 492          * send the stop command or waiting for NBUSY in this case.
 493          */
 494         if (data) {
 495                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 496                 tasklet_schedule(&host->tasklet);
 497         }
 498 }
 499
 500 static int dw_mci_idmac_init(struct dw_mci *host)
 501 {
 502         int i;
 503
 504         if (host->dma_64bit_address == 1) {
 505                 struct idmac_desc_64addr *p;
 506                 /* Number of descriptors in the ring buffer */
 507                 host->ring_size =
 508                         DESC_RING_BUF_SZ / sizeof(struct idmac_desc_64addr);
 509
 510                 /* Forward link the descriptor list */
 511                 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
 512                                                                 i++, p++) {
 513                         p->des6 = (host->sg_dma +
 514                                         (sizeof(struct idmac_desc_64addr) *
 515                                                         (i + 1))) & 0xffffffff;
 516
 517                         p->des7 = (u64)(host->sg_dma +
 518                                         (sizeof(struct idmac_desc_64addr) *
 519                                                         (i + 1))) >> 32;
 520                         /* Initialize reserved and buffer size fields to "0" */
 521                         p->des1 = 0;
 522                         p->des2 = 0;
 523                         p->des3 = 0;
 524                 }
 525
 526                 /* Set the last descriptor as the end-of-ring descriptor */
 527                 p->des6 = host->sg_dma & 0xffffffff;
 528                 p->des7 = (u64)host->sg_dma >> 32;
 529                 p->des0 = IDMAC_DES0_ER;
 530
 531         } else {
 532                 struct idmac_desc *p;
 533                 /* Number of descriptors in the ring buffer */
 534                 host->ring_size =
 535                         DESC_RING_BUF_SZ / sizeof(struct idmac_desc);
 536
 537                 /* Forward link the descriptor list */
 538                 for (i = 0, p = host->sg_cpu;
 539                      i < host->ring_size - 1;
 540                      i++, p++) {
 541                         p->des3 = cpu_to_le32(host->sg_dma +
 542                                         (sizeof(struct idmac_desc) * (i + 1)));
 543                         p->des1 = 0;
 544                 }
 545
 546                 /* Set the last descriptor as the end-of-ring descriptor */
 547                 p->des3 = cpu_to_le32(host->sg_dma);
 548                 p->des0 = cpu_to_le32(IDMAC_DES0_ER);
 549         }
 550
 551         dw_mci_idmac_reset(host);
 552
 553         if (host->dma_64bit_address == 1) {
 554                 /* Mask out interrupts - get Tx & Rx complete only */
 555                 mci_writel(host, IDSTS64, IDMAC_INT_CLR);
 556                 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
 557                                 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
 558
 559                 /* Set the descriptor base address */
 560                 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
 561                 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
 562
 563         } else {
 564                 /* Mask out interrupts - get Tx & Rx complete only */
 565                 mci_writel(host, IDSTS, IDMAC_INT_CLR);
 566                 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
 567                                 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
 568
 569                 /* Set the descriptor base address */
 570                 mci_writel(host, DBADDR, host->sg_dma);
 571         }
 572
 573         return 0;
 574 }
 575
 576 static inline int dw_mci_prepare_desc64(struct dw_mci *host,
 577                                          struct mmc_data *data,
 578                                          unsigned int sg_len)
 579 {
 580         unsigned int desc_len;
 581         struct idmac_desc_64addr *desc_first, *desc_last, *desc;
 582         u32 val;
 583         int i;
 584
 585         desc_first = desc_last = desc = host->sg_cpu;
 586
 587         for (i = 0; i < sg_len; i++) {
 588                 unsigned int length = sg_dma_len(&data->sg[i]);
 589
 590                 u64 mem_addr = sg_dma_address(&data->sg[i]);
 591
 592                 for ( ; length ; desc++) {
 593                         desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
 594                                    length : DW_MCI_DESC_DATA_LENGTH;
 595
 596                         length -= desc_len;
 597
 598                         /*
 599                          * Wait for the former clear OWN bit operation
 600                          * of IDMAC to make sure that this descriptor
 601                          * isn't still owned by IDMAC as IDMAC's write
 602                          * ops and CPU's read ops are asynchronous.
 603                          */
 604                         if (readl_poll_timeout_atomic(&desc->des0, val,
 605                                                 !(val & IDMAC_DES0_OWN),
 606                                                 10, 100 * USEC_PER_MSEC))
 607                                 goto err_own_bit;
 608
 609                         /*
 610                          * Set the OWN bit and disable interrupts
 611                          * for this descriptor
 612                          */
 613                         desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
 614                                                 IDMAC_DES0_CH;
 615
 616                         /* Buffer length */
 617                         IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len);
 618
 619                         /* Physical address to DMA to/from */
 620                         desc->des4 = mem_addr & 0xffffffff;
 621                         desc->des5 = mem_addr >> 32;
 622
 623                         /* Update physical address for the next desc */
 624                         mem_addr += desc_len;
 625
 626                         /* Save pointer to the last descriptor */
 627                         desc_last = desc;
 628                 }
 629         }
 630
 631         /* Set first descriptor */
 632         desc_first->des0 |= IDMAC_DES0_FD;
 633
 634         /* Set last descriptor */
 635         desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
 636         desc_last->des0 |= IDMAC_DES0_LD;
 637
 638         return 0;
 639 err_own_bit:
 640         /* restore the descriptor chain as it's polluted */
 641         dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
 642         memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
 643         dw_mci_idmac_init(host);
 644         return -EINVAL;
 645 }
 646
 647
 648 static inline int dw_mci_prepare_desc32(struct dw_mci *host,
 649                                          struct mmc_data *data,
 650                                          unsigned int sg_len)
 651 {
 652         unsigned int desc_len;
 653         struct idmac_desc *desc_first, *desc_last, *desc;
 654         u32 val;
 655         int i;
 656
 657         desc_first = desc_last = desc = host->sg_cpu;
 658
 659         for (i = 0; i < sg_len; i++) {
 660                 unsigned int length = sg_dma_len(&data->sg[i]);
 661
 662                 u32 mem_addr = sg_dma_address(&data->sg[i]);
 663
 664                 for ( ; length ; desc++) {
 665                         desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
 666                                    length : DW_MCI_DESC_DATA_LENGTH;
 667
 668                         length -= desc_len;
 669
 670                         /*
 671                          * Wait for the former clear OWN bit operation
 672                          * of IDMAC to make sure that this descriptor
 673                          * isn't still owned by IDMAC as IDMAC's write
 674                          * ops and CPU's read ops are asynchronous.
 675                          */
 676                         if (readl_poll_timeout_atomic(&desc->des0, val,
 677                                                       IDMAC_OWN_CLR64(val),
 678                                                       10,
 679                                                       100 * USEC_PER_MSEC))
 680                                 goto err_own_bit;
 681
 682                         /*
 683                          * Set the OWN bit and disable interrupts
 684                          * for this descriptor
 685                          */
 686                         desc->des0 = cpu_to_le32(IDMAC_DES0_OWN |
 687                                                  IDMAC_DES0_DIC |
 688                                                  IDMAC_DES0_CH);
 689
 690                         /* Buffer length */
 691                         IDMAC_SET_BUFFER1_SIZE(desc, desc_len);
 692
 693                         /* Physical address to DMA to/from */
 694                         desc->des2 = cpu_to_le32(mem_addr);
 695
 696                         /* Update physical address for the next desc */
 697                         mem_addr += desc_len;
 698
 699                         /* Save pointer to the last descriptor */
 700                         desc_last = desc;
 701                 }
 702         }
 703
 704         /* Set first descriptor */
 705         desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD);
 706
 707         /* Set last descriptor */
 708         desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH |
 709                                        IDMAC_DES0_DIC));
 710         desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD);
 711
 712         return 0;
 713 err_own_bit:
 714         /* restore the descriptor chain as it's polluted */
 715         dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
 716         memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
 717         dw_mci_idmac_init(host);
 718         return -EINVAL;
 719 }
 720
 721 static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
 722 {
 723         u32 temp;
 724         int ret;
 725
 726         if (host->dma_64bit_address == 1)
 727                 ret = dw_mci_prepare_desc64(host, host->data, sg_len);
 728         else
 729                 ret = dw_mci_prepare_desc32(host, host->data, sg_len);
 730
 731         if (ret)
 732                 goto out;
 733
 734         /* drain writebuffer */
 735         wmb();
 736
 737         /* Make sure to reset DMA in case we did PIO before this */
 738         dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
 739         dw_mci_idmac_reset(host);
 740
 741         /* Select IDMAC interface */
 742         temp = mci_readl(host, CTRL);
 743         temp |= SDMMC_CTRL_USE_IDMAC;
 744         mci_writel(host, CTRL, temp);
 745
 746         /* drain writebuffer */
 747         wmb();
 748
 749         /* Enable the IDMAC */
 750         temp = mci_readl(host, BMOD);
 751         temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
 752         mci_writel(host, BMOD, temp);
 753
 754         /* Start it running */
 755         mci_writel(host, PLDMND, 1);
 756
 757 out:
 758         return ret;
 759 }
 760
 761 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
 762         .init = dw_mci_idmac_init,
 763         .start = dw_mci_idmac_start_dma,
 764         .stop = dw_mci_idmac_stop_dma,
 765         .complete = dw_mci_dmac_complete_dma,
 766         .cleanup = dw_mci_dma_cleanup,
 767 };
 768
 769 static void dw_mci_edmac_stop_dma(struct dw_mci *host)
 770 {
 771         dmaengine_terminate_async(host->dms->ch);
 772 }
 773
 774 static int dw_mci_edmac_start_dma(struct dw_mci *host,
 775                                             unsigned int sg_len)
 776 {
 777         struct dma_slave_config cfg;
 778         struct dma_async_tx_descriptor *desc = NULL;
 779         struct scatterlist *sgl = host->data->sg;
 780         const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
 781         u32 sg_elems = host->data->sg_len;
 782         u32 fifoth_val;
 783         u32 fifo_offset = host->fifo_reg - host->regs;
 784         int ret = 0;
 785
 786         /* Set external dma config: burst size, burst width */
 787         cfg.dst_addr = host->phy_regs + fifo_offset;
 788         cfg.src_addr = cfg.dst_addr;
 789         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 790         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 791
 792         /* Match burst msize with external dma config */
 793         fifoth_val = mci_readl(host, FIFOTH);
 794         cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7];
 795         cfg.src_maxburst = cfg.dst_maxburst;
 796
 797         if (host->data->flags & MMC_DATA_WRITE)
 798                 cfg.direction = DMA_MEM_TO_DEV;
 799         else
 800                 cfg.direction = DMA_DEV_TO_MEM;
 801
 802         ret = dmaengine_slave_config(host->dms->ch, &cfg);
 803         if (ret) {
 804                 dev_err(host->dev, "Failed to config edmac.\n");
 805                 return -EBUSY;
 806         }
 807
 808         desc = dmaengine_prep_slave_sg(host->dms->ch, sgl,
 809                                        sg_len, cfg.direction,
 810                                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 811         if (!desc) {
 812                 dev_err(host->dev, "Can't prepare slave sg.\n");
 813                 return -EBUSY;
 814         }
 815
 816         /* Set dw_mci_dmac_complete_dma as callback */
 817         desc->callback = dw_mci_dmac_complete_dma;
 818         desc->callback_param = (void *)host;
 819         dmaengine_submit(desc);
 820
 821         /* Flush cache before write */
 822         if (host->data->flags & MMC_DATA_WRITE)
 823                 dma_sync_sg_for_device(mmc_dev(host->cur_slot->mmc), sgl,
 824                                        sg_elems, DMA_TO_DEVICE);
 825
 826         dma_async_issue_pending(host->dms->ch);
 827
 828         return 0;
 829 }
 830
 831 static int dw_mci_edmac_init(struct dw_mci *host)
 832 {
 833         /* Request external dma channel */
 834         host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
 835         if (!host->dms)
 836                 return -ENOMEM;
 837
 838         host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx");
 839         if (!host->dms->ch) {
 840                 dev_err(host->dev, "Failed to get external DMA channel.\n");
 841                 kfree(host->dms);
 842                 host->dms = NULL;
 843                 return -ENXIO;
 844         }
 845
 846         return 0;
 847 }
 848
 849 static void dw_mci_edmac_exit(struct dw_mci *host)
 850 {
 851         if (host->dms) {
 852                 if (host->dms->ch) {
 853                         dma_release_channel(host->dms->ch);
 854                         host->dms->ch = NULL;
 855                 }
 856                 kfree(host->dms);
 857                 host->dms = NULL;
 858         }
 859 }
 860
 861 static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
 862         .init = dw_mci_edmac_init,
 863         .exit = dw_mci_edmac_exit,
 864         .start = dw_mci_edmac_start_dma,
 865         .stop = dw_mci_edmac_stop_dma,
 866         .complete = dw_mci_dmac_complete_dma,
 867         .cleanup = dw_mci_dma_cleanup,
 868 };
 869
 870 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
 871                                    struct mmc_data *data,
 872                                    int cookie)
 873 {
 874         struct scatterlist *sg;
 875         unsigned int i, sg_len;
 876
 877         if (data->host_cookie == COOKIE_PRE_MAPPED)
 878                 return data->sg_len;
 879
 880         /*
 881          * We don't do DMA on "complex" transfers, i.e. with
 882          * non-word-aligned buffers or lengths. Also, we don't bother
 883          * with all the DMA setup overhead for short transfers.
 884          */
 885         if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
 886                 return -EINVAL;
 887
 888         if (data->blksz & 3)
 889                 return -EINVAL;
 890
 891         for_each_sg(data->sg, sg, data->sg_len, i) {
 892                 if (sg->offset & 3 || sg->length & 3)
 893                         return -EINVAL;
 894         }
 895
 896         sg_len = dma_map_sg(host->dev,
 897                             data->sg,
 898                             data->sg_len,
 899                             mmc_get_dma_dir(data));
 900         if (sg_len == 0)
 901                 return -EINVAL;
 902
 903         data->host_cookie = cookie;
 904
 905         return sg_len;
 906 }
 907
 908 static void dw_mci_pre_req(struct mmc_host *mmc,
 909                            struct mmc_request *mrq)
 910 {
 911         struct dw_mci_slot *slot = mmc_priv(mmc);
 912         struct mmc_data *data = mrq->data;
 913
 914         if (!slot->host->use_dma || !data)
 915                 return;
 916
 917         /* This data might be unmapped at this time */
 918         data->host_cookie = COOKIE_UNMAPPED;
 919
 920         if (dw_mci_pre_dma_transfer(slot->host, mrq->data,
 921                                 COOKIE_PRE_MAPPED) < 0)
 922                 data->host_cookie = COOKIE_UNMAPPED;
 923 }
 924
 925 static void dw_mci_post_req(struct mmc_host *mmc,
 926                             struct mmc_request *mrq,
 927                             int err)
 928 {
 929         struct dw_mci_slot *slot = mmc_priv(mmc);
 930         struct mmc_data *data = mrq->data;
 931
 932         if (!slot->host->use_dma || !data)
 933                 return;
 934
 935         if (data->host_cookie != COOKIE_UNMAPPED)
 936                 dma_unmap_sg(slot->host->dev,
 937                              data->sg,
 938                              data->sg_len,
 939                              mmc_get_dma_dir(data));
 940         data->host_cookie = COOKIE_UNMAPPED;
 941 }
 942
 943 static int dw_mci_get_cd(struct mmc_host *mmc)
 944 {
 945         int present;
 946         struct dw_mci_slot *slot = mmc_priv(mmc);
 947         struct dw_mci *host = slot->host;
 948         int gpio_cd = mmc_gpio_get_cd(mmc);
 949
 950         /* Use platform get_cd function, else try onboard card detect */
 951         if (((mmc->caps & MMC_CAP_NEEDS_POLL)
 952                                 || !mmc_card_is_removable(mmc))) {
 953                 present = 1;
 954
 955                 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
 956                         if (mmc->caps & MMC_CAP_NEEDS_POLL) {
 957                                 dev_info(&mmc->class_dev,
 958                                         "card is polling.\n");
 959                         } else {
 960                                 dev_info(&mmc->class_dev,
 961                                         "card is non-removable.\n");
 962                         }
 963                         set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
 964                 }
 965
 966                 return present;
 967         } else if (gpio_cd >= 0)
 968                 present = gpio_cd;
 969         else
 970                 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
 971                         == 0 ? 1 : 0;
 972
 973         spin_lock_bh(&host->lock);
 974         if (present && !test_and_set_bit(DW_MMC_CARD_PRESENT, &slot->flags))
 975                 dev_dbg(&mmc->class_dev, "card is present\n");
 976         else if (!present &&
 977                         !test_and_clear_bit(DW_MMC_CARD_PRESENT, &slot->flags))
 978                 dev_dbg(&mmc->class_dev, "card is not present\n");
 979         spin_unlock_bh(&host->lock);
 980
 981         return present;
 982 }
 983
 984 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
 985 {
 986         unsigned int blksz = data->blksz;
 987         const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
 988         u32 fifo_width = 1 << host->data_shift;
 989         u32 blksz_depth = blksz / fifo_width, fifoth_val;
 990         u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
 991         int idx = ARRAY_SIZE(mszs) - 1;
 992
 993         /* pio should ship this scenario */
 994         if (!host->use_dma)
 995                 return;
 996
 997         tx_wmark = (host->fifo_depth) / 2;
 998         tx_wmark_invers = host->fifo_depth - tx_wmark;
 999
1000         /*
1001          * MSIZE is '1',
1002          * if blksz is not a multiple of the FIFO width
1003          */
1004         if (blksz % fifo_width)
1005                 goto done;
1006
1007         do {
1008                 if (!((blksz_depth % mszs[idx]) ||
1009                      (tx_wmark_invers % mszs[idx]))) {
1010                         msize = idx;
1011                         rx_wmark = mszs[idx] - 1;
1012                         break;
1013                 }
1014         } while (--idx > 0);
1015         /*
1016          * If idx is '0', it won't be tried
1017          * Thus, initial values are uesed
1018          */
1019 done:
1020         fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
1021         mci_writel(host, FIFOTH, fifoth_val);
1022 }
1023
1024 static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data)
1025 {
1026         unsigned int blksz = data->blksz;
1027         u32 blksz_depth, fifo_depth;
1028         u16 thld_size;
1029         u8 enable;
1030
1031         /*
1032          * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
1033          * in the FIFO region, so we really shouldn't access it).
1034          */
1035         if (host->verid < DW_MMC_240A ||
1036                 (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE))
1037                 return;
1038
1039         /*
1040          * Card write Threshold is introduced since 2.80a
1041          * It's used when HS400 mode is enabled.
1042          */
1043         if (data->flags & MMC_DATA_WRITE &&
1044                 !(host->timing != MMC_TIMING_MMC_HS400))
1045                 return;
1046
1047         if (data->flags & MMC_DATA_WRITE)
1048                 enable = SDMMC_CARD_WR_THR_EN;
1049         else
1050                 enable = SDMMC_CARD_RD_THR_EN;
1051
1052         if (host->timing != MMC_TIMING_MMC_HS200 &&
1053             host->timing != MMC_TIMING_UHS_SDR104)
1054                 goto disable;
1055
1056         blksz_depth = blksz / (1 << host->data_shift);
1057         fifo_depth = host->fifo_depth;
1058
1059         if (blksz_depth > fifo_depth)
1060                 goto disable;
1061
1062         /*
1063          * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
1064          * If (blksz_depth) <  (fifo_depth >> 1), should be thld_size = blksz
1065          * Currently just choose blksz.
1066          */
1067         thld_size = blksz;
1068         mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable));
1069         return;
1070
1071 disable:
1072         mci_writel(host, CDTHRCTL, 0);
1073 }
1074
1075 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
1076 {
1077         unsigned long irqflags;
1078         int sg_len;
1079         u32 temp;
1080
1081         host->using_dma = 0;
1082
1083         /* If we don't have a channel, we can't do DMA */
1084         if (!host->use_dma)
1085                 return -ENODEV;
1086
1087         sg_len = dw_mci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1088         if (sg_len < 0) {
1089                 host->dma_ops->stop(host);
1090                 return sg_len;
1091         }
1092
1093         host->using_dma = 1;
1094
1095         if (host->use_dma == TRANS_MODE_IDMAC)
1096                 dev_vdbg(host->dev,
1097                          "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
1098                          (unsigned long)host->sg_cpu,
1099                          (unsigned long)host->sg_dma,
1100                          sg_len);
1101
1102         /*
1103          * Decide the MSIZE and RX/TX Watermark.
1104          * If current block size is same with previous size,
1105          * no need to update fifoth.
1106          */
1107         if (host->prev_blksz != data->blksz)
1108                 dw_mci_adjust_fifoth(host, data);
1109
1110         /* Enable the DMA interface */
1111         temp = mci_readl(host, CTRL);
1112         temp |= SDMMC_CTRL_DMA_ENABLE;
1113         mci_writel(host, CTRL, temp);
1114
1115         /* Disable RX/TX IRQs, let DMA handle it */
1116         spin_lock_irqsave(&host->irq_lock, irqflags);
1117         temp = mci_readl(host, INTMASK);
1118         temp  &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
1119         mci_writel(host, INTMASK, temp);
1120         spin_unlock_irqrestore(&host->irq_lock, irqflags);
1121
1122         if (host->dma_ops->start(host, sg_len)) {
1123                 host->dma_ops->stop(host);
1124                 /* We can't do DMA, try PIO for this one */
1125                 dev_dbg(host->dev,
1126                         "%s: fall back to PIO mode for current transfer\n",
1127                         __func__);
1128                 return -ENODEV;
1129         }
1130
1131         return 0;
1132 }
1133
1134 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
1135 {
1136         unsigned long irqflags;
1137         int flags = SG_MITER_ATOMIC;
1138         u32 temp;
1139
1140         data->error = -EINPROGRESS;
1141
1142         WARN_ON(host->data);
1143         host->sg = NULL;
1144         host->data = data;
1145
1146         if (data->flags & MMC_DATA_READ)
1147                 host->dir_status = DW_MCI_RECV_STATUS;
1148         else
1149                 host->dir_status = DW_MCI_SEND_STATUS;
1150
1151         dw_mci_ctrl_thld(host, data);
1152
1153         if (dw_mci_submit_data_dma(host, data)) {
1154                 if (host->data->flags & MMC_DATA_READ)
1155                         flags |= SG_MITER_TO_SG;
1156                 else
1157                         flags |= SG_MITER_FROM_SG;
1158
1159                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1160                 host->sg = data->sg;
1161                 host->part_buf_start = 0;
1162                 host->part_buf_count = 0;
1163
1164                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
1165
1166                 spin_lock_irqsave(&host->irq_lock, irqflags);
1167                 temp = mci_readl(host, INTMASK);
1168                 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
1169                 mci_writel(host, INTMASK, temp);
1170                 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1171
1172                 temp = mci_readl(host, CTRL);
1173                 temp &= ~SDMMC_CTRL_DMA_ENABLE;
1174                 mci_writel(host, CTRL, temp);
1175
1176                 /*
1177                  * Use the initial fifoth_val for PIO mode. If wm_algined
1178                  * is set, we set watermark same as data size.
1179                  * If next issued data may be transfered by DMA mode,
1180                  * prev_blksz should be invalidated.
1181                  */
1182                 if (host->wm_aligned)
1183                         dw_mci_adjust_fifoth(host, data);
1184                 else
1185                         mci_writel(host, FIFOTH, host->fifoth_val);
1186                 host->prev_blksz = 0;
1187         } else {
1188                 /*
1189                  * Keep the current block size.
1190                  * It will be used to decide whether to update
1191                  * fifoth register next time.
1192                  */
1193                 host->prev_blksz = data->blksz;
1194         }
1195 }
1196
1197 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
1198 {
1199         struct dw_mci *host = slot->host;
1200         unsigned int clock = slot->clock;
1201         u32 div;
1202         u32 clk_en_a;
1203         u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
1204
1205         /* We must continue to set bit 28 in CMD until the change is complete */
1206         if (host->state == STATE_WAITING_CMD11_DONE)
1207                 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
1208
1209         if (!clock) {
1210                 mci_writel(host, CLKENA, 0);
1211                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1212         } else if (clock != host->current_speed || force_clkinit) {
1213                 div = host->bus_hz / clock;
1214                 if (host->bus_hz % clock && host->bus_hz > clock)
1215                         /*
1216                          * move the + 1 after the divide to prevent
1217                          * over-clocking the card.
1218                          */
1219                         div += 1;
1220
1221                 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
1222
1223                 if ((clock != slot->__clk_old &&
1224                         !test_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags)) ||
1225                         force_clkinit) {
1226                         /* Silent the verbose log if calling from PM context */
1227                         if (!force_clkinit)
1228                                 dev_info(&slot->mmc->class_dev,
1229                                          "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1230                                          slot->id, host->bus_hz, clock,
1231                                          div ? ((host->bus_hz / div) >> 1) :
1232                                          host->bus_hz, div);
1233
1234                         /*
1235                          * If card is polling, display the message only
1236                          * one time at boot time.
1237                          */
1238                         if (slot->mmc->caps & MMC_CAP_NEEDS_POLL &&
1239                                         slot->mmc->f_min == clock)
1240                                 set_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags);
1241                 }
1242
1243                 /* disable clock */
1244                 mci_writel(host, CLKENA, 0);
1245                 mci_writel(host, CLKSRC, 0);
1246
1247                 /* inform CIU */
1248                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1249
1250                 /* set clock to desired speed */
1251                 mci_writel(host, CLKDIV, div);
1252
1253                 /* inform CIU */
1254                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1255
1256                 /* enable clock; only low power if no SDIO */
1257                 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
1258                 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
1259                         clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1260                 mci_writel(host, CLKENA, clk_en_a);
1261
1262                 /* inform CIU */
1263                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1264
1265                 /* keep the last clock value that was requested from core */
1266                 slot->__clk_old = clock;
1267         }
1268
1269         host->current_speed = clock;
1270
1271         /* Set the current slot bus width */
1272         mci_writel(host, CTYPE, (slot->ctype << slot->id));
1273 }
1274
1275 static void __dw_mci_start_request(struct dw_mci *host,
1276                                    struct dw_mci_slot *slot,
1277                                    struct mmc_command *cmd)
1278 {
1279         struct mmc_request *mrq;
1280         struct mmc_data *data;
1281         u32 cmdflags;
1282
1283         mrq = slot->mrq;
1284
1285         host->cur_slot = slot;
1286         host->mrq = mrq;
1287
1288         host->pending_events = 0;
1289         host->completed_events = 0;
1290         host->cmd_status = 0;
1291         host->data_status = 0;
1292         host->dir_status = 0;
1293
1294         data = cmd->data;
1295         if (data) {
1296                 mci_writel(host, TMOUT, 0xFFFFFFFF);
1297                 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1298                 mci_writel(host, BLKSIZ, data->blksz);
1299         }
1300
1301         cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1302
1303         /* this is the first command, send the initialization clock */
1304         if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1305                 cmdflags |= SDMMC_CMD_INIT;
1306
1307         if (data) {
1308                 dw_mci_submit_data(host, data);
1309                 wmb(); /* drain writebuffer */
1310         }
1311
1312         dw_mci_start_command(host, cmd, cmdflags);
1313
1314         if (cmd->opcode == SD_SWITCH_VOLTAGE) {
1315                 unsigned long irqflags;
1316
1317                 /*
1318                  * Databook says to fail after 2ms w/ no response, but evidence
1319                  * shows that sometimes the cmd11 interrupt takes over 130ms.
1320                  * We'll set to 500ms, plus an extra jiffy just in case jiffies
1321                  * is just about to roll over.
1322                  *
1323                  * We do this whole thing under spinlock and only if the
1324                  * command hasn't already completed (indicating the the irq
1325                  * already ran so we don't want the timeout).
1326                  */
1327                 spin_lock_irqsave(&host->irq_lock, irqflags);
1328                 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1329                         mod_timer(&host->cmd11_timer,
1330                                 jiffies + msecs_to_jiffies(500) + 1);
1331                 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1332         }
1333
1334         host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
1335 }
1336
1337 static void dw_mci_start_request(struct dw_mci *host,
1338                                  struct dw_mci_slot *slot)
1339 {
1340         struct mmc_request *mrq = slot->mrq;
1341         struct mmc_command *cmd;
1342
1343         cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1344         __dw_mci_start_request(host, slot, cmd);
1345 }
1346
1347 /* must be called with host->lock held */
1348 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1349                                  struct mmc_request *mrq)
1350 {
1351         dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1352                  host->state);
1353
1354         slot->mrq = mrq;
1355
1356         if (host->state == STATE_WAITING_CMD11_DONE) {
1357                 dev_warn(&slot->mmc->class_dev,
1358                          "Voltage change didn't complete\n");
1359                 /*
1360                  * this case isn't expected to happen, so we can
1361                  * either crash here or just try to continue on
1362                  * in the closest possible state
1363                  */
1364                 host->state = STATE_IDLE;
1365         }
1366
1367         if (host->state == STATE_IDLE) {
1368                 host->state = STATE_SENDING_CMD;
1369                 dw_mci_start_request(host, slot);
1370         } else {
1371                 list_add_tail(&slot->queue_node, &host->queue);
1372         }
1373 }
1374
1375 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1376 {
1377         struct dw_mci_slot *slot = mmc_priv(mmc);
1378         struct dw_mci *host = slot->host;
1379
1380         WARN_ON(slot->mrq);
1381
1382         /*
1383          * The check for card presence and queueing of the request must be
1384          * atomic, otherwise the card could be removed in between and the
1385          * request wouldn't fail until another card was inserted.
1386          */
1387
1388         if (!dw_mci_get_cd(mmc)) {
1389                 mrq->cmd->error = -ENOMEDIUM;
1390                 mmc_request_done(mmc, mrq);
1391                 return;
1392         }
1393
1394         spin_lock_bh(&host->lock);
1395
1396         dw_mci_queue_request(host, slot, mrq);
1397
1398         spin_unlock_bh(&host->lock);
1399 }
1400
1401 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1402 {
1403         struct dw_mci_slot *slot = mmc_priv(mmc);
1404         const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1405         u32 regs;
1406         int ret;
1407
1408         switch (ios->bus_width) {
1409         case MMC_BUS_WIDTH_4:
1410                 slot->ctype = SDMMC_CTYPE_4BIT;
1411                 break;
1412         case MMC_BUS_WIDTH_8:
1413                 slot->ctype = SDMMC_CTYPE_8BIT;
1414                 break;
1415         default:
1416                 /* set default 1 bit mode */
1417                 slot->ctype = SDMMC_CTYPE_1BIT;
1418         }
1419
1420         regs = mci_readl(slot->host, UHS_REG);
1421
1422         /* DDR mode set */
1423         if (ios->timing == MMC_TIMING_MMC_DDR52 ||
1424             ios->timing == MMC_TIMING_UHS_DDR50 ||
1425             ios->timing == MMC_TIMING_MMC_HS400)
1426                 regs |= ((0x1 << slot->id) << 16);
1427         else
1428                 regs &= ~((0x1 << slot->id) << 16);
1429
1430         mci_writel(slot->host, UHS_REG, regs);
1431         slot->host->timing = ios->timing;
1432
1433         /*
1434          * Use mirror of ios->clock to prevent race with mmc
1435          * core ios update when finding the minimum.
1436          */
1437         slot->clock = ios->clock;
1438
1439         if (drv_data && drv_data->set_ios)
1440                 drv_data->set_ios(slot->host, ios);
1441
1442         switch (ios->power_mode) {
1443         case MMC_POWER_UP:
1444                 if (!IS_ERR(mmc->supply.vmmc)) {
1445                         ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1446                                         ios->vdd);
1447                         if (ret) {
1448                                 dev_err(slot->host->dev,
1449                                         "failed to enable vmmc regulator\n");
1450                                 /*return, if failed turn on vmmc*/
1451                                 return;
1452                         }
1453                 }
1454                 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1455                 regs = mci_readl(slot->host, PWREN);
1456                 regs |= (1 << slot->id);
1457                 mci_writel(slot->host, PWREN, regs);
1458                 break;
1459         case MMC_POWER_ON:
1460                 if (!slot->host->vqmmc_enabled) {
1461                         if (!IS_ERR(mmc->supply.vqmmc)) {
1462                                 ret = regulator_enable(mmc->supply.vqmmc);
1463                                 if (ret < 0)
1464                                         dev_err(slot->host->dev,
1465                                                 "failed to enable vqmmc\n");
1466                                 else
1467                                         slot->host->vqmmc_enabled = true;
1468
1469                         } else {
1470                                 /* Keep track so we don't reset again */
1471                                 slot->host->vqmmc_enabled = true;
1472                         }
1473
1474                         /* Reset our state machine after powering on */
1475                         dw_mci_ctrl_reset(slot->host,
1476                                           SDMMC_CTRL_ALL_RESET_FLAGS);
1477                 }
1478
1479                 /* Adjust clock / bus width after power is up */
1480                 dw_mci_setup_bus(slot, false);
1481
1482                 break;
1483         case MMC_POWER_OFF:
1484                 /* Turn clock off before power goes down */
1485                 dw_mci_setup_bus(slot, false);
1486
1487                 if (!IS_ERR(mmc->supply.vmmc))
1488                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1489
1490                 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
1491                         regulator_disable(mmc->supply.vqmmc);
1492                 slot->host->vqmmc_enabled = false;
1493
1494                 regs = mci_readl(slot->host, PWREN);
1495                 regs &= ~(1 << slot->id);
1496                 mci_writel(slot->host, PWREN, regs);
1497                 break;
1498         default:
1499                 break;
1500         }
1501
1502         if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1503                 slot->host->state = STATE_IDLE;
1504 }
1505
1506 static int dw_mci_card_busy(struct mmc_host *mmc)
1507 {
1508         struct dw_mci_slot *slot = mmc_priv(mmc);
1509         u32 status;
1510
1511         /*
1512          * Check the busy bit which is low when DAT[3:0]
1513          * (the data lines) are 0000
1514          */
1515         status = mci_readl(slot->host, STATUS);
1516
1517         return !!(status & SDMMC_STATUS_BUSY);
1518 }
1519
1520 static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1521 {
1522         struct dw_mci_slot *slot = mmc_priv(mmc);
1523         struct dw_mci *host = slot->host;
1524         const struct dw_mci_drv_data *drv_data = host->drv_data;
1525         u32 uhs;
1526         u32 v18 = SDMMC_UHS_18V << slot->id;
1527         int ret;
1528
1529         if (drv_data && drv_data->switch_voltage)
1530                 return drv_data->switch_voltage(mmc, ios);
1531
1532         /*
1533          * Program the voltage.  Note that some instances of dw_mmc may use
1534          * the UHS_REG for this.  For other instances (like exynos) the UHS_REG
1535          * does no harm but you need to set the regulator directly.  Try both.
1536          */
1537         uhs = mci_readl(host, UHS_REG);
1538         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1539                 uhs &= ~v18;
1540         else
1541                 uhs |= v18;
1542
1543         if (!IS_ERR(mmc->supply.vqmmc)) {
1544                 ret = mmc_regulator_set_vqmmc(mmc, ios);
1545
1546                 if (ret) {
1547                         dev_dbg(&mmc->class_dev,
1548                                          "Regulator set error %d - %s V\n",
1549                                          ret, uhs & v18 ? "1.8" : "3.3");
1550                         return ret;
1551                 }
1552         }
1553         mci_writel(host, UHS_REG, uhs);
1554
1555         return 0;
1556 }
1557
1558 static int dw_mci_get_ro(struct mmc_host *mmc)
1559 {
1560         int read_only;
1561         struct dw_mci_slot *slot = mmc_priv(mmc);
1562         int gpio_ro = mmc_gpio_get_ro(mmc);
1563
1564         /* Use platform get_ro function, else try on board write protect */
1565         if (gpio_ro >= 0)
1566                 read_only = gpio_ro;
1567         else
1568                 read_only =
1569                         mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1570
1571         dev_dbg(&mmc->class_dev, "card is %s\n",
1572                 read_only ? "read-only" : "read-write");
1573
1574         return read_only;
1575 }
1576
1577 static void dw_mci_hw_reset(struct mmc_host *mmc)
1578 {
1579         struct dw_mci_slot *slot = mmc_priv(mmc);
1580         struct dw_mci *host = slot->host;
1581         int reset;
1582
1583         if (host->use_dma == TRANS_MODE_IDMAC)
1584                 dw_mci_idmac_reset(host);
1585
1586         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET |
1587                                      SDMMC_CTRL_FIFO_RESET))
1588                 return;
1589
1590         /*
1591          * According to eMMC spec, card reset procedure:
1592          * tRstW >= 1us:   RST_n pulse width
1593          * tRSCA >= 200us: RST_n to Command time
1594          * tRSTH >= 1us:   RST_n high period
1595          */
1596         reset = mci_readl(host, RST_N);
1597         reset &= ~(SDMMC_RST_HWACTIVE << slot->id);
1598         mci_writel(host, RST_N, reset);
1599         usleep_range(1, 2);
1600         reset |= SDMMC_RST_HWACTIVE << slot->id;
1601         mci_writel(host, RST_N, reset);
1602         usleep_range(200, 300);
1603 }
1604
1605 static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card)
1606 {
1607         struct dw_mci_slot *slot = mmc_priv(mmc);
1608         struct dw_mci *host = slot->host;
1609
1610         /*
1611          * Low power mode will stop the card clock when idle.  According to the
1612          * description of the CLKENA register we should disable low power mode
1613          * for SDIO cards if we need SDIO interrupts to work.
1614          */
1615         if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1616                 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1617                 u32 clk_en_a_old;
1618                 u32 clk_en_a;
1619
1620                 clk_en_a_old = mci_readl(host, CLKENA);
1621
1622                 if (card->type == MMC_TYPE_SDIO ||
1623                     card->type == MMC_TYPE_SD_COMBO) {
1624                         set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1625                         clk_en_a = clk_en_a_old & ~clken_low_pwr;
1626                 } else {
1627                         clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1628                         clk_en_a = clk_en_a_old | clken_low_pwr;
1629                 }
1630
1631                 if (clk_en_a != clk_en_a_old) {
1632                         mci_writel(host, CLKENA, clk_en_a);
1633                         mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1634                                      SDMMC_CMD_PRV_DAT_WAIT, 0);
1635                 }
1636         }
1637 }
1638
1639 static void __dw_mci_enable_sdio_irq(struct dw_mci_slot *slot, int enb)
1640 {
1641         struct dw_mci *host = slot->host;
1642         unsigned long irqflags;
1643         u32 int_mask;
1644
1645         spin_lock_irqsave(&host->irq_lock, irqflags);
1646
1647         /* Enable/disable Slot Specific SDIO interrupt */
1648         int_mask = mci_readl(host, INTMASK);
1649         if (enb)
1650                 int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
1651         else
1652                 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
1653         mci_writel(host, INTMASK, int_mask);
1654
1655         spin_unlock_irqrestore(&host->irq_lock, irqflags);
1656 }
1657
1658 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1659 {
1660         struct dw_mci_slot *slot = mmc_priv(mmc);
1661         struct dw_mci *host = slot->host;
1662
1663         __dw_mci_enable_sdio_irq(slot, enb);
1664
1665         /* Avoid runtime suspending the device when SDIO IRQ is enabled */
1666         if (enb)
1667                 pm_runtime_get_noresume(host->dev);
1668         else
1669                 pm_runtime_put_noidle(host->dev);
1670 }
1671
1672 static void dw_mci_ack_sdio_irq(struct mmc_host *mmc)
1673 {
1674         struct dw_mci_slot *slot = mmc_priv(mmc);
1675
1676         __dw_mci_enable_sdio_irq(slot, 1);
1677 }
1678
1679 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1680 {
1681         struct dw_mci_slot *slot = mmc_priv(mmc);
1682         struct dw_mci *host = slot->host;
1683         const struct dw_mci_drv_data *drv_data = host->drv_data;
1684         int err = -EINVAL;
1685
1686         if (drv_data && drv_data->execute_tuning)
1687                 err = drv_data->execute_tuning(slot, opcode);
1688         return err;
1689 }
1690
1691 static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc,
1692                                        struct mmc_ios *ios)
1693 {
1694         struct dw_mci_slot *slot = mmc_priv(mmc);
1695         struct dw_mci *host = slot->host;
1696         const struct dw_mci_drv_data *drv_data = host->drv_data;
1697
1698         if (drv_data && drv_data->prepare_hs400_tuning)
1699                 return drv_data->prepare_hs400_tuning(host, ios);
1700
1701         return 0;
1702 }
1703
1704 static bool dw_mci_reset(struct dw_mci *host)
1705 {
1706         u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
1707         bool ret = false;
1708         u32 status = 0;
1709
1710         /*
1711          * Resetting generates a block interrupt, hence setting
1712          * the scatter-gather pointer to NULL.
1713          */
1714         if (host->sg) {
1715                 sg_miter_stop(&host->sg_miter);
1716                 host->sg = NULL;
1717         }
1718
1719         if (host->use_dma)
1720                 flags |= SDMMC_CTRL_DMA_RESET;
1721
1722         if (dw_mci_ctrl_reset(host, flags)) {
1723                 /*
1724                  * In all cases we clear the RAWINTS
1725                  * register to clear any interrupts.
1726                  */
1727                 mci_writel(host, RINTSTS, 0xFFFFFFFF);
1728
1729                 if (!host->use_dma) {
1730                         ret = true;
1731                         goto ciu_out;
1732                 }
1733
1734                 /* Wait for dma_req to be cleared */
1735                 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
1736                                               status,
1737                                               !(status & SDMMC_STATUS_DMA_REQ),
1738                                               1, 500 * USEC_PER_MSEC)) {
1739                         dev_err(host->dev,
1740                                 "%s: Timeout waiting for dma_req to be cleared\n",
1741                                 __func__);
1742                         goto ciu_out;
1743                 }
1744
1745                 /* when using DMA next we reset the fifo again */
1746                 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
1747                         goto ciu_out;
1748         } else {
1749                 /* if the controller reset bit did clear, then set clock regs */
1750                 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
1751                         dev_err(host->dev,
1752                                 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
1753                                 __func__);
1754                         goto ciu_out;
1755                 }
1756         }
1757
1758         if (host->use_dma == TRANS_MODE_IDMAC)
1759                 /* It is also recommended that we reset and reprogram idmac */
1760                 dw_mci_idmac_reset(host);
1761
1762         ret = true;
1763
1764 ciu_out:
1765         /* After a CTRL reset we need to have CIU set clock registers  */
1766         mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0);
1767
1768         return ret;
1769 }
1770
1771 static const struct mmc_host_ops dw_mci_ops = {
1772         .request                = dw_mci_request,
1773         .pre_req                = dw_mci_pre_req,
1774         .post_req               = dw_mci_post_req,
1775         .set_ios                = dw_mci_set_ios,
1776         .get_ro                 = dw_mci_get_ro,
1777         .get_cd                 = dw_mci_get_cd,
1778         .hw_reset               = dw_mci_hw_reset,
1779         .enable_sdio_irq        = dw_mci_enable_sdio_irq,
1780         .ack_sdio_irq           = dw_mci_ack_sdio_irq,
1781         .execute_tuning         = dw_mci_execute_tuning,
1782         .card_busy              = dw_mci_card_busy,
1783         .start_signal_voltage_switch = dw_mci_switch_voltage,
1784         .init_card              = dw_mci_init_card,
1785         .prepare_hs400_tuning   = dw_mci_prepare_hs400_tuning,
1786 };
1787
1788 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1789         __releases(&host->lock)
1790         __acquires(&host->lock)
1791 {
1792         struct dw_mci_slot *slot;
1793         struct mmc_host *prev_mmc = host->cur_slot->mmc;
1794
1795         WARN_ON(host->cmd || host->data);
1796
1797         host->cur_slot->mrq = NULL;
1798         host->mrq = NULL;
1799         if (!list_empty(&host->queue)) {
1800                 slot = list_entry(host->queue.next,
1801                                   struct dw_mci_slot, queue_node);
1802                 list_del(&slot->queue_node);
1803                 dev_vdbg(host->dev, "list not empty: %s is next\n",
1804                          mmc_hostname(slot->mmc));
1805                 host->state = STATE_SENDING_CMD;
1806                 dw_mci_start_request(host, slot);
1807         } else {
1808                 dev_vdbg(host->dev, "list empty\n");
1809
1810                 if (host->state == STATE_SENDING_CMD11)
1811                         host->state = STATE_WAITING_CMD11_DONE;
1812                 else
1813                         host->state = STATE_IDLE;
1814         }
1815
1816         spin_unlock(&host->lock);
1817         mmc_request_done(prev_mmc, mrq);
1818         spin_lock(&host->lock);
1819 }
1820
1821 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
1822 {
1823         u32 status = host->cmd_status;
1824
1825         host->cmd_status = 0;
1826
1827         /* Read the response from the card (up to 16 bytes) */
1828         if (cmd->flags & MMC_RSP_PRESENT) {
1829                 if (cmd->flags & MMC_RSP_136) {
1830                         cmd->resp[3] = mci_readl(host, RESP0);
1831                         cmd->resp[2] = mci_readl(host, RESP1);
1832                         cmd->resp[1] = mci_readl(host, RESP2);
1833                         cmd->resp[0] = mci_readl(host, RESP3);
1834                 } else {
1835                         cmd->resp[0] = mci_readl(host, RESP0);
1836                         cmd->resp[1] = 0;
1837                         cmd->resp[2] = 0;
1838                         cmd->resp[3] = 0;
1839                 }
1840         }
1841
1842         if (status & SDMMC_INT_RTO)
1843                 cmd->error = -ETIMEDOUT;
1844         else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1845                 cmd->error = -EILSEQ;
1846         else if (status & SDMMC_INT_RESP_ERR)
1847                 cmd->error = -EIO;
1848         else
1849                 cmd->error = 0;
1850
1851         return cmd->error;
1852 }
1853
1854 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1855 {
1856         u32 status = host->data_status;
1857
1858         if (status & DW_MCI_DATA_ERROR_FLAGS) {
1859                 if (status & SDMMC_INT_DRTO) {
1860                         data->error = -ETIMEDOUT;
1861                 } else if (status & SDMMC_INT_DCRC) {
1862                         data->error = -EILSEQ;
1863                 } else if (status & SDMMC_INT_EBE) {
1864                         if (host->dir_status ==
1865                                 DW_MCI_SEND_STATUS) {
1866                                 /*
1867                                  * No data CRC status was returned.
1868                                  * The number of bytes transferred
1869                                  * will be exaggerated in PIO mode.
1870                                  */
1871                                 data->bytes_xfered = 0;
1872                                 data->error = -ETIMEDOUT;
1873                         } else if (host->dir_status ==
1874                                         DW_MCI_RECV_STATUS) {
1875                                 data->error = -EILSEQ;
1876                         }
1877                 } else {
1878                         /* SDMMC_INT_SBE is included */
1879                         data->error = -EILSEQ;
1880                 }
1881
1882                 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
1883
1884                 /*
1885                  * After an error, there may be data lingering
1886                  * in the FIFO
1887                  */
1888                 dw_mci_reset(host);
1889         } else {
1890                 data->bytes_xfered = data->blocks * data->blksz;
1891                 data->error = 0;
1892         }
1893
1894         return data->error;
1895 }
1896
1897 static void dw_mci_set_drto(struct dw_mci *host)
1898 {
1899         unsigned int drto_clks;
1900         unsigned int drto_ms;
1901
1902         drto_clks = mci_readl(host, TMOUT) >> 8;
1903         drto_ms = DIV_ROUND_UP(drto_clks, host->bus_hz / 1000);
1904
1905         /* add a bit spare time */
1906         drto_ms += 10;
1907
1908         mod_timer(&host->dto_timer, jiffies + msecs_to_jiffies(drto_ms));
1909 }
1910
1911 static void dw_mci_tasklet_func(unsigned long priv)
1912 {
1913         struct dw_mci *host = (struct dw_mci *)priv;
1914         struct mmc_data *data;
1915         struct mmc_command *cmd;
1916         struct mmc_request *mrq;
1917         enum dw_mci_state state;
1918         enum dw_mci_state prev_state;
1919         unsigned int err;
1920
1921         spin_lock(&host->lock);
1922
1923         state = host->state;
1924         data = host->data;
1925         mrq = host->mrq;
1926
1927         do {
1928                 prev_state = state;
1929
1930                 switch (state) {
1931                 case STATE_IDLE:
1932                 case STATE_WAITING_CMD11_DONE:
1933                         break;
1934
1935                 case STATE_SENDING_CMD11:
1936                 case STATE_SENDING_CMD:
1937                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1938                                                 &host->pending_events))
1939                                 break;
1940
1941                         cmd = host->cmd;
1942                         host->cmd = NULL;
1943                         set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
1944                         err = dw_mci_command_complete(host, cmd);
1945                         if (cmd == mrq->sbc && !err) {
1946                                 prev_state = state = STATE_SENDING_CMD;
1947                                 __dw_mci_start_request(host, host->cur_slot,
1948                                                        mrq->cmd);
1949                                 goto unlock;
1950                         }
1951
1952                         if (cmd->data && err) {
1953                                 /*
1954                                  * During UHS tuning sequence, sending the stop
1955                                  * command after the response CRC error would
1956                                  * throw the system into a confused state
1957                                  * causing all future tuning phases to report
1958                                  * failure.
1959                                  *
1960                                  * In such case controller will move into a data
1961                                  * transfer state after a response error or
1962                                  * response CRC error. Let's let that finish
1963                                  * before trying to send a stop, so we'll go to
1964                                  * STATE_SENDING_DATA.
1965                                  *
1966                                  * Although letting the data transfer take place
1967                                  * will waste a bit of time (we already know
1968                                  * the command was bad), it can't cause any
1969                                  * errors since it's possible it would have
1970                                  * taken place anyway if this tasklet got
1971                                  * delayed. Allowing the transfer to take place
1972                                  * avoids races and keeps things simple.
1973                                  */
1974                                 if ((err != -ETIMEDOUT) &&
1975                                     (cmd->opcode == MMC_SEND_TUNING_BLOCK)) {
1976                                         state = STATE_SENDING_DATA;
1977                                         continue;
1978                                 }
1979
1980                                 dw_mci_stop_dma(host);
1981                                 send_stop_abort(host, data);
1982                                 state = STATE_SENDING_STOP;
1983                                 break;
1984                         }
1985
1986                         if (!cmd->data || err) {
1987                                 dw_mci_request_end(host, mrq);
1988                                 goto unlock;
1989                         }
1990
1991                         prev_state = state = STATE_SENDING_DATA;
1992                         /* fall through */
1993
1994                 case STATE_SENDING_DATA:
1995                         /*
1996                          * We could get a data error and never a transfer
1997                          * complete so we'd better check for it here.
1998                          *
1999                          * Note that we don't really care if we also got a
2000                          * transfer complete; stopping the DMA and sending an
2001                          * abort won't hurt.
2002                          */
2003                         if (test_and_clear_bit(EVENT_DATA_ERROR,
2004                                                &host->pending_events)) {
2005                                 dw_mci_stop_dma(host);
2006                                 if (!(host->data_status & (SDMMC_INT_DRTO |
2007                                                            SDMMC_INT_EBE)))
2008                                         send_stop_abort(host, data);
2009                                 state = STATE_DATA_ERROR;
2010                                 break;
2011                         }
2012
2013                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2014                                                 &host->pending_events)) {
2015                                 /*
2016                                  * If all data-related interrupts don't come
2017                                  * within the given time in reading data state.
2018                                  */
2019                                 if (host->dir_status == DW_MCI_RECV_STATUS)
2020                                         dw_mci_set_drto(host);
2021                                 break;
2022                         }
2023
2024                         set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
2025
2026                         /*
2027                          * Handle an EVENT_DATA_ERROR that might have shown up
2028                          * before the transfer completed.  This might not have
2029                          * been caught by the check above because the interrupt
2030                          * could have gone off between the previous check and
2031                          * the check for transfer complete.
2032                          *
2033                          * Technically this ought not be needed assuming we
2034                          * get a DATA_COMPLETE eventually (we'll notice the
2035                          * error and end the request), but it shouldn't hurt.
2036                          *
2037                          * This has the advantage of sending the stop command.
2038                          */
2039                         if (test_and_clear_bit(EVENT_DATA_ERROR,
2040                                                &host->pending_events)) {
2041                                 dw_mci_stop_dma(host);
2042                                 if (!(host->data_status & (SDMMC_INT_DRTO |
2043                                                            SDMMC_INT_EBE)))
2044                                         send_stop_abort(host, data);
2045                                 state = STATE_DATA_ERROR;
2046                                 break;
2047                         }
2048                         prev_state = state = STATE_DATA_BUSY;
2049
2050                         /* fall through */
2051
2052                 case STATE_DATA_BUSY:
2053                         if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
2054                                                 &host->pending_events)) {
2055                                 /*
2056                                  * If data error interrupt comes but data over
2057                                  * interrupt doesn't come within the given time.
2058                                  * in reading data state.
2059                                  */
2060                                 if (host->dir_status == DW_MCI_RECV_STATUS)
2061                                         dw_mci_set_drto(host);
2062                                 break;
2063                         }
2064
2065                         host->data = NULL;
2066                         set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
2067                         err = dw_mci_data_complete(host, data);
2068
2069                         if (!err) {
2070                                 if (!data->stop || mrq->sbc) {
2071                                         if (mrq->sbc && data->stop)
2072                                                 data->stop->error = 0;
2073                                         dw_mci_request_end(host, mrq);
2074                                         goto unlock;
2075                                 }
2076
2077                                 /* stop command for open-ended transfer*/
2078                                 if (data->stop)
2079                                         send_stop_abort(host, data);
2080                         } else {
2081                                 /*
2082                                  * If we don't have a command complete now we'll
2083                                  * never get one since we just reset everything;
2084                                  * better end the request.
2085                                  *
2086                                  * If we do have a command complete we'll fall
2087                                  * through to the SENDING_STOP command and
2088                                  * everything will be peachy keen.
2089                                  */
2090                                 if (!test_bit(EVENT_CMD_COMPLETE,
2091                                               &host->pending_events)) {
2092                                         host->cmd = NULL;
2093                                         dw_mci_request_end(host, mrq);
2094                                         goto unlock;
2095                                 }
2096                         }
2097
2098                         /*
2099                          * If err has non-zero,
2100                          * stop-abort command has been already issued.
2101                          */
2102                         prev_state = state = STATE_SENDING_STOP;
2103
2104                         /* fall through */
2105
2106                 case STATE_SENDING_STOP:
2107                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
2108                                                 &host->pending_events))
2109                                 break;
2110
2111                         /* CMD error in data command */
2112                         if (mrq->cmd->error && mrq->data)
2113                                 dw_mci_reset(host);
2114
2115                         host->cmd = NULL;
2116                         host->data = NULL;
2117
2118                         if (!mrq->sbc && mrq->stop)
2119                                 dw_mci_command_complete(host, mrq->stop);
2120                         else
2121                                 host->cmd_status = 0;
2122
2123                         dw_mci_request_end(host, mrq);
2124                         goto unlock;
2125
2126                 case STATE_DATA_ERROR:
2127                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2128                                                 &host->pending_events))
2129                                 break;
2130
2131                         state = STATE_DATA_BUSY;
2132                         break;
2133                 }
2134         } while (state != prev_state);
2135
2136         host->state = state;
2137 unlock:
2138         spin_unlock(&host->lock);
2139
2140 }
2141
2142 /* push final bytes to part_buf, only use during push */
2143 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
2144 {
2145         memcpy((void *)&host->part_buf, buf, cnt);
2146         host->part_buf_count = cnt;
2147 }
2148
2149 /* append bytes to part_buf, only use during push */
2150 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
2151 {
2152         cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
2153         memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
2154         host->part_buf_count += cnt;
2155         return cnt;
2156 }
2157
2158 /* pull first bytes from part_buf, only use during pull */
2159 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
2160 {
2161         cnt = min_t(int, cnt, host->part_buf_count);
2162         if (cnt) {
2163                 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
2164                        cnt);
2165                 host->part_buf_count -= cnt;
2166                 host->part_buf_start += cnt;
2167         }
2168         return cnt;
2169 }
2170
2171 /* pull final bytes from the part_buf, assuming it's just been filled */
2172 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
2173 {
2174         memcpy(buf, &host->part_buf, cnt);
2175         host->part_buf_start = cnt;
2176         host->part_buf_count = (1 << host->data_shift) - cnt;
2177 }
2178
2179 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
2180 {
2181         struct mmc_data *data = host->data;
2182         int init_cnt = cnt;
2183
2184         /* try and push anything in the part_buf */
2185         if (unlikely(host->part_buf_count)) {
2186                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2187
2188                 buf += len;
2189                 cnt -= len;
2190                 if (host->part_buf_count == 2) {
2191                         mci_fifo_writew(host->fifo_reg, host->part_buf16);
2192                         host->part_buf_count = 0;
2193                 }
2194         }
2195 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2196         if (unlikely((unsigned long)buf & 0x1)) {
2197                 while (cnt >= 2) {
2198                         u16 aligned_buf[64];
2199                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
2200                         int items = len >> 1;
2201                         int i;
2202                         /* memcpy from input buffer into aligned buffer */
2203                         memcpy(aligned_buf, buf, len);
2204                         buf += len;
2205                         cnt -= len;
2206                         /* push data from aligned buffer into fifo */
2207                         for (i = 0; i < items; ++i)
2208                                 mci_fifo_writew(host->fifo_reg, aligned_buf[i]);
2209                 }
2210         } else
2211 #endif
2212         {
2213                 u16 *pdata = buf;
2214
2215                 for (; cnt >= 2; cnt -= 2)
2216                         mci_fifo_writew(host->fifo_reg, *pdata++);
2217                 buf = pdata;
2218         }
2219         /* put anything remaining in the part_buf */
2220         if (cnt) {
2221                 dw_mci_set_part_bytes(host, buf, cnt);
2222                  /* Push data if we have reached the expected data length */
2223                 if ((data->bytes_xfered + init_cnt) ==
2224                     (data->blksz * data->blocks))
2225                         mci_fifo_writew(host->fifo_reg, host->part_buf16);
2226         }
2227 }
2228
2229 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2230 {
2231 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2232         if (unlikely((unsigned long)buf & 0x1)) {
2233                 while (cnt >= 2) {
2234                         /* pull data from fifo into aligned buffer */
2235                         u16 aligned_buf[64];
2236                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
2237                         int items = len >> 1;
2238                         int i;
2239
2240                         for (i = 0; i < items; ++i)
2241                                 aligned_buf[i] = mci_fifo_readw(host->fifo_reg);
2242                         /* memcpy from aligned buffer into output buffer */
2243                         memcpy(buf, aligned_buf, len);
2244                         buf += len;
2245                         cnt -= len;
2246                 }
2247         } else
2248 #endif
2249         {
2250                 u16 *pdata = buf;
2251
2252                 for (; cnt >= 2; cnt -= 2)
2253                         *pdata++ = mci_fifo_readw(host->fifo_reg);
2254                 buf = pdata;
2255         }
2256         if (cnt) {
2257                 host->part_buf16 = mci_fifo_readw(host->fifo_reg);
2258                 dw_mci_pull_final_bytes(host, buf, cnt);
2259         }
2260 }
2261
2262 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2263 {
2264         struct mmc_data *data = host->data;
2265         int init_cnt = cnt;
2266
2267         /* try and push anything in the part_buf */
2268         if (unlikely(host->part_buf_count)) {
2269                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2270
2271                 buf += len;
2272                 cnt -= len;
2273                 if (host->part_buf_count == 4) {
2274                         mci_fifo_writel(host->fifo_reg, host->part_buf32);
2275                         host->part_buf_count = 0;
2276                 }
2277         }
2278 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2279         if (unlikely((unsigned long)buf & 0x3)) {
2280                 while (cnt >= 4) {
2281                         u32 aligned_buf[32];
2282                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
2283                         int items = len >> 2;
2284                         int i;
2285                         /* memcpy from input buffer into aligned buffer */
2286                         memcpy(aligned_buf, buf, len);
2287                         buf += len;
2288                         cnt -= len;
2289                         /* push data from aligned buffer into fifo */
2290                         for (i = 0; i < items; ++i)
2291                                 mci_fifo_writel(host->fifo_reg, aligned_buf[i]);
2292                 }
2293         } else
2294 #endif
2295         {
2296                 u32 *pdata = buf;
2297
2298                 for (; cnt >= 4; cnt -= 4)
2299                         mci_fifo_writel(host->fifo_reg, *pdata++);
2300                 buf = pdata;
2301         }
2302         /* put anything remaining in the part_buf */
2303         if (cnt) {
2304                 dw_mci_set_part_bytes(host, buf, cnt);
2305                  /* Push data if we have reached the expected data length */
2306                 if ((data->bytes_xfered + init_cnt) ==
2307                     (data->blksz * data->blocks))
2308                         mci_fifo_writel(host->fifo_reg, host->part_buf32);
2309         }
2310 }
2311
2312 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2313 {
2314 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2315         if (unlikely((unsigned long)buf & 0x3)) {
2316                 while (cnt >= 4) {
2317                         /* pull data from fifo into aligned buffer */
2318                         u32 aligned_buf[32];
2319                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
2320                         int items = len >> 2;
2321                         int i;
2322
2323                         for (i = 0; i < items; ++i)
2324                                 aligned_buf[i] = mci_fifo_readl(host->fifo_reg);
2325                         /* memcpy from aligned buffer into output buffer */
2326                         memcpy(buf, aligned_buf, len);
2327                         buf += len;
2328                         cnt -= len;
2329                 }
2330         } else
2331 #endif
2332         {
2333                 u32 *pdata = buf;
2334
2335                 for (; cnt >= 4; cnt -= 4)
2336                         *pdata++ = mci_fifo_readl(host->fifo_reg);
2337                 buf = pdata;
2338         }
2339         if (cnt) {
2340                 host->part_buf32 = mci_fifo_readl(host->fifo_reg);
2341                 dw_mci_pull_final_bytes(host, buf, cnt);
2342         }
2343 }
2344
2345 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2346 {
2347         struct mmc_data *data = host->data;
2348         int init_cnt = cnt;
2349
2350         /* try and push anything in the part_buf */
2351         if (unlikely(host->part_buf_count)) {
2352                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2353
2354                 buf += len;
2355                 cnt -= len;
2356
2357                 if (host->part_buf_count == 8) {
2358                         mci_fifo_writeq(host->fifo_reg, host->part_buf);
2359                         host->part_buf_count = 0;
2360                 }
2361         }
2362 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2363         if (unlikely((unsigned long)buf & 0x7)) {
2364                 while (cnt >= 8) {
2365                         u64 aligned_buf[16];
2366                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
2367                         int items = len >> 3;
2368                         int i;
2369                         /* memcpy from input buffer into aligned buffer */
2370                         memcpy(aligned_buf, buf, len);
2371                         buf += len;
2372                         cnt -= len;
2373                         /* push data from aligned buffer into fifo */
2374                         for (i = 0; i < items; ++i)
2375                                 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]);
2376                 }
2377         } else
2378 #endif
2379         {
2380                 u64 *pdata = buf;
2381
2382                 for (; cnt >= 8; cnt -= 8)
2383                         mci_fifo_writeq(host->fifo_reg, *pdata++);
2384                 buf = pdata;
2385         }
2386         /* put anything remaining in the part_buf */
2387         if (cnt) {
2388                 dw_mci_set_part_bytes(host, buf, cnt);
2389                 /* Push data if we have reached the expected data length */
2390                 if ((data->bytes_xfered + init_cnt) ==
2391                     (data->blksz * data->blocks))
2392                         mci_fifo_writeq(host->fifo_reg, host->part_buf);
2393         }
2394 }
2395
2396 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2397 {
2398 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2399         if (unlikely((unsigned long)buf & 0x7)) {
2400                 while (cnt >= 8) {
2401                         /* pull data from fifo into aligned buffer */
2402                         u64 aligned_buf[16];
2403                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
2404                         int items = len >> 3;
2405                         int i;
2406
2407                         for (i = 0; i < items; ++i)
2408                                 aligned_buf[i] = mci_fifo_readq(host->fifo_reg);
2409
2410                         /* memcpy from aligned buffer into output buffer */
2411                         memcpy(buf, aligned_buf, len);
2412                         buf += len;
2413                         cnt -= len;
2414                 }
2415         } else
2416 #endif
2417         {
2418                 u64 *pdata = buf;
2419
2420                 for (; cnt >= 8; cnt -= 8)
2421                         *pdata++ = mci_fifo_readq(host->fifo_reg);
2422                 buf = pdata;
2423         }
2424         if (cnt) {
2425                 host->part_buf = mci_fifo_readq(host->fifo_reg);
2426                 dw_mci_pull_final_bytes(host, buf, cnt);
2427         }
2428 }
2429
2430 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2431 {
2432         int len;
2433
2434         /* get remaining partial bytes */
2435         len = dw_mci_pull_part_bytes(host, buf, cnt);
2436         if (unlikely(len == cnt))
2437                 return;
2438         buf += len;
2439         cnt -= len;
2440
2441         /* get the rest of the data */
2442         host->pull_data(host, buf, cnt);
2443 }
2444
2445 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
2446 {
2447         struct sg_mapping_iter *sg_miter = &host->sg_miter;
2448         void *buf;
2449         unsigned int offset;
2450         struct mmc_data *data = host->data;
2451         int shift = host->data_shift;
2452         u32 status;
2453         unsigned int len;
2454         unsigned int remain, fcnt;
2455
2456         do {
2457                 if (!sg_miter_next(sg_miter))
2458                         goto done;
2459
2460                 host->sg = sg_miter->piter.sg;
2461                 buf = sg_miter->addr;
2462                 remain = sg_miter->length;
2463                 offset = 0;
2464
2465                 do {
2466                         fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2467                                         << shift) + host->part_buf_count;
2468                         len = min(remain, fcnt);
2469                         if (!len)
2470                                 break;
2471                         dw_mci_pull_data(host, (void *)(buf + offset), len);
2472                         data->bytes_xfered += len;
2473                         offset += len;
2474                         remain -= len;
2475                 } while (remain);
2476
2477                 sg_miter->consumed = offset;
2478                 status = mci_readl(host, MINTSTS);
2479                 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2480         /* if the RXDR is ready read again */
2481         } while ((status & SDMMC_INT_RXDR) ||
2482                  (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
2483
2484         if (!remain) {
2485                 if (!sg_miter_next(sg_miter))
2486                         goto done;
2487                 sg_miter->consumed = 0;
2488         }
2489         sg_miter_stop(sg_miter);
2490         return;
2491
2492 done:
2493         sg_miter_stop(sg_miter);
2494         host->sg = NULL;
2495         smp_wmb(); /* drain writebuffer */
2496         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2497 }
2498
2499 static void dw_mci_write_data_pio(struct dw_mci *host)
2500 {
2501         struct sg_mapping_iter *sg_miter = &host->sg_miter;
2502         void *buf;
2503         unsigned int offset;
2504         struct mmc_data *data = host->data;
2505         int shift = host->data_shift;
2506         u32 status;
2507         unsigned int len;
2508         unsigned int fifo_depth = host->fifo_depth;
2509         unsigned int remain, fcnt;
2510
2511         do {
2512                 if (!sg_miter_next(sg_miter))
2513                         goto done;
2514
2515                 host->sg = sg_miter->piter.sg;
2516                 buf = sg_miter->addr;
2517                 remain = sg_miter->length;
2518                 offset = 0;
2519
2520                 do {
2521                         fcnt = ((fifo_depth -
2522                                  SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2523                                         << shift) - host->part_buf_count;
2524                         len = min(remain, fcnt);
2525                         if (!len)
2526                                 break;
2527                         host->push_data(host, (void *)(buf + offset), len);
2528                         data->bytes_xfered += len;
2529                         offset += len;
2530                         remain -= len;
2531                 } while (remain);
2532
2533                 sg_miter->consumed = offset;
2534                 status = mci_readl(host, MINTSTS);
2535                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2536         } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
2537
2538         if (!remain) {
2539                 if (!sg_miter_next(sg_miter))
2540                         goto done;
2541                 sg_miter->consumed = 0;
2542         }
2543         sg_miter_stop(sg_miter);
2544         return;
2545
2546 done:
2547         sg_miter_stop(sg_miter);
2548         host->sg = NULL;
2549         smp_wmb(); /* drain writebuffer */
2550         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2551 }
2552
2553 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2554 {
2555         if (!host->cmd_status)
2556                 host->cmd_status = status;
2557
2558         smp_wmb(); /* drain writebuffer */
2559
2560         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2561         tasklet_schedule(&host->tasklet);
2562 }
2563
2564 static void dw_mci_handle_cd(struct dw_mci *host)
2565 {
2566         int i = 0;
2567         struct dw_mci_slot *slot = host->slot[i];
2568
2569         if (slot->mmc->ops->card_event)
2570                 slot->mmc->ops->card_event(slot->mmc);
2571         mmc_detect_change(slot->mmc,
2572                 msecs_to_jiffies(host->pdata->detect_delay_ms));
2573 }
2574
2575 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2576 {
2577         struct dw_mci *host = dev_id;
2578         u32 pending;
2579         int i = 0;
2580         struct dw_mci_slot *slot = host->slot[i];
2581
2582         pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2583
2584         if (pending) {
2585                 /* Check volt switch first, since it can look like an error */
2586                 if ((host->state == STATE_SENDING_CMD11) &&
2587                     (pending & SDMMC_INT_VOLT_SWITCH)) {
2588                         unsigned long irqflags;
2589
2590                         mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
2591                         pending &= ~SDMMC_INT_VOLT_SWITCH;
2592
2593                         /*
2594                          * Hold the lock; we know cmd11_timer can't be kicked
2595                          * off after the lock is released, so safe to delete.
2596                          */
2597                         spin_lock_irqsave(&host->irq_lock, irqflags);
2598                         dw_mci_cmd_interrupt(host, pending);
2599                         spin_unlock_irqrestore(&host->irq_lock, irqflags);
2600
2601                         del_timer(&host->cmd11_timer);
2602                 }
2603
2604                 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2605                         mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
2606                         host->cmd_status = pending;
2607                         smp_wmb(); /* drain writebuffer */
2608                         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2609                 }
2610
2611                 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2612                         /* if there is an error report DATA_ERROR */
2613                         mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2614                         host->data_status = pending;
2615                         smp_wmb(); /* drain writebuffer */
2616                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
2617                         tasklet_schedule(&host->tasklet);
2618                 }
2619
2620                 if (pending & SDMMC_INT_DATA_OVER) {
2621                         del_timer(&host->dto_timer);
2622
2623                         mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2624                         if (!host->data_status)
2625                                 host->data_status = pending;
2626                         smp_wmb(); /* drain writebuffer */
2627                         if (host->dir_status == DW_MCI_RECV_STATUS) {
2628                                 if (host->sg != NULL)
2629                                         dw_mci_read_data_pio(host, true);
2630                         }
2631                         set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2632                         tasklet_schedule(&host->tasklet);
2633                 }
2634
2635                 if (pending & SDMMC_INT_RXDR) {
2636                         mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2637                         if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2638                                 dw_mci_read_data_pio(host, false);
2639                 }
2640
2641                 if (pending & SDMMC_INT_TXDR) {
2642                         mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2643                         if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2644                                 dw_mci_write_data_pio(host);
2645                 }
2646
2647                 if (pending & SDMMC_INT_CMD_DONE) {
2648                         mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2649                         dw_mci_cmd_interrupt(host, pending);
2650                 }
2651
2652                 if (pending & SDMMC_INT_CD) {
2653                         mci_writel(host, RINTSTS, SDMMC_INT_CD);
2654                         dw_mci_handle_cd(host);
2655                 }
2656
2657                 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
2658                         mci_writel(host, RINTSTS,
2659                                    SDMMC_INT_SDIO(slot->sdio_id));
2660                         __dw_mci_enable_sdio_irq(slot, 0);
2661                         sdio_signal_irq(slot->mmc);
2662                 }
2663
2664         }
2665
2666         if (host->use_dma != TRANS_MODE_IDMAC)
2667                 return IRQ_HANDLED;
2668
2669         /* Handle IDMA interrupts */
2670         if (host->dma_64bit_address == 1) {
2671                 pending = mci_readl(host, IDSTS64);
2672                 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2673                         mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2674                                                         SDMMC_IDMAC_INT_RI);
2675                         mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
2676                         if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2677                                 host->dma_ops->complete((void *)host);
2678                 }
2679         } else {
2680                 pending = mci_readl(host, IDSTS);
2681                 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2682                         mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2683                                                         SDMMC_IDMAC_INT_RI);
2684                         mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
2685                         if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2686                                 host->dma_ops->complete((void *)host);
2687                 }
2688         }
2689
2690         return IRQ_HANDLED;
2691 }
2692
2693 static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
2694 {
2695         struct mmc_host *mmc;
2696         struct dw_mci_slot *slot;
2697         const struct dw_mci_drv_data *drv_data = host->drv_data;
2698         int ctrl_id, ret;
2699         u32 freq[2];
2700
2701         mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
2702         if (!mmc)
2703                 return -ENOMEM;
2704
2705         slot = mmc_priv(mmc);
2706         slot->id = id;
2707         slot->sdio_id = host->sdio_id0 + id;
2708         slot->mmc = mmc;
2709         slot->host = host;
2710         host->slot[id] = slot;
2711
2712         mmc->ops = &dw_mci_ops;
2713         if (device_property_read_u32_array(host->dev, "clock-freq-min-max",
2714                                            freq, 2)) {
2715                 mmc->f_min = DW_MCI_FREQ_MIN;
2716                 mmc->f_max = DW_MCI_FREQ_MAX;
2717         } else {
2718                 dev_info(host->dev,
2719                         "'clock-freq-min-max' property was deprecated.\n");
2720                 mmc->f_min = freq[0];
2721                 mmc->f_max = freq[1];
2722         }
2723
2724         /*if there are external regulators, get them*/
2725         ret = mmc_regulator_get_supply(mmc);
2726         if (ret == -EPROBE_DEFER)
2727                 goto err_host_allocated;
2728
2729         if (!mmc->ocr_avail)
2730                 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2731
2732         if (host->pdata->caps)
2733                 mmc->caps = host->pdata->caps;
2734
2735         /*
2736          * Support MMC_CAP_ERASE by default.
2737          * It needs to use trim/discard/erase commands.
2738          */
2739         mmc->caps |= MMC_CAP_ERASE;
2740
2741         if (host->pdata->pm_caps)
2742                 mmc->pm_caps = host->pdata->pm_caps;
2743
2744         if (host->dev->of_node) {
2745                 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2746                 if (ctrl_id < 0)
2747                         ctrl_id = 0;
2748         } else {
2749                 ctrl_id = to_platform_device(host->dev)->id;
2750         }
2751         if (drv_data && drv_data->caps)
2752                 mmc->caps |= drv_data->caps[ctrl_id];
2753
2754         if (host->pdata->caps2)
2755                 mmc->caps2 = host->pdata->caps2;
2756
2757         ret = mmc_of_parse(mmc);
2758         if (ret)
2759                 goto err_host_allocated;
2760
2761         /* Process SDIO IRQs through the sdio_irq_work. */
2762         if (mmc->caps & MMC_CAP_SDIO_IRQ)
2763                 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
2764
2765         /* Useful defaults if platform data is unset. */
2766         if (host->use_dma == TRANS_MODE_IDMAC) {
2767                 mmc->max_segs = host->ring_size;
2768                 mmc->max_blk_size = 65535;
2769                 mmc->max_seg_size = 0x1000;
2770                 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2771                 mmc->max_blk_count = mmc->max_req_size / 512;
2772         } else if (host->use_dma == TRANS_MODE_EDMAC) {
2773                 mmc->max_segs = 64;
2774                 mmc->max_blk_size = 65535;
2775                 mmc->max_blk_count = 65535;
2776                 mmc->max_req_size =
2777                                 mmc->max_blk_size * mmc->max_blk_count;
2778                 mmc->max_seg_size = mmc->max_req_size;
2779         } else {
2780                 /* TRANS_MODE_PIO */
2781                 mmc->max_segs = 64;
2782                 mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */
2783                 mmc->max_blk_count = 512;
2784                 mmc->max_req_size = mmc->max_blk_size *
2785                                     mmc->max_blk_count;
2786                 mmc->max_seg_size = mmc->max_req_size;
2787         }
2788
2789         dw_mci_get_cd(mmc);
2790
2791         ret = mmc_add_host(mmc);
2792         if (ret)
2793                 goto err_host_allocated;
2794
2795 #if defined(CONFIG_DEBUG_FS)
2796         dw_mci_init_debugfs(slot);
2797 #endif
2798
2799         return 0;
2800
2801 err_host_allocated:
2802         mmc_free_host(mmc);
2803         return ret;
2804 }
2805
2806 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
2807 {
2808         /* Debugfs stuff is cleaned up by mmc core */
2809         mmc_remove_host(slot->mmc);
2810         slot->host->slot[id] = NULL;
2811         mmc_free_host(slot->mmc);
2812 }
2813
2814 static void dw_mci_init_dma(struct dw_mci *host)
2815 {
2816         int addr_config;
2817         struct device *dev = host->dev;
2818
2819         /*
2820         * Check tansfer mode from HCON[17:16]
2821         * Clear the ambiguous description of dw_mmc databook:
2822         * 2b'00: No DMA Interface -> Actually means using Internal DMA block
2823         * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block
2824         * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block
2825         * 2b'11: Non DW DMA Interface -> pio only
2826         * Compared to DesignWare DMA Interface, Generic DMA Interface has a
2827         * simpler request/acknowledge handshake mechanism and both of them
2828         * are regarded as external dma master for dw_mmc.
2829         */
2830         host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
2831         if (host->use_dma == DMA_INTERFACE_IDMA) {
2832                 host->use_dma = TRANS_MODE_IDMAC;
2833         } else if (host->use_dma == DMA_INTERFACE_DWDMA ||
2834                    host->use_dma == DMA_INTERFACE_GDMA) {
2835                 host->use_dma = TRANS_MODE_EDMAC;
2836         } else {
2837                 goto no_dma;
2838         }
2839
2840         /* Determine which DMA interface to use */
2841         if (host->use_dma == TRANS_MODE_IDMAC) {
2842                 /*
2843                 * Check ADDR_CONFIG bit in HCON to find
2844                 * IDMAC address bus width
2845                 */
2846                 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
2847
2848                 if (addr_config == 1) {
2849                         /* host supports IDMAC in 64-bit address mode */
2850                         host->dma_64bit_address = 1;
2851                         dev_info(host->dev,
2852                                  "IDMAC supports 64-bit address mode.\n");
2853                         if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
2854                                 dma_set_coherent_mask(host->dev,
2855                                                       DMA_BIT_MASK(64));
2856                 } else {
2857                         /* host supports IDMAC in 32-bit address mode */
2858                         host->dma_64bit_address = 0;
2859                         dev_info(host->dev,
2860                                  "IDMAC supports 32-bit address mode.\n");
2861                 }
2862
2863                 /* Alloc memory for sg translation */
2864                 host->sg_cpu = dmam_alloc_coherent(host->dev,
2865                                                    DESC_RING_BUF_SZ,
2866                                                    &host->sg_dma, GFP_KERNEL);
2867                 if (!host->sg_cpu) {
2868                         dev_err(host->dev,
2869                                 "%s: could not alloc DMA memory\n",
2870                                 __func__);
2871                         goto no_dma;
2872                 }
2873
2874                 host->dma_ops = &dw_mci_idmac_ops;
2875                 dev_info(host->dev, "Using internal DMA controller.\n");
2876         } else {
2877                 /* TRANS_MODE_EDMAC: check dma bindings again */
2878                 if ((device_property_read_string_array(dev, "dma-names",
2879                                                        NULL, 0) < 0) ||
2880                     !device_property_present(dev, "dmas")) {
2881                         goto no_dma;
2882                 }
2883                 host->dma_ops = &dw_mci_edmac_ops;
2884                 dev_info(host->dev, "Using external DMA controller.\n");
2885         }
2886
2887         if (host->dma_ops->init && host->dma_ops->start &&
2888             host->dma_ops->stop && host->dma_ops->cleanup) {
2889                 if (host->dma_ops->init(host)) {
2890                         dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n",
2891                                 __func__);
2892                         goto no_dma;
2893                 }
2894         } else {
2895                 dev_err(host->dev, "DMA initialization not found.\n");
2896                 goto no_dma;
2897         }
2898
2899         return;
2900
2901 no_dma:
2902         dev_info(host->dev, "Using PIO mode.\n");
2903         host->use_dma = TRANS_MODE_PIO;
2904 }
2905
2906 static void dw_mci_cmd11_timer(unsigned long arg)
2907 {
2908         struct dw_mci *host = (struct dw_mci *)arg;
2909
2910         if (host->state != STATE_SENDING_CMD11) {
2911                 dev_warn(host->dev, "Unexpected CMD11 timeout\n");
2912                 return;
2913         }
2914
2915         host->cmd_status = SDMMC_INT_RTO;
2916         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2917         tasklet_schedule(&host->tasklet);
2918 }
2919
2920 static void dw_mci_dto_timer(unsigned long arg)
2921 {
2922         struct dw_mci *host = (struct dw_mci *)arg;
2923
2924         switch (host->state) {
2925         case STATE_SENDING_DATA:
2926         case STATE_DATA_BUSY:
2927                 /*
2928                  * If DTO interrupt does NOT come in sending data state,
2929                  * we should notify the driver to terminate current transfer
2930                  * and report a data timeout to the core.
2931                  */
2932                 host->data_status = SDMMC_INT_DRTO;
2933                 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2934                 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2935                 tasklet_schedule(&host->tasklet);
2936                 break;
2937         default:
2938                 break;
2939         }
2940 }
2941
2942 #ifdef CONFIG_OF
2943 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2944 {
2945         struct dw_mci_board *pdata;
2946         struct device *dev = host->dev;
2947         const struct dw_mci_drv_data *drv_data = host->drv_data;
2948         int ret;
2949         u32 clock_frequency;
2950
2951         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2952         if (!pdata)
2953                 return ERR_PTR(-ENOMEM);
2954
2955         /* find reset controller when exist */
2956         pdata->rstc = devm_reset_control_get_optional(dev, "reset");
2957         if (IS_ERR(pdata->rstc)) {
2958                 if (PTR_ERR(pdata->rstc) == -EPROBE_DEFER)
2959                         return ERR_PTR(-EPROBE_DEFER);
2960         }
2961
2962         /* find out number of slots supported */
2963         if (device_property_read_u32(dev, "num-slots", &pdata->num_slots))
2964                 dev_info(dev, "'num-slots' was deprecated.\n");
2965
2966         if (device_property_read_u32(dev, "fifo-depth", &pdata->fifo_depth))
2967                 dev_info(dev,
2968                          "fifo-depth property not found, using value of FIFOTH register as default\n");
2969
2970         device_property_read_u32(dev, "card-detect-delay",
2971                                  &pdata->detect_delay_ms);
2972
2973         device_property_read_u32(dev, "data-addr", &host->data_addr_override);
2974
2975         if (device_property_present(dev, "fifo-watermark-aligned"))
2976                 host->wm_aligned = true;
2977
2978         if (!device_property_read_u32(dev, "clock-frequency", &clock_frequency))
2979                 pdata->bus_hz = clock_frequency;
2980
2981         if (drv_data && drv_data->parse_dt) {
2982                 ret = drv_data->parse_dt(host);
2983                 if (ret)
2984                         return ERR_PTR(ret);
2985         }
2986
2987         return pdata;
2988 }
2989
2990 #else /* CONFIG_OF */
2991 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2992 {
2993         return ERR_PTR(-EINVAL);
2994 }
2995 #endif /* CONFIG_OF */
2996
2997 static void dw_mci_enable_cd(struct dw_mci *host)
2998 {
2999         unsigned long irqflags;
3000         u32 temp;
3001         int i = 0;
3002         struct dw_mci_slot *slot;
3003
3004         /*
3005          * No need for CD if all slots have a non-error GPIO
3006          * as well as broken card detection is found.
3007          */
3008         slot = host->slot[i];
3009         if (slot->mmc->caps & MMC_CAP_NEEDS_POLL)
3010                 return;
3011
3012         if (mmc_gpio_get_cd(slot->mmc) < 0) {
3013                 spin_lock_irqsave(&host->irq_lock, irqflags);
3014                 temp = mci_readl(host, INTMASK);
3015                 temp  |= SDMMC_INT_CD;
3016                 mci_writel(host, INTMASK, temp);
3017                 spin_unlock_irqrestore(&host->irq_lock, irqflags);
3018         }
3019 }
3020
3021 int dw_mci_probe(struct dw_mci *host)
3022 {
3023         const struct dw_mci_drv_data *drv_data = host->drv_data;
3024         int width, i, ret = 0;
3025         u32 fifo_size;
3026
3027         if (!host->pdata) {
3028                 host->pdata = dw_mci_parse_dt(host);
3029                 if (PTR_ERR(host->pdata) == -EPROBE_DEFER) {
3030                         return -EPROBE_DEFER;
3031                 } else if (IS_ERR(host->pdata)) {
3032                         dev_err(host->dev, "platform data not available\n");
3033                         return -EINVAL;
3034                 }
3035         }
3036
3037         host->biu_clk = devm_clk_get(host->dev, "biu");
3038         if (IS_ERR(host->biu_clk)) {
3039                 dev_dbg(host->dev, "biu clock not available\n");
3040         } else {
3041                 ret = clk_prepare_enable(host->biu_clk);
3042                 if (ret) {
3043                         dev_err(host->dev, "failed to enable biu clock\n");
3044                         return ret;
3045                 }
3046         }
3047
3048         host->ciu_clk = devm_clk_get(host->dev, "ciu");
3049         if (IS_ERR(host->ciu_clk)) {
3050                 dev_dbg(host->dev, "ciu clock not available\n");
3051                 host->bus_hz = host->pdata->bus_hz;
3052         } else {
3053                 ret = clk_prepare_enable(host->ciu_clk);
3054                 if (ret) {
3055                         dev_err(host->dev, "failed to enable ciu clock\n");
3056                         goto err_clk_biu;
3057                 }
3058
3059                 if (host->pdata->bus_hz) {
3060                         ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
3061                         if (ret)
3062                                 dev_warn(host->dev,
3063                                          "Unable to set bus rate to %uHz\n",
3064                                          host->pdata->bus_hz);
3065                 }
3066                 host->bus_hz = clk_get_rate(host->ciu_clk);
3067         }
3068
3069         if (!host->bus_hz) {
3070                 dev_err(host->dev,
3071                         "Platform data must supply bus speed\n");
3072                 ret = -ENODEV;
3073                 goto err_clk_ciu;
3074         }
3075
3076         if (drv_data && drv_data->init) {
3077                 ret = drv_data->init(host);
3078                 if (ret) {
3079                         dev_err(host->dev,
3080                                 "implementation specific init failed\n");
3081                         goto err_clk_ciu;
3082                 }
3083         }
3084
3085         if (!IS_ERR(host->pdata->rstc)) {
3086                 reset_control_assert(host->pdata->rstc);
3087                 usleep_range(10, 50);
3088                 reset_control_deassert(host->pdata->rstc);
3089         }
3090
3091         setup_timer(&host->cmd11_timer,
3092                     dw_mci_cmd11_timer, (unsigned long)host);
3093
3094         setup_timer(&host->dto_timer,
3095                     dw_mci_dto_timer, (unsigned long)host);
3096
3097         spin_lock_init(&host->lock);
3098         spin_lock_init(&host->irq_lock);
3099         INIT_LIST_HEAD(&host->queue);
3100
3101         /*
3102          * Get the host data width - this assumes that HCON has been set with
3103          * the correct values.
3104          */
3105         i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));
3106         if (!i) {
3107                 host->push_data = dw_mci_push_data16;
3108                 host->pull_data = dw_mci_pull_data16;
3109                 width = 16;
3110                 host->data_shift = 1;
3111         } else if (i == 2) {
3112                 host->push_data = dw_mci_push_data64;
3113                 host->pull_data = dw_mci_pull_data64;
3114                 width = 64;
3115                 host->data_shift = 3;
3116         } else {
3117                 /* Check for a reserved value, and warn if it is */
3118                 WARN((i != 1),
3119                      "HCON reports a reserved host data width!\n"
3120                      "Defaulting to 32-bit access.\n");
3121                 host->push_data = dw_mci_push_data32;
3122                 host->pull_data = dw_mci_pull_data32;
3123                 width = 32;
3124                 host->data_shift = 2;
3125         }
3126
3127         /* Reset all blocks */
3128         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3129                 ret = -ENODEV;
3130                 goto err_clk_ciu;
3131         }
3132
3133         host->dma_ops = host->pdata->dma_ops;
3134         dw_mci_init_dma(host);
3135
3136         /* Clear the interrupts for the host controller */
3137         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3138         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3139
3140         /* Put in max timeout */
3141         mci_writel(host, TMOUT, 0xFFFFFFFF);
3142
3143         /*
3144          * FIFO threshold settings  RxMark  = fifo_size / 2 - 1,
3145          *                          Tx Mark = fifo_size / 2 DMA Size = 8
3146          */
3147         if (!host->pdata->fifo_depth) {
3148                 /*
3149                  * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
3150                  * have been overwritten by the bootloader, just like we're
3151                  * about to do, so if you know the value for your hardware, you
3152                  * should put it in the platform data.
3153                  */
3154                 fifo_size = mci_readl(host, FIFOTH);
3155                 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
3156         } else {
3157                 fifo_size = host->pdata->fifo_depth;
3158         }
3159         host->fifo_depth = fifo_size;
3160         host->fifoth_val =
3161                 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
3162         mci_writel(host, FIFOTH, host->fifoth_val);
3163
3164         /* disable clock to CIU */
3165         mci_writel(host, CLKENA, 0);
3166         mci_writel(host, CLKSRC, 0);
3167
3168         /*
3169          * In 2.40a spec, Data offset is changed.
3170          * Need to check the version-id and set data-offset for DATA register.
3171          */
3172         host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
3173         dev_info(host->dev, "Version ID is %04x\n", host->verid);
3174
3175         if (host->data_addr_override)
3176                 host->fifo_reg = host->regs + host->data_addr_override;
3177         else if (host->verid < DW_MMC_240A)
3178                 host->fifo_reg = host->regs + DATA_OFFSET;
3179         else
3180                 host->fifo_reg = host->regs + DATA_240A_OFFSET;
3181
3182         tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
3183         ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
3184                                host->irq_flags, "dw-mci", host);
3185         if (ret)
3186                 goto err_dmaunmap;
3187
3188         /*
3189          * Enable interrupts for command done, data over, data empty,
3190          * receive ready and error such as transmit, receive timeout, crc error
3191          */
3192         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3193                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3194                    DW_MCI_ERROR_FLAGS);
3195         /* Enable mci interrupt */
3196         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3197
3198         dev_info(host->dev,
3199                  "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n",
3200                  host->irq, width, fifo_size);
3201
3202         /* We need at least one slot to succeed */
3203         ret = dw_mci_init_slot(host, 0);
3204         if (ret) {
3205                 dev_dbg(host->dev, "slot %d init failed\n", i);
3206                 goto err_dmaunmap;
3207         }
3208
3209         /* Now that slots are all setup, we can enable card detect */
3210         dw_mci_enable_cd(host);
3211
3212         return 0;
3213
3214 err_dmaunmap:
3215         if (host->use_dma && host->dma_ops->exit)
3216                 host->dma_ops->exit(host);
3217
3218         if (!IS_ERR(host->pdata->rstc))
3219                 reset_control_assert(host->pdata->rstc);
3220
3221 err_clk_ciu:
3222         clk_disable_unprepare(host->ciu_clk);
3223
3224 err_clk_biu:
3225         clk_disable_unprepare(host->biu_clk);
3226
3227         return ret;
3228 }
3229 EXPORT_SYMBOL(dw_mci_probe);
3230
3231 void dw_mci_remove(struct dw_mci *host)
3232 {
3233         int i = 0;
3234
3235         dev_dbg(host->dev, "remove slot %d\n", i);
3236         if (host->slot[i])
3237                 dw_mci_cleanup_slot(host->slot[i], i);
3238
3239         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3240         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3241
3242         /* disable clock to CIU */
3243         mci_writel(host, CLKENA, 0);
3244         mci_writel(host, CLKSRC, 0);
3245
3246         if (host->use_dma && host->dma_ops->exit)
3247                 host->dma_ops->exit(host);
3248
3249         if (!IS_ERR(host->pdata->rstc))
3250                 reset_control_assert(host->pdata->rstc);
3251
3252         clk_disable_unprepare(host->ciu_clk);
3253         clk_disable_unprepare(host->biu_clk);
3254 }
3255 EXPORT_SYMBOL(dw_mci_remove);
3256
3257
3258
3259 #ifdef CONFIG_PM
3260 int dw_mci_runtime_suspend(struct device *dev)
3261 {
3262         struct dw_mci *host = dev_get_drvdata(dev);
3263
3264         if (host->use_dma && host->dma_ops->exit)
3265                 host->dma_ops->exit(host);
3266
3267         clk_disable_unprepare(host->ciu_clk);
3268
3269         if (host->cur_slot &&
3270             (mmc_can_gpio_cd(host->cur_slot->mmc) ||
3271              !mmc_card_is_removable(host->cur_slot->mmc)))
3272                 clk_disable_unprepare(host->biu_clk);
3273
3274         return 0;
3275 }
3276 EXPORT_SYMBOL(dw_mci_runtime_suspend);
3277
3278 int dw_mci_runtime_resume(struct device *dev)
3279 {
3280         int i = 0, ret = 0;
3281         struct dw_mci *host = dev_get_drvdata(dev);
3282         struct dw_mci_slot *slot = host->slot[i];
3283
3284         if (host->cur_slot &&
3285             (mmc_can_gpio_cd(host->cur_slot->mmc) ||
3286              !mmc_card_is_removable(host->cur_slot->mmc))) {
3287                 ret = clk_prepare_enable(host->biu_clk);
3288                 if (ret)
3289                         return ret;
3290         }
3291
3292         ret = clk_prepare_enable(host->ciu_clk);
3293         if (ret)
3294                 goto err;
3295
3296         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3297                 clk_disable_unprepare(host->ciu_clk);
3298                 ret = -ENODEV;
3299                 goto err;
3300         }
3301
3302         if (host->use_dma && host->dma_ops->init)
3303                 host->dma_ops->init(host);
3304
3305         /*
3306          * Restore the initial value at FIFOTH register
3307          * And Invalidate the prev_blksz with zero
3308          */
3309          mci_writel(host, FIFOTH, host->fifoth_val);
3310          host->prev_blksz = 0;
3311
3312         /* Put in max timeout */
3313         mci_writel(host, TMOUT, 0xFFFFFFFF);
3314
3315         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3316         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3317                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3318                    DW_MCI_ERROR_FLAGS);
3319         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3320
3321
3322         if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER)
3323                 dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
3324
3325         /* Force setup bus to guarantee available clock output */
3326         dw_mci_setup_bus(slot, true);
3327
3328         /* Now that slots are all setup, we can enable card detect */
3329         dw_mci_enable_cd(host);
3330
3331         return 0;
3332
3333 err:
3334         if (host->cur_slot &&
3335             (mmc_can_gpio_cd(host->cur_slot->mmc) ||
3336              !mmc_card_is_removable(host->cur_slot->mmc)))
3337                 clk_disable_unprepare(host->biu_clk);
3338
3339         return ret;
3340 }
3341 EXPORT_SYMBOL(dw_mci_runtime_resume);
3342 #endif /* CONFIG_PM */
3343
3344 static int __init dw_mci_init(void)
3345 {
3346         pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
3347         return 0;
3348 }
3349
3350 static void __exit dw_mci_exit(void)
3351 {
3352 }
3353
3354 module_init(dw_mci_init);
3355 module_exit(dw_mci_exit);
3356
3357 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
3358 MODULE_AUTHOR("NXP Semiconductor VietNam");
3359 MODULE_AUTHOR("Imagination Technologies Ltd");
3360 MODULE_LICENSE("GPL v2");