2 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include <linux/module.h>
11 #include <linux/platform_device.h>
12 #include <linux/clk.h>
13 #include <linux/mmc/host.h>
14 #include <linux/mmc/dw_mmc.h>
15 #include <linux/of_address.h>
16 #include <linux/slab.h>
19 #include "dw_mmc-pltfm.h"
21 #define RK3288_CLKGEN_DIV 2
23 struct dw_mci_rockchip_priv_data {
25 struct clk *sample_clk;
26 int default_sample_phase;
29 static void dw_mci_rockchip_prepare_command(struct dw_mci *host, u32 *cmdr)
31 *cmdr |= SDMMC_CMD_USE_HOLD_REG;
34 static int dw_mci_rk3288_setup_clock(struct dw_mci *host)
36 host->bus_hz /= RK3288_CLKGEN_DIV;
41 static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios)
43 struct dw_mci_rockchip_priv_data *priv = host->priv;
52 * cclkin: source clock of mmc controller
53 * bus_hz: card interface clock generated by CLKGEN
54 * bus_hz = cclkin / RK3288_CLKGEN_DIV
55 * ios->clock = (div == 0) ? bus_hz : (bus_hz / (2 * div))
57 * Note: div can only be 0 or 1
58 * if DDR50 8bit mode(only emmc work in 8bit mode),
61 if (ios->bus_width == MMC_BUS_WIDTH_8 &&
62 ios->timing == MMC_TIMING_MMC_DDR52)
63 cclkin = 2 * ios->clock * RK3288_CLKGEN_DIV;
65 cclkin = ios->clock * RK3288_CLKGEN_DIV;
67 ret = clk_set_rate(host->ciu_clk, cclkin);
69 dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock);
71 bus_hz = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV;
72 if (bus_hz != host->bus_hz) {
73 host->bus_hz = bus_hz;
74 /* force dw_mci_setup_bus() */
75 host->current_speed = 0;
78 /* Make sure we use phases which we can enumerate with */
79 if (!IS_ERR(priv->sample_clk))
80 clk_set_phase(priv->sample_clk, priv->default_sample_phase);
83 #define NUM_PHASES 360
84 #define TUNING_ITERATION_TO_PHASE(i) (DIV_ROUND_UP((i) * 360, NUM_PHASES))
86 static int dw_mci_rk3288_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
88 struct dw_mci *host = slot->host;
89 struct dw_mci_rockchip_priv_data *priv = host->priv;
90 struct mmc_host *mmc = slot->mmc;
93 bool v, prev_v = 0, first_v;
96 int end; /* inclusive */
98 struct range_t *ranges;
99 unsigned int range_count = 0;
100 int longest_range_len = -1;
101 int longest_range = -1;
104 if (IS_ERR(priv->sample_clk)) {
105 dev_err(host->dev, "Tuning clock (sample_clk) not defined.\n");
109 ranges = kmalloc_array(NUM_PHASES / 2 + 1, sizeof(*ranges), GFP_KERNEL);
113 /* Try each phase and extract good ranges */
114 for (i = 0; i < NUM_PHASES; ) {
115 clk_set_phase(priv->sample_clk, TUNING_ITERATION_TO_PHASE(i));
117 v = !mmc_send_tuning(mmc, opcode, NULL);
122 if ((!prev_v) && v) {
124 ranges[range_count-1].start = i;
127 ranges[range_count-1].end = i;
129 } else if (i == NUM_PHASES - 1) {
130 /* No extra skipping rules if we're at the end */
134 * No need to check too close to an invalid
135 * one since testing bad phases is slow. Skip
138 i += DIV_ROUND_UP(20 * NUM_PHASES, 360);
140 /* Always test the last one */
148 if (range_count == 0) {
149 dev_warn(host->dev, "All phases bad!");
154 /* wrap around case, merge the end points */
155 if ((range_count > 1) && first_v && v) {
156 ranges[0].start = ranges[range_count-1].start;
160 if (ranges[0].start == 0 && ranges[0].end == NUM_PHASES - 1) {
161 clk_set_phase(priv->sample_clk, priv->default_sample_phase);
162 dev_info(host->dev, "All phases work, using default phase %d.",
163 priv->default_sample_phase);
167 /* Find the longest range */
168 for (i = 0; i < range_count; i++) {
169 int len = (ranges[i].end - ranges[i].start + 1);
174 if (longest_range_len < len) {
175 longest_range_len = len;
179 dev_dbg(host->dev, "Good phase range %d-%d (%d len)\n",
180 TUNING_ITERATION_TO_PHASE(ranges[i].start),
181 TUNING_ITERATION_TO_PHASE(ranges[i].end),
186 dev_dbg(host->dev, "Best phase range %d-%d (%d len)\n",
187 TUNING_ITERATION_TO_PHASE(ranges[longest_range].start),
188 TUNING_ITERATION_TO_PHASE(ranges[longest_range].end),
192 middle_phase = ranges[longest_range].start + longest_range_len / 2;
193 middle_phase %= NUM_PHASES;
194 dev_info(host->dev, "Successfully tuned phase to %d\n",
195 TUNING_ITERATION_TO_PHASE(middle_phase));
197 clk_set_phase(priv->sample_clk,
198 TUNING_ITERATION_TO_PHASE(middle_phase));
205 static int dw_mci_rk3288_parse_dt(struct dw_mci *host)
207 struct device_node *np = host->dev->of_node;
208 struct dw_mci_rockchip_priv_data *priv;
210 priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
214 if (of_property_read_u32(np, "rockchip,default-sample-phase",
215 &priv->default_sample_phase))
216 priv->default_sample_phase = 0;
218 priv->drv_clk = devm_clk_get(host->dev, "ciu-drive");
219 if (IS_ERR(priv->drv_clk))
220 dev_dbg(host->dev, "ciu_drv not available\n");
222 priv->sample_clk = devm_clk_get(host->dev, "ciu-sample");
223 if (IS_ERR(priv->sample_clk))
224 dev_dbg(host->dev, "ciu_sample not available\n");
231 static int dw_mci_rockchip_init(struct dw_mci *host)
233 /* It is slot 8 on Rockchip SoCs */
236 /* It needs this quirk on all Rockchip SoCs */
237 host->pdata->quirks |= DW_MCI_QUIRK_BROKEN_DTO;
242 static const struct dw_mci_drv_data rk2928_drv_data = {
243 .prepare_command = dw_mci_rockchip_prepare_command,
244 .init = dw_mci_rockchip_init,
247 static const struct dw_mci_drv_data rk3288_drv_data = {
248 .prepare_command = dw_mci_rockchip_prepare_command,
249 .set_ios = dw_mci_rk3288_set_ios,
250 .execute_tuning = dw_mci_rk3288_execute_tuning,
251 .parse_dt = dw_mci_rk3288_parse_dt,
252 .setup_clock = dw_mci_rk3288_setup_clock,
253 .init = dw_mci_rockchip_init,
256 static const struct of_device_id dw_mci_rockchip_match[] = {
257 { .compatible = "rockchip,rk2928-dw-mshc",
258 .data = &rk2928_drv_data },
259 { .compatible = "rockchip,rk3288-dw-mshc",
260 .data = &rk3288_drv_data },
263 MODULE_DEVICE_TABLE(of, dw_mci_rockchip_match);
265 static int dw_mci_rockchip_probe(struct platform_device *pdev)
267 const struct dw_mci_drv_data *drv_data;
268 const struct of_device_id *match;
270 if (!pdev->dev.of_node)
273 match = of_match_node(dw_mci_rockchip_match, pdev->dev.of_node);
274 drv_data = match->data;
276 return dw_mci_pltfm_register(pdev, drv_data);
279 #ifdef CONFIG_PM_SLEEP
280 static int dw_mci_rockchip_suspend(struct device *dev)
282 struct dw_mci *host = dev_get_drvdata(dev);
284 return dw_mci_suspend(host);
287 static int dw_mci_rockchip_resume(struct device *dev)
289 struct dw_mci *host = dev_get_drvdata(dev);
291 return dw_mci_resume(host);
293 #endif /* CONFIG_PM_SLEEP */
295 static SIMPLE_DEV_PM_OPS(dw_mci_rockchip_pmops,
296 dw_mci_rockchip_suspend,
297 dw_mci_rockchip_resume);
299 static struct platform_driver dw_mci_rockchip_pltfm_driver = {
300 .probe = dw_mci_rockchip_probe,
301 .remove = dw_mci_pltfm_remove,
303 .name = "dwmmc_rockchip",
304 .of_match_table = dw_mci_rockchip_match,
305 .pm = &dw_mci_rockchip_pmops,
309 module_platform_driver(dw_mci_rockchip_pltfm_driver);
311 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
312 MODULE_DESCRIPTION("Rockchip Specific DW-MSHC Driver Extension");
313 MODULE_ALIAS("platform:dwmmc_rockchip");
314 MODULE_LICENSE("GPL v2");