drivers/mmc/host/bfin_sdh.c

   1 /*
   2  * bfin_sdh.c - Analog Devices Blackfin SDH Controller
   3  *
   4  * Copyright (C) 2007-2009 Analog Device Inc.
   5  *
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 #define DRIVER_NAME     "bfin-sdh"
  10
  11 #include <linux/module.h>
  12 #include <linux/init.h>
  13 #include <linux/ioport.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/delay.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/mmc/host.h>
  19 #include <linux/proc_fs.h>
  20 #include <linux/gfp.h>
  21
  22 #include <asm/cacheflush.h>
  23 #include <asm/dma.h>
  24 #include <asm/portmux.h>
  25 #include <asm/bfin_sdh.h>
  26
  27 #if defined(CONFIG_BF51x)
  28 #define bfin_read_SDH_PWR_CTL           bfin_read_RSI_PWR_CTL
  29 #define bfin_write_SDH_PWR_CTL          bfin_write_RSI_PWR_CTL
  30 #define bfin_read_SDH_CLK_CTL           bfin_read_RSI_CLK_CTL
  31 #define bfin_write_SDH_CLK_CTL          bfin_write_RSI_CLK_CTL
  32 #define bfin_write_SDH_ARGUMENT         bfin_write_RSI_ARGUMENT
  33 #define bfin_write_SDH_COMMAND          bfin_write_RSI_COMMAND
  34 #define bfin_write_SDH_DATA_TIMER       bfin_write_RSI_DATA_TIMER
  35 #define bfin_read_SDH_RESPONSE0         bfin_read_RSI_RESPONSE0
  36 #define bfin_read_SDH_RESPONSE1         bfin_read_RSI_RESPONSE1
  37 #define bfin_read_SDH_RESPONSE2         bfin_read_RSI_RESPONSE2
  38 #define bfin_read_SDH_RESPONSE3         bfin_read_RSI_RESPONSE3
  39 #define bfin_write_SDH_DATA_LGTH        bfin_write_RSI_DATA_LGTH
  40 #define bfin_read_SDH_DATA_CTL          bfin_read_RSI_DATA_CTL
  41 #define bfin_write_SDH_DATA_CTL         bfin_write_RSI_DATA_CTL
  42 #define bfin_read_SDH_DATA_CNT          bfin_read_RSI_DATA_CNT
  43 #define bfin_write_SDH_STATUS_CLR       bfin_write_RSI_STATUS_CLR
  44 #define bfin_read_SDH_E_STATUS          bfin_read_RSI_E_STATUS
  45 #define bfin_write_SDH_E_STATUS         bfin_write_RSI_E_STATUS
  46 #define bfin_read_SDH_STATUS            bfin_read_RSI_STATUS
  47 #define bfin_write_SDH_MASK0            bfin_write_RSI_MASK0
  48 #define bfin_read_SDH_CFG               bfin_read_RSI_CFG
  49 #define bfin_write_SDH_CFG              bfin_write_RSI_CFG
  50 #endif
  51
  52 struct dma_desc_array {
  53         unsigned long   start_addr;
  54         unsigned short  cfg;
  55         unsigned short  x_count;
  56         short           x_modify;
  57 } __packed;
  58
  59 struct sdh_host {
  60         struct mmc_host         *mmc;
  61         spinlock_t              lock;
  62         struct resource         *res;
  63         void __iomem            *base;
  64         int                     irq;
  65         int                     stat_irq;
  66         int                     dma_ch;
  67         int                     dma_dir;
  68         struct dma_desc_array   *sg_cpu;
  69         dma_addr_t              sg_dma;
  70         int                     dma_len;
  71
  72         unsigned int            imask;
  73         unsigned int            power_mode;
  74         unsigned int            clk_div;
  75
  76         struct mmc_request      *mrq;
  77         struct mmc_command      *cmd;
  78         struct mmc_data         *data;
  79 };
  80
  81 static struct bfin_sd_host *get_sdh_data(struct platform_device *pdev)
  82 {
  83         return pdev->dev.platform_data;
  84 }
  85
  86 static void sdh_stop_clock(struct sdh_host *host)
  87 {
  88         bfin_write_SDH_CLK_CTL(bfin_read_SDH_CLK_CTL() & ~CLK_E);
  89         SSYNC();
  90 }
  91
  92 static void sdh_enable_stat_irq(struct sdh_host *host, unsigned int mask)
  93 {
  94         unsigned long flags;
  95
  96         spin_lock_irqsave(&host->lock, flags);
  97         host->imask |= mask;
  98         bfin_write_SDH_MASK0(mask);
  99         SSYNC();
 100         spin_unlock_irqrestore(&host->lock, flags);
 101 }
 102
 103 static void sdh_disable_stat_irq(struct sdh_host *host, unsigned int mask)
 104 {
 105         unsigned long flags;
 106
 107         spin_lock_irqsave(&host->lock, flags);
 108         host->imask &= ~mask;
 109         bfin_write_SDH_MASK0(host->imask);
 110         SSYNC();
 111         spin_unlock_irqrestore(&host->lock, flags);
 112 }
 113
 114 static int sdh_setup_data(struct sdh_host *host, struct mmc_data *data)
 115 {
 116         unsigned int length;
 117         unsigned int data_ctl;
 118         unsigned int dma_cfg;
 119         unsigned int cycle_ns, timeout;
 120
 121         dev_dbg(mmc_dev(host->mmc), "%s enter flags: 0x%x\n", __func__, data->flags);
 122         host->data = data;
 123         data_ctl = 0;
 124         dma_cfg = 0;
 125
 126         length = data->blksz * data->blocks;
 127         bfin_write_SDH_DATA_LGTH(length);
 128
 129         if (data->flags & MMC_DATA_STREAM)
 130                 data_ctl |= DTX_MODE;
 131
 132         if (data->flags & MMC_DATA_READ)
 133                 data_ctl |= DTX_DIR;
 134         /* Only supports power-of-2 block size */
 135         if (data->blksz & (data->blksz - 1))
 136                 return -EINVAL;
 137         data_ctl |= ((ffs(data->blksz) - 1) << 4);
 138
 139         bfin_write_SDH_DATA_CTL(data_ctl);
 140         /* the time of a host clock period in ns */
 141         cycle_ns = 1000000000 / (get_sclk() / (2 * (host->clk_div + 1)));
 142         timeout = data->timeout_ns / cycle_ns;
 143         timeout += data->timeout_clks;
 144         bfin_write_SDH_DATA_TIMER(timeout);
 145         SSYNC();
 146
 147         if (data->flags & MMC_DATA_READ) {
 148                 host->dma_dir = DMA_FROM_DEVICE;
 149                 dma_cfg |= WNR;
 150         } else
 151                 host->dma_dir = DMA_TO_DEVICE;
 152
 153         sdh_enable_stat_irq(host, (DAT_CRC_FAIL | DAT_TIME_OUT | DAT_END));
 154         host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma_dir);
 155 #if defined(CONFIG_BF54x)
 156         dma_cfg |= DMAFLOW_ARRAY | NDSIZE_5 | RESTART | WDSIZE_32 | DMAEN;
 157         {
 158                 struct scatterlist *sg;
 159                 int i;
 160                 for_each_sg(data->sg, sg, host->dma_len, i) {
 161                         host->sg_cpu[i].start_addr = sg_dma_address(sg);
 162                         host->sg_cpu[i].cfg = dma_cfg;
 163                         host->sg_cpu[i].x_count = sg_dma_len(sg) / 4;
 164                         host->sg_cpu[i].x_modify = 4;
 165                         dev_dbg(mmc_dev(host->mmc), "%d: start_addr:0x%lx, "
 166                                 "cfg:0x%x, x_count:0x%x, x_modify:0x%x\n",
 167                                 i, host->sg_cpu[i].start_addr,
 168                                 host->sg_cpu[i].cfg, host->sg_cpu[i].x_count,
 169                                 host->sg_cpu[i].x_modify);
 170                 }
 171         }
 172         flush_dcache_range((unsigned int)host->sg_cpu,
 173                 (unsigned int)host->sg_cpu +
 174                         host->dma_len * sizeof(struct dma_desc_array));
 175         /* Set the last descriptor to stop mode */
 176         host->sg_cpu[host->dma_len - 1].cfg &= ~(DMAFLOW | NDSIZE);
 177         host->sg_cpu[host->dma_len - 1].cfg |= DI_EN;
 178
 179         set_dma_curr_desc_addr(host->dma_ch, (unsigned long *)host->sg_dma);
 180         set_dma_x_count(host->dma_ch, 0);
 181         set_dma_x_modify(host->dma_ch, 0);
 182         set_dma_config(host->dma_ch, dma_cfg);
 183 #elif defined(CONFIG_BF51x)
 184         /* RSI DMA doesn't work in array mode */
 185         dma_cfg |= WDSIZE_32 | DMAEN;
 186         set_dma_start_addr(host->dma_ch, sg_dma_address(&data->sg[0]));
 187         set_dma_x_count(host->dma_ch, length / 4);
 188         set_dma_x_modify(host->dma_ch, 4);
 189         set_dma_config(host->dma_ch, dma_cfg);
 190 #endif
 191         bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() | DTX_DMA_E | DTX_E);
 192
 193         SSYNC();
 194
 195         dev_dbg(mmc_dev(host->mmc), "%s exit\n", __func__);
 196         return 0;
 197 }
 198
 199 static void sdh_start_cmd(struct sdh_host *host, struct mmc_command *cmd)
 200 {
 201         unsigned int sdh_cmd;
 202         unsigned int stat_mask;
 203
 204         dev_dbg(mmc_dev(host->mmc), "%s enter cmd: 0x%p\n", __func__, cmd);
 205         WARN_ON(host->cmd != NULL);
 206         host->cmd = cmd;
 207
 208         sdh_cmd = 0;
 209         stat_mask = 0;
 210
 211         sdh_cmd |= cmd->opcode;
 212
 213         if (cmd->flags & MMC_RSP_PRESENT) {
 214                 sdh_cmd |= CMD_RSP;
 215                 stat_mask |= CMD_RESP_END;
 216         } else {
 217                 stat_mask |= CMD_SENT;
 218         }
 219
 220         if (cmd->flags & MMC_RSP_136)
 221                 sdh_cmd |= CMD_L_RSP;
 222
 223         stat_mask |= CMD_CRC_FAIL | CMD_TIME_OUT;
 224
 225         sdh_enable_stat_irq(host, stat_mask);
 226
 227         bfin_write_SDH_ARGUMENT(cmd->arg);
 228         bfin_write_SDH_COMMAND(sdh_cmd | CMD_E);
 229         bfin_write_SDH_CLK_CTL(bfin_read_SDH_CLK_CTL() | CLK_E);
 230         SSYNC();
 231 }
 232
 233 static void sdh_finish_request(struct sdh_host *host, struct mmc_request *mrq)
 234 {
 235         dev_dbg(mmc_dev(host->mmc), "%s enter\n", __func__);
 236         host->mrq = NULL;
 237         host->cmd = NULL;
 238         host->data = NULL;
 239         mmc_request_done(host->mmc, mrq);
 240 }
 241
 242 static int sdh_cmd_done(struct sdh_host *host, unsigned int stat)
 243 {
 244         struct mmc_command *cmd = host->cmd;
 245         int ret = 0;
 246
 247         dev_dbg(mmc_dev(host->mmc), "%s enter cmd: %p\n", __func__, cmd);
 248         if (!cmd)
 249                 return 0;
 250
 251         host->cmd = NULL;
 252
 253         if (cmd->flags & MMC_RSP_PRESENT) {
 254                 cmd->resp[0] = bfin_read_SDH_RESPONSE0();
 255                 if (cmd->flags & MMC_RSP_136) {
 256                         cmd->resp[1] = bfin_read_SDH_RESPONSE1();
 257                         cmd->resp[2] = bfin_read_SDH_RESPONSE2();
 258                         cmd->resp[3] = bfin_read_SDH_RESPONSE3();
 259                 }
 260         }
 261         if (stat & CMD_TIME_OUT)
 262                 cmd->error = -ETIMEDOUT;
 263         else if (stat & CMD_CRC_FAIL && cmd->flags & MMC_RSP_CRC)
 264                 cmd->error = -EILSEQ;
 265
 266         sdh_disable_stat_irq(host, (CMD_SENT | CMD_RESP_END | CMD_TIME_OUT | CMD_CRC_FAIL));
 267
 268         if (host->data && !cmd->error) {
 269                 if (host->data->flags & MMC_DATA_WRITE) {
 270                         ret = sdh_setup_data(host, host->data);
 271                         if (ret)
 272                                 return 0;
 273                 }
 274
 275                 sdh_enable_stat_irq(host, DAT_END | RX_OVERRUN | TX_UNDERRUN | DAT_TIME_OUT);
 276         } else
 277                 sdh_finish_request(host, host->mrq);
 278
 279         return 1;
 280 }
 281
 282 static int sdh_data_done(struct sdh_host *host, unsigned int stat)
 283 {
 284         struct mmc_data *data = host->data;
 285
 286         dev_dbg(mmc_dev(host->mmc), "%s enter stat: 0x%x\n", __func__, stat);
 287         if (!data)
 288                 return 0;
 289
 290         disable_dma(host->dma_ch);
 291         dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
 292                      host->dma_dir);
 293
 294         if (stat & DAT_TIME_OUT)
 295                 data->error = -ETIMEDOUT;
 296         else if (stat & DAT_CRC_FAIL)
 297                 data->error = -EILSEQ;
 298         else if (stat & (RX_OVERRUN | TX_UNDERRUN))
 299                 data->error = -EIO;
 300
 301         if (!data->error)
 302                 data->bytes_xfered = data->blocks * data->blksz;
 303         else
 304                 data->bytes_xfered = 0;
 305
 306         sdh_disable_stat_irq(host, DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL | RX_OVERRUN | TX_UNDERRUN);
 307         bfin_write_SDH_STATUS_CLR(DAT_END_STAT | DAT_TIMEOUT_STAT | \
 308                         DAT_CRC_FAIL_STAT | DAT_BLK_END_STAT | RX_OVERRUN | TX_UNDERRUN);
 309         bfin_write_SDH_DATA_CTL(0);
 310         SSYNC();
 311
 312         host->data = NULL;
 313         if (host->mrq->stop) {
 314                 sdh_stop_clock(host);
 315                 sdh_start_cmd(host, host->mrq->stop);
 316         } else {
 317                 sdh_finish_request(host, host->mrq);
 318         }
 319
 320         return 1;
 321 }
 322
 323 static void sdh_request(struct mmc_host *mmc, struct mmc_request *mrq)
 324 {
 325         struct sdh_host *host = mmc_priv(mmc);
 326         int ret = 0;
 327
 328         dev_dbg(mmc_dev(host->mmc), "%s enter, mrp:%p, cmd:%p\n", __func__, mrq, mrq->cmd);
 329         WARN_ON(host->mrq != NULL);
 330
 331         host->mrq = mrq;
 332         host->data = mrq->data;
 333
 334         if (mrq->data && mrq->data->flags & MMC_DATA_READ) {
 335                 ret = sdh_setup_data(host, mrq->data);
 336                 if (ret)
 337                         return;
 338         }
 339
 340         sdh_start_cmd(host, mrq->cmd);
 341 }
 342
 343 static void sdh_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 344 {
 345         struct sdh_host *host;
 346         unsigned long flags;
 347         u16 clk_ctl = 0;
 348         u16 pwr_ctl = 0;
 349         u16 cfg;
 350         host = mmc_priv(mmc);
 351
 352         spin_lock_irqsave(&host->lock, flags);
 353         if (ios->clock) {
 354                 unsigned long  sys_clk, ios_clk;
 355                 unsigned char clk_div;
 356                 ios_clk = 2 * ios->clock;
 357                 sys_clk = get_sclk();
 358                 clk_div = sys_clk / ios_clk;
 359                 if (sys_clk % ios_clk == 0)
 360                         clk_div -= 1;
 361                 clk_div = min_t(unsigned char, clk_div, 0xFF);
 362                 clk_ctl |= clk_div;
 363                 clk_ctl |= CLK_E;
 364                 host->clk_div = clk_div;
 365         } else
 366                 sdh_stop_clock(host);
 367
 368         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 369 #ifdef CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND
 370                 pwr_ctl |= ROD_CTL;
 371 #else
 372                 pwr_ctl |= SD_CMD_OD | ROD_CTL;
 373 #endif
 374
 375         if (ios->bus_width == MMC_BUS_WIDTH_4) {
 376                 cfg = bfin_read_SDH_CFG();
 377                 cfg &= ~PD_SDDAT3;
 378                 cfg |= PUP_SDDAT3;
 379                 /* Enable 4 bit SDIO */
 380                 cfg |= (SD4E | MWE);
 381                 bfin_write_SDH_CFG(cfg);
 382                 clk_ctl |= WIDE_BUS;
 383         } else {
 384                 cfg = bfin_read_SDH_CFG();
 385                 cfg |= MWE;
 386                 bfin_write_SDH_CFG(cfg);
 387         }
 388
 389         bfin_write_SDH_CLK_CTL(clk_ctl);
 390
 391         host->power_mode = ios->power_mode;
 392         if (ios->power_mode == MMC_POWER_ON)
 393                 pwr_ctl |= PWR_ON;
 394
 395         bfin_write_SDH_PWR_CTL(pwr_ctl);
 396         SSYNC();
 397
 398         spin_unlock_irqrestore(&host->lock, flags);
 399
 400         dev_dbg(mmc_dev(host->mmc), "SDH: clk_div = 0x%x actual clock:%ld expected clock:%d\n",
 401                 host->clk_div,
 402                 host->clk_div ? get_sclk() / (2 * (host->clk_div + 1)) : 0,
 403                 ios->clock);
 404 }
 405
 406 static const struct mmc_host_ops sdh_ops = {
 407         .request        = sdh_request,
 408         .set_ios        = sdh_set_ios,
 409 };
 410
 411 static irqreturn_t sdh_dma_irq(int irq, void *devid)
 412 {
 413         struct sdh_host *host = devid;
 414
 415         dev_dbg(mmc_dev(host->mmc), "%s enter, irq_stat: 0x%04x\n", __func__,
 416                 get_dma_curr_irqstat(host->dma_ch));
 417         clear_dma_irqstat(host->dma_ch);
 418         SSYNC();
 419
 420         return IRQ_HANDLED;
 421 }
 422
 423 static irqreturn_t sdh_stat_irq(int irq, void *devid)
 424 {
 425         struct sdh_host *host = devid;
 426         unsigned int status;
 427         int handled = 0;
 428
 429         dev_dbg(mmc_dev(host->mmc), "%s enter\n", __func__);
 430         status = bfin_read_SDH_E_STATUS();
 431         if (status & SD_CARD_DET) {
 432                 mmc_detect_change(host->mmc, 0);
 433                 bfin_write_SDH_E_STATUS(SD_CARD_DET);
 434         }
 435         status = bfin_read_SDH_STATUS();
 436         if (status & (CMD_SENT | CMD_RESP_END | CMD_TIME_OUT | CMD_CRC_FAIL)) {
 437                 handled |= sdh_cmd_done(host, status);
 438                 bfin_write_SDH_STATUS_CLR(CMD_SENT_STAT | CMD_RESP_END_STAT | \
 439                                 CMD_TIMEOUT_STAT | CMD_CRC_FAIL_STAT);
 440                 SSYNC();
 441         }
 442
 443         status = bfin_read_SDH_STATUS();
 444         if (status & (DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL | RX_OVERRUN | TX_UNDERRUN))
 445                 handled |= sdh_data_done(host, status);
 446
 447         dev_dbg(mmc_dev(host->mmc), "%s exit\n\n", __func__);
 448
 449         return IRQ_RETVAL(handled);
 450 }
 451
 452 static int __devinit sdh_probe(struct platform_device *pdev)
 453 {
 454         struct mmc_host *mmc;
 455         struct sdh_host *host;
 456         struct bfin_sd_host *drv_data = get_sdh_data(pdev);
 457         int ret;
 458
 459         if (!drv_data) {
 460                 dev_err(&pdev->dev, "missing platform driver data\n");
 461                 ret = -EINVAL;
 462                 goto out;
 463         }
 464
 465         mmc = mmc_alloc_host(sizeof(struct sdh_host), &pdev->dev);
 466         if (!mmc) {
 467                 ret = -ENOMEM;
 468                 goto out;
 469         }
 470
 471         mmc->ops = &sdh_ops;
 472         mmc->max_segs = 32;
 473         mmc->max_seg_size = 1 << 16;
 474         mmc->max_blk_size = 1 << 11;
 475         mmc->max_blk_count = 1 << 11;
 476         mmc->max_req_size = PAGE_SIZE;
 477         mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
 478         mmc->f_max = get_sclk();
 479         mmc->f_min = mmc->f_max >> 9;
 480         mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_NEEDS_POLL;
 481         host = mmc_priv(mmc);
 482         host->mmc = mmc;
 483
 484         spin_lock_init(&host->lock);
 485         host->irq = drv_data->irq_int0;
 486         host->dma_ch = drv_data->dma_chan;
 487
 488         ret = request_dma(host->dma_ch, DRIVER_NAME "DMA");
 489         if (ret) {
 490                 dev_err(&pdev->dev, "unable to request DMA channel\n");
 491                 goto out1;
 492         }
 493
 494         ret = set_dma_callback(host->dma_ch, sdh_dma_irq, host);
 495         if (ret) {
 496                 dev_err(&pdev->dev, "unable to request DMA irq\n");
 497                 goto out2;
 498         }
 499
 500         host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &host->sg_dma, GFP_KERNEL);
 501         if (host->sg_cpu == NULL) {
 502                 ret = -ENOMEM;
 503                 goto out2;
 504         }
 505
 506         platform_set_drvdata(pdev, mmc);
 507         mmc_add_host(mmc);
 508
 509         ret = request_irq(host->irq, sdh_stat_irq, 0, "SDH Status IRQ", host);
 510         if (ret) {
 511                 dev_err(&pdev->dev, "unable to request status irq\n");
 512                 goto out3;
 513         }
 514
 515         ret = peripheral_request_list(drv_data->pin_req, DRIVER_NAME);
 516         if (ret) {
 517                 dev_err(&pdev->dev, "unable to request peripheral pins\n");
 518                 goto out4;
 519         }
 520 #if defined(CONFIG_BF54x)
 521         /* Secure Digital Host shares DMA with Nand controller */
 522         bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() | 0x1);
 523 #endif
 524
 525         bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN);
 526         SSYNC();
 527
 528         /* Disable card inserting detection pin. set MMC_CAP_NEES_POLL, and
 529          * mmc stack will do the detection.
 530          */
 531         bfin_write_SDH_CFG((bfin_read_SDH_CFG() & 0x1F) | (PUP_SDDAT | PUP_SDDAT3));
 532         SSYNC();
 533
 534         return 0;
 535
 536 out4:
 537         free_irq(host->irq, host);
 538 out3:
 539         mmc_remove_host(mmc);
 540         dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
 541 out2:
 542         free_dma(host->dma_ch);
 543 out1:
 544         mmc_free_host(mmc);
 545  out:
 546         return ret;
 547 }
 548
 549 static int __devexit sdh_remove(struct platform_device *pdev)
 550 {
 551         struct mmc_host *mmc = platform_get_drvdata(pdev);
 552
 553         platform_set_drvdata(pdev, NULL);
 554
 555         if (mmc) {
 556                 struct sdh_host *host = mmc_priv(mmc);
 557
 558                 mmc_remove_host(mmc);
 559
 560                 sdh_stop_clock(host);
 561                 free_irq(host->irq, host);
 562                 free_dma(host->dma_ch);
 563                 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
 564
 565                 mmc_free_host(mmc);
 566         }
 567
 568         return 0;
 569 }
 570
 571 #ifdef CONFIG_PM
 572 static int sdh_suspend(struct platform_device *dev, pm_message_t state)
 573 {
 574         struct mmc_host *mmc = platform_get_drvdata(dev);
 575         struct bfin_sd_host *drv_data = get_sdh_data(dev);
 576         int ret = 0;
 577
 578         if (mmc)
 579                 ret = mmc_suspend_host(mmc);
 580
 581         bfin_write_SDH_PWR_CTL(bfin_read_SDH_PWR_CTL() & ~PWR_ON);
 582         peripheral_free_list(drv_data->pin_req);
 583
 584         return ret;
 585 }
 586
 587 static int sdh_resume(struct platform_device *dev)
 588 {
 589         struct mmc_host *mmc = platform_get_drvdata(dev);
 590         struct bfin_sd_host *drv_data = get_sdh_data(dev);
 591         int ret = 0;
 592
 593         ret = peripheral_request_list(drv_data->pin_req, DRIVER_NAME);
 594         if (ret) {
 595                 dev_err(&dev->dev, "unable to request peripheral pins\n");
 596                 return ret;
 597         }
 598
 599         bfin_write_SDH_PWR_CTL(bfin_read_SDH_PWR_CTL() | PWR_ON);
 600 #if defined(CONFIG_BF54x)
 601         /* Secure Digital Host shares DMA with Nand controller */
 602         bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() | 0x1);
 603 #endif
 604         bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN);
 605         SSYNC();
 606
 607         bfin_write_SDH_CFG((bfin_read_SDH_CFG() & 0x1F) | (PUP_SDDAT | PUP_SDDAT3));
 608         SSYNC();
 609
 610         if (mmc)
 611                 ret = mmc_resume_host(mmc);
 612
 613         return ret;
 614 }
 615 #else
 616 # define sdh_suspend NULL
 617 # define sdh_resume  NULL
 618 #endif
 619
 620 static struct platform_driver sdh_driver = {
 621         .probe   = sdh_probe,
 622         .remove  = __devexit_p(sdh_remove),
 623         .suspend = sdh_suspend,
 624         .resume  = sdh_resume,
 625         .driver  = {
 626                 .name = DRIVER_NAME,
 627         },
 628 };
 629
 630 static int __init sdh_init(void)
 631 {
 632         return platform_driver_register(&sdh_driver);
 633 }
 634 module_init(sdh_init);
 635
 636 static void __exit sdh_exit(void)
 637 {
 638         platform_driver_unregister(&sdh_driver);
 639 }
 640 module_exit(sdh_exit);
 641
 642 MODULE_DESCRIPTION("Blackfin Secure Digital Host Driver");
 643 MODULE_AUTHOR("Cliff Cai, Roy Huang");
 644 MODULE_LICENSE("GPL");