3 * Rob Emanuele <rob@emanuele.us>
4 * Reinhard Meyer, EMK Elektronik <reinhard.meyer@emk-elektronik.de>
7 * Copyright (C) 2004-2006 Atmel Corporation
9 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/errno.h>
18 #include <asm/byteorder.h>
19 #include <asm/arch/clk.h>
20 #include <asm/arch/hardware.h>
21 #include "atmel_mci.h"
23 #ifndef CONFIG_SYS_MMC_CLK_OD
24 # define CONFIG_SYS_MMC_CLK_OD 150000
27 #define MMC_DEFAULT_BLKLEN 512
29 #if defined(CONFIG_ATMEL_MCI_PORTB)
35 static int initialized = 0;
37 /* Read Atmel MCI IP version */
38 static unsigned int atmel_mci_get_version(struct atmel_mci *mci)
40 return readl(&mci->version) & 0x00000fff;
44 * Print command and status:
46 * - always when DEBUG is defined
49 static void dump_cmd(u32 cmdr, u32 arg, u32 status, const char* msg)
51 debug("gen_atmel_mci: CMDR %08x (%2u) ARGR %08x (SR: %08x) %s\n",
52 cmdr, cmdr & 0x3F, arg, status, msg);
55 /* Setup for MCI Clock and Block Size */
56 static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen)
58 atmel_mci_t *mci = mmc->priv;
59 u32 bus_hz = get_mci_clk_rate();
61 unsigned int version = atmel_mci_get_version(mci);
65 debug("mci: bus_hz is %u, setting clock %u Hz, block size %u\n",
68 if (version >= 0x500) {
69 clkdiv = DIV_ROUND_UP(bus_hz, hz) - 2;
76 debug("mci: setting clock %u Hz, block size %u\n",
77 bus_hz / (clkdiv * 2 + clkodd + 2), blklen);
79 /* find clkdiv yielding a rate <= than requested */
80 for (clkdiv = 0; clkdiv < 255; clkdiv++) {
81 if ((bus_hz / (clkdiv + 1) / 2) <= hz)
84 debug("mci: setting clock %u Hz, block size %u\n",
85 (bus_hz / (clkdiv + 1)) / 2, blklen);
92 mr = MMCI_BF(CLKDIV, clkdiv);
94 /* MCI IP version >= 0x200 has R/WPROOF */
96 mr |= MMCI_BIT(RDPROOF) | MMCI_BIT(WRPROOF);
99 * MCI IP version >= 0x500 use bit 16 as clkodd.
100 * MCI IP version < 0x500 use upper 16 bits for blklen.
102 if (version >= 0x500)
103 mr |= MMCI_BF(CLKODD, clkodd);
105 mr |= MMCI_BF(BLKLEN, blklen);
107 writel(mr, &mci->mr);
109 /* MCI IP version >= 0x200 has blkr */
110 if (version >= 0x200)
111 writel(MMCI_BF(BLKLEN, blklen), &mci->blkr);
113 if (mmc->card_caps & mmc->cfg->host_caps & MMC_MODE_HS)
114 writel(MMCI_BIT(HSMODE), &mci->cfg);
121 /* Return the CMDR with flags for a given command and data packet */
122 static u32 mci_encode_cmd(
123 struct mmc_cmd *cmd, struct mmc_data *data, u32* error_flags)
127 /* Default Flags for Errors */
128 *error_flags |= (MMCI_BIT(DTOE) | MMCI_BIT(RDIRE) | MMCI_BIT(RENDE) |
129 MMCI_BIT(RINDE) | MMCI_BIT(RTOE));
131 /* Default Flags for the Command */
132 cmdr |= MMCI_BIT(MAXLAT);
135 cmdr |= MMCI_BF(TRCMD, 1);
136 if (data->blocks > 1)
137 cmdr |= MMCI_BF(TRTYP, 1);
138 if (data->flags & MMC_DATA_READ)
139 cmdr |= MMCI_BIT(TRDIR);
142 if (cmd->resp_type & MMC_RSP_CRC)
143 *error_flags |= MMCI_BIT(RCRCE);
144 if (cmd->resp_type & MMC_RSP_136)
145 cmdr |= MMCI_BF(RSPTYP, 2);
146 else if (cmd->resp_type & MMC_RSP_BUSY)
147 cmdr |= MMCI_BF(RSPTYP, 3);
148 else if (cmd->resp_type & MMC_RSP_PRESENT)
149 cmdr |= MMCI_BF(RSPTYP, 1);
151 return cmdr | MMCI_BF(CMDNB, cmd->cmdidx);
154 /* Entered into function pointer in mci_send_cmd */
155 static u32 mci_data_read(atmel_mci_t *mci, u32* data, u32 error_flags)
160 status = readl(&mci->sr);
161 if (status & (error_flags | MMCI_BIT(OVRE)))
163 } while (!(status & MMCI_BIT(RXRDY)));
165 if (status & MMCI_BIT(RXRDY)) {
166 *data = readl(&mci->rdr);
173 /* Entered into function pointer in mci_send_cmd */
174 static u32 mci_data_write(atmel_mci_t *mci, u32* data, u32 error_flags)
179 status = readl(&mci->sr);
180 if (status & (error_flags | MMCI_BIT(UNRE)))
182 } while (!(status & MMCI_BIT(TXRDY)));
184 if (status & MMCI_BIT(TXRDY)) {
185 writel(*data, &mci->tdr);
193 * Entered into mmc structure during driver init
195 * Sends a command out on the bus and deals with the block data.
196 * Takes the mmc pointer, a command pointer, and an optional data pointer.
199 mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
201 atmel_mci_t *mci = mmc->priv;
207 puts ("MCI not initialized!\n");
211 /* Figure out the transfer arguments */
212 cmdr = mci_encode_cmd(cmd, data, &error_flags);
214 /* For multi blocks read/write, set the block register */
215 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK)
216 || (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK))
217 writel(data->blocks | MMCI_BF(BLKLEN, mmc->read_bl_len),
220 /* Send the command */
221 writel(cmd->cmdarg, &mci->argr);
222 writel(cmdr, &mci->cmdr);
225 dump_cmd(cmdr, cmd->cmdarg, 0, "DEBUG");
228 /* Wait for the command to complete */
229 while (!((status = readl(&mci->sr)) & MMCI_BIT(CMDRDY)));
231 if ((status & error_flags) & MMCI_BIT(RTOE)) {
232 dump_cmd(cmdr, cmd->cmdarg, status, "Command Time Out");
234 } else if (status & error_flags) {
235 dump_cmd(cmdr, cmd->cmdarg, status, "Command Failed");
239 /* Copy the response to the response buffer */
240 if (cmd->resp_type & MMC_RSP_136) {
241 cmd->response[0] = readl(&mci->rspr);
242 cmd->response[1] = readl(&mci->rspr1);
243 cmd->response[2] = readl(&mci->rspr2);
244 cmd->response[3] = readl(&mci->rspr3);
246 cmd->response[0] = readl(&mci->rspr);
248 /* transfer all of the blocks */
250 u32 word_count, block_count;
252 u32 sys_blocksize, dummy, i;
254 (atmel_mci_t *mci, u32* data, u32 error_flags);
256 if (data->flags & MMC_DATA_READ) {
257 mci_data_op = mci_data_read;
258 sys_blocksize = mmc->read_bl_len;
259 ioptr = (u32*)data->dest;
261 mci_data_op = mci_data_write;
262 sys_blocksize = mmc->write_bl_len;
263 ioptr = (u32*)data->src;
267 for (block_count = 0;
268 block_count < data->blocks && !status;
272 status = mci_data_op(mci, ioptr, error_flags);
275 } while (!status && word_count < (data->blocksize/4));
277 if (data->flags & MMC_DATA_READ)
279 u32 cnt = word_count * 4;
280 printf("Read Data:\n");
281 print_buffer(0, data->dest + cnt * block_count,
286 if (!status && word_count < (sys_blocksize / 4))
287 printf("filling rest of block...\n");
289 /* fill the rest of a full block */
290 while (!status && word_count < (sys_blocksize / 4)) {
291 status = mci_data_op(mci, &dummy,
296 dump_cmd(cmdr, cmd->cmdarg, status,
297 "Data Transfer Failed");
302 /* Wait for Transfer End */
305 status = readl(&mci->sr);
307 if (status & error_flags) {
308 dump_cmd(cmdr, cmd->cmdarg, status,
313 } while ((status & MMCI_BIT(DTIP)) && i < 10000);
314 if (status & MMCI_BIT(DTIP)) {
315 dump_cmd(cmdr, cmd->cmdarg, status,
316 "XFER DTIP never unset, ignoring");
323 /* Entered into mmc structure during driver init */
324 static void mci_set_ios(struct mmc *mmc)
326 atmel_mci_t *mci = mmc->priv;
327 int bus_width = mmc->bus_width;
328 unsigned int version = atmel_mci_get_version(mci);
331 /* Set the clock speed */
332 mci_set_mode(mmc, mmc->clock, MMC_DEFAULT_BLKLEN);
335 * set the bus width and select slot for this interface
336 * there is no capability for multiple slots on the same interface yet
338 if ((version & 0xf00) >= 0x300) {
351 writel(busw << 6 | MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr);
353 busw = (bus_width == 4) ? 1 : 0;
355 writel(busw << 7 | MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr);
359 /* Entered into mmc structure during driver init */
360 static int mci_init(struct mmc *mmc)
362 atmel_mci_t *mci = mmc->priv;
364 /* Initialize controller */
365 writel(MMCI_BIT(SWRST), &mci->cr); /* soft reset */
366 writel(MMCI_BIT(PWSDIS), &mci->cr); /* disable power save */
367 writel(MMCI_BIT(MCIEN), &mci->cr); /* enable mci */
368 writel(MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr); /* select port */
370 /* This delay can be optimized, but stick with max value */
371 writel(0x7f, &mci->dtor);
372 /* Disable Interrupts */
373 writel(~0UL, &mci->idr);
375 /* Set default clocks and blocklen */
376 mci_set_mode(mmc, CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN);
381 static const struct mmc_ops atmel_mci_ops = {
382 .send_cmd = mci_send_cmd,
383 .set_ios = mci_set_ios,
388 * This is the only exported function
390 * Call it with the MCI register base address
392 int atmel_mci_init(void *regs)
395 struct mmc_config *cfg;
396 struct atmel_mci *mci;
397 unsigned int version;
399 cfg = malloc(sizeof(*cfg));
402 memset(cfg, 0, sizeof(*cfg));
404 mci = (struct atmel_mci *)regs;
407 cfg->ops = &atmel_mci_ops;
409 /* need to be able to pass these in on a board by board basis */
410 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
411 version = atmel_mci_get_version(mci);
412 if ((version & 0xf00) >= 0x300) {
413 cfg->host_caps = MMC_MODE_8BIT;
414 cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
417 cfg->host_caps |= MMC_MODE_4BIT;
420 * min and max frequencies determined by
421 * max and min of clock divider
423 cfg->f_min = get_mci_clk_rate() / (2*256);
424 cfg->f_max = get_mci_clk_rate() / (2*1);
426 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
428 mmc = mmc_create(cfg, regs);
434 /* NOTE: possibly leaking the cfg structure */