3 * Rob Emanuele <rob@emanuele.us>
4 * Reinhard Meyer, EMK Elektronik <reinhard.meyer@emk-elektronik.de>
7 * Copyright (C) 2004-2006 Atmel Corporation
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/errno.h>
34 #include <asm/byteorder.h>
35 #include <asm/arch/clk.h>
36 #include <asm/arch/hardware.h>
37 #include "atmel_mci.h"
39 #ifndef CONFIG_SYS_MMC_CLK_OD
40 # define CONFIG_SYS_MMC_CLK_OD 150000
43 #define MMC_DEFAULT_BLKLEN 512
45 #if defined(CONFIG_ATMEL_MCI_PORTB)
51 static int initialized = 0;
53 /* Read Atmel MCI IP version */
54 static unsigned int atmel_mci_get_version(struct atmel_mci *mci)
56 return readl(&mci->version) & 0x00000fff;
60 * Print command and status:
62 * - always when DEBUG is defined
65 static void dump_cmd(u32 cmdr, u32 arg, u32 status, const char* msg)
67 printf("gen_atmel_mci: CMDR %08x (%2u) ARGR %08x (SR: %08x) %s\n",
68 cmdr, cmdr&0x3F, arg, status, msg);
71 /* Setup for MCI Clock and Block Size */
72 static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen)
74 atmel_mci_t *mci = (atmel_mci_t *)mmc->priv;
75 u32 bus_hz = get_mci_clk_rate();
78 debug("mci: bus_hz is %u, setting clock %u Hz, block size %u\n",
81 /* find lowest clkdiv yielding a rate <= than requested */
82 for (clkdiv=0; clkdiv<255; clkdiv++) {
83 if ((bus_hz / (clkdiv+1) / 2) <= hz)
87 printf("mci: setting clock %u Hz, block size %u\n",
88 (bus_hz / (clkdiv+1)) / 2, blklen);
91 /* On some platforms RDPROOF and WRPROOF are ignored */
92 writel((MMCI_BF(CLKDIV, clkdiv)
93 | MMCI_BF(BLKLEN, blklen)
95 | MMCI_BIT(WRPROOF)), &mci->mr);
97 * On some new platforms BLKLEN in mci->mr is ignored.
98 * Should use the BLKLEN in the block register.
100 writel(MMCI_BF(BLKLEN, blklen), &mci->blkr);
104 /* Return the CMDR with flags for a given command and data packet */
105 static u32 mci_encode_cmd(
106 struct mmc_cmd *cmd, struct mmc_data *data, u32* error_flags)
110 /* Default Flags for Errors */
111 *error_flags |= (MMCI_BIT(DTOE) | MMCI_BIT(RDIRE) | MMCI_BIT(RENDE) |
112 MMCI_BIT(RINDE) | MMCI_BIT(RTOE));
114 /* Default Flags for the Command */
115 cmdr |= MMCI_BIT(MAXLAT);
118 cmdr |= MMCI_BF(TRCMD, 1);
119 if (data->blocks > 1)
120 cmdr |= MMCI_BF(TRTYP, 1);
121 if (data->flags & MMC_DATA_READ)
122 cmdr |= MMCI_BIT(TRDIR);
125 if (cmd->resp_type & MMC_RSP_CRC)
126 *error_flags |= MMCI_BIT(RCRCE);
127 if (cmd->resp_type & MMC_RSP_136)
128 cmdr |= MMCI_BF(RSPTYP, 2);
129 else if (cmd->resp_type & MMC_RSP_BUSY)
130 cmdr |= MMCI_BF(RSPTYP, 3);
131 else if (cmd->resp_type & MMC_RSP_PRESENT)
132 cmdr |= MMCI_BF(RSPTYP, 1);
134 return cmdr | MMCI_BF(CMDNB, cmd->cmdidx);
137 /* Entered into function pointer in mci_send_cmd */
138 static u32 mci_data_read(atmel_mci_t *mci, u32* data, u32 error_flags)
143 status = readl(&mci->sr);
144 if (status & (error_flags | MMCI_BIT(OVRE)))
146 } while (!(status & MMCI_BIT(RXRDY)));
148 if (status & MMCI_BIT(RXRDY)) {
149 *data = readl(&mci->rdr);
156 /* Entered into function pointer in mci_send_cmd */
157 static u32 mci_data_write(atmel_mci_t *mci, u32* data, u32 error_flags)
162 status = readl(&mci->sr);
163 if (status & (error_flags | MMCI_BIT(UNRE)))
165 } while (!(status & MMCI_BIT(TXRDY)));
167 if (status & MMCI_BIT(TXRDY)) {
168 writel(*data, &mci->tdr);
176 * Entered into mmc structure during driver init
178 * Sends a command out on the bus and deals with the block data.
179 * Takes the mmc pointer, a command pointer, and an optional data pointer.
182 mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
184 atmel_mci_t *mci = (atmel_mci_t *)mmc->priv;
190 puts ("MCI not initialized!\n");
194 /* Figure out the transfer arguments */
195 cmdr = mci_encode_cmd(cmd, data, &error_flags);
197 /* For multi blocks read/write, set the block register */
198 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK)
199 || (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK))
200 writel(data->blocks | MMCI_BF(BLKLEN, mmc->read_bl_len),
203 /* Send the command */
204 writel(cmd->cmdarg, &mci->argr);
205 writel(cmdr, &mci->cmdr);
208 dump_cmd(cmdr, cmd->cmdarg, 0, "DEBUG");
211 /* Wait for the command to complete */
212 while (!((status = readl(&mci->sr)) & MMCI_BIT(CMDRDY)));
214 if (status & error_flags) {
215 dump_cmd(cmdr, cmd->cmdarg, status, "Command Failed");
219 /* Copy the response to the response buffer */
220 if (cmd->resp_type & MMC_RSP_136) {
221 cmd->response[0] = readl(&mci->rspr);
222 cmd->response[1] = readl(&mci->rspr1);
223 cmd->response[2] = readl(&mci->rspr2);
224 cmd->response[3] = readl(&mci->rspr3);
226 cmd->response[0] = readl(&mci->rspr);
228 /* transfer all of the blocks */
230 u32 word_count, block_count;
232 u32 sys_blocksize, dummy, i;
234 (atmel_mci_t *mci, u32* data, u32 error_flags);
236 if (data->flags & MMC_DATA_READ) {
237 mci_data_op = mci_data_read;
238 sys_blocksize = mmc->read_bl_len;
239 ioptr = (u32*)data->dest;
241 mci_data_op = mci_data_write;
242 sys_blocksize = mmc->write_bl_len;
243 ioptr = (u32*)data->src;
247 for (block_count = 0;
248 block_count < data->blocks && !status;
252 status = mci_data_op(mci, ioptr, error_flags);
255 } while (!status && word_count < (data->blocksize/4));
257 if (data->flags & MMC_DATA_READ)
259 printf("Read Data:\n");
260 print_buffer(0, data->dest, 1,
265 if (!status && word_count < (sys_blocksize / 4))
266 printf("filling rest of block...\n");
268 /* fill the rest of a full block */
269 while (!status && word_count < (sys_blocksize / 4)) {
270 status = mci_data_op(mci, &dummy,
275 dump_cmd(cmdr, cmd->cmdarg, status,
276 "Data Transfer Failed");
281 /* Wait for Transfer End */
284 status = readl(&mci->sr);
286 if (status & error_flags) {
287 dump_cmd(cmdr, cmd->cmdarg, status,
292 } while ((status & MMCI_BIT(DTIP)) && i < 10000);
293 if (status & MMCI_BIT(DTIP)) {
294 dump_cmd(cmdr, cmd->cmdarg, status,
295 "XFER DTIP never unset, ignoring");
302 /* Entered into mmc structure during driver init */
303 static void mci_set_ios(struct mmc *mmc)
305 atmel_mci_t *mci = (atmel_mci_t *)mmc->priv;
306 int bus_width = mmc->bus_width;
307 unsigned int version = atmel_mci_get_version(mci);
310 /* Set the clock speed */
311 mci_set_mode(mmc, mmc->clock, MMC_DEFAULT_BLKLEN);
314 * set the bus width and select slot for this interface
315 * there is no capability for multiple slots on the same interface yet
317 if ((version & 0xf00) >= 0x300) {
330 writel(busw << 6 | MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr);
332 busw = (bus_width == 4) ? 1 : 0;
334 writel(busw << 7 | MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr);
338 /* Entered into mmc structure during driver init */
339 static int mci_init(struct mmc *mmc)
341 atmel_mci_t *mci = (atmel_mci_t *)mmc->priv;
343 /* Initialize controller */
344 writel(MMCI_BIT(SWRST), &mci->cr); /* soft reset */
345 writel(MMCI_BIT(PWSDIS), &mci->cr); /* disable power save */
346 writel(MMCI_BIT(MCIEN), &mci->cr); /* enable mci */
347 writel(MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr); /* select port */
349 /* This delay can be optimized, but stick with max value */
350 writel(0x7f, &mci->dtor);
351 /* Disable Interrupts */
352 writel(~0UL, &mci->idr);
354 /* Set default clocks and blocklen */
355 mci_set_mode(mmc, CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN);
361 * This is the only exported function
363 * Call it with the MCI register base address
365 int atmel_mci_init(void *regs)
367 struct mmc *mmc = malloc(sizeof(struct mmc));
368 struct atmel_mci *mci;
369 unsigned int version;
374 strcpy(mmc->name, "mci");
376 mmc->send_cmd = mci_send_cmd;
377 mmc->set_ios = mci_set_ios;
378 mmc->init = mci_init;
382 /* need to be able to pass these in on a board by board basis */
383 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
384 mci = (struct atmel_mci *)mmc->priv;
385 version = atmel_mci_get_version(mci);
386 if ((version & 0xf00) >= 0x300)
387 mmc->host_caps = MMC_MODE_8BIT;
389 mmc->host_caps |= MMC_MODE_4BIT;
392 * min and max frequencies determined by
393 * max and min of clock divider
395 mmc->f_min = get_mci_clk_rate() / (2*256);
396 mmc->f_max = get_mci_clk_rate() / (2*1);