1 // SPDX-License-Identifier: GPL-2.0+
3 * Faraday MMC/SD Host Controller
5 * (C) Copyright 2010 Faraday Technology
6 * Dante Su <dantesu@faraday-tech.com>
8 * Copyright 2018 Andes Technology, Inc.
9 * Author: Rick Chen (rick@andestech.com)
18 #include <linux/bitops.h>
20 #include <linux/errno.h>
21 #include <asm/byteorder.h>
22 #include <faraday/ftsdc010.h>
23 #include "ftsdc010_mci.h"
25 #include <dt-structs.h>
30 #include <linux/err.h>
32 DECLARE_GLOBAL_DATA_PTR;
34 #define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 4) /* 250 ms */
35 #define CFG_RST_TIMEOUT CONFIG_SYS_HZ /* 1 sec reset timeout */
37 #if CONFIG_IS_ENABLED(OF_PLATDATA)
40 bool cap_mmc_highspeed;
41 bool cap_sd_highspeed;
42 fdt32_t clock_freq_min_max[2];
43 struct phandle_2_cell clocks[4];
49 struct ftsdc010_plat {
50 #if CONFIG_IS_ENABLED(OF_PLATDATA)
51 struct ftsdc010 dtplat;
53 struct mmc_config cfg;
59 struct ftsdc010_chip chip;
65 static inline int ftsdc010_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd)
67 struct ftsdc010_chip *chip = mmc->priv;
68 struct ftsdc010_mmc __iomem *regs = chip->regs;
71 uint32_t cmd = FTSDC010_CMD_IDX(mmc_cmd->cmdidx);
72 uint32_t arg = mmc_cmd->cmdarg;
73 uint32_t flags = mmc_cmd->resp_type;
75 cmd |= FTSDC010_CMD_CMD_EN;
78 cmd |= FTSDC010_CMD_APP_CMD;
82 if (flags & MMC_RSP_PRESENT)
83 cmd |= FTSDC010_CMD_NEED_RSP;
85 if (flags & MMC_RSP_136)
86 cmd |= FTSDC010_CMD_LONG_RSP;
88 writel(FTSDC010_STATUS_RSP_MASK | FTSDC010_STATUS_CMD_SEND,
90 writel(arg, ®s->argu);
91 writel(cmd, ®s->cmd);
93 if (!(flags & (MMC_RSP_PRESENT | MMC_RSP_136))) {
94 for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
95 if (readl(®s->status) & FTSDC010_STATUS_CMD_SEND) {
96 writel(FTSDC010_STATUS_CMD_SEND, ®s->clr);
103 for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
104 st = readl(®s->status);
105 writel(st & FTSDC010_STATUS_RSP_MASK, ®s->clr);
106 if (st & FTSDC010_STATUS_RSP_MASK)
109 if (st & FTSDC010_STATUS_RSP_CRC_OK) {
110 if (flags & MMC_RSP_136) {
111 mmc_cmd->response[0] = readl(®s->rsp3);
112 mmc_cmd->response[1] = readl(®s->rsp2);
113 mmc_cmd->response[2] = readl(®s->rsp1);
114 mmc_cmd->response[3] = readl(®s->rsp0);
116 mmc_cmd->response[0] = readl(®s->rsp0);
120 debug("ftsdc010: rsp err (cmd=%d, st=0x%x)\n",
121 mmc_cmd->cmdidx, st);
126 debug("ftsdc010: cmd timeout (op code=%d)\n",
128 } else if (mmc_cmd->cmdidx == MMC_CMD_APP_CMD) {
135 static void ftsdc010_clkset(struct mmc *mmc, uint32_t rate)
137 struct ftsdc010_chip *chip = mmc->priv;
138 struct ftsdc010_mmc __iomem *regs = chip->regs;
141 for (div = 0; div < 0x7f; ++div) {
142 if (rate >= chip->sclk / (2 * (div + 1)))
145 chip->rate = chip->sclk / (2 * (div + 1));
147 writel(FTSDC010_CCR_CLK_DIV(div), ®s->ccr);
150 setbits_le32(®s->ccr, FTSDC010_CCR_CLK_SD);
152 if (chip->rate > 25000000)
153 setbits_le32(®s->ccr, FTSDC010_CCR_CLK_HISPD);
155 clrbits_le32(®s->ccr, FTSDC010_CCR_CLK_HISPD);
159 static int ftsdc010_wait(struct ftsdc010_mmc __iomem *regs, uint32_t mask)
161 int ret = -ETIMEDOUT;
162 uint32_t st, timeout = 10000000;
164 st = readl(®s->status);
167 writel(st & mask, ®s->clr);
173 debug("ftsdc010: wait st(0x%x) timeout\n", mask);
182 static int ftsdc010_request(struct udevice *dev, struct mmc_cmd *cmd,
183 struct mmc_data *data)
185 struct mmc *mmc = mmc_get_mmc_dev(dev);
186 int ret = -EOPNOTSUPP;
188 struct ftsdc010_chip *chip = mmc->priv;
189 struct ftsdc010_mmc __iomem *regs = chip->regs;
191 if (data && (data->flags & MMC_DATA_WRITE) && chip->wprot) {
192 printf("ftsdc010: the card is write protected!\n");
199 len = data->blocksize * data->blocks;
201 /* 1. data disable + fifo reset */
203 #ifdef CONFIG_FTSDC010_SDIO
204 dcr |= FTSDC010_DCR_FIFO_RST;
206 writel(dcr, ®s->dcr);
208 /* 2. clear status register */
209 writel(FTSDC010_STATUS_DATA_MASK | FTSDC010_STATUS_FIFO_URUN
210 | FTSDC010_STATUS_FIFO_ORUN, ®s->clr);
212 /* 3. data timeout (1 sec) */
213 writel(chip->rate, ®s->dtr);
215 /* 4. data length (bytes) */
216 writel(len, ®s->dlr);
219 dcr = (ffs(data->blocksize) - 1) | FTSDC010_DCR_DATA_EN;
220 if (data->flags & MMC_DATA_WRITE)
221 dcr |= FTSDC010_DCR_DATA_WRITE;
222 writel(dcr, ®s->dcr);
225 ret = ftsdc010_send_cmd(mmc, cmd);
227 printf("ftsdc010: CMD%d failed\n", cmd->cmdidx);
234 if (data->flags & MMC_DATA_WRITE) {
235 const uint8_t *buf = (const uint8_t *)data->src;
240 /* wait for tx ready */
241 ret = ftsdc010_wait(regs, FTSDC010_STATUS_FIFO_URUN);
245 /* write bytes to ftsdc010 */
246 for (wlen = 0; wlen < len && wlen < chip->fifo; ) {
247 writel(*(uint32_t *)buf, ®s->dwr);
256 uint8_t *buf = (uint8_t *)data->dest;
261 /* wait for rx ready */
262 ret = ftsdc010_wait(regs, FTSDC010_STATUS_FIFO_ORUN);
266 /* fetch bytes from ftsdc010 */
267 for (rlen = 0; rlen < len && rlen < chip->fifo; ) {
268 *(uint32_t *)buf = readl(®s->dwr);
279 ret = ftsdc010_wait(regs,
280 FTSDC010_STATUS_DATA_END | FTSDC010_STATUS_DATA_CRC_OK);
286 static int ftsdc010_set_ios(struct udevice *dev)
288 struct mmc *mmc = mmc_get_mmc_dev(dev);
289 struct ftsdc010_chip *chip = mmc->priv;
290 struct ftsdc010_mmc __iomem *regs = chip->regs;
292 ftsdc010_clkset(mmc, mmc->clock);
294 clrbits_le32(®s->bwr, FTSDC010_BWR_MODE_MASK);
295 switch (mmc->bus_width) {
297 setbits_le32(®s->bwr, FTSDC010_BWR_MODE_4BIT);
300 setbits_le32(®s->bwr, FTSDC010_BWR_MODE_8BIT);
303 setbits_le32(®s->bwr, FTSDC010_BWR_MODE_1BIT);
310 static int ftsdc010_get_cd(struct udevice *dev)
312 struct mmc *mmc = mmc_get_mmc_dev(dev);
313 struct ftsdc010_chip *chip = mmc->priv;
314 struct ftsdc010_mmc __iomem *regs = chip->regs;
315 return !(readl(®s->status) & FTSDC010_STATUS_CARD_DETECT);
318 static int ftsdc010_get_wp(struct udevice *dev)
320 struct mmc *mmc = mmc_get_mmc_dev(dev);
321 struct ftsdc010_chip *chip = mmc->priv;
322 struct ftsdc010_mmc __iomem *regs = chip->regs;
323 if (readl(®s->status) & FTSDC010_STATUS_WRITE_PROT) {
324 printf("ftsdc010: write protected\n");
331 static int ftsdc010_init(struct mmc *mmc)
333 struct ftsdc010_chip *chip = mmc->priv;
334 struct ftsdc010_mmc __iomem *regs = chip->regs;
337 chip->fifo = (readl(®s->feature) & 0xff) << 2;
340 writel(FTSDC010_CMD_SDC_RST, ®s->cmd);
341 for (ts = get_timer(0); get_timer(ts) < CFG_RST_TIMEOUT; ) {
342 if (readl(®s->cmd) & FTSDC010_CMD_SDC_RST)
346 if (readl(®s->cmd) & FTSDC010_CMD_SDC_RST) {
347 printf("ftsdc010: reset failed\n");
351 /* 2. enter low speed mode (400k card detection) */
352 ftsdc010_clkset(mmc, 400000);
354 /* 3. interrupt disabled */
355 writel(0, ®s->int_mask);
360 static int ftsdc010_probe(struct udevice *dev)
362 struct mmc *mmc = mmc_get_mmc_dev(dev);
363 return ftsdc010_init(mmc);
366 const struct dm_mmc_ops dm_ftsdc010_mmc_ops = {
367 .send_cmd = ftsdc010_request,
368 .set_ios = ftsdc010_set_ios,
369 .get_cd = ftsdc010_get_cd,
370 .get_wp = ftsdc010_get_wp,
373 static void ftsdc_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
374 uint caps, u32 max_clk, u32 min_clk)
377 cfg->f_min = min_clk;
378 cfg->f_max = max_clk;
379 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
380 cfg->host_caps = caps;
382 cfg->host_caps |= MMC_MODE_8BIT;
383 cfg->host_caps &= ~MMC_MODE_4BIT;
385 cfg->host_caps |= MMC_MODE_4BIT;
386 cfg->host_caps &= ~MMC_MODE_8BIT;
388 cfg->part_type = PART_TYPE_DOS;
389 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
392 static int ftsdc010_mmc_ofdata_to_platdata(struct udevice *dev)
394 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
395 struct ftsdc_priv *priv = dev_get_priv(dev);
396 struct ftsdc010_chip *chip = &priv->chip;
397 chip->name = dev->name;
398 chip->ioaddr = dev_read_addr_ptr(dev);
399 chip->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
402 priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
404 priv->fifo_mode = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
406 if (fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
407 "clock-freq-min-max", priv->minmax, 2)) {
408 int val = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
409 "max-frequency", -EINVAL);
413 priv->minmax[0] = 400000; /* 400 kHz */
414 priv->minmax[1] = val;
416 debug("%s: 'clock-freq-min-max' property was deprecated.\n",
420 chip->sclk = priv->minmax[1];
421 chip->regs = chip->ioaddr;
425 static int ftsdc010_mmc_probe(struct udevice *dev)
427 struct ftsdc010_plat *plat = dev_get_platdata(dev);
428 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
429 struct ftsdc_priv *priv = dev_get_priv(dev);
430 struct ftsdc010_chip *chip = &priv->chip;
431 struct udevice *pwr_dev __maybe_unused;
433 #if CONFIG_IS_ENABLED(OF_PLATDATA)
435 struct ftsdc010 *dtplat = &plat->dtplat;
436 chip->name = dev->name;
437 chip->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
438 chip->buswidth = dtplat->bus_width;
441 memcpy(priv->minmax, dtplat->clock_freq_min_max, sizeof(priv->minmax));
442 ret = clk_get_by_driver_info(dev, dtplat->clocks, &priv->clk);
447 if (dev_read_bool(dev, "cap-mmc-highspeed") || \
448 dev_read_bool(dev, "cap-sd-highspeed"))
449 chip->caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
451 ftsdc_setup_cfg(&plat->cfg, dev->name, chip->buswidth, chip->caps,
452 priv->minmax[1] , priv->minmax[0]);
453 chip->mmc = &plat->mmc;
454 chip->mmc->priv = &priv->chip;
455 chip->mmc->dev = dev;
456 upriv->mmc = chip->mmc;
457 return ftsdc010_probe(dev);
460 int ftsdc010_mmc_bind(struct udevice *dev)
462 struct ftsdc010_plat *plat = dev_get_platdata(dev);
464 return mmc_bind(dev, &plat->mmc, &plat->cfg);
467 static const struct udevice_id ftsdc010_mmc_ids[] = {
468 { .compatible = "andestech,atfsdc010" },
472 U_BOOT_DRIVER(ftsdc010_mmc) = {
473 .name = "ftsdc010_mmc",
475 .of_match = ftsdc010_mmc_ids,
476 .ofdata_to_platdata = ftsdc010_mmc_ofdata_to_platdata,
477 .ops = &dm_ftsdc010_mmc_ops,
478 .bind = ftsdc010_mmc_bind,
479 .probe = ftsdc010_mmc_probe,
480 .priv_auto_alloc_size = sizeof(struct ftsdc_priv),
481 .platdata_auto_alloc_size = sizeof(struct ftsdc010_plat),