drivers/mmc/ftsdc010_mci.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Faraday MMC/SD Host Controller
   4  *
   5  * (C) Copyright 2010 Faraday Technology
   6  * Dante Su <dantesu@faraday-tech.com>
   7  *
   8  * Copyright 2018 Andes Technology, Inc.
   9  * Author: Rick Chen (rick@andestech.com)
  10  */
  11
  12 #include <common.h>
  13 #include <clk.h>
  14 #include <log.h>
  15 #include <malloc.h>
  16 #include <part.h>
  17 #include <mmc.h>
  18 #include <linux/bitops.h>
  19 #include <linux/io.h>
  20 #include <linux/errno.h>
  21 #include <asm/byteorder.h>
  22 #include <faraday/ftsdc010.h>
  23 #include "ftsdc010_mci.h"
  24 #include <dm.h>
  25 #include <dt-structs.h>
  26 #include <errno.h>
  27 #include <mapmem.h>
  28 #include <pwrseq.h>
  29 #include <syscon.h>
  30 #include <linux/err.h>
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 #define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 4) /* 250 ms */
  35 #define CFG_RST_TIMEOUT CONFIG_SYS_HZ /* 1 sec reset timeout */
  36
  37 #if CONFIG_IS_ENABLED(OF_PLATDATA)
  38 struct ftsdc010 {
  39         fdt32_t         bus_width;
  40         bool            cap_mmc_highspeed;
  41         bool            cap_sd_highspeed;
  42         fdt32_t         clock_freq_min_max[2];
  43         struct phandle_2_cell   clocks[4];
  44         fdt32_t         fifo_depth;
  45         fdt32_t         reg[2];
  46 };
  47 #endif
  48
  49 struct ftsdc010_plat {
  50 #if CONFIG_IS_ENABLED(OF_PLATDATA)
  51         struct ftsdc010 dtplat;
  52 #endif
  53         struct mmc_config cfg;
  54         struct mmc mmc;
  55 };
  56
  57 struct ftsdc_priv {
  58         struct clk clk;
  59         struct ftsdc010_chip chip;
  60         int fifo_depth;
  61         bool fifo_mode;
  62         u32 minmax[2];
  63 };
  64
  65 static inline int ftsdc010_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd)
  66 {
  67         struct ftsdc010_chip *chip = mmc->priv;
  68         struct ftsdc010_mmc __iomem *regs = chip->regs;
  69         int ret = -ETIMEDOUT;
  70         uint32_t ts, st;
  71         uint32_t cmd   = FTSDC010_CMD_IDX(mmc_cmd->cmdidx);
  72         uint32_t arg   = mmc_cmd->cmdarg;
  73         uint32_t flags = mmc_cmd->resp_type;
  74
  75         cmd |= FTSDC010_CMD_CMD_EN;
  76
  77         if (chip->acmd) {
  78                 cmd |= FTSDC010_CMD_APP_CMD;
  79                 chip->acmd = 0;
  80         }
  81
  82         if (flags & MMC_RSP_PRESENT)
  83                 cmd |= FTSDC010_CMD_NEED_RSP;
  84
  85         if (flags & MMC_RSP_136)
  86                 cmd |= FTSDC010_CMD_LONG_RSP;
  87
  88         writel(FTSDC010_STATUS_RSP_MASK | FTSDC010_STATUS_CMD_SEND,
  89                 &regs->clr);
  90         writel(arg, &regs->argu);
  91         writel(cmd, &regs->cmd);
  92
  93         if (!(flags & (MMC_RSP_PRESENT | MMC_RSP_136))) {
  94                 for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
  95                         if (readl(&regs->status) & FTSDC010_STATUS_CMD_SEND) {
  96                                 writel(FTSDC010_STATUS_CMD_SEND, &regs->clr);
  97                                 ret = 0;
  98                                 break;
  99                         }
 100                 }
 101         } else {
 102                 st = 0;
 103                 for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
 104                         st = readl(&regs->status);
 105                         writel(st & FTSDC010_STATUS_RSP_MASK, &regs->clr);
 106                         if (st & FTSDC010_STATUS_RSP_MASK)
 107                                 break;
 108                 }
 109                 if (st & FTSDC010_STATUS_RSP_CRC_OK) {
 110                         if (flags & MMC_RSP_136) {
 111                                 mmc_cmd->response[0] = readl(&regs->rsp3);
 112                                 mmc_cmd->response[1] = readl(&regs->rsp2);
 113                                 mmc_cmd->response[2] = readl(&regs->rsp1);
 114                                 mmc_cmd->response[3] = readl(&regs->rsp0);
 115                         } else {
 116                                 mmc_cmd->response[0] = readl(&regs->rsp0);
 117                         }
 118                         ret = 0;
 119                 } else {
 120                         debug("ftsdc010: rsp err (cmd=%d, st=0x%x)\n",
 121                                 mmc_cmd->cmdidx, st);
 122                 }
 123         }
 124
 125         if (ret) {
 126                 debug("ftsdc010: cmd timeout (op code=%d)\n",
 127                         mmc_cmd->cmdidx);
 128         } else if (mmc_cmd->cmdidx == MMC_CMD_APP_CMD) {
 129                 chip->acmd = 1;
 130         }
 131
 132         return ret;
 133 }
 134
 135 static void ftsdc010_clkset(struct mmc *mmc, uint32_t rate)
 136 {
 137         struct ftsdc010_chip *chip = mmc->priv;
 138         struct ftsdc010_mmc __iomem *regs = chip->regs;
 139         uint32_t div;
 140
 141         for (div = 0; div < 0x7f; ++div) {
 142                 if (rate >= chip->sclk / (2 * (div + 1)))
 143                         break;
 144         }
 145         chip->rate = chip->sclk / (2 * (div + 1));
 146
 147         writel(FTSDC010_CCR_CLK_DIV(div), &regs->ccr);
 148
 149         if (IS_SD(mmc)) {
 150                 setbits_le32(&regs->ccr, FTSDC010_CCR_CLK_SD);
 151
 152                 if (chip->rate > 25000000)
 153                         setbits_le32(&regs->ccr, FTSDC010_CCR_CLK_HISPD);
 154                 else
 155                         clrbits_le32(&regs->ccr, FTSDC010_CCR_CLK_HISPD);
 156         }
 157 }
 158
 159 static int ftsdc010_wait(struct ftsdc010_mmc __iomem *regs, uint32_t mask)
 160 {
 161         int ret = -ETIMEDOUT;
 162         uint32_t st, timeout = 10000000;
 163         while (timeout--) {
 164                 st = readl(&regs->status);
 165                 if (!(st & mask))
 166                         continue;
 167                 writel(st & mask, &regs->clr);
 168                 ret = 0;
 169                 break;
 170         }
 171
 172         if (ret){
 173                 debug("ftsdc010: wait st(0x%x) timeout\n", mask);
 174         }
 175
 176         return ret;
 177 }
 178
 179 /*
 180  * u-boot mmc api
 181  */
 182 static int ftsdc010_request(struct udevice *dev, struct mmc_cmd *cmd,
 183         struct mmc_data *data)
 184 {
 185         struct mmc *mmc = mmc_get_mmc_dev(dev);
 186         int ret = -EOPNOTSUPP;
 187         uint32_t len = 0;
 188         struct ftsdc010_chip *chip = mmc->priv;
 189         struct ftsdc010_mmc __iomem *regs = chip->regs;
 190
 191         if (data && (data->flags & MMC_DATA_WRITE) && chip->wprot) {
 192                 printf("ftsdc010: the card is write protected!\n");
 193                 return ret;
 194         }
 195
 196         if (data) {
 197                 uint32_t dcr;
 198
 199                 len = data->blocksize * data->blocks;
 200
 201                 /* 1. data disable + fifo reset */
 202                 dcr = 0;
 203 #ifdef CONFIG_FTSDC010_SDIO
 204                 dcr |= FTSDC010_DCR_FIFO_RST;
 205 #endif
 206                 writel(dcr, &regs->dcr);
 207
 208                 /* 2. clear status register */
 209                 writel(FTSDC010_STATUS_DATA_MASK | FTSDC010_STATUS_FIFO_URUN
 210                         | FTSDC010_STATUS_FIFO_ORUN, &regs->clr);
 211
 212                 /* 3. data timeout (1 sec) */
 213                 writel(chip->rate, &regs->dtr);
 214
 215                 /* 4. data length (bytes) */
 216                 writel(len, &regs->dlr);
 217
 218                 /* 5. data enable */
 219                 dcr = (ffs(data->blocksize) - 1) | FTSDC010_DCR_DATA_EN;
 220                 if (data->flags & MMC_DATA_WRITE)
 221                         dcr |= FTSDC010_DCR_DATA_WRITE;
 222                 writel(dcr, &regs->dcr);
 223         }
 224
 225         ret = ftsdc010_send_cmd(mmc, cmd);
 226         if (ret) {
 227                 printf("ftsdc010: CMD%d failed\n", cmd->cmdidx);
 228                 return ret;
 229         }
 230
 231         if (!data)
 232                 return ret;
 233
 234         if (data->flags & MMC_DATA_WRITE) {
 235                 const uint8_t *buf = (const uint8_t *)data->src;
 236
 237                 while (len > 0) {
 238                         int wlen;
 239
 240                         /* wait for tx ready */
 241                         ret = ftsdc010_wait(regs, FTSDC010_STATUS_FIFO_URUN);
 242                         if (ret)
 243                                 break;
 244
 245                         /* write bytes to ftsdc010 */
 246                         for (wlen = 0; wlen < len && wlen < chip->fifo; ) {
 247                                 writel(*(uint32_t *)buf, &regs->dwr);
 248                                 buf  += 4;
 249                                 wlen += 4;
 250                         }
 251
 252                         len -= wlen;
 253                 }
 254
 255         } else {
 256                 uint8_t *buf = (uint8_t *)data->dest;
 257
 258                 while (len > 0) {
 259                         int rlen;
 260
 261                         /* wait for rx ready */
 262                         ret = ftsdc010_wait(regs, FTSDC010_STATUS_FIFO_ORUN);
 263                         if (ret)
 264                                 break;
 265
 266                         /* fetch bytes from ftsdc010 */
 267                         for (rlen = 0; rlen < len && rlen < chip->fifo; ) {
 268                                 *(uint32_t *)buf = readl(&regs->dwr);
 269                                 buf  += 4;
 270                                 rlen += 4;
 271                         }
 272
 273                         len -= rlen;
 274                 }
 275
 276         }
 277
 278         if (!ret) {
 279                 ret = ftsdc010_wait(regs,
 280                         FTSDC010_STATUS_DATA_END | FTSDC010_STATUS_DATA_CRC_OK);
 281         }
 282
 283         return ret;
 284 }
 285
 286 static int ftsdc010_set_ios(struct udevice *dev)
 287 {
 288         struct mmc *mmc = mmc_get_mmc_dev(dev);
 289         struct ftsdc010_chip *chip = mmc->priv;
 290         struct ftsdc010_mmc __iomem *regs = chip->regs;
 291
 292         ftsdc010_clkset(mmc, mmc->clock);
 293
 294         clrbits_le32(&regs->bwr, FTSDC010_BWR_MODE_MASK);
 295         switch (mmc->bus_width) {
 296         case 4:
 297                 setbits_le32(&regs->bwr, FTSDC010_BWR_MODE_4BIT);
 298                 break;
 299         case 8:
 300                 setbits_le32(&regs->bwr, FTSDC010_BWR_MODE_8BIT);
 301                 break;
 302         default:
 303                 setbits_le32(&regs->bwr, FTSDC010_BWR_MODE_1BIT);
 304                 break;
 305         }
 306
 307         return 0;
 308 }
 309
 310 static int ftsdc010_get_cd(struct udevice *dev)
 311 {
 312         struct mmc *mmc = mmc_get_mmc_dev(dev);
 313         struct ftsdc010_chip *chip = mmc->priv;
 314         struct ftsdc010_mmc __iomem *regs = chip->regs;
 315         return !(readl(&regs->status) & FTSDC010_STATUS_CARD_DETECT);
 316 }
 317
 318 static int ftsdc010_get_wp(struct udevice *dev)
 319 {
 320         struct mmc *mmc = mmc_get_mmc_dev(dev);
 321         struct ftsdc010_chip *chip = mmc->priv;
 322         struct ftsdc010_mmc __iomem *regs = chip->regs;
 323         if (readl(&regs->status) & FTSDC010_STATUS_WRITE_PROT) {
 324                 printf("ftsdc010: write protected\n");
 325                 chip->wprot = 1;
 326         }
 327
 328         return 0;
 329 }
 330
 331 static int ftsdc010_init(struct mmc *mmc)
 332 {
 333         struct ftsdc010_chip *chip = mmc->priv;
 334         struct ftsdc010_mmc __iomem *regs = chip->regs;
 335         uint32_t ts;
 336
 337         chip->fifo = (readl(&regs->feature) & 0xff) << 2;
 338
 339         /* 1. chip reset */
 340         writel(FTSDC010_CMD_SDC_RST, &regs->cmd);
 341         for (ts = get_timer(0); get_timer(ts) < CFG_RST_TIMEOUT; ) {
 342                 if (readl(&regs->cmd) & FTSDC010_CMD_SDC_RST)
 343                         continue;
 344                 break;
 345         }
 346         if (readl(&regs->cmd) & FTSDC010_CMD_SDC_RST) {
 347                 printf("ftsdc010: reset failed\n");
 348                 return -EOPNOTSUPP;
 349         }
 350
 351         /* 2. enter low speed mode (400k card detection) */
 352         ftsdc010_clkset(mmc, 400000);
 353
 354         /* 3. interrupt disabled */
 355         writel(0, &regs->int_mask);
 356
 357         return 0;
 358 }
 359
 360 static int ftsdc010_probe(struct udevice *dev)
 361 {
 362         struct mmc *mmc = mmc_get_mmc_dev(dev);
 363         return ftsdc010_init(mmc);
 364 }
 365
 366 const struct dm_mmc_ops dm_ftsdc010_mmc_ops = {
 367         .send_cmd       = ftsdc010_request,
 368         .set_ios        = ftsdc010_set_ios,
 369         .get_cd         = ftsdc010_get_cd,
 370         .get_wp         = ftsdc010_get_wp,
 371 };
 372
 373 static void ftsdc_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
 374                      uint caps, u32 max_clk, u32 min_clk)
 375 {
 376         cfg->name = name;
 377         cfg->f_min = min_clk;
 378         cfg->f_max = max_clk;
 379         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 380         cfg->host_caps = caps;
 381         if (buswidth == 8) {
 382                 cfg->host_caps |= MMC_MODE_8BIT;
 383                 cfg->host_caps &= ~MMC_MODE_4BIT;
 384         } else {
 385                 cfg->host_caps |= MMC_MODE_4BIT;
 386                 cfg->host_caps &= ~MMC_MODE_8BIT;
 387         }
 388         cfg->part_type = PART_TYPE_DOS;
 389         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 390 }
 391
 392 static int ftsdc010_mmc_ofdata_to_platdata(struct udevice *dev)
 393 {
 394 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 395         struct ftsdc_priv *priv = dev_get_priv(dev);
 396         struct ftsdc010_chip *chip = &priv->chip;
 397         chip->name = dev->name;
 398         chip->ioaddr = (void *)devfdt_get_addr(dev);
 399         chip->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
 400                                         "bus-width", 4);
 401         chip->priv = dev;
 402         priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
 403                                     "fifo-depth", 0);
 404         priv->fifo_mode = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
 405                                           "fifo-mode");
 406         if (fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
 407                          "clock-freq-min-max", priv->minmax, 2)) {
 408                 int val = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
 409                                   "max-frequency", -EINVAL);
 410                 if (val < 0)
 411                         return val;
 412
 413                 priv->minmax[0] = 400000;  /* 400 kHz */
 414                 priv->minmax[1] = val;
 415         } else {
 416                 debug("%s: 'clock-freq-min-max' property was deprecated.\n",
 417                 __func__);
 418         }
 419 #endif
 420         chip->sclk = priv->minmax[1];
 421         chip->regs = chip->ioaddr;
 422         return 0;
 423 }
 424
 425 static int ftsdc010_mmc_probe(struct udevice *dev)
 426 {
 427         struct ftsdc010_plat *plat = dev_get_platdata(dev);
 428         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 429         struct ftsdc_priv *priv = dev_get_priv(dev);
 430         struct ftsdc010_chip *chip = &priv->chip;
 431         struct udevice *pwr_dev __maybe_unused;
 432
 433 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 434         int ret;
 435         struct ftsdc010 *dtplat = &plat->dtplat;
 436         chip->name = dev->name;
 437         chip->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
 438         chip->buswidth = dtplat->bus_width;
 439         chip->priv = dev;
 440         chip->dev_index = 1;
 441         memcpy(priv->minmax, dtplat->clock_freq_min_max, sizeof(priv->minmax));
 442         ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);
 443         if (ret < 0)
 444                 return ret;
 445 #endif
 446
 447         if (dev_read_bool(dev, "cap-mmc-highspeed") || \
 448                   dev_read_bool(dev, "cap-sd-highspeed"))
 449                 chip->caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
 450
 451         ftsdc_setup_cfg(&plat->cfg, dev->name, chip->buswidth, chip->caps,
 452                         priv->minmax[1] , priv->minmax[0]);
 453         chip->mmc = &plat->mmc;
 454         chip->mmc->priv = &priv->chip;
 455         chip->mmc->dev = dev;
 456         upriv->mmc = chip->mmc;
 457         return ftsdc010_probe(dev);
 458 }
 459
 460 int ftsdc010_mmc_bind(struct udevice *dev)
 461 {
 462         struct ftsdc010_plat *plat = dev_get_platdata(dev);
 463
 464         return mmc_bind(dev, &plat->mmc, &plat->cfg);
 465 }
 466
 467 static const struct udevice_id ftsdc010_mmc_ids[] = {
 468         { .compatible = "andestech,atfsdc010" },
 469         { }
 470 };
 471
 472 U_BOOT_DRIVER(ftsdc010_mmc) = {
 473         .name           = "ftsdc010_mmc",
 474         .id             = UCLASS_MMC,
 475         .of_match       = ftsdc010_mmc_ids,
 476         .ofdata_to_platdata = ftsdc010_mmc_ofdata_to_platdata,
 477         .ops            = &dm_ftsdc010_mmc_ops,
 478         .bind           = ftsdc010_mmc_bind,
 479         .probe          = ftsdc010_mmc_probe,
 480         .priv_auto_alloc_size = sizeof(struct ftsdc_priv),
 481         .platdata_auto_alloc_size = sizeof(struct ftsdc010_plat),
 482 };