1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
4 * Copyright 2019 NXP Semiconductors
6 * Yangbo Lu <yangbo.lu@nxp.com>
8 * Based vaguely on the pxa mmc code:
10 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
21 #include <power/regulator.h>
23 #include <fsl_esdhc_imx.h>
24 #include <fdt_support.h>
27 #include <asm-generic/gpio.h>
28 #include <dm/pinctrl.h>
30 #if !CONFIG_IS_ENABLED(BLK)
31 #include "mmc_private.h"
34 DECLARE_GLOBAL_DATA_PTR;
36 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
38 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
39 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
40 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
42 #define MAX_TUNING_LOOP 40
43 #define ESDHC_DRIVER_STAGE_VALUE 0xffffffff
46 uint dsaddr; /* SDMA system address register */
47 uint blkattr; /* Block attributes register */
48 uint cmdarg; /* Command argument register */
49 uint xfertyp; /* Transfer type register */
50 uint cmdrsp0; /* Command response 0 register */
51 uint cmdrsp1; /* Command response 1 register */
52 uint cmdrsp2; /* Command response 2 register */
53 uint cmdrsp3; /* Command response 3 register */
54 uint datport; /* Buffer data port register */
55 uint prsstat; /* Present state register */
56 uint proctl; /* Protocol control register */
57 uint sysctl; /* System Control Register */
58 uint irqstat; /* Interrupt status register */
59 uint irqstaten; /* Interrupt status enable register */
60 uint irqsigen; /* Interrupt signal enable register */
61 uint autoc12err; /* Auto CMD error status register */
62 uint hostcapblt; /* Host controller capabilities register */
63 uint wml; /* Watermark level register */
64 uint mixctrl; /* For USDHC */
65 char reserved1[4]; /* reserved */
66 uint fevt; /* Force event register */
67 uint admaes; /* ADMA error status register */
68 uint adsaddr; /* ADMA system address register */
72 uint clktunectrlstatus;
80 uint tuning_ctrl; /* on i.MX6/7/8 */
82 uint hostver; /* Host controller version register */
83 char reserved6[4]; /* reserved */
84 uint dmaerraddr; /* DMA error address register */
85 char reserved7[4]; /* reserved */
86 uint dmaerrattr; /* DMA error attribute register */
87 char reserved8[4]; /* reserved */
88 uint hostcapblt2; /* Host controller capabilities register 2 */
89 char reserved9[8]; /* reserved */
90 uint tcr; /* Tuning control register */
91 char reserved10[28]; /* reserved */
92 uint sddirctl; /* SD direction control register */
93 char reserved11[712];/* reserved */
94 uint scr; /* eSDHC control register */
97 struct fsl_esdhc_plat {
98 struct mmc_config cfg;
102 struct esdhc_soc_data {
107 * struct fsl_esdhc_priv
109 * @esdhc_regs: registers of the sdhc controller
110 * @sdhc_clk: Current clk of the sdhc controller
111 * @bus_width: bus width, 1bit, 4bit or 8bit
114 * Following is used when Driver Model is enabled for MMC
115 * @dev: pointer for the device
116 * @non_removable: 0: removable; 1: non-removable
117 * @wp_enable: 1: enable checking wp; 0: no check
118 * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
119 * @flags: ESDHC_FLAG_xx in include/fsl_esdhc_imx.h
120 * @caps: controller capabilities
121 * @tuning_step: tuning step setting in tuning_ctrl register
122 * @start_tuning_tap: the start point for tuning in tuning_ctrl register
123 * @strobe_dll_delay_target: settings in strobe_dllctrl
124 * @signal_voltage: indicating the current voltage
125 * @cd_gpio: gpio for card detection
126 * @wp_gpio: gpio for write protection
128 struct fsl_esdhc_priv {
129 struct fsl_esdhc *esdhc_regs;
130 unsigned int sdhc_clk;
134 unsigned int bus_width;
135 #if !CONFIG_IS_ENABLED(BLK)
145 u32 tuning_start_tap;
146 u32 strobe_dll_delay_target;
148 #if CONFIG_IS_ENABLED(DM_REGULATOR)
149 struct udevice *vqmmc_dev;
150 struct udevice *vmmc_dev;
152 #ifdef CONFIG_DM_GPIO
153 struct gpio_desc cd_gpio;
154 struct gpio_desc wp_gpio;
158 /* Return the XFERTYP flags for a given command and data packet */
159 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
164 xfertyp |= XFERTYP_DPSEL;
165 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
166 xfertyp |= XFERTYP_DMAEN;
168 if (data->blocks > 1) {
169 xfertyp |= XFERTYP_MSBSEL;
170 xfertyp |= XFERTYP_BCEN;
171 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
172 xfertyp |= XFERTYP_AC12EN;
176 if (data->flags & MMC_DATA_READ)
177 xfertyp |= XFERTYP_DTDSEL;
180 if (cmd->resp_type & MMC_RSP_CRC)
181 xfertyp |= XFERTYP_CCCEN;
182 if (cmd->resp_type & MMC_RSP_OPCODE)
183 xfertyp |= XFERTYP_CICEN;
184 if (cmd->resp_type & MMC_RSP_136)
185 xfertyp |= XFERTYP_RSPTYP_136;
186 else if (cmd->resp_type & MMC_RSP_BUSY)
187 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
188 else if (cmd->resp_type & MMC_RSP_PRESENT)
189 xfertyp |= XFERTYP_RSPTYP_48;
191 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
192 xfertyp |= XFERTYP_CMDTYP_ABORT;
194 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
197 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
199 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
201 static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
202 struct mmc_data *data)
204 struct fsl_esdhc *regs = priv->esdhc_regs;
212 if (data->flags & MMC_DATA_READ) {
213 blocks = data->blocks;
216 start = get_timer(0);
217 size = data->blocksize;
218 irqstat = esdhc_read32(®s->irqstat);
219 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)) {
220 if (get_timer(start) > PIO_TIMEOUT) {
221 printf("\nData Read Failed in PIO Mode.");
225 while (size && (!(irqstat & IRQSTAT_TC))) {
226 udelay(100); /* Wait before last byte transfer complete */
227 irqstat = esdhc_read32(®s->irqstat);
228 databuf = in_le32(®s->datport);
229 *((uint *)buffer) = databuf;
236 blocks = data->blocks;
237 buffer = (char *)data->src;
239 start = get_timer(0);
240 size = data->blocksize;
241 irqstat = esdhc_read32(®s->irqstat);
242 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)) {
243 if (get_timer(start) > PIO_TIMEOUT) {
244 printf("\nData Write Failed in PIO Mode.");
248 while (size && (!(irqstat & IRQSTAT_TC))) {
249 udelay(100); /* Wait before last byte transfer complete */
250 databuf = *((uint *)buffer);
253 irqstat = esdhc_read32(®s->irqstat);
254 out_le32(®s->datport, databuf);
262 static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
263 struct mmc_data *data)
266 struct fsl_esdhc *regs = priv->esdhc_regs;
267 #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
272 wml_value = data->blocksize/4;
274 if (data->flags & MMC_DATA_READ) {
275 if (wml_value > WML_RD_WML_MAX)
276 wml_value = WML_RD_WML_MAX_VAL;
278 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
279 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
280 #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
281 addr = virt_to_phys((void *)(data->dest));
282 if (upper_32_bits(addr))
283 printf("Error found for upper 32 bits\n");
285 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
287 esdhc_write32(®s->dsaddr, (u32)data->dest);
291 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
292 flush_dcache_range((ulong)data->src,
293 (ulong)data->src+data->blocks
296 if (wml_value > WML_WR_WML_MAX)
297 wml_value = WML_WR_WML_MAX_VAL;
298 if (priv->wp_enable) {
299 if ((esdhc_read32(®s->prsstat) &
300 PRSSTAT_WPSPL) == 0) {
301 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
305 #ifdef CONFIG_DM_GPIO
306 if (dm_gpio_is_valid(&priv->wp_gpio) && dm_gpio_get_value(&priv->wp_gpio)) {
307 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
313 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
315 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
316 #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
317 addr = virt_to_phys((void *)(data->src));
318 if (upper_32_bits(addr))
319 printf("Error found for upper 32 bits\n");
321 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
323 esdhc_write32(®s->dsaddr, (u32)data->src);
328 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
330 /* Calculate the timeout period for data transactions */
332 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
333 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
334 * So, Number of SD Clock cycles for 0.25sec should be minimum
335 * (SD Clock/sec * 0.25 sec) SD Clock cycles
336 * = (mmc->clock * 1/4) SD Clock cycles
338 * => (2^(timeout+13)) >= mmc->clock * 1/4
339 * Taking log2 both the sides
340 * => timeout + 13 >= log2(mmc->clock/4)
341 * Rounding up to next power of 2
342 * => timeout + 13 = log2(mmc->clock/4) + 1
343 * => timeout + 13 = fls(mmc->clock/4)
345 * However, the MMC spec "It is strongly recommended for hosts to
346 * implement more than 500ms timeout value even if the card
347 * indicates the 250ms maximum busy length." Even the previous
348 * value of 300ms is known to be insufficient for some cards.
350 * => timeout + 13 = fls(mmc->clock/2)
352 timeout = fls(mmc->clock/2);
361 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
362 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
366 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
369 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
374 static void check_and_invalidate_dcache_range
375 (struct mmc_cmd *cmd,
376 struct mmc_data *data) {
379 unsigned size = roundup(ARCH_DMA_MINALIGN,
380 data->blocks*data->blocksize);
381 #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
384 addr = virt_to_phys((void *)(data->dest));
385 if (upper_32_bits(addr))
386 printf("Error found for upper 32 bits\n");
388 start = lower_32_bits(addr);
390 start = (unsigned)data->dest;
393 invalidate_dcache_range(start, end);
396 #ifdef CONFIG_MCF5441x
398 * Swaps 32-bit words to little-endian byte order.
400 static inline void sd_swap_dma_buff(struct mmc_data *data)
402 int i, size = data->blocksize >> 2;
403 u32 *buffer = (u32 *)data->dest;
406 while (data->blocks--) {
407 for (i = 0; i < size; i++) {
408 sw = __sw32(*buffer);
416 * Sends a command out on the bus. Takes the mmc pointer,
417 * a command pointer, and an optional data pointer.
419 static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
420 struct mmc_cmd *cmd, struct mmc_data *data)
425 u32 flags = IRQSTAT_CC | IRQSTAT_CTOE;
426 struct fsl_esdhc *regs = priv->esdhc_regs;
429 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
430 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
434 esdhc_write32(®s->irqstat, -1);
438 /* Wait for the bus to be idle */
439 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
440 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
443 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
446 /* Wait at least 8 SD clock cycles before the next command */
448 * Note: This is way more than 8 cycles, but 1ms seems to
449 * resolve timing issues with some cards
453 /* Set up for a data transfer if we have one */
455 err = esdhc_setup_data(priv, mmc, data);
459 if (data->flags & MMC_DATA_READ)
460 check_and_invalidate_dcache_range(cmd, data);
463 /* Figure out the transfer arguments */
464 xfertyp = esdhc_xfertyp(cmd, data);
467 esdhc_write32(®s->irqsigen, 0);
469 /* Send the command */
470 esdhc_write32(®s->cmdarg, cmd->cmdarg);
471 #if defined(CONFIG_FSL_USDHC)
472 esdhc_write32(®s->mixctrl,
473 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
474 | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
475 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000);
477 esdhc_write32(®s->xfertyp, xfertyp);
480 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
481 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))
484 /* Wait for the command to complete */
485 start = get_timer(0);
486 while (!(esdhc_read32(®s->irqstat) & flags)) {
487 if (get_timer(start) > 1000) {
493 irqstat = esdhc_read32(®s->irqstat);
495 if (irqstat & CMD_ERR) {
500 if (irqstat & IRQSTAT_CTOE) {
505 /* Switch voltage to 1.8V if CMD11 succeeded */
506 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
507 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
509 printf("Run CMD11 1.8V switch\n");
510 /* Sleep for 5 ms - max time for card to switch to 1.8V */
514 /* Workaround for ESDHC errata ENGcm03648 */
515 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
518 /* Poll on DATA0 line for cmd with busy signal for 600 ms */
519 while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
526 printf("Timeout waiting for DAT0 to go high!\n");
532 /* Copy the response to the response buffer */
533 if (cmd->resp_type & MMC_RSP_136) {
534 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
536 cmdrsp3 = esdhc_read32(®s->cmdrsp3);
537 cmdrsp2 = esdhc_read32(®s->cmdrsp2);
538 cmdrsp1 = esdhc_read32(®s->cmdrsp1);
539 cmdrsp0 = esdhc_read32(®s->cmdrsp0);
540 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
541 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
542 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
543 cmd->response[3] = (cmdrsp0 << 8);
545 cmd->response[0] = esdhc_read32(®s->cmdrsp0);
547 /* Wait until all of the blocks are transferred */
549 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
550 esdhc_pio_read_write(priv, data);
552 flags = DATA_COMPLETE;
553 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
554 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) {
559 irqstat = esdhc_read32(®s->irqstat);
561 if (irqstat & IRQSTAT_DTOE) {
566 if (irqstat & DATA_ERR) {
570 } while ((irqstat & flags) != flags);
573 * Need invalidate the dcache here again to avoid any
574 * cache-fill during the DMA operations such as the
575 * speculative pre-fetching etc.
577 if (data->flags & MMC_DATA_READ) {
578 check_and_invalidate_dcache_range(cmd, data);
579 #ifdef CONFIG_MCF5441x
580 sd_swap_dma_buff(data);
587 /* Reset CMD and DATA portions on error */
589 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
591 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC)
595 esdhc_write32(®s->sysctl,
596 esdhc_read32(®s->sysctl) |
598 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
602 /* If this was CMD11, then notify that power cycle is needed */
603 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
604 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
607 esdhc_write32(®s->irqstat, -1);
612 static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
614 struct fsl_esdhc *regs = priv->esdhc_regs;
618 /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
619 int pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1;
626 int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
627 int sdhc_clk = priv->sdhc_clk;
630 if (clock < mmc->cfg->f_min)
631 clock = mmc->cfg->f_min;
633 while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
636 while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
642 clk = (pre_div << 8) | (div << 4);
644 #ifdef CONFIG_FSL_USDHC
645 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
647 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
650 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
654 #ifdef CONFIG_FSL_USDHC
655 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
657 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
663 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
664 static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
666 struct fsl_esdhc *regs = priv->esdhc_regs;
670 value = esdhc_read32(®s->sysctl);
673 value |= SYSCTL_CKEN;
675 value &= ~SYSCTL_CKEN;
677 esdhc_write32(®s->sysctl, value);
680 value = PRSSTAT_SDSTB;
681 while (!(esdhc_read32(®s->prsstat) & value)) {
683 printf("fsl_esdhc: Internal clock never stabilised.\n");
692 #ifdef MMC_SUPPORTS_TUNING
693 static int esdhc_change_pinstate(struct udevice *dev)
695 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
698 switch (priv->mode) {
701 ret = pinctrl_select_state(dev, "state_100mhz");
706 ret = pinctrl_select_state(dev, "state_200mhz");
709 ret = pinctrl_select_state(dev, "default");
714 printf("%s %d error\n", __func__, priv->mode);
719 static void esdhc_reset_tuning(struct mmc *mmc)
721 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
722 struct fsl_esdhc *regs = priv->esdhc_regs;
724 if (priv->flags & ESDHC_FLAG_USDHC) {
725 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
726 esdhc_clrbits32(®s->autoc12err,
727 MIX_CTRL_SMPCLK_SEL |
733 static void esdhc_set_strobe_dll(struct mmc *mmc)
735 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
736 struct fsl_esdhc *regs = priv->esdhc_regs;
739 if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
740 writel(ESDHC_STROBE_DLL_CTRL_RESET, ®s->strobe_dllctrl);
743 * enable strobe dll ctrl and adjust the delay target
744 * for the uSDHC loopback read clock
746 val = ESDHC_STROBE_DLL_CTRL_ENABLE |
747 (priv->strobe_dll_delay_target <<
748 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
749 writel(val, ®s->strobe_dllctrl);
750 /* wait 1us to make sure strobe dll status register stable */
752 val = readl(®s->strobe_dllstat);
753 if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK))
754 pr_warn("HS400 strobe DLL status REF not lock!\n");
755 if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK))
756 pr_warn("HS400 strobe DLL status SLV not lock!\n");
760 static int esdhc_set_timing(struct mmc *mmc)
762 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
763 struct fsl_esdhc *regs = priv->esdhc_regs;
766 mixctrl = readl(®s->mixctrl);
767 mixctrl &= ~(MIX_CTRL_DDREN | MIX_CTRL_HS400_EN);
769 switch (mmc->selected_mode) {
772 esdhc_reset_tuning(mmc);
773 writel(mixctrl, ®s->mixctrl);
776 mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN;
777 writel(mixctrl, ®s->mixctrl);
778 esdhc_set_strobe_dll(mmc);
788 writel(mixctrl, ®s->mixctrl);
792 mixctrl |= MIX_CTRL_DDREN;
793 writel(mixctrl, ®s->mixctrl);
796 printf("Not supported %d\n", mmc->selected_mode);
800 priv->mode = mmc->selected_mode;
802 return esdhc_change_pinstate(mmc->dev);
805 static int esdhc_set_voltage(struct mmc *mmc)
807 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
808 struct fsl_esdhc *regs = priv->esdhc_regs;
811 priv->signal_voltage = mmc->signal_voltage;
812 switch (mmc->signal_voltage) {
813 case MMC_SIGNAL_VOLTAGE_330:
814 if (priv->vs18_enable)
816 #if CONFIG_IS_ENABLED(DM_REGULATOR)
817 if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
818 ret = regulator_set_value(priv->vqmmc_dev, 3300000);
820 printf("Setting to 3.3V error");
828 esdhc_clrbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
829 if (!(esdhc_read32(®s->vendorspec) &
830 ESDHC_VENDORSPEC_VSELECT))
834 case MMC_SIGNAL_VOLTAGE_180:
835 #if CONFIG_IS_ENABLED(DM_REGULATOR)
836 if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
837 ret = regulator_set_value(priv->vqmmc_dev, 1800000);
839 printf("Setting to 1.8V error");
844 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
845 if (esdhc_read32(®s->vendorspec) & ESDHC_VENDORSPEC_VSELECT)
849 case MMC_SIGNAL_VOLTAGE_120:
856 static void esdhc_stop_tuning(struct mmc *mmc)
860 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
862 cmd.resp_type = MMC_RSP_R1b;
864 dm_mmc_send_cmd(mmc->dev, &cmd, NULL);
867 static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
869 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
870 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
871 struct fsl_esdhc *regs = priv->esdhc_regs;
872 struct mmc *mmc = &plat->mmc;
873 u32 irqstaten = readl(®s->irqstaten);
874 u32 irqsigen = readl(®s->irqsigen);
875 int i, ret = -ETIMEDOUT;
878 /* clock tuning is not needed for upto 52MHz */
879 if (mmc->clock <= 52000000)
882 /* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */
883 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
884 val = readl(®s->autoc12err);
885 mixctrl = readl(®s->mixctrl);
886 val &= ~MIX_CTRL_SMPCLK_SEL;
887 mixctrl &= ~(MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN);
889 val |= MIX_CTRL_EXE_TUNE;
890 mixctrl |= MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN;
892 writel(val, ®s->autoc12err);
893 writel(mixctrl, ®s->mixctrl);
896 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); */
897 mixctrl = readl(®s->mixctrl);
898 mixctrl = MIX_CTRL_DTDSEL_READ | (mixctrl & ~MIX_CTRL_SDHCI_MASK);
899 writel(mixctrl, ®s->mixctrl);
901 writel(IRQSTATEN_BRR, ®s->irqstaten);
902 writel(IRQSTATEN_BRR, ®s->irqsigen);
905 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
906 * of loops reaches 40 times.
908 for (i = 0; i < MAX_TUNING_LOOP; i++) {
911 if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) {
912 if (mmc->bus_width == 8)
913 writel(0x7080, ®s->blkattr);
914 else if (mmc->bus_width == 4)
915 writel(0x7040, ®s->blkattr);
917 writel(0x7040, ®s->blkattr);
920 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE) */
921 val = readl(®s->mixctrl);
922 val = MIX_CTRL_DTDSEL_READ | (val & ~MIX_CTRL_SDHCI_MASK);
923 writel(val, ®s->mixctrl);
925 /* We are using STD tuning, no need to check return value */
926 mmc_send_tuning(mmc, opcode, NULL);
928 ctrl = readl(®s->autoc12err);
929 if ((!(ctrl & MIX_CTRL_EXE_TUNE)) &&
930 (ctrl & MIX_CTRL_SMPCLK_SEL)) {
932 * need to wait some time, make sure sd/mmc fininsh
933 * send out tuning data, otherwise, the sd/mmc can't
934 * response to any command when the card still out
935 * put the tuning data.
942 /* Add 1ms delay for SD and eMMC */
946 writel(irqstaten, ®s->irqstaten);
947 writel(irqsigen, ®s->irqsigen);
949 esdhc_stop_tuning(mmc);
955 static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
957 struct fsl_esdhc *regs = priv->esdhc_regs;
958 int ret __maybe_unused;
960 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
961 /* Select to use peripheral clock */
962 esdhc_clock_control(priv, false);
963 esdhc_setbits32(®s->scr, ESDHCCTL_PCS);
964 esdhc_clock_control(priv, true);
966 /* Set the clock speed */
967 if (priv->clock != mmc->clock)
968 set_sysctl(priv, mmc, mmc->clock);
970 #ifdef MMC_SUPPORTS_TUNING
971 if (mmc->clk_disable) {
972 #ifdef CONFIG_FSL_USDHC
973 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
975 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
978 #ifdef CONFIG_FSL_USDHC
979 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
982 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
986 if (priv->mode != mmc->selected_mode) {
987 ret = esdhc_set_timing(mmc);
989 printf("esdhc_set_timing error %d\n", ret);
994 if (priv->signal_voltage != mmc->signal_voltage) {
995 ret = esdhc_set_voltage(mmc);
997 printf("esdhc_set_voltage error %d\n", ret);
1003 /* Set the bus width */
1004 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
1006 if (mmc->bus_width == 4)
1007 esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
1008 else if (mmc->bus_width == 8)
1009 esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
1014 static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
1016 struct fsl_esdhc *regs = priv->esdhc_regs;
1019 /* Reset the entire host controller */
1020 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
1022 /* Wait until the controller is available */
1023 start = get_timer(0);
1024 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
1025 if (get_timer(start) > 1000)
1029 #if defined(CONFIG_FSL_USDHC)
1030 /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
1031 esdhc_write32(®s->mmcboot, 0x0);
1032 /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
1033 esdhc_write32(®s->mixctrl, 0x0);
1034 esdhc_write32(®s->clktunectrlstatus, 0x0);
1036 /* Put VEND_SPEC to default value */
1037 if (priv->vs18_enable)
1038 esdhc_write32(®s->vendorspec, (VENDORSPEC_INIT |
1039 ESDHC_VENDORSPEC_VSELECT));
1041 esdhc_write32(®s->vendorspec, VENDORSPEC_INIT);
1043 /* Disable DLL_CTRL delay line */
1044 esdhc_write32(®s->dllctrl, 0x0);
1048 /* Enable cache snooping */
1049 esdhc_write32(®s->scr, 0x00000040);
1052 #ifndef CONFIG_FSL_USDHC
1053 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
1055 esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
1058 /* Set the initial clock speed */
1059 mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
1061 /* Disable the BRR and BWR bits in IRQSTAT */
1062 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
1064 #ifdef CONFIG_MCF5441x
1065 esdhc_write32(®s->proctl, PROCTL_INIT | PROCTL_D3CD);
1067 /* Put the PROCTL reg back to the default */
1068 esdhc_write32(®s->proctl, PROCTL_INIT);
1071 /* Set timout to the maximum value */
1072 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
1077 static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
1079 struct fsl_esdhc *regs = priv->esdhc_regs;
1082 #ifdef CONFIG_ESDHC_DETECT_QUIRK
1083 if (CONFIG_ESDHC_DETECT_QUIRK)
1087 #if CONFIG_IS_ENABLED(DM_MMC)
1088 if (priv->non_removable)
1090 #ifdef CONFIG_DM_GPIO
1091 if (dm_gpio_is_valid(&priv->cd_gpio))
1092 return dm_gpio_get_value(&priv->cd_gpio);
1096 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
1102 static int esdhc_reset(struct fsl_esdhc *regs)
1106 /* reset the controller */
1107 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
1109 /* hardware clears the bit when it is done */
1110 start = get_timer(0);
1111 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
1112 if (get_timer(start) > 100) {
1113 printf("MMC/SD: Reset never completed.\n");
1121 #if !CONFIG_IS_ENABLED(DM_MMC)
1122 static int esdhc_getcd(struct mmc *mmc)
1124 struct fsl_esdhc_priv *priv = mmc->priv;
1126 return esdhc_getcd_common(priv);
1129 static int esdhc_init(struct mmc *mmc)
1131 struct fsl_esdhc_priv *priv = mmc->priv;
1133 return esdhc_init_common(priv, mmc);
1136 static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
1137 struct mmc_data *data)
1139 struct fsl_esdhc_priv *priv = mmc->priv;
1141 return esdhc_send_cmd_common(priv, mmc, cmd, data);
1144 static int esdhc_set_ios(struct mmc *mmc)
1146 struct fsl_esdhc_priv *priv = mmc->priv;
1148 return esdhc_set_ios_common(priv, mmc);
1151 static const struct mmc_ops esdhc_ops = {
1152 .getcd = esdhc_getcd,
1154 .send_cmd = esdhc_send_cmd,
1155 .set_ios = esdhc_set_ios,
1159 static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
1160 struct fsl_esdhc_plat *plat)
1162 struct mmc_config *cfg;
1163 struct fsl_esdhc *regs;
1164 u32 caps, voltage_caps;
1170 regs = priv->esdhc_regs;
1172 /* First reset the eSDHC controller */
1173 ret = esdhc_reset(regs);
1177 #ifdef CONFIG_MCF5441x
1178 /* ColdFire, using SDHC_DATA[3] for card detection */
1179 esdhc_write32(®s->proctl, PROCTL_INIT | PROCTL_D3CD);
1182 #ifndef CONFIG_FSL_USDHC
1183 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
1184 | SYSCTL_IPGEN | SYSCTL_CKEN);
1185 /* Clearing tuning bits in case ROM has set it already */
1186 esdhc_write32(®s->mixctrl, 0);
1187 esdhc_write32(®s->autoc12err, 0);
1188 esdhc_write32(®s->clktunectrlstatus, 0);
1190 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
1191 VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
1194 if (priv->vs18_enable)
1195 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
1197 writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
1199 #ifndef CONFIG_DM_MMC
1200 memset(cfg, '\0', sizeof(*cfg));
1204 caps = esdhc_read32(®s->hostcapblt);
1206 #ifdef CONFIG_MCF5441x
1208 * MCF5441x RM declares in more points that sdhc clock speed must
1209 * never exceed 25 Mhz. From this, the HS bit needs to be disabled
1210 * from host capabilities.
1212 caps &= ~ESDHC_HOSTCAPBLT_HSS;
1215 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
1216 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
1217 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
1220 /* T4240 host controller capabilities register should have VS33 bit */
1221 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
1222 caps = caps | ESDHC_HOSTCAPBLT_VS33;
1225 if (caps & ESDHC_HOSTCAPBLT_VS18)
1226 voltage_caps |= MMC_VDD_165_195;
1227 if (caps & ESDHC_HOSTCAPBLT_VS30)
1228 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
1229 if (caps & ESDHC_HOSTCAPBLT_VS33)
1230 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
1232 cfg->name = "FSL_SDHC";
1233 #if !CONFIG_IS_ENABLED(DM_MMC)
1234 cfg->ops = &esdhc_ops;
1236 #ifdef CONFIG_SYS_SD_VOLTAGE
1237 cfg->voltages = CONFIG_SYS_SD_VOLTAGE;
1239 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
1241 if ((cfg->voltages & voltage_caps) == 0) {
1242 printf("voltage not supported by controller\n");
1246 if (priv->bus_width == 8)
1247 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
1248 else if (priv->bus_width == 4)
1249 cfg->host_caps = MMC_MODE_4BIT;
1251 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
1252 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
1253 cfg->host_caps |= MMC_MODE_DDR_52MHz;
1256 if (priv->bus_width > 0) {
1257 if (priv->bus_width < 8)
1258 cfg->host_caps &= ~MMC_MODE_8BIT;
1259 if (priv->bus_width < 4)
1260 cfg->host_caps &= ~MMC_MODE_4BIT;
1263 if (caps & ESDHC_HOSTCAPBLT_HSS)
1264 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1266 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
1267 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
1268 cfg->host_caps &= ~MMC_MODE_8BIT;
1271 cfg->host_caps |= priv->caps;
1273 cfg->f_min = 400000;
1274 cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
1276 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1278 writel(0, ®s->dllctrl);
1279 if (priv->flags & ESDHC_FLAG_USDHC) {
1280 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
1281 u32 val = readl(®s->tuning_ctrl);
1283 val |= ESDHC_STD_TUNING_EN;
1284 val &= ~ESDHC_TUNING_START_TAP_MASK;
1285 val |= priv->tuning_start_tap;
1286 val &= ~ESDHC_TUNING_STEP_MASK;
1287 val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT;
1288 writel(val, ®s->tuning_ctrl);
1295 #if !CONFIG_IS_ENABLED(DM_MMC)
1296 static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
1297 struct fsl_esdhc_priv *priv)
1302 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
1303 priv->bus_width = cfg->max_bus_width;
1304 priv->sdhc_clk = cfg->sdhc_clk;
1305 priv->wp_enable = cfg->wp_enable;
1306 priv->vs18_enable = cfg->vs18_enable;
1311 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
1313 struct fsl_esdhc_plat *plat;
1314 struct fsl_esdhc_priv *priv;
1321 priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
1324 plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
1330 ret = fsl_esdhc_cfg_to_priv(cfg, priv);
1332 debug("%s xlate failure\n", __func__);
1338 ret = fsl_esdhc_init(priv, plat);
1340 debug("%s init failure\n", __func__);
1346 mmc = mmc_create(&plat->cfg, priv);
1355 int fsl_esdhc_mmc_init(bd_t *bis)
1357 struct fsl_esdhc_cfg *cfg;
1359 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
1360 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
1361 cfg->sdhc_clk = gd->arch.sdhc_clk;
1362 return fsl_esdhc_initialize(bis, cfg);
1366 #ifdef CONFIG_OF_LIBFDT
1367 __weak int esdhc_status_fixup(void *blob, const char *compat)
1369 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
1370 if (!hwconfig("esdhc")) {
1371 do_fixup_by_compat(blob, compat, "status", "disabled",
1372 sizeof("disabled"), 1);
1379 void fdt_fixup_esdhc(void *blob, bd_t *bd)
1381 const char *compat = "fsl,esdhc";
1383 if (esdhc_status_fixup(blob, compat))
1386 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
1387 do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
1388 gd->arch.sdhc_clk, 1);
1390 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
1391 gd->arch.sdhc_clk, 1);
1396 #if CONFIG_IS_ENABLED(DM_MMC)
1397 #include <asm/arch/clock.h>
1398 __weak void init_clk_usdhc(u32 index)
1402 static int fsl_esdhc_probe(struct udevice *dev)
1404 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1405 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1406 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1407 const void *fdt = gd->fdt_blob;
1408 int node = dev_of_offset(dev);
1409 struct esdhc_soc_data *data =
1410 (struct esdhc_soc_data *)dev_get_driver_data(dev);
1411 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1412 struct udevice *vqmmc_dev;
1417 #if !CONFIG_IS_ENABLED(BLK)
1418 struct blk_desc *bdesc;
1422 addr = dev_read_addr(dev);
1423 if (addr == FDT_ADDR_T_NONE)
1425 priv->esdhc_regs = (struct fsl_esdhc *)addr;
1429 priv->flags = data->flags;
1431 val = dev_read_u32_default(dev, "bus-width", -1);
1433 priv->bus_width = 8;
1435 priv->bus_width = 4;
1437 priv->bus_width = 1;
1439 val = fdtdec_get_int(fdt, node, "fsl,tuning-step", 1);
1440 priv->tuning_step = val;
1441 val = fdtdec_get_int(fdt, node, "fsl,tuning-start-tap",
1442 ESDHC_TUNING_START_TAP_DEFAULT);
1443 priv->tuning_start_tap = val;
1444 val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target",
1445 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT);
1446 priv->strobe_dll_delay_target = val;
1448 if (dev_read_bool(dev, "non-removable")) {
1449 priv->non_removable = 1;
1451 priv->non_removable = 0;
1452 #ifdef CONFIG_DM_GPIO
1453 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
1458 if (dev_read_prop(dev, "fsl,wp-controller", NULL)) {
1459 priv->wp_enable = 1;
1461 priv->wp_enable = 0;
1462 #ifdef CONFIG_DM_GPIO
1463 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
1468 priv->vs18_enable = 0;
1470 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1472 * If emmc I/O has a fixed voltage at 1.8V, this must be provided,
1473 * otherwise, emmc will work abnormally.
1475 ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
1477 dev_dbg(dev, "no vqmmc-supply\n");
1479 ret = regulator_set_enable(vqmmc_dev, true);
1481 dev_err(dev, "fail to enable vqmmc-supply\n");
1485 if (regulator_get_value(vqmmc_dev) == 1800000)
1486 priv->vs18_enable = 1;
1492 * Because lack of clk driver, if SDHC clk is not enabled,
1493 * need to enable it first before this driver is invoked.
1495 * we use MXC_ESDHC_CLK to get clk freq.
1496 * If one would like to make this function work,
1497 * the aliases should be provided in dts as this:
1505 * Then if your board only supports mmc2 and mmc3, but we can
1506 * correctly get the seq as 2 and 3, then let mxc_get_clock
1510 init_clk_usdhc(dev->seq);
1512 if (CONFIG_IS_ENABLED(CLK)) {
1513 /* Assigned clock already set clock */
1514 ret = clk_get_by_name(dev, "per", &priv->per_clk);
1516 printf("Failed to get per_clk\n");
1519 ret = clk_enable(&priv->per_clk);
1521 printf("Failed to enable per_clk\n");
1525 priv->sdhc_clk = clk_get_rate(&priv->per_clk);
1527 priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
1528 if (priv->sdhc_clk <= 0) {
1529 dev_err(dev, "Unable to get clk for %s\n", dev->name);
1534 ret = fsl_esdhc_init(priv, plat);
1536 dev_err(dev, "fsl_esdhc_init failure\n");
1540 ret = mmc_of_parse(dev, &plat->cfg);
1545 mmc->cfg = &plat->cfg;
1547 #if !CONFIG_IS_ENABLED(BLK)
1550 /* Setup dsr related values */
1552 mmc->dsr = ESDHC_DRIVER_STAGE_VALUE;
1553 /* Setup the universal parts of the block interface just once */
1554 bdesc = mmc_get_blk_desc(mmc);
1555 bdesc->if_type = IF_TYPE_MMC;
1556 bdesc->removable = 1;
1557 bdesc->devnum = mmc_get_next_devnum();
1558 bdesc->block_read = mmc_bread;
1559 bdesc->block_write = mmc_bwrite;
1560 bdesc->block_erase = mmc_berase;
1562 /* setup initial part type */
1563 bdesc->part_type = mmc->cfg->part_type;
1569 return esdhc_init_common(priv, mmc);
1572 #if CONFIG_IS_ENABLED(DM_MMC)
1573 static int fsl_esdhc_get_cd(struct udevice *dev)
1575 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1577 return esdhc_getcd_common(priv);
1580 static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1581 struct mmc_data *data)
1583 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1584 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1586 return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
1589 static int fsl_esdhc_set_ios(struct udevice *dev)
1591 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1592 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1594 return esdhc_set_ios_common(priv, &plat->mmc);
1597 static const struct dm_mmc_ops fsl_esdhc_ops = {
1598 .get_cd = fsl_esdhc_get_cd,
1599 .send_cmd = fsl_esdhc_send_cmd,
1600 .set_ios = fsl_esdhc_set_ios,
1601 #ifdef MMC_SUPPORTS_TUNING
1602 .execute_tuning = fsl_esdhc_execute_tuning,
1607 static struct esdhc_soc_data usdhc_imx7d_data = {
1608 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
1609 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
1613 static const struct udevice_id fsl_esdhc_ids[] = {
1614 { .compatible = "fsl,imx53-esdhc", },
1615 { .compatible = "fsl,imx6ul-usdhc", },
1616 { .compatible = "fsl,imx6sx-usdhc", },
1617 { .compatible = "fsl,imx6sl-usdhc", },
1618 { .compatible = "fsl,imx6q-usdhc", },
1619 { .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,},
1620 { .compatible = "fsl,imx7ulp-usdhc", },
1621 { .compatible = "fsl,esdhc", },
1625 #if CONFIG_IS_ENABLED(BLK)
1626 static int fsl_esdhc_bind(struct udevice *dev)
1628 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1630 return mmc_bind(dev, &plat->mmc, &plat->cfg);
1634 U_BOOT_DRIVER(fsl_esdhc) = {
1635 .name = "fsl-esdhc-mmc",
1637 .of_match = fsl_esdhc_ids,
1638 .ops = &fsl_esdhc_ops,
1639 #if CONFIG_IS_ENABLED(BLK)
1640 .bind = fsl_esdhc_bind,
1642 .probe = fsl_esdhc_probe,
1643 .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
1644 .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),