1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
4 * Copyright 2019 NXP Semiconductors
6 * Yangbo Lu <yangbo.lu@nxp.com>
8 * Based vaguely on the pxa mmc code:
10 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
23 #include <asm/cache.h>
24 #include <dm/device_compat.h>
25 #include <linux/bitops.h>
26 #include <linux/delay.h>
27 #include <linux/err.h>
28 #include <power/regulator.h>
30 #include <fsl_esdhc_imx.h>
31 #include <fdt_support.h>
34 #include <asm-generic/gpio.h>
35 #include <dm/pinctrl.h>
36 #include <dt-structs.h>
38 #include <dm/ofnode.h>
39 #include <linux/iopoll.h>
41 #if !CONFIG_IS_ENABLED(BLK)
42 #include "mmc_private.h"
45 DECLARE_GLOBAL_DATA_PTR;
47 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
49 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
50 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
51 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
53 #define MAX_TUNING_LOOP 40
54 #define ESDHC_DRIVER_STAGE_VALUE 0xffffffff
57 uint dsaddr; /* SDMA system address register */
58 uint blkattr; /* Block attributes register */
59 uint cmdarg; /* Command argument register */
60 uint xfertyp; /* Transfer type register */
61 uint cmdrsp0; /* Command response 0 register */
62 uint cmdrsp1; /* Command response 1 register */
63 uint cmdrsp2; /* Command response 2 register */
64 uint cmdrsp3; /* Command response 3 register */
65 uint datport; /* Buffer data port register */
66 uint prsstat; /* Present state register */
67 uint proctl; /* Protocol control register */
68 uint sysctl; /* System Control Register */
69 uint irqstat; /* Interrupt status register */
70 uint irqstaten; /* Interrupt status enable register */
71 uint irqsigen; /* Interrupt signal enable register */
72 uint autoc12err; /* Auto CMD error status register */
73 uint hostcapblt; /* Host controller capabilities register */
74 uint wml; /* Watermark level register */
75 uint mixctrl; /* For USDHC */
76 char reserved1[4]; /* reserved */
77 uint fevt; /* Force event register */
78 uint admaes; /* ADMA error status register */
79 uint adsaddr; /* ADMA system address register */
83 uint clktunectrlstatus;
91 uint tuning_ctrl; /* on i.MX6/7/8/RT */
93 uint hostver; /* Host controller version register */
94 char reserved6[4]; /* reserved */
95 uint dmaerraddr; /* DMA error address register */
96 char reserved7[4]; /* reserved */
97 uint dmaerrattr; /* DMA error attribute register */
98 char reserved8[4]; /* reserved */
99 uint hostcapblt2; /* Host controller capabilities register 2 */
100 char reserved9[8]; /* reserved */
101 uint tcr; /* Tuning control register */
102 char reserved10[28]; /* reserved */
103 uint sddirctl; /* SD direction control register */
104 char reserved11[712];/* reserved */
105 uint scr; /* eSDHC control register */
108 struct fsl_esdhc_plat {
109 #if CONFIG_IS_ENABLED(OF_PLATDATA)
110 /* Put this first since driver model will copy the data here */
111 struct dtd_fsl_esdhc dtplat;
114 struct mmc_config cfg;
118 struct esdhc_soc_data {
123 * struct fsl_esdhc_priv
125 * @esdhc_regs: registers of the sdhc controller
126 * @sdhc_clk: Current clk of the sdhc controller
127 * @bus_width: bus width, 1bit, 4bit or 8bit
130 * Following is used when Driver Model is enabled for MMC
131 * @dev: pointer for the device
132 * @non_removable: 0: removable; 1: non-removable
133 * @broken_cd: 0: use GPIO for card detect; 1: Do not use GPIO for card detect
134 * @wp_enable: 1: enable checking wp; 0: no check
135 * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
136 * @flags: ESDHC_FLAG_xx in include/fsl_esdhc_imx.h
137 * @caps: controller capabilities
138 * @tuning_step: tuning step setting in tuning_ctrl register
139 * @start_tuning_tap: the start point for tuning in tuning_ctrl register
140 * @strobe_dll_delay_target: settings in strobe_dllctrl
141 * @signal_voltage: indicating the current voltage
142 * @cd_gpio: gpio for card detection
143 * @wp_gpio: gpio for write protection
145 struct fsl_esdhc_priv {
146 struct fsl_esdhc *esdhc_regs;
147 unsigned int sdhc_clk;
151 unsigned int bus_width;
152 #if !CONFIG_IS_ENABLED(BLK)
163 u32 tuning_start_tap;
164 u32 strobe_dll_delay_target;
166 #if CONFIG_IS_ENABLED(DM_REGULATOR)
167 struct udevice *vqmmc_dev;
168 struct udevice *vmmc_dev;
170 #if CONFIG_IS_ENABLED(DM_GPIO)
171 struct gpio_desc cd_gpio;
172 struct gpio_desc wp_gpio;
176 /* Return the XFERTYP flags for a given command and data packet */
177 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
182 xfertyp |= XFERTYP_DPSEL;
183 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
184 xfertyp |= XFERTYP_DMAEN;
186 if (data->blocks > 1) {
187 xfertyp |= XFERTYP_MSBSEL;
188 xfertyp |= XFERTYP_BCEN;
189 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
190 xfertyp |= XFERTYP_AC12EN;
194 if (data->flags & MMC_DATA_READ)
195 xfertyp |= XFERTYP_DTDSEL;
198 if (cmd->resp_type & MMC_RSP_CRC)
199 xfertyp |= XFERTYP_CCCEN;
200 if (cmd->resp_type & MMC_RSP_OPCODE)
201 xfertyp |= XFERTYP_CICEN;
202 if (cmd->resp_type & MMC_RSP_136)
203 xfertyp |= XFERTYP_RSPTYP_136;
204 else if (cmd->resp_type & MMC_RSP_BUSY)
205 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
206 else if (cmd->resp_type & MMC_RSP_PRESENT)
207 xfertyp |= XFERTYP_RSPTYP_48;
209 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
210 xfertyp |= XFERTYP_CMDTYP_ABORT;
212 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
215 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
217 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
219 static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
220 struct mmc_data *data)
222 struct fsl_esdhc *regs = priv->esdhc_regs;
230 if (data->flags & MMC_DATA_READ) {
231 blocks = data->blocks;
234 start = get_timer(0);
235 size = data->blocksize;
236 irqstat = esdhc_read32(®s->irqstat);
237 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)) {
238 if (get_timer(start) > PIO_TIMEOUT) {
239 printf("\nData Read Failed in PIO Mode.");
243 while (size && (!(irqstat & IRQSTAT_TC))) {
244 udelay(100); /* Wait before last byte transfer complete */
245 irqstat = esdhc_read32(®s->irqstat);
246 databuf = in_le32(®s->datport);
247 *((uint *)buffer) = databuf;
254 blocks = data->blocks;
255 buffer = (char *)data->src;
257 start = get_timer(0);
258 size = data->blocksize;
259 irqstat = esdhc_read32(®s->irqstat);
260 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)) {
261 if (get_timer(start) > PIO_TIMEOUT) {
262 printf("\nData Write Failed in PIO Mode.");
266 while (size && (!(irqstat & IRQSTAT_TC))) {
267 udelay(100); /* Wait before last byte transfer complete */
268 databuf = *((uint *)buffer);
271 irqstat = esdhc_read32(®s->irqstat);
272 out_le32(®s->datport, databuf);
280 static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
281 struct mmc_data *data)
284 struct fsl_esdhc *regs = priv->esdhc_regs;
285 #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
290 wml_value = data->blocksize/4;
292 if (data->flags & MMC_DATA_READ) {
293 if (wml_value > WML_RD_WML_MAX)
294 wml_value = WML_RD_WML_MAX_VAL;
296 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
297 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
298 #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
299 addr = virt_to_phys((void *)(data->dest));
300 if (upper_32_bits(addr))
301 printf("Error found for upper 32 bits\n");
303 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
305 esdhc_write32(®s->dsaddr, (u32)data->dest);
309 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
310 flush_dcache_range((ulong)data->src,
311 (ulong)data->src+data->blocks
314 if (wml_value > WML_WR_WML_MAX)
315 wml_value = WML_WR_WML_MAX_VAL;
316 if (priv->wp_enable) {
317 if ((esdhc_read32(®s->prsstat) &
318 PRSSTAT_WPSPL) == 0) {
319 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
323 #if CONFIG_IS_ENABLED(DM_GPIO)
324 if (dm_gpio_is_valid(&priv->wp_gpio) &&
325 dm_gpio_get_value(&priv->wp_gpio)) {
326 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
332 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
334 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
335 #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
336 addr = virt_to_phys((void *)(data->src));
337 if (upper_32_bits(addr))
338 printf("Error found for upper 32 bits\n");
340 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
342 esdhc_write32(®s->dsaddr, (u32)data->src);
347 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
349 /* Calculate the timeout period for data transactions */
351 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
352 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
353 * So, Number of SD Clock cycles for 0.25sec should be minimum
354 * (SD Clock/sec * 0.25 sec) SD Clock cycles
355 * = (mmc->clock * 1/4) SD Clock cycles
357 * => (2^(timeout+13)) >= mmc->clock * 1/4
358 * Taking log2 both the sides
359 * => timeout + 13 >= log2(mmc->clock/4)
360 * Rounding up to next power of 2
361 * => timeout + 13 = log2(mmc->clock/4) + 1
362 * => timeout + 13 = fls(mmc->clock/4)
364 * However, the MMC spec "It is strongly recommended for hosts to
365 * implement more than 500ms timeout value even if the card
366 * indicates the 250ms maximum busy length." Even the previous
367 * value of 300ms is known to be insufficient for some cards.
369 * => timeout + 13 = fls(mmc->clock/2)
371 timeout = fls(mmc->clock/2);
380 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
381 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
385 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
388 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
393 static void check_and_invalidate_dcache_range
394 (struct mmc_cmd *cmd,
395 struct mmc_data *data) {
398 unsigned size = roundup(ARCH_DMA_MINALIGN,
399 data->blocks*data->blocksize);
400 #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
403 addr = virt_to_phys((void *)(data->dest));
404 if (upper_32_bits(addr))
405 printf("Error found for upper 32 bits\n");
407 start = lower_32_bits(addr);
409 start = (unsigned)data->dest;
412 invalidate_dcache_range(start, end);
415 #ifdef CONFIG_MCF5441x
417 * Swaps 32-bit words to little-endian byte order.
419 static inline void sd_swap_dma_buff(struct mmc_data *data)
421 int i, size = data->blocksize >> 2;
422 u32 *buffer = (u32 *)data->dest;
425 while (data->blocks--) {
426 for (i = 0; i < size; i++) {
427 sw = __sw32(*buffer);
435 * Sends a command out on the bus. Takes the mmc pointer,
436 * a command pointer, and an optional data pointer.
438 static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
439 struct mmc_cmd *cmd, struct mmc_data *data)
444 u32 flags = IRQSTAT_CC | IRQSTAT_CTOE;
445 struct fsl_esdhc *regs = priv->esdhc_regs;
448 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
449 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
453 esdhc_write32(®s->irqstat, -1);
457 /* Wait for the bus to be idle */
458 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
459 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
462 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
465 /* Set up for a data transfer if we have one */
467 err = esdhc_setup_data(priv, mmc, data);
471 if (data->flags & MMC_DATA_READ)
472 check_and_invalidate_dcache_range(cmd, data);
475 /* Figure out the transfer arguments */
476 xfertyp = esdhc_xfertyp(cmd, data);
479 esdhc_write32(®s->irqsigen, 0);
481 /* Send the command */
482 esdhc_write32(®s->cmdarg, cmd->cmdarg);
483 #if defined(CONFIG_FSL_USDHC)
484 esdhc_write32(®s->mixctrl,
485 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
486 | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
487 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000);
489 esdhc_write32(®s->xfertyp, xfertyp);
492 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
493 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))
496 /* Wait for the command to complete */
497 start = get_timer(0);
498 while (!(esdhc_read32(®s->irqstat) & flags)) {
499 if (get_timer(start) > 1000) {
505 irqstat = esdhc_read32(®s->irqstat);
507 if (irqstat & CMD_ERR) {
512 if (irqstat & IRQSTAT_CTOE) {
517 /* Switch voltage to 1.8V if CMD11 succeeded */
518 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
519 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
521 printf("Run CMD11 1.8V switch\n");
522 /* Sleep for 5 ms - max time for card to switch to 1.8V */
526 /* Workaround for ESDHC errata ENGcm03648 */
527 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
530 /* Poll on DATA0 line for cmd with busy signal for 5000 ms */
531 while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
538 printf("Timeout waiting for DAT0 to go high!\n");
544 /* Copy the response to the response buffer */
545 if (cmd->resp_type & MMC_RSP_136) {
546 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
548 cmdrsp3 = esdhc_read32(®s->cmdrsp3);
549 cmdrsp2 = esdhc_read32(®s->cmdrsp2);
550 cmdrsp1 = esdhc_read32(®s->cmdrsp1);
551 cmdrsp0 = esdhc_read32(®s->cmdrsp0);
552 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
553 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
554 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
555 cmd->response[3] = (cmdrsp0 << 8);
557 cmd->response[0] = esdhc_read32(®s->cmdrsp0);
559 /* Wait until all of the blocks are transferred */
561 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
562 esdhc_pio_read_write(priv, data);
564 flags = DATA_COMPLETE;
565 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
566 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) {
571 irqstat = esdhc_read32(®s->irqstat);
573 if (irqstat & IRQSTAT_DTOE) {
578 if (irqstat & DATA_ERR) {
582 } while ((irqstat & flags) != flags);
585 * Need invalidate the dcache here again to avoid any
586 * cache-fill during the DMA operations such as the
587 * speculative pre-fetching etc.
589 if (data->flags & MMC_DATA_READ) {
590 check_and_invalidate_dcache_range(cmd, data);
591 #ifdef CONFIG_MCF5441x
592 sd_swap_dma_buff(data);
599 /* Reset CMD and DATA portions on error */
601 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
603 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC)
607 esdhc_write32(®s->sysctl,
608 esdhc_read32(®s->sysctl) |
610 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
614 /* If this was CMD11, then notify that power cycle is needed */
615 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
616 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
619 esdhc_write32(®s->irqstat, -1);
624 static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
626 struct fsl_esdhc *regs = priv->esdhc_regs;
632 /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
633 int pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1;
640 int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
641 int sdhc_clk = priv->sdhc_clk;
644 while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
647 while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
653 clk = (pre_div << 8) | (div << 4);
655 #ifdef CONFIG_FSL_USDHC
656 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
658 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
661 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
663 ret = readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp, tmp & PRSSTAT_SDSTB, 100);
665 pr_warn("fsl_esdhc_imx: Internal clock never stabilised.\n");
667 #ifdef CONFIG_FSL_USDHC
668 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
670 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
676 #ifdef MMC_SUPPORTS_TUNING
677 static int esdhc_change_pinstate(struct udevice *dev)
679 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
682 switch (priv->mode) {
685 ret = pinctrl_select_state(dev, "state_100mhz");
691 ret = pinctrl_select_state(dev, "state_200mhz");
694 ret = pinctrl_select_state(dev, "default");
699 printf("%s %d error\n", __func__, priv->mode);
704 static void esdhc_reset_tuning(struct mmc *mmc)
706 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
707 struct fsl_esdhc *regs = priv->esdhc_regs;
709 if (priv->flags & ESDHC_FLAG_USDHC) {
710 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
711 esdhc_clrbits32(®s->autoc12err,
712 MIX_CTRL_SMPCLK_SEL |
718 static void esdhc_set_strobe_dll(struct mmc *mmc)
720 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
721 struct fsl_esdhc *regs = priv->esdhc_regs;
724 if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
725 esdhc_write32(®s->strobe_dllctrl, ESDHC_STROBE_DLL_CTRL_RESET);
728 * enable strobe dll ctrl and adjust the delay target
729 * for the uSDHC loopback read clock
731 val = ESDHC_STROBE_DLL_CTRL_ENABLE |
732 (priv->strobe_dll_delay_target <<
733 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
734 esdhc_write32(®s->strobe_dllctrl, val);
735 /* wait 1us to make sure strobe dll status register stable */
737 val = esdhc_read32(®s->strobe_dllstat);
738 if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK))
739 pr_warn("HS400 strobe DLL status REF not lock!\n");
740 if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK))
741 pr_warn("HS400 strobe DLL status SLV not lock!\n");
745 static int esdhc_set_timing(struct mmc *mmc)
747 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
748 struct fsl_esdhc *regs = priv->esdhc_regs;
751 mixctrl = esdhc_read32(®s->mixctrl);
752 mixctrl &= ~(MIX_CTRL_DDREN | MIX_CTRL_HS400_EN);
754 switch (mmc->selected_mode) {
756 esdhc_reset_tuning(mmc);
757 esdhc_write32(®s->mixctrl, mixctrl);
761 mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN;
762 esdhc_write32(®s->mixctrl, mixctrl);
763 esdhc_set_strobe_dll(mmc);
773 esdhc_write32(®s->mixctrl, mixctrl);
777 mixctrl |= MIX_CTRL_DDREN;
778 esdhc_write32(®s->mixctrl, mixctrl);
781 printf("Not supported %d\n", mmc->selected_mode);
785 priv->mode = mmc->selected_mode;
787 return esdhc_change_pinstate(mmc->dev);
790 static int esdhc_set_voltage(struct mmc *mmc)
792 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
793 struct fsl_esdhc *regs = priv->esdhc_regs;
796 priv->signal_voltage = mmc->signal_voltage;
797 switch (mmc->signal_voltage) {
798 case MMC_SIGNAL_VOLTAGE_330:
799 if (priv->vs18_enable)
801 #if CONFIG_IS_ENABLED(DM_REGULATOR)
802 if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
803 ret = regulator_set_value(priv->vqmmc_dev, 3300000);
805 printf("Setting to 3.3V error");
813 esdhc_clrbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
814 if (!(esdhc_read32(®s->vendorspec) &
815 ESDHC_VENDORSPEC_VSELECT))
819 case MMC_SIGNAL_VOLTAGE_180:
820 #if CONFIG_IS_ENABLED(DM_REGULATOR)
821 if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
822 ret = regulator_set_value(priv->vqmmc_dev, 1800000);
824 printf("Setting to 1.8V error");
829 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
830 if (esdhc_read32(®s->vendorspec) & ESDHC_VENDORSPEC_VSELECT)
834 case MMC_SIGNAL_VOLTAGE_120:
841 static void esdhc_stop_tuning(struct mmc *mmc)
845 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
847 cmd.resp_type = MMC_RSP_R1b;
849 dm_mmc_send_cmd(mmc->dev, &cmd, NULL);
852 static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
854 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
855 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
856 struct fsl_esdhc *regs = priv->esdhc_regs;
857 struct mmc *mmc = &plat->mmc;
858 u32 irqstaten = esdhc_read32(®s->irqstaten);
859 u32 irqsigen = esdhc_read32(®s->irqsigen);
860 int i, ret = -ETIMEDOUT;
863 /* clock tuning is not needed for upto 52MHz */
864 if (mmc->clock <= 52000000)
867 /* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */
868 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
869 val = esdhc_read32(®s->autoc12err);
870 mixctrl = esdhc_read32(®s->mixctrl);
871 val &= ~MIX_CTRL_SMPCLK_SEL;
872 mixctrl &= ~(MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN);
874 val |= MIX_CTRL_EXE_TUNE;
875 mixctrl |= MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN;
877 esdhc_write32(®s->autoc12err, val);
878 esdhc_write32(®s->mixctrl, mixctrl);
881 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); */
882 mixctrl = esdhc_read32(®s->mixctrl);
883 mixctrl = MIX_CTRL_DTDSEL_READ | (mixctrl & ~MIX_CTRL_SDHCI_MASK);
884 esdhc_write32(®s->mixctrl, mixctrl);
886 esdhc_write32(®s->irqstaten, IRQSTATEN_BRR);
887 esdhc_write32(®s->irqsigen, IRQSTATEN_BRR);
890 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
891 * of loops reaches 40 times.
893 for (i = 0; i < MAX_TUNING_LOOP; i++) {
896 if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) {
897 if (mmc->bus_width == 8)
898 esdhc_write32(®s->blkattr, 0x7080);
899 else if (mmc->bus_width == 4)
900 esdhc_write32(®s->blkattr, 0x7040);
902 esdhc_write32(®s->blkattr, 0x7040);
905 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE) */
906 val = esdhc_read32(®s->mixctrl);
907 val = MIX_CTRL_DTDSEL_READ | (val & ~MIX_CTRL_SDHCI_MASK);
908 esdhc_write32(®s->mixctrl, val);
910 /* We are using STD tuning, no need to check return value */
911 mmc_send_tuning(mmc, opcode, NULL);
913 ctrl = esdhc_read32(®s->autoc12err);
914 if ((!(ctrl & MIX_CTRL_EXE_TUNE)) &&
915 (ctrl & MIX_CTRL_SMPCLK_SEL)) {
921 esdhc_write32(®s->irqstaten, irqstaten);
922 esdhc_write32(®s->irqsigen, irqsigen);
924 esdhc_stop_tuning(mmc);
930 static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
932 struct fsl_esdhc *regs = priv->esdhc_regs;
933 int ret __maybe_unused;
936 /* Set the clock speed */
938 if (clock < mmc->cfg->f_min)
939 clock = mmc->cfg->f_min;
941 if (priv->clock != clock)
942 set_sysctl(priv, mmc, clock);
944 #ifdef MMC_SUPPORTS_TUNING
945 if (mmc->clk_disable) {
946 #ifdef CONFIG_FSL_USDHC
947 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
949 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
952 #ifdef CONFIG_FSL_USDHC
953 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
956 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
960 if (priv->mode != mmc->selected_mode) {
961 ret = esdhc_set_timing(mmc);
963 printf("esdhc_set_timing error %d\n", ret);
968 if (priv->signal_voltage != mmc->signal_voltage) {
969 ret = esdhc_set_voltage(mmc);
971 if (ret != -ENOTSUPP)
972 printf("esdhc_set_voltage error %d\n", ret);
978 /* Set the bus width */
979 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
981 if (mmc->bus_width == 4)
982 esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
983 else if (mmc->bus_width == 8)
984 esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
989 static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
991 struct fsl_esdhc *regs = priv->esdhc_regs;
994 /* Reset the entire host controller */
995 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
997 /* Wait until the controller is available */
998 start = get_timer(0);
999 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
1000 if (get_timer(start) > 1000)
1004 #if defined(CONFIG_FSL_USDHC)
1005 /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
1006 esdhc_write32(®s->mmcboot, 0x0);
1007 /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
1008 esdhc_write32(®s->mixctrl, 0x0);
1009 esdhc_write32(®s->clktunectrlstatus, 0x0);
1011 /* Put VEND_SPEC to default value */
1012 if (priv->vs18_enable)
1013 esdhc_write32(®s->vendorspec, (VENDORSPEC_INIT |
1014 ESDHC_VENDORSPEC_VSELECT));
1016 esdhc_write32(®s->vendorspec, VENDORSPEC_INIT);
1018 /* Disable DLL_CTRL delay line */
1019 esdhc_write32(®s->dllctrl, 0x0);
1023 /* Enable cache snooping */
1024 esdhc_write32(®s->scr, 0x00000040);
1027 #ifndef CONFIG_FSL_USDHC
1028 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
1030 esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
1033 /* Set the initial clock speed */
1034 mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
1036 /* Disable the BRR and BWR bits in IRQSTAT */
1037 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
1039 #ifdef CONFIG_MCF5441x
1040 esdhc_write32(®s->proctl, PROCTL_INIT | PROCTL_D3CD);
1042 /* Put the PROCTL reg back to the default */
1043 esdhc_write32(®s->proctl, PROCTL_INIT);
1046 /* Set timout to the maximum value */
1047 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
1052 static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
1054 struct fsl_esdhc *regs = priv->esdhc_regs;
1057 #ifdef CONFIG_ESDHC_DETECT_QUIRK
1058 if (CONFIG_ESDHC_DETECT_QUIRK)
1062 #if CONFIG_IS_ENABLED(DM_MMC)
1063 if (priv->non_removable)
1066 if (priv->broken_cd)
1068 #if CONFIG_IS_ENABLED(DM_GPIO)
1069 if (dm_gpio_is_valid(&priv->cd_gpio))
1070 return dm_gpio_get_value(&priv->cd_gpio);
1074 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
1080 static int esdhc_reset(struct fsl_esdhc *regs)
1084 /* reset the controller */
1085 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
1087 /* hardware clears the bit when it is done */
1088 start = get_timer(0);
1089 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
1090 if (get_timer(start) > 100) {
1091 printf("MMC/SD: Reset never completed.\n");
1099 #if !CONFIG_IS_ENABLED(DM_MMC)
1100 static int esdhc_getcd(struct mmc *mmc)
1102 struct fsl_esdhc_priv *priv = mmc->priv;
1104 return esdhc_getcd_common(priv);
1107 static int esdhc_init(struct mmc *mmc)
1109 struct fsl_esdhc_priv *priv = mmc->priv;
1111 return esdhc_init_common(priv, mmc);
1114 static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
1115 struct mmc_data *data)
1117 struct fsl_esdhc_priv *priv = mmc->priv;
1119 return esdhc_send_cmd_common(priv, mmc, cmd, data);
1122 static int esdhc_set_ios(struct mmc *mmc)
1124 struct fsl_esdhc_priv *priv = mmc->priv;
1126 return esdhc_set_ios_common(priv, mmc);
1129 static const struct mmc_ops esdhc_ops = {
1130 .getcd = esdhc_getcd,
1132 .send_cmd = esdhc_send_cmd,
1133 .set_ios = esdhc_set_ios,
1137 static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
1138 struct fsl_esdhc_plat *plat)
1140 struct mmc_config *cfg;
1141 struct fsl_esdhc *regs;
1142 u32 caps, voltage_caps;
1148 regs = priv->esdhc_regs;
1150 /* First reset the eSDHC controller */
1151 ret = esdhc_reset(regs);
1155 #ifdef CONFIG_MCF5441x
1156 /* ColdFire, using SDHC_DATA[3] for card detection */
1157 esdhc_write32(®s->proctl, PROCTL_INIT | PROCTL_D3CD);
1160 #ifndef CONFIG_FSL_USDHC
1161 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
1162 | SYSCTL_IPGEN | SYSCTL_CKEN);
1163 /* Clearing tuning bits in case ROM has set it already */
1164 esdhc_write32(®s->mixctrl, 0);
1165 esdhc_write32(®s->autoc12err, 0);
1166 esdhc_write32(®s->clktunectrlstatus, 0);
1168 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
1169 VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
1172 if (priv->vs18_enable)
1173 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
1175 esdhc_write32(®s->irqstaten, SDHCI_IRQ_EN_BITS);
1177 #ifndef CONFIG_DM_MMC
1178 memset(cfg, '\0', sizeof(*cfg));
1182 caps = esdhc_read32(®s->hostcapblt);
1184 #ifdef CONFIG_MCF5441x
1186 * MCF5441x RM declares in more points that sdhc clock speed must
1187 * never exceed 25 Mhz. From this, the HS bit needs to be disabled
1188 * from host capabilities.
1190 caps &= ~ESDHC_HOSTCAPBLT_HSS;
1193 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
1194 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
1195 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
1198 /* T4240 host controller capabilities register should have VS33 bit */
1199 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
1200 caps = caps | ESDHC_HOSTCAPBLT_VS33;
1203 if (caps & ESDHC_HOSTCAPBLT_VS18)
1204 voltage_caps |= MMC_VDD_165_195;
1205 if (caps & ESDHC_HOSTCAPBLT_VS30)
1206 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
1207 if (caps & ESDHC_HOSTCAPBLT_VS33)
1208 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
1210 cfg->name = "FSL_SDHC";
1211 #if !CONFIG_IS_ENABLED(DM_MMC)
1212 cfg->ops = &esdhc_ops;
1214 #ifdef CONFIG_SYS_SD_VOLTAGE
1215 cfg->voltages = CONFIG_SYS_SD_VOLTAGE;
1217 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
1219 if ((cfg->voltages & voltage_caps) == 0) {
1220 printf("voltage not supported by controller\n");
1224 if (priv->bus_width == 8)
1225 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
1226 else if (priv->bus_width == 4)
1227 cfg->host_caps = MMC_MODE_4BIT;
1229 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
1230 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
1231 cfg->host_caps |= MMC_MODE_DDR_52MHz;
1234 if (priv->bus_width > 0) {
1235 if (priv->bus_width < 8)
1236 cfg->host_caps &= ~MMC_MODE_8BIT;
1237 if (priv->bus_width < 4)
1238 cfg->host_caps &= ~MMC_MODE_4BIT;
1241 if (caps & ESDHC_HOSTCAPBLT_HSS)
1242 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1244 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
1245 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
1246 cfg->host_caps &= ~MMC_MODE_8BIT;
1249 cfg->host_caps |= priv->caps;
1251 cfg->f_min = 400000;
1252 cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
1254 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1256 esdhc_write32(®s->dllctrl, 0);
1257 if (priv->flags & ESDHC_FLAG_USDHC) {
1258 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
1259 u32 val = esdhc_read32(®s->tuning_ctrl);
1261 val |= ESDHC_STD_TUNING_EN;
1262 val &= ~ESDHC_TUNING_START_TAP_MASK;
1263 val |= priv->tuning_start_tap;
1264 val &= ~ESDHC_TUNING_STEP_MASK;
1265 val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT;
1267 /* Disable the CMD CRC check for tuning, if not, need to
1268 * add some delay after every tuning command, because
1269 * hardware standard tuning logic will directly go to next
1270 * step once it detect the CMD CRC error, will not wait for
1271 * the card side to finally send out the tuning data, trigger
1272 * the buffer read ready interrupt immediately. If usdhc send
1273 * the next tuning command some eMMC card will stuck, can't
1274 * response, block the tuning procedure or the first command
1275 * after the whole tuning procedure always can't get any response.
1277 val |= ESDHC_TUNING_CMD_CRC_CHECK_DISABLE;
1278 esdhc_write32(®s->tuning_ctrl, val);
1285 #if !CONFIG_IS_ENABLED(DM_MMC)
1286 static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
1287 struct fsl_esdhc_priv *priv)
1292 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
1293 priv->bus_width = cfg->max_bus_width;
1294 priv->sdhc_clk = cfg->sdhc_clk;
1295 priv->wp_enable = cfg->wp_enable;
1296 priv->vs18_enable = cfg->vs18_enable;
1301 int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg)
1303 struct fsl_esdhc_plat *plat;
1304 struct fsl_esdhc_priv *priv;
1311 priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
1314 plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
1320 ret = fsl_esdhc_cfg_to_priv(cfg, priv);
1322 debug("%s xlate failure\n", __func__);
1328 ret = fsl_esdhc_init(priv, plat);
1330 debug("%s init failure\n", __func__);
1336 mmc = mmc_create(&plat->cfg, priv);
1345 int fsl_esdhc_mmc_init(struct bd_info *bis)
1347 struct fsl_esdhc_cfg *cfg;
1349 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
1350 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
1351 cfg->sdhc_clk = gd->arch.sdhc_clk;
1352 return fsl_esdhc_initialize(bis, cfg);
1356 #ifdef CONFIG_OF_LIBFDT
1357 __weak int esdhc_status_fixup(void *blob, const char *compat)
1359 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
1360 if (!hwconfig("esdhc")) {
1361 do_fixup_by_compat(blob, compat, "status", "disabled",
1362 sizeof("disabled"), 1);
1369 void fdt_fixup_esdhc(void *blob, struct bd_info *bd)
1371 const char *compat = "fsl,esdhc";
1373 if (esdhc_status_fixup(blob, compat))
1376 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
1377 gd->arch.sdhc_clk, 1);
1381 #if CONFIG_IS_ENABLED(DM_MMC)
1382 #include <asm/arch/clock.h>
1383 __weak void init_clk_usdhc(u32 index)
1387 static int fsl_esdhc_ofdata_to_platdata(struct udevice *dev)
1389 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1390 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1391 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1392 struct udevice *vqmmc_dev;
1395 const void *fdt = gd->fdt_blob;
1396 int node = dev_of_offset(dev);
1401 addr = dev_read_addr(dev);
1402 if (addr == FDT_ADDR_T_NONE)
1404 priv->esdhc_regs = (struct fsl_esdhc *)addr;
1408 val = dev_read_u32_default(dev, "bus-width", -1);
1410 priv->bus_width = 8;
1412 priv->bus_width = 4;
1414 priv->bus_width = 1;
1416 val = fdtdec_get_int(fdt, node, "fsl,tuning-step", 1);
1417 priv->tuning_step = val;
1418 val = fdtdec_get_int(fdt, node, "fsl,tuning-start-tap",
1419 ESDHC_TUNING_START_TAP_DEFAULT);
1420 priv->tuning_start_tap = val;
1421 val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target",
1422 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT);
1423 priv->strobe_dll_delay_target = val;
1425 if (dev_read_bool(dev, "broken-cd"))
1426 priv->broken_cd = 1;
1428 if (dev_read_bool(dev, "non-removable")) {
1429 priv->non_removable = 1;
1431 priv->non_removable = 0;
1432 #if CONFIG_IS_ENABLED(DM_GPIO)
1433 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
1438 if (dev_read_prop(dev, "fsl,wp-controller", NULL)) {
1439 priv->wp_enable = 1;
1441 priv->wp_enable = 0;
1442 #if CONFIG_IS_ENABLED(DM_GPIO)
1443 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
1448 priv->vs18_enable = 0;
1450 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1452 * If emmc I/O has a fixed voltage at 1.8V, this must be provided,
1453 * otherwise, emmc will work abnormally.
1455 ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
1457 dev_dbg(dev, "no vqmmc-supply\n");
1459 priv->vqmmc_dev = vqmmc_dev;
1460 ret = regulator_set_enable(vqmmc_dev, true);
1462 dev_err(dev, "fail to enable vqmmc-supply\n");
1466 if (regulator_get_value(vqmmc_dev) == 1800000)
1467 priv->vs18_enable = 1;
1474 static int fsl_esdhc_probe(struct udevice *dev)
1476 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1477 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1478 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1479 struct esdhc_soc_data *data =
1480 (struct esdhc_soc_data *)dev_get_driver_data(dev);
1482 #if !CONFIG_IS_ENABLED(BLK)
1483 struct blk_desc *bdesc;
1487 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1488 struct dtd_fsl_esdhc *dtplat = &plat->dtplat;
1491 priv->esdhc_regs = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
1492 val = plat->dtplat.bus_width;
1494 priv->bus_width = 8;
1496 priv->bus_width = 4;
1498 priv->bus_width = 1;
1500 if (dtplat->non_removable)
1501 priv->non_removable = 1;
1503 priv->non_removable = 0;
1505 if (CONFIG_IS_ENABLED(DM_GPIO) && !priv->non_removable) {
1506 struct udevice *gpiodev;
1508 ret = device_get_by_driver_info_idx(dtplat->cd_gpios->idx,
1513 ret = gpio_dev_request_index(gpiodev, gpiodev->name, "cd-gpios",
1514 dtplat->cd_gpios->arg[0], GPIOD_IS_IN,
1515 dtplat->cd_gpios->arg[1], &priv->cd_gpio);
1523 priv->flags = data->flags;
1527 * Because lack of clk driver, if SDHC clk is not enabled,
1528 * need to enable it first before this driver is invoked.
1530 * we use MXC_ESDHC_CLK to get clk freq.
1531 * If one would like to make this function work,
1532 * the aliases should be provided in dts as this:
1540 * Then if your board only supports mmc2 and mmc3, but we can
1541 * correctly get the seq as 2 and 3, then let mxc_get_clock
1545 init_clk_usdhc(dev->seq);
1547 #if CONFIG_IS_ENABLED(CLK)
1548 /* Assigned clock already set clock */
1549 ret = clk_get_by_name(dev, "per", &priv->per_clk);
1551 printf("Failed to get per_clk\n");
1554 ret = clk_enable(&priv->per_clk);
1556 printf("Failed to enable per_clk\n");
1560 priv->sdhc_clk = clk_get_rate(&priv->per_clk);
1562 priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
1563 if (priv->sdhc_clk <= 0) {
1564 dev_err(dev, "Unable to get clk for %s\n", dev->name);
1569 ret = fsl_esdhc_init(priv, plat);
1571 dev_err(dev, "fsl_esdhc_init failure\n");
1575 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1576 ret = mmc_of_parse(dev, &plat->cfg);
1582 mmc->cfg = &plat->cfg;
1584 #if !CONFIG_IS_ENABLED(BLK)
1587 /* Setup dsr related values */
1589 mmc->dsr = ESDHC_DRIVER_STAGE_VALUE;
1590 /* Setup the universal parts of the block interface just once */
1591 bdesc = mmc_get_blk_desc(mmc);
1592 bdesc->if_type = IF_TYPE_MMC;
1593 bdesc->removable = 1;
1594 bdesc->devnum = mmc_get_next_devnum();
1595 bdesc->block_read = mmc_bread;
1596 bdesc->block_write = mmc_bwrite;
1597 bdesc->block_erase = mmc_berase;
1599 /* setup initial part type */
1600 bdesc->part_type = mmc->cfg->part_type;
1606 return esdhc_init_common(priv, mmc);
1609 #if CONFIG_IS_ENABLED(DM_MMC)
1610 static int fsl_esdhc_get_cd(struct udevice *dev)
1612 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1614 return esdhc_getcd_common(priv);
1617 static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1618 struct mmc_data *data)
1620 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1621 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1623 return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
1626 static int fsl_esdhc_set_ios(struct udevice *dev)
1628 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1629 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1631 return esdhc_set_ios_common(priv, &plat->mmc);
1634 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
1635 static int fsl_esdhc_set_enhanced_strobe(struct udevice *dev)
1637 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1638 struct fsl_esdhc *regs = priv->esdhc_regs;
1641 m = esdhc_read32(®s->mixctrl);
1642 m |= MIX_CTRL_HS400_ES;
1643 esdhc_write32(®s->mixctrl, m);
1649 static const struct dm_mmc_ops fsl_esdhc_ops = {
1650 .get_cd = fsl_esdhc_get_cd,
1651 .send_cmd = fsl_esdhc_send_cmd,
1652 .set_ios = fsl_esdhc_set_ios,
1653 #ifdef MMC_SUPPORTS_TUNING
1654 .execute_tuning = fsl_esdhc_execute_tuning,
1656 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
1657 .set_enhanced_strobe = fsl_esdhc_set_enhanced_strobe,
1662 static struct esdhc_soc_data usdhc_imx7d_data = {
1663 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
1664 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
1668 static struct esdhc_soc_data usdhc_imx8qm_data = {
1669 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING |
1670 ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 |
1671 ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES,
1674 static const struct udevice_id fsl_esdhc_ids[] = {
1675 { .compatible = "fsl,imx53-esdhc", },
1676 { .compatible = "fsl,imx6ul-usdhc", },
1677 { .compatible = "fsl,imx6sx-usdhc", },
1678 { .compatible = "fsl,imx6sl-usdhc", },
1679 { .compatible = "fsl,imx6q-usdhc", },
1680 { .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,},
1681 { .compatible = "fsl,imx7ulp-usdhc", },
1682 { .compatible = "fsl,imx8qm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
1683 { .compatible = "fsl,imx8mm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
1684 { .compatible = "fsl,imx8mn-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
1685 { .compatible = "fsl,imx8mq-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
1686 { .compatible = "fsl,imxrt-usdhc", },
1687 { .compatible = "fsl,esdhc", },
1691 #if CONFIG_IS_ENABLED(BLK)
1692 static int fsl_esdhc_bind(struct udevice *dev)
1694 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1696 return mmc_bind(dev, &plat->mmc, &plat->cfg);
1700 U_BOOT_DRIVER(fsl_esdhc) = {
1701 .name = "fsl_esdhc",
1703 .of_match = fsl_esdhc_ids,
1704 .ofdata_to_platdata = fsl_esdhc_ofdata_to_platdata,
1705 .ops = &fsl_esdhc_ops,
1706 #if CONFIG_IS_ENABLED(BLK)
1707 .bind = fsl_esdhc_bind,
1709 .probe = fsl_esdhc_probe,
1710 .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
1711 .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),
1714 U_BOOT_DRIVER_ALIAS(fsl_esdhc, fsl_imx6q_usdhc)