1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
4 * Copyright 2019 NXP Semiconductors
6 * Yangbo Lu <yangbo.lu@nxp.com>
8 * Based vaguely on the pxa mmc code:
10 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
21 #include <power/regulator.h>
23 #include <fsl_esdhc_imx.h>
24 #include <fdt_support.h>
27 #include <asm-generic/gpio.h>
28 #include <dm/pinctrl.h>
30 #if !CONFIG_IS_ENABLED(BLK)
31 #include "mmc_private.h"
34 DECLARE_GLOBAL_DATA_PTR;
36 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
38 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
39 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
40 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
42 #define MAX_TUNING_LOOP 40
43 #define ESDHC_DRIVER_STAGE_VALUE 0xffffffff
46 uint dsaddr; /* SDMA system address register */
47 uint blkattr; /* Block attributes register */
48 uint cmdarg; /* Command argument register */
49 uint xfertyp; /* Transfer type register */
50 uint cmdrsp0; /* Command response 0 register */
51 uint cmdrsp1; /* Command response 1 register */
52 uint cmdrsp2; /* Command response 2 register */
53 uint cmdrsp3; /* Command response 3 register */
54 uint datport; /* Buffer data port register */
55 uint prsstat; /* Present state register */
56 uint proctl; /* Protocol control register */
57 uint sysctl; /* System Control Register */
58 uint irqstat; /* Interrupt status register */
59 uint irqstaten; /* Interrupt status enable register */
60 uint irqsigen; /* Interrupt signal enable register */
61 uint autoc12err; /* Auto CMD error status register */
62 uint hostcapblt; /* Host controller capabilities register */
63 uint wml; /* Watermark level register */
64 uint mixctrl; /* For USDHC */
65 char reserved1[4]; /* reserved */
66 uint fevt; /* Force event register */
67 uint admaes; /* ADMA error status register */
68 uint adsaddr; /* ADMA system address register */
72 uint clktunectrlstatus;
80 uint tuning_ctrl; /* on i.MX6/7/8 */
82 uint hostver; /* Host controller version register */
83 char reserved6[4]; /* reserved */
84 uint dmaerraddr; /* DMA error address register */
85 char reserved7[4]; /* reserved */
86 uint dmaerrattr; /* DMA error attribute register */
87 char reserved8[4]; /* reserved */
88 uint hostcapblt2; /* Host controller capabilities register 2 */
89 char reserved9[8]; /* reserved */
90 uint tcr; /* Tuning control register */
91 char reserved10[28]; /* reserved */
92 uint sddirctl; /* SD direction control register */
93 char reserved11[712];/* reserved */
94 uint scr; /* eSDHC control register */
97 struct fsl_esdhc_plat {
98 struct mmc_config cfg;
102 struct esdhc_soc_data {
108 * struct fsl_esdhc_priv
110 * @esdhc_regs: registers of the sdhc controller
111 * @sdhc_clk: Current clk of the sdhc controller
112 * @bus_width: bus width, 1bit, 4bit or 8bit
115 * Following is used when Driver Model is enabled for MMC
116 * @dev: pointer for the device
117 * @non_removable: 0: removable; 1: non-removable
118 * @wp_enable: 1: enable checking wp; 0: no check
119 * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
120 * @flags: ESDHC_FLAG_xx in include/fsl_esdhc_imx.h
121 * @caps: controller capabilities
122 * @tuning_step: tuning step setting in tuning_ctrl register
123 * @start_tuning_tap: the start point for tuning in tuning_ctrl register
124 * @strobe_dll_delay_target: settings in strobe_dllctrl
125 * @signal_voltage: indicating the current voltage
126 * @cd_gpio: gpio for card detection
127 * @wp_gpio: gpio for write protection
129 struct fsl_esdhc_priv {
130 struct fsl_esdhc *esdhc_regs;
131 unsigned int sdhc_clk;
135 unsigned int bus_width;
136 #if !CONFIG_IS_ENABLED(BLK)
146 u32 tuning_start_tap;
147 u32 strobe_dll_delay_target;
149 #if IS_ENABLED(CONFIG_DM_REGULATOR)
150 struct udevice *vqmmc_dev;
151 struct udevice *vmmc_dev;
153 #ifdef CONFIG_DM_GPIO
154 struct gpio_desc cd_gpio;
155 struct gpio_desc wp_gpio;
159 /* Return the XFERTYP flags for a given command and data packet */
160 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
165 xfertyp |= XFERTYP_DPSEL;
166 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
167 xfertyp |= XFERTYP_DMAEN;
169 if (data->blocks > 1) {
170 xfertyp |= XFERTYP_MSBSEL;
171 xfertyp |= XFERTYP_BCEN;
172 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
173 xfertyp |= XFERTYP_AC12EN;
177 if (data->flags & MMC_DATA_READ)
178 xfertyp |= XFERTYP_DTDSEL;
181 if (cmd->resp_type & MMC_RSP_CRC)
182 xfertyp |= XFERTYP_CCCEN;
183 if (cmd->resp_type & MMC_RSP_OPCODE)
184 xfertyp |= XFERTYP_CICEN;
185 if (cmd->resp_type & MMC_RSP_136)
186 xfertyp |= XFERTYP_RSPTYP_136;
187 else if (cmd->resp_type & MMC_RSP_BUSY)
188 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
189 else if (cmd->resp_type & MMC_RSP_PRESENT)
190 xfertyp |= XFERTYP_RSPTYP_48;
192 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
193 xfertyp |= XFERTYP_CMDTYP_ABORT;
195 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
198 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
200 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
202 static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
203 struct mmc_data *data)
205 struct fsl_esdhc *regs = priv->esdhc_regs;
213 if (data->flags & MMC_DATA_READ) {
214 blocks = data->blocks;
217 start = get_timer(0);
218 size = data->blocksize;
219 irqstat = esdhc_read32(®s->irqstat);
220 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)) {
221 if (get_timer(start) > PIO_TIMEOUT) {
222 printf("\nData Read Failed in PIO Mode.");
226 while (size && (!(irqstat & IRQSTAT_TC))) {
227 udelay(100); /* Wait before last byte transfer complete */
228 irqstat = esdhc_read32(®s->irqstat);
229 databuf = in_le32(®s->datport);
230 *((uint *)buffer) = databuf;
237 blocks = data->blocks;
238 buffer = (char *)data->src;
240 start = get_timer(0);
241 size = data->blocksize;
242 irqstat = esdhc_read32(®s->irqstat);
243 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)) {
244 if (get_timer(start) > PIO_TIMEOUT) {
245 printf("\nData Write Failed in PIO Mode.");
249 while (size && (!(irqstat & IRQSTAT_TC))) {
250 udelay(100); /* Wait before last byte transfer complete */
251 databuf = *((uint *)buffer);
254 irqstat = esdhc_read32(®s->irqstat);
255 out_le32(®s->datport, databuf);
263 static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
264 struct mmc_data *data)
267 struct fsl_esdhc *regs = priv->esdhc_regs;
268 #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
273 wml_value = data->blocksize/4;
275 if (data->flags & MMC_DATA_READ) {
276 if (wml_value > WML_RD_WML_MAX)
277 wml_value = WML_RD_WML_MAX_VAL;
279 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
280 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
281 #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
282 addr = virt_to_phys((void *)(data->dest));
283 if (upper_32_bits(addr))
284 printf("Error found for upper 32 bits\n");
286 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
288 esdhc_write32(®s->dsaddr, (u32)data->dest);
292 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
293 flush_dcache_range((ulong)data->src,
294 (ulong)data->src+data->blocks
297 if (wml_value > WML_WR_WML_MAX)
298 wml_value = WML_WR_WML_MAX_VAL;
299 if (priv->wp_enable) {
300 if ((esdhc_read32(®s->prsstat) &
301 PRSSTAT_WPSPL) == 0) {
302 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
306 #ifdef CONFIG_DM_GPIO
307 if (dm_gpio_is_valid(&priv->wp_gpio) && dm_gpio_get_value(&priv->wp_gpio)) {
308 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
314 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
316 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
317 #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
318 addr = virt_to_phys((void *)(data->src));
319 if (upper_32_bits(addr))
320 printf("Error found for upper 32 bits\n");
322 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
324 esdhc_write32(®s->dsaddr, (u32)data->src);
329 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
331 /* Calculate the timeout period for data transactions */
333 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
334 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
335 * So, Number of SD Clock cycles for 0.25sec should be minimum
336 * (SD Clock/sec * 0.25 sec) SD Clock cycles
337 * = (mmc->clock * 1/4) SD Clock cycles
339 * => (2^(timeout+13)) >= mmc->clock * 1/4
340 * Taking log2 both the sides
341 * => timeout + 13 >= log2(mmc->clock/4)
342 * Rounding up to next power of 2
343 * => timeout + 13 = log2(mmc->clock/4) + 1
344 * => timeout + 13 = fls(mmc->clock/4)
346 * However, the MMC spec "It is strongly recommended for hosts to
347 * implement more than 500ms timeout value even if the card
348 * indicates the 250ms maximum busy length." Even the previous
349 * value of 300ms is known to be insufficient for some cards.
351 * => timeout + 13 = fls(mmc->clock/2)
353 timeout = fls(mmc->clock/2);
362 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
363 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
367 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
370 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
375 static void check_and_invalidate_dcache_range
376 (struct mmc_cmd *cmd,
377 struct mmc_data *data) {
380 unsigned size = roundup(ARCH_DMA_MINALIGN,
381 data->blocks*data->blocksize);
382 #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
385 addr = virt_to_phys((void *)(data->dest));
386 if (upper_32_bits(addr))
387 printf("Error found for upper 32 bits\n");
389 start = lower_32_bits(addr);
391 start = (unsigned)data->dest;
394 invalidate_dcache_range(start, end);
397 #ifdef CONFIG_MCF5441x
399 * Swaps 32-bit words to little-endian byte order.
401 static inline void sd_swap_dma_buff(struct mmc_data *data)
403 int i, size = data->blocksize >> 2;
404 u32 *buffer = (u32 *)data->dest;
407 while (data->blocks--) {
408 for (i = 0; i < size; i++) {
409 sw = __sw32(*buffer);
417 * Sends a command out on the bus. Takes the mmc pointer,
418 * a command pointer, and an optional data pointer.
420 static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
421 struct mmc_cmd *cmd, struct mmc_data *data)
426 u32 flags = IRQSTAT_CC | IRQSTAT_CTOE;
427 struct fsl_esdhc *regs = priv->esdhc_regs;
430 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
431 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
435 esdhc_write32(®s->irqstat, -1);
439 /* Wait for the bus to be idle */
440 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
441 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
444 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
447 /* Wait at least 8 SD clock cycles before the next command */
449 * Note: This is way more than 8 cycles, but 1ms seems to
450 * resolve timing issues with some cards
454 /* Set up for a data transfer if we have one */
456 err = esdhc_setup_data(priv, mmc, data);
460 if (data->flags & MMC_DATA_READ)
461 check_and_invalidate_dcache_range(cmd, data);
464 /* Figure out the transfer arguments */
465 xfertyp = esdhc_xfertyp(cmd, data);
468 esdhc_write32(®s->irqsigen, 0);
470 /* Send the command */
471 esdhc_write32(®s->cmdarg, cmd->cmdarg);
472 #if defined(CONFIG_FSL_USDHC)
473 esdhc_write32(®s->mixctrl,
474 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
475 | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
476 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000);
478 esdhc_write32(®s->xfertyp, xfertyp);
481 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
482 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))
485 /* Wait for the command to complete */
486 start = get_timer(0);
487 while (!(esdhc_read32(®s->irqstat) & flags)) {
488 if (get_timer(start) > 1000) {
494 irqstat = esdhc_read32(®s->irqstat);
496 if (irqstat & CMD_ERR) {
501 if (irqstat & IRQSTAT_CTOE) {
506 /* Switch voltage to 1.8V if CMD11 succeeded */
507 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
508 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
510 printf("Run CMD11 1.8V switch\n");
511 /* Sleep for 5 ms - max time for card to switch to 1.8V */
515 /* Workaround for ESDHC errata ENGcm03648 */
516 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
519 /* Poll on DATA0 line for cmd with busy signal for 600 ms */
520 while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
527 printf("Timeout waiting for DAT0 to go high!\n");
533 /* Copy the response to the response buffer */
534 if (cmd->resp_type & MMC_RSP_136) {
535 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
537 cmdrsp3 = esdhc_read32(®s->cmdrsp3);
538 cmdrsp2 = esdhc_read32(®s->cmdrsp2);
539 cmdrsp1 = esdhc_read32(®s->cmdrsp1);
540 cmdrsp0 = esdhc_read32(®s->cmdrsp0);
541 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
542 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
543 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
544 cmd->response[3] = (cmdrsp0 << 8);
546 cmd->response[0] = esdhc_read32(®s->cmdrsp0);
548 /* Wait until all of the blocks are transferred */
550 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
551 esdhc_pio_read_write(priv, data);
553 flags = DATA_COMPLETE;
554 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
555 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) {
560 irqstat = esdhc_read32(®s->irqstat);
562 if (irqstat & IRQSTAT_DTOE) {
567 if (irqstat & DATA_ERR) {
571 } while ((irqstat & flags) != flags);
574 * Need invalidate the dcache here again to avoid any
575 * cache-fill during the DMA operations such as the
576 * speculative pre-fetching etc.
578 if (data->flags & MMC_DATA_READ) {
579 check_and_invalidate_dcache_range(cmd, data);
580 #ifdef CONFIG_MCF5441x
581 sd_swap_dma_buff(data);
588 /* Reset CMD and DATA portions on error */
590 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
592 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC)
596 esdhc_write32(®s->sysctl,
597 esdhc_read32(®s->sysctl) |
599 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
603 /* If this was CMD11, then notify that power cycle is needed */
604 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
605 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
608 esdhc_write32(®s->irqstat, -1);
613 static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
615 struct fsl_esdhc *regs = priv->esdhc_regs;
619 /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
620 int pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1;
627 int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
628 int sdhc_clk = priv->sdhc_clk;
631 if (clock < mmc->cfg->f_min)
632 clock = mmc->cfg->f_min;
634 while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
637 while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
643 clk = (pre_div << 8) | (div << 4);
645 #ifdef CONFIG_FSL_USDHC
646 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
648 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
651 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
655 #ifdef CONFIG_FSL_USDHC
656 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
658 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
664 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
665 static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
667 struct fsl_esdhc *regs = priv->esdhc_regs;
671 value = esdhc_read32(®s->sysctl);
674 value |= SYSCTL_CKEN;
676 value &= ~SYSCTL_CKEN;
678 esdhc_write32(®s->sysctl, value);
681 value = PRSSTAT_SDSTB;
682 while (!(esdhc_read32(®s->prsstat) & value)) {
684 printf("fsl_esdhc: Internal clock never stabilised.\n");
693 #ifdef MMC_SUPPORTS_TUNING
694 static int esdhc_change_pinstate(struct udevice *dev)
696 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
699 switch (priv->mode) {
702 ret = pinctrl_select_state(dev, "state_100mhz");
707 ret = pinctrl_select_state(dev, "state_200mhz");
710 ret = pinctrl_select_state(dev, "default");
715 printf("%s %d error\n", __func__, priv->mode);
720 static void esdhc_reset_tuning(struct mmc *mmc)
722 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
723 struct fsl_esdhc *regs = priv->esdhc_regs;
725 if (priv->flags & ESDHC_FLAG_USDHC) {
726 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
727 esdhc_clrbits32(®s->autoc12err,
728 MIX_CTRL_SMPCLK_SEL |
734 static void esdhc_set_strobe_dll(struct mmc *mmc)
736 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
737 struct fsl_esdhc *regs = priv->esdhc_regs;
740 if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
741 writel(ESDHC_STROBE_DLL_CTRL_RESET, ®s->strobe_dllctrl);
744 * enable strobe dll ctrl and adjust the delay target
745 * for the uSDHC loopback read clock
747 val = ESDHC_STROBE_DLL_CTRL_ENABLE |
748 (priv->strobe_dll_delay_target <<
749 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
750 writel(val, ®s->strobe_dllctrl);
751 /* wait 1us to make sure strobe dll status register stable */
753 val = readl(®s->strobe_dllstat);
754 if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK))
755 pr_warn("HS400 strobe DLL status REF not lock!\n");
756 if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK))
757 pr_warn("HS400 strobe DLL status SLV not lock!\n");
761 static int esdhc_set_timing(struct mmc *mmc)
763 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
764 struct fsl_esdhc *regs = priv->esdhc_regs;
767 mixctrl = readl(®s->mixctrl);
768 mixctrl &= ~(MIX_CTRL_DDREN | MIX_CTRL_HS400_EN);
770 switch (mmc->selected_mode) {
773 esdhc_reset_tuning(mmc);
774 writel(mixctrl, ®s->mixctrl);
777 mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN;
778 writel(mixctrl, ®s->mixctrl);
779 esdhc_set_strobe_dll(mmc);
789 writel(mixctrl, ®s->mixctrl);
793 mixctrl |= MIX_CTRL_DDREN;
794 writel(mixctrl, ®s->mixctrl);
797 printf("Not supported %d\n", mmc->selected_mode);
801 priv->mode = mmc->selected_mode;
803 return esdhc_change_pinstate(mmc->dev);
806 static int esdhc_set_voltage(struct mmc *mmc)
808 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
809 struct fsl_esdhc *regs = priv->esdhc_regs;
812 priv->signal_voltage = mmc->signal_voltage;
813 switch (mmc->signal_voltage) {
814 case MMC_SIGNAL_VOLTAGE_330:
815 if (priv->vs18_enable)
817 #if CONFIG_IS_ENABLED(DM_REGULATOR)
818 if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
819 ret = regulator_set_value(priv->vqmmc_dev, 3300000);
821 printf("Setting to 3.3V error");
829 esdhc_clrbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
830 if (!(esdhc_read32(®s->vendorspec) &
831 ESDHC_VENDORSPEC_VSELECT))
835 case MMC_SIGNAL_VOLTAGE_180:
836 #if CONFIG_IS_ENABLED(DM_REGULATOR)
837 if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
838 ret = regulator_set_value(priv->vqmmc_dev, 1800000);
840 printf("Setting to 1.8V error");
845 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
846 if (esdhc_read32(®s->vendorspec) & ESDHC_VENDORSPEC_VSELECT)
850 case MMC_SIGNAL_VOLTAGE_120:
857 static void esdhc_stop_tuning(struct mmc *mmc)
861 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
863 cmd.resp_type = MMC_RSP_R1b;
865 dm_mmc_send_cmd(mmc->dev, &cmd, NULL);
868 static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
870 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
871 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
872 struct fsl_esdhc *regs = priv->esdhc_regs;
873 struct mmc *mmc = &plat->mmc;
874 u32 irqstaten = readl(®s->irqstaten);
875 u32 irqsigen = readl(®s->irqsigen);
876 int i, ret = -ETIMEDOUT;
879 /* clock tuning is not needed for upto 52MHz */
880 if (mmc->clock <= 52000000)
883 /* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */
884 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
885 val = readl(®s->autoc12err);
886 mixctrl = readl(®s->mixctrl);
887 val &= ~MIX_CTRL_SMPCLK_SEL;
888 mixctrl &= ~(MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN);
890 val |= MIX_CTRL_EXE_TUNE;
891 mixctrl |= MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN;
893 writel(val, ®s->autoc12err);
894 writel(mixctrl, ®s->mixctrl);
897 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); */
898 mixctrl = readl(®s->mixctrl);
899 mixctrl = MIX_CTRL_DTDSEL_READ | (mixctrl & ~MIX_CTRL_SDHCI_MASK);
900 writel(mixctrl, ®s->mixctrl);
902 writel(IRQSTATEN_BRR, ®s->irqstaten);
903 writel(IRQSTATEN_BRR, ®s->irqsigen);
906 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
907 * of loops reaches 40 times.
909 for (i = 0; i < MAX_TUNING_LOOP; i++) {
912 if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) {
913 if (mmc->bus_width == 8)
914 writel(0x7080, ®s->blkattr);
915 else if (mmc->bus_width == 4)
916 writel(0x7040, ®s->blkattr);
918 writel(0x7040, ®s->blkattr);
921 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE) */
922 val = readl(®s->mixctrl);
923 val = MIX_CTRL_DTDSEL_READ | (val & ~MIX_CTRL_SDHCI_MASK);
924 writel(val, ®s->mixctrl);
926 /* We are using STD tuning, no need to check return value */
927 mmc_send_tuning(mmc, opcode, NULL);
929 ctrl = readl(®s->autoc12err);
930 if ((!(ctrl & MIX_CTRL_EXE_TUNE)) &&
931 (ctrl & MIX_CTRL_SMPCLK_SEL)) {
933 * need to wait some time, make sure sd/mmc fininsh
934 * send out tuning data, otherwise, the sd/mmc can't
935 * response to any command when the card still out
936 * put the tuning data.
943 /* Add 1ms delay for SD and eMMC */
947 writel(irqstaten, ®s->irqstaten);
948 writel(irqsigen, ®s->irqsigen);
950 esdhc_stop_tuning(mmc);
956 static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
958 struct fsl_esdhc *regs = priv->esdhc_regs;
959 int ret __maybe_unused;
961 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
962 /* Select to use peripheral clock */
963 esdhc_clock_control(priv, false);
964 esdhc_setbits32(®s->scr, ESDHCCTL_PCS);
965 esdhc_clock_control(priv, true);
967 /* Set the clock speed */
968 if (priv->clock != mmc->clock)
969 set_sysctl(priv, mmc, mmc->clock);
971 #ifdef MMC_SUPPORTS_TUNING
972 if (mmc->clk_disable) {
973 #ifdef CONFIG_FSL_USDHC
974 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
976 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
979 #ifdef CONFIG_FSL_USDHC
980 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
983 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
987 if (priv->mode != mmc->selected_mode) {
988 ret = esdhc_set_timing(mmc);
990 printf("esdhc_set_timing error %d\n", ret);
995 if (priv->signal_voltage != mmc->signal_voltage) {
996 ret = esdhc_set_voltage(mmc);
998 printf("esdhc_set_voltage error %d\n", ret);
1004 /* Set the bus width */
1005 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
1007 if (mmc->bus_width == 4)
1008 esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
1009 else if (mmc->bus_width == 8)
1010 esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
1015 static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
1017 struct fsl_esdhc *regs = priv->esdhc_regs;
1020 /* Reset the entire host controller */
1021 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
1023 /* Wait until the controller is available */
1024 start = get_timer(0);
1025 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
1026 if (get_timer(start) > 1000)
1030 #if defined(CONFIG_FSL_USDHC)
1031 /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
1032 esdhc_write32(®s->mmcboot, 0x0);
1033 /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
1034 esdhc_write32(®s->mixctrl, 0x0);
1035 esdhc_write32(®s->clktunectrlstatus, 0x0);
1037 /* Put VEND_SPEC to default value */
1038 if (priv->vs18_enable)
1039 esdhc_write32(®s->vendorspec, (VENDORSPEC_INIT |
1040 ESDHC_VENDORSPEC_VSELECT));
1042 esdhc_write32(®s->vendorspec, VENDORSPEC_INIT);
1044 /* Disable DLL_CTRL delay line */
1045 esdhc_write32(®s->dllctrl, 0x0);
1049 /* Enable cache snooping */
1050 esdhc_write32(®s->scr, 0x00000040);
1053 #ifndef CONFIG_FSL_USDHC
1054 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
1056 esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
1059 /* Set the initial clock speed */
1060 mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
1062 /* Disable the BRR and BWR bits in IRQSTAT */
1063 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
1065 #ifdef CONFIG_MCF5441x
1066 esdhc_write32(®s->proctl, PROCTL_INIT | PROCTL_D3CD);
1068 /* Put the PROCTL reg back to the default */
1069 esdhc_write32(®s->proctl, PROCTL_INIT);
1072 /* Set timout to the maximum value */
1073 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
1078 static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
1080 struct fsl_esdhc *regs = priv->esdhc_regs;
1083 #ifdef CONFIG_ESDHC_DETECT_QUIRK
1084 if (CONFIG_ESDHC_DETECT_QUIRK)
1088 #if CONFIG_IS_ENABLED(DM_MMC)
1089 if (priv->non_removable)
1091 #ifdef CONFIG_DM_GPIO
1092 if (dm_gpio_is_valid(&priv->cd_gpio))
1093 return dm_gpio_get_value(&priv->cd_gpio);
1097 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
1103 static int esdhc_reset(struct fsl_esdhc *regs)
1107 /* reset the controller */
1108 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
1110 /* hardware clears the bit when it is done */
1111 start = get_timer(0);
1112 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
1113 if (get_timer(start) > 100) {
1114 printf("MMC/SD: Reset never completed.\n");
1122 #if !CONFIG_IS_ENABLED(DM_MMC)
1123 static int esdhc_getcd(struct mmc *mmc)
1125 struct fsl_esdhc_priv *priv = mmc->priv;
1127 return esdhc_getcd_common(priv);
1130 static int esdhc_init(struct mmc *mmc)
1132 struct fsl_esdhc_priv *priv = mmc->priv;
1134 return esdhc_init_common(priv, mmc);
1137 static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
1138 struct mmc_data *data)
1140 struct fsl_esdhc_priv *priv = mmc->priv;
1142 return esdhc_send_cmd_common(priv, mmc, cmd, data);
1145 static int esdhc_set_ios(struct mmc *mmc)
1147 struct fsl_esdhc_priv *priv = mmc->priv;
1149 return esdhc_set_ios_common(priv, mmc);
1152 static const struct mmc_ops esdhc_ops = {
1153 .getcd = esdhc_getcd,
1155 .send_cmd = esdhc_send_cmd,
1156 .set_ios = esdhc_set_ios,
1160 static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
1161 struct fsl_esdhc_plat *plat)
1163 struct mmc_config *cfg;
1164 struct fsl_esdhc *regs;
1165 u32 caps, voltage_caps;
1171 regs = priv->esdhc_regs;
1173 /* First reset the eSDHC controller */
1174 ret = esdhc_reset(regs);
1178 #ifdef CONFIG_MCF5441x
1179 /* ColdFire, using SDHC_DATA[3] for card detection */
1180 esdhc_write32(®s->proctl, PROCTL_INIT | PROCTL_D3CD);
1183 #ifndef CONFIG_FSL_USDHC
1184 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
1185 | SYSCTL_IPGEN | SYSCTL_CKEN);
1186 /* Clearing tuning bits in case ROM has set it already */
1187 esdhc_write32(®s->mixctrl, 0);
1188 esdhc_write32(®s->autoc12err, 0);
1189 esdhc_write32(®s->clktunectrlstatus, 0);
1191 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
1192 VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
1195 if (priv->vs18_enable)
1196 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
1198 writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
1200 #ifndef CONFIG_DM_MMC
1201 memset(cfg, '\0', sizeof(*cfg));
1205 caps = esdhc_read32(®s->hostcapblt);
1207 #ifdef CONFIG_MCF5441x
1209 * MCF5441x RM declares in more points that sdhc clock speed must
1210 * never exceed 25 Mhz. From this, the HS bit needs to be disabled
1211 * from host capabilities.
1213 caps &= ~ESDHC_HOSTCAPBLT_HSS;
1216 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
1217 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
1218 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
1221 /* T4240 host controller capabilities register should have VS33 bit */
1222 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
1223 caps = caps | ESDHC_HOSTCAPBLT_VS33;
1226 if (caps & ESDHC_HOSTCAPBLT_VS18)
1227 voltage_caps |= MMC_VDD_165_195;
1228 if (caps & ESDHC_HOSTCAPBLT_VS30)
1229 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
1230 if (caps & ESDHC_HOSTCAPBLT_VS33)
1231 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
1233 cfg->name = "FSL_SDHC";
1234 #if !CONFIG_IS_ENABLED(DM_MMC)
1235 cfg->ops = &esdhc_ops;
1237 #ifdef CONFIG_SYS_SD_VOLTAGE
1238 cfg->voltages = CONFIG_SYS_SD_VOLTAGE;
1240 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
1242 if ((cfg->voltages & voltage_caps) == 0) {
1243 printf("voltage not supported by controller\n");
1247 if (priv->bus_width == 8)
1248 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
1249 else if (priv->bus_width == 4)
1250 cfg->host_caps = MMC_MODE_4BIT;
1252 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
1253 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
1254 cfg->host_caps |= MMC_MODE_DDR_52MHz;
1257 if (priv->bus_width > 0) {
1258 if (priv->bus_width < 8)
1259 cfg->host_caps &= ~MMC_MODE_8BIT;
1260 if (priv->bus_width < 4)
1261 cfg->host_caps &= ~MMC_MODE_4BIT;
1264 if (caps & ESDHC_HOSTCAPBLT_HSS)
1265 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1267 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
1268 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
1269 cfg->host_caps &= ~MMC_MODE_8BIT;
1272 cfg->host_caps |= priv->caps;
1274 cfg->f_min = 400000;
1275 cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
1277 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1279 writel(0, ®s->dllctrl);
1280 if (priv->flags & ESDHC_FLAG_USDHC) {
1281 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
1282 u32 val = readl(®s->tuning_ctrl);
1284 val |= ESDHC_STD_TUNING_EN;
1285 val &= ~ESDHC_TUNING_START_TAP_MASK;
1286 val |= priv->tuning_start_tap;
1287 val &= ~ESDHC_TUNING_STEP_MASK;
1288 val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT;
1289 writel(val, ®s->tuning_ctrl);
1296 #if !CONFIG_IS_ENABLED(DM_MMC)
1297 static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
1298 struct fsl_esdhc_priv *priv)
1303 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
1304 priv->bus_width = cfg->max_bus_width;
1305 priv->sdhc_clk = cfg->sdhc_clk;
1306 priv->wp_enable = cfg->wp_enable;
1307 priv->vs18_enable = cfg->vs18_enable;
1312 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
1314 struct fsl_esdhc_plat *plat;
1315 struct fsl_esdhc_priv *priv;
1322 priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
1325 plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
1331 ret = fsl_esdhc_cfg_to_priv(cfg, priv);
1333 debug("%s xlate failure\n", __func__);
1339 ret = fsl_esdhc_init(priv, plat);
1341 debug("%s init failure\n", __func__);
1347 mmc = mmc_create(&plat->cfg, priv);
1356 int fsl_esdhc_mmc_init(bd_t *bis)
1358 struct fsl_esdhc_cfg *cfg;
1360 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
1361 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
1362 cfg->sdhc_clk = gd->arch.sdhc_clk;
1363 return fsl_esdhc_initialize(bis, cfg);
1367 #ifdef CONFIG_OF_LIBFDT
1368 __weak int esdhc_status_fixup(void *blob, const char *compat)
1370 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
1371 if (!hwconfig("esdhc")) {
1372 do_fixup_by_compat(blob, compat, "status", "disabled",
1373 sizeof("disabled"), 1);
1380 void fdt_fixup_esdhc(void *blob, bd_t *bd)
1382 const char *compat = "fsl,esdhc";
1384 if (esdhc_status_fixup(blob, compat))
1387 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
1388 do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
1389 gd->arch.sdhc_clk, 1);
1391 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
1392 gd->arch.sdhc_clk, 1);
1397 #if CONFIG_IS_ENABLED(DM_MMC)
1398 #include <asm/arch/clock.h>
1399 __weak void init_clk_usdhc(u32 index)
1403 static int fsl_esdhc_probe(struct udevice *dev)
1405 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1406 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1407 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1408 const void *fdt = gd->fdt_blob;
1409 int node = dev_of_offset(dev);
1410 struct esdhc_soc_data *data =
1411 (struct esdhc_soc_data *)dev_get_driver_data(dev);
1412 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1413 struct udevice *vqmmc_dev;
1418 #if !CONFIG_IS_ENABLED(BLK)
1419 struct blk_desc *bdesc;
1423 addr = dev_read_addr(dev);
1424 if (addr == FDT_ADDR_T_NONE)
1426 priv->esdhc_regs = (struct fsl_esdhc *)addr;
1430 priv->flags = data->flags;
1431 priv->caps = data->caps;
1434 val = dev_read_u32_default(dev, "bus-width", -1);
1436 priv->bus_width = 8;
1438 priv->bus_width = 4;
1440 priv->bus_width = 1;
1442 val = fdtdec_get_int(fdt, node, "fsl,tuning-step", 1);
1443 priv->tuning_step = val;
1444 val = fdtdec_get_int(fdt, node, "fsl,tuning-start-tap",
1445 ESDHC_TUNING_START_TAP_DEFAULT);
1446 priv->tuning_start_tap = val;
1447 val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target",
1448 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT);
1449 priv->strobe_dll_delay_target = val;
1451 if (dev_read_bool(dev, "non-removable")) {
1452 priv->non_removable = 1;
1454 priv->non_removable = 0;
1455 #ifdef CONFIG_DM_GPIO
1456 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
1461 if (dev_read_prop(dev, "fsl,wp-controller", NULL)) {
1462 priv->wp_enable = 1;
1464 priv->wp_enable = 0;
1465 #ifdef CONFIG_DM_GPIO
1466 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
1471 priv->vs18_enable = 0;
1473 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1475 * If emmc I/O has a fixed voltage at 1.8V, this must be provided,
1476 * otherwise, emmc will work abnormally.
1478 ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
1480 dev_dbg(dev, "no vqmmc-supply\n");
1482 ret = regulator_set_enable(vqmmc_dev, true);
1484 dev_err(dev, "fail to enable vqmmc-supply\n");
1488 if (regulator_get_value(vqmmc_dev) == 1800000)
1489 priv->vs18_enable = 1;
1493 if (fdt_get_property(fdt, node, "no-1-8-v", NULL))
1494 priv->caps &= ~(UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_HS400);
1498 * Because lack of clk driver, if SDHC clk is not enabled,
1499 * need to enable it first before this driver is invoked.
1501 * we use MXC_ESDHC_CLK to get clk freq.
1502 * If one would like to make this function work,
1503 * the aliases should be provided in dts as this:
1511 * Then if your board only supports mmc2 and mmc3, but we can
1512 * correctly get the seq as 2 and 3, then let mxc_get_clock
1516 init_clk_usdhc(dev->seq);
1518 if (IS_ENABLED(CONFIG_CLK)) {
1519 /* Assigned clock already set clock */
1520 ret = clk_get_by_name(dev, "per", &priv->per_clk);
1522 printf("Failed to get per_clk\n");
1525 ret = clk_enable(&priv->per_clk);
1527 printf("Failed to enable per_clk\n");
1531 priv->sdhc_clk = clk_get_rate(&priv->per_clk);
1533 priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
1534 if (priv->sdhc_clk <= 0) {
1535 dev_err(dev, "Unable to get clk for %s\n", dev->name);
1540 ret = fsl_esdhc_init(priv, plat);
1542 dev_err(dev, "fsl_esdhc_init failure\n");
1547 mmc->cfg = &plat->cfg;
1549 #if !CONFIG_IS_ENABLED(BLK)
1552 /* Setup dsr related values */
1554 mmc->dsr = ESDHC_DRIVER_STAGE_VALUE;
1555 /* Setup the universal parts of the block interface just once */
1556 bdesc = mmc_get_blk_desc(mmc);
1557 bdesc->if_type = IF_TYPE_MMC;
1558 bdesc->removable = 1;
1559 bdesc->devnum = mmc_get_next_devnum();
1560 bdesc->block_read = mmc_bread;
1561 bdesc->block_write = mmc_bwrite;
1562 bdesc->block_erase = mmc_berase;
1564 /* setup initial part type */
1565 bdesc->part_type = mmc->cfg->part_type;
1571 return esdhc_init_common(priv, mmc);
1574 #if CONFIG_IS_ENABLED(DM_MMC)
1575 static int fsl_esdhc_get_cd(struct udevice *dev)
1577 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1579 return esdhc_getcd_common(priv);
1582 static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1583 struct mmc_data *data)
1585 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1586 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1588 return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
1591 static int fsl_esdhc_set_ios(struct udevice *dev)
1593 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1594 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1596 return esdhc_set_ios_common(priv, &plat->mmc);
1599 static const struct dm_mmc_ops fsl_esdhc_ops = {
1600 .get_cd = fsl_esdhc_get_cd,
1601 .send_cmd = fsl_esdhc_send_cmd,
1602 .set_ios = fsl_esdhc_set_ios,
1603 #ifdef MMC_SUPPORTS_TUNING
1604 .execute_tuning = fsl_esdhc_execute_tuning,
1609 static struct esdhc_soc_data usdhc_imx7d_data = {
1610 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
1611 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
1613 .caps = UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_DDR_52MHz |
1614 MMC_MODE_HS_52MHz | MMC_MODE_HS,
1617 static const struct udevice_id fsl_esdhc_ids[] = {
1618 { .compatible = "fsl,imx53-esdhc", },
1619 { .compatible = "fsl,imx6ul-usdhc", },
1620 { .compatible = "fsl,imx6sx-usdhc", },
1621 { .compatible = "fsl,imx6sl-usdhc", },
1622 { .compatible = "fsl,imx6q-usdhc", },
1623 { .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,},
1624 { .compatible = "fsl,imx7ulp-usdhc", },
1625 { .compatible = "fsl,esdhc", },
1629 #if CONFIG_IS_ENABLED(BLK)
1630 static int fsl_esdhc_bind(struct udevice *dev)
1632 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1634 return mmc_bind(dev, &plat->mmc, &plat->cfg);
1638 U_BOOT_DRIVER(fsl_esdhc) = {
1639 .name = "fsl-esdhc-mmc",
1641 .of_match = fsl_esdhc_ids,
1642 .ops = &fsl_esdhc_ops,
1643 #if CONFIG_IS_ENABLED(BLK)
1644 .bind = fsl_esdhc_bind,
1646 .probe = fsl_esdhc_probe,
1647 .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
1648 .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),