1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
4 * Copyright 2019 NXP Semiconductors
6 * Yangbo Lu <yangbo.lu@nxp.com>
8 * Based vaguely on the pxa mmc code:
10 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
22 #include <power/regulator.h>
24 #include <fsl_esdhc_imx.h>
25 #include <fdt_support.h>
28 #include <asm-generic/gpio.h>
29 #include <dm/pinctrl.h>
31 #if !CONFIG_IS_ENABLED(BLK)
32 #include "mmc_private.h"
35 DECLARE_GLOBAL_DATA_PTR;
37 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
39 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
40 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
41 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
43 #define MAX_TUNING_LOOP 40
44 #define ESDHC_DRIVER_STAGE_VALUE 0xffffffff
47 uint dsaddr; /* SDMA system address register */
48 uint blkattr; /* Block attributes register */
49 uint cmdarg; /* Command argument register */
50 uint xfertyp; /* Transfer type register */
51 uint cmdrsp0; /* Command response 0 register */
52 uint cmdrsp1; /* Command response 1 register */
53 uint cmdrsp2; /* Command response 2 register */
54 uint cmdrsp3; /* Command response 3 register */
55 uint datport; /* Buffer data port register */
56 uint prsstat; /* Present state register */
57 uint proctl; /* Protocol control register */
58 uint sysctl; /* System Control Register */
59 uint irqstat; /* Interrupt status register */
60 uint irqstaten; /* Interrupt status enable register */
61 uint irqsigen; /* Interrupt signal enable register */
62 uint autoc12err; /* Auto CMD error status register */
63 uint hostcapblt; /* Host controller capabilities register */
64 uint wml; /* Watermark level register */
65 uint mixctrl; /* For USDHC */
66 char reserved1[4]; /* reserved */
67 uint fevt; /* Force event register */
68 uint admaes; /* ADMA error status register */
69 uint adsaddr; /* ADMA system address register */
73 uint clktunectrlstatus;
81 uint tuning_ctrl; /* on i.MX6/7/8 */
83 uint hostver; /* Host controller version register */
84 char reserved6[4]; /* reserved */
85 uint dmaerraddr; /* DMA error address register */
86 char reserved7[4]; /* reserved */
87 uint dmaerrattr; /* DMA error attribute register */
88 char reserved8[4]; /* reserved */
89 uint hostcapblt2; /* Host controller capabilities register 2 */
90 char reserved9[8]; /* reserved */
91 uint tcr; /* Tuning control register */
92 char reserved10[28]; /* reserved */
93 uint sddirctl; /* SD direction control register */
94 char reserved11[712];/* reserved */
95 uint scr; /* eSDHC control register */
98 struct fsl_esdhc_plat {
99 struct mmc_config cfg;
103 struct esdhc_soc_data {
108 * struct fsl_esdhc_priv
110 * @esdhc_regs: registers of the sdhc controller
111 * @sdhc_clk: Current clk of the sdhc controller
112 * @bus_width: bus width, 1bit, 4bit or 8bit
115 * Following is used when Driver Model is enabled for MMC
116 * @dev: pointer for the device
117 * @non_removable: 0: removable; 1: non-removable
118 * @broken_cd: 0: use GPIO for card detect; 1: Do not use GPIO for card detect
119 * @wp_enable: 1: enable checking wp; 0: no check
120 * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
121 * @flags: ESDHC_FLAG_xx in include/fsl_esdhc_imx.h
122 * @caps: controller capabilities
123 * @tuning_step: tuning step setting in tuning_ctrl register
124 * @start_tuning_tap: the start point for tuning in tuning_ctrl register
125 * @strobe_dll_delay_target: settings in strobe_dllctrl
126 * @signal_voltage: indicating the current voltage
127 * @cd_gpio: gpio for card detection
128 * @wp_gpio: gpio for write protection
130 struct fsl_esdhc_priv {
131 struct fsl_esdhc *esdhc_regs;
132 unsigned int sdhc_clk;
136 unsigned int bus_width;
137 #if !CONFIG_IS_ENABLED(BLK)
148 u32 tuning_start_tap;
149 u32 strobe_dll_delay_target;
151 #if CONFIG_IS_ENABLED(DM_REGULATOR)
152 struct udevice *vqmmc_dev;
153 struct udevice *vmmc_dev;
155 #if CONFIG_IS_ENABLED(DM_GPIO)
156 struct gpio_desc cd_gpio;
157 struct gpio_desc wp_gpio;
161 /* Return the XFERTYP flags for a given command and data packet */
162 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
167 xfertyp |= XFERTYP_DPSEL;
168 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
169 xfertyp |= XFERTYP_DMAEN;
171 if (data->blocks > 1) {
172 xfertyp |= XFERTYP_MSBSEL;
173 xfertyp |= XFERTYP_BCEN;
174 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
175 xfertyp |= XFERTYP_AC12EN;
179 if (data->flags & MMC_DATA_READ)
180 xfertyp |= XFERTYP_DTDSEL;
183 if (cmd->resp_type & MMC_RSP_CRC)
184 xfertyp |= XFERTYP_CCCEN;
185 if (cmd->resp_type & MMC_RSP_OPCODE)
186 xfertyp |= XFERTYP_CICEN;
187 if (cmd->resp_type & MMC_RSP_136)
188 xfertyp |= XFERTYP_RSPTYP_136;
189 else if (cmd->resp_type & MMC_RSP_BUSY)
190 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
191 else if (cmd->resp_type & MMC_RSP_PRESENT)
192 xfertyp |= XFERTYP_RSPTYP_48;
194 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
195 xfertyp |= XFERTYP_CMDTYP_ABORT;
197 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
200 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
202 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
204 static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
205 struct mmc_data *data)
207 struct fsl_esdhc *regs = priv->esdhc_regs;
215 if (data->flags & MMC_DATA_READ) {
216 blocks = data->blocks;
219 start = get_timer(0);
220 size = data->blocksize;
221 irqstat = esdhc_read32(®s->irqstat);
222 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)) {
223 if (get_timer(start) > PIO_TIMEOUT) {
224 printf("\nData Read Failed in PIO Mode.");
228 while (size && (!(irqstat & IRQSTAT_TC))) {
229 udelay(100); /* Wait before last byte transfer complete */
230 irqstat = esdhc_read32(®s->irqstat);
231 databuf = in_le32(®s->datport);
232 *((uint *)buffer) = databuf;
239 blocks = data->blocks;
240 buffer = (char *)data->src;
242 start = get_timer(0);
243 size = data->blocksize;
244 irqstat = esdhc_read32(®s->irqstat);
245 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)) {
246 if (get_timer(start) > PIO_TIMEOUT) {
247 printf("\nData Write Failed in PIO Mode.");
251 while (size && (!(irqstat & IRQSTAT_TC))) {
252 udelay(100); /* Wait before last byte transfer complete */
253 databuf = *((uint *)buffer);
256 irqstat = esdhc_read32(®s->irqstat);
257 out_le32(®s->datport, databuf);
265 static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
266 struct mmc_data *data)
269 struct fsl_esdhc *regs = priv->esdhc_regs;
270 #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
275 wml_value = data->blocksize/4;
277 if (data->flags & MMC_DATA_READ) {
278 if (wml_value > WML_RD_WML_MAX)
279 wml_value = WML_RD_WML_MAX_VAL;
281 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
282 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
283 #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
284 addr = virt_to_phys((void *)(data->dest));
285 if (upper_32_bits(addr))
286 printf("Error found for upper 32 bits\n");
288 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
290 esdhc_write32(®s->dsaddr, (u32)data->dest);
294 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
295 flush_dcache_range((ulong)data->src,
296 (ulong)data->src+data->blocks
299 if (wml_value > WML_WR_WML_MAX)
300 wml_value = WML_WR_WML_MAX_VAL;
301 if (priv->wp_enable) {
302 if ((esdhc_read32(®s->prsstat) &
303 PRSSTAT_WPSPL) == 0) {
304 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
308 #if CONFIG_IS_ENABLED(DM_GPIO)
309 if (dm_gpio_is_valid(&priv->wp_gpio) &&
310 dm_gpio_get_value(&priv->wp_gpio)) {
311 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
317 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
319 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
320 #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
321 addr = virt_to_phys((void *)(data->src));
322 if (upper_32_bits(addr))
323 printf("Error found for upper 32 bits\n");
325 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
327 esdhc_write32(®s->dsaddr, (u32)data->src);
332 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
334 /* Calculate the timeout period for data transactions */
336 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
337 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
338 * So, Number of SD Clock cycles for 0.25sec should be minimum
339 * (SD Clock/sec * 0.25 sec) SD Clock cycles
340 * = (mmc->clock * 1/4) SD Clock cycles
342 * => (2^(timeout+13)) >= mmc->clock * 1/4
343 * Taking log2 both the sides
344 * => timeout + 13 >= log2(mmc->clock/4)
345 * Rounding up to next power of 2
346 * => timeout + 13 = log2(mmc->clock/4) + 1
347 * => timeout + 13 = fls(mmc->clock/4)
349 * However, the MMC spec "It is strongly recommended for hosts to
350 * implement more than 500ms timeout value even if the card
351 * indicates the 250ms maximum busy length." Even the previous
352 * value of 300ms is known to be insufficient for some cards.
354 * => timeout + 13 = fls(mmc->clock/2)
356 timeout = fls(mmc->clock/2);
365 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
366 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
370 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
373 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
378 static void check_and_invalidate_dcache_range
379 (struct mmc_cmd *cmd,
380 struct mmc_data *data) {
383 unsigned size = roundup(ARCH_DMA_MINALIGN,
384 data->blocks*data->blocksize);
385 #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
388 addr = virt_to_phys((void *)(data->dest));
389 if (upper_32_bits(addr))
390 printf("Error found for upper 32 bits\n");
392 start = lower_32_bits(addr);
394 start = (unsigned)data->dest;
397 invalidate_dcache_range(start, end);
400 #ifdef CONFIG_MCF5441x
402 * Swaps 32-bit words to little-endian byte order.
404 static inline void sd_swap_dma_buff(struct mmc_data *data)
406 int i, size = data->blocksize >> 2;
407 u32 *buffer = (u32 *)data->dest;
410 while (data->blocks--) {
411 for (i = 0; i < size; i++) {
412 sw = __sw32(*buffer);
420 * Sends a command out on the bus. Takes the mmc pointer,
421 * a command pointer, and an optional data pointer.
423 static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
424 struct mmc_cmd *cmd, struct mmc_data *data)
429 u32 flags = IRQSTAT_CC | IRQSTAT_CTOE;
430 struct fsl_esdhc *regs = priv->esdhc_regs;
433 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
434 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
438 esdhc_write32(®s->irqstat, -1);
442 /* Wait for the bus to be idle */
443 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
444 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
447 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
450 /* Wait at least 8 SD clock cycles before the next command */
452 * Note: This is way more than 8 cycles, but 1ms seems to
453 * resolve timing issues with some cards
457 /* Set up for a data transfer if we have one */
459 err = esdhc_setup_data(priv, mmc, data);
463 if (data->flags & MMC_DATA_READ)
464 check_and_invalidate_dcache_range(cmd, data);
467 /* Figure out the transfer arguments */
468 xfertyp = esdhc_xfertyp(cmd, data);
471 esdhc_write32(®s->irqsigen, 0);
473 /* Send the command */
474 esdhc_write32(®s->cmdarg, cmd->cmdarg);
475 #if defined(CONFIG_FSL_USDHC)
476 esdhc_write32(®s->mixctrl,
477 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
478 | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
479 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000);
481 esdhc_write32(®s->xfertyp, xfertyp);
484 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
485 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))
488 /* Wait for the command to complete */
489 start = get_timer(0);
490 while (!(esdhc_read32(®s->irqstat) & flags)) {
491 if (get_timer(start) > 1000) {
497 irqstat = esdhc_read32(®s->irqstat);
499 if (irqstat & CMD_ERR) {
504 if (irqstat & IRQSTAT_CTOE) {
509 /* Switch voltage to 1.8V if CMD11 succeeded */
510 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
511 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
513 printf("Run CMD11 1.8V switch\n");
514 /* Sleep for 5 ms - max time for card to switch to 1.8V */
518 /* Workaround for ESDHC errata ENGcm03648 */
519 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
522 /* Poll on DATA0 line for cmd with busy signal for 5000 ms */
523 while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
530 printf("Timeout waiting for DAT0 to go high!\n");
536 /* Copy the response to the response buffer */
537 if (cmd->resp_type & MMC_RSP_136) {
538 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
540 cmdrsp3 = esdhc_read32(®s->cmdrsp3);
541 cmdrsp2 = esdhc_read32(®s->cmdrsp2);
542 cmdrsp1 = esdhc_read32(®s->cmdrsp1);
543 cmdrsp0 = esdhc_read32(®s->cmdrsp0);
544 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
545 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
546 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
547 cmd->response[3] = (cmdrsp0 << 8);
549 cmd->response[0] = esdhc_read32(®s->cmdrsp0);
551 /* Wait until all of the blocks are transferred */
553 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
554 esdhc_pio_read_write(priv, data);
556 flags = DATA_COMPLETE;
557 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
558 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) {
563 irqstat = esdhc_read32(®s->irqstat);
565 if (irqstat & IRQSTAT_DTOE) {
570 if (irqstat & DATA_ERR) {
574 } while ((irqstat & flags) != flags);
577 * Need invalidate the dcache here again to avoid any
578 * cache-fill during the DMA operations such as the
579 * speculative pre-fetching etc.
581 if (data->flags & MMC_DATA_READ) {
582 check_and_invalidate_dcache_range(cmd, data);
583 #ifdef CONFIG_MCF5441x
584 sd_swap_dma_buff(data);
591 /* Reset CMD and DATA portions on error */
593 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
595 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC)
599 esdhc_write32(®s->sysctl,
600 esdhc_read32(®s->sysctl) |
602 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
606 /* If this was CMD11, then notify that power cycle is needed */
607 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
608 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
611 esdhc_write32(®s->irqstat, -1);
616 static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
618 struct fsl_esdhc *regs = priv->esdhc_regs;
622 /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
623 int pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1;
630 int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
631 int sdhc_clk = priv->sdhc_clk;
634 while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
637 while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
643 clk = (pre_div << 8) | (div << 4);
645 #ifdef CONFIG_FSL_USDHC
646 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
648 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
651 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
655 #ifdef CONFIG_FSL_USDHC
656 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
658 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
664 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
665 static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
667 struct fsl_esdhc *regs = priv->esdhc_regs;
671 value = esdhc_read32(®s->sysctl);
674 value |= SYSCTL_CKEN;
676 value &= ~SYSCTL_CKEN;
678 esdhc_write32(®s->sysctl, value);
681 value = PRSSTAT_SDSTB;
682 while (!(esdhc_read32(®s->prsstat) & value)) {
684 printf("fsl_esdhc: Internal clock never stabilised.\n");
693 #ifdef MMC_SUPPORTS_TUNING
694 static int esdhc_change_pinstate(struct udevice *dev)
696 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
699 switch (priv->mode) {
702 ret = pinctrl_select_state(dev, "state_100mhz");
708 ret = pinctrl_select_state(dev, "state_200mhz");
711 ret = pinctrl_select_state(dev, "default");
716 printf("%s %d error\n", __func__, priv->mode);
721 static void esdhc_reset_tuning(struct mmc *mmc)
723 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
724 struct fsl_esdhc *regs = priv->esdhc_regs;
726 if (priv->flags & ESDHC_FLAG_USDHC) {
727 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
728 esdhc_clrbits32(®s->autoc12err,
729 MIX_CTRL_SMPCLK_SEL |
735 static void esdhc_set_strobe_dll(struct mmc *mmc)
737 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
738 struct fsl_esdhc *regs = priv->esdhc_regs;
741 if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
742 writel(ESDHC_STROBE_DLL_CTRL_RESET, ®s->strobe_dllctrl);
745 * enable strobe dll ctrl and adjust the delay target
746 * for the uSDHC loopback read clock
748 val = ESDHC_STROBE_DLL_CTRL_ENABLE |
749 (priv->strobe_dll_delay_target <<
750 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
751 writel(val, ®s->strobe_dllctrl);
752 /* wait 1us to make sure strobe dll status register stable */
754 val = readl(®s->strobe_dllstat);
755 if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK))
756 pr_warn("HS400 strobe DLL status REF not lock!\n");
757 if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK))
758 pr_warn("HS400 strobe DLL status SLV not lock!\n");
762 static int esdhc_set_timing(struct mmc *mmc)
764 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
765 struct fsl_esdhc *regs = priv->esdhc_regs;
768 mixctrl = readl(®s->mixctrl);
769 mixctrl &= ~(MIX_CTRL_DDREN | MIX_CTRL_HS400_EN);
771 switch (mmc->selected_mode) {
774 esdhc_reset_tuning(mmc);
775 writel(mixctrl, ®s->mixctrl);
779 mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN;
780 writel(mixctrl, ®s->mixctrl);
781 esdhc_set_strobe_dll(mmc);
791 writel(mixctrl, ®s->mixctrl);
795 mixctrl |= MIX_CTRL_DDREN;
796 writel(mixctrl, ®s->mixctrl);
799 printf("Not supported %d\n", mmc->selected_mode);
803 priv->mode = mmc->selected_mode;
805 return esdhc_change_pinstate(mmc->dev);
808 static int esdhc_set_voltage(struct mmc *mmc)
810 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
811 struct fsl_esdhc *regs = priv->esdhc_regs;
814 priv->signal_voltage = mmc->signal_voltage;
815 switch (mmc->signal_voltage) {
816 case MMC_SIGNAL_VOLTAGE_330:
817 if (priv->vs18_enable)
819 #if CONFIG_IS_ENABLED(DM_REGULATOR)
820 if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
821 ret = regulator_set_value(priv->vqmmc_dev, 3300000);
823 printf("Setting to 3.3V error");
831 esdhc_clrbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
832 if (!(esdhc_read32(®s->vendorspec) &
833 ESDHC_VENDORSPEC_VSELECT))
837 case MMC_SIGNAL_VOLTAGE_180:
838 #if CONFIG_IS_ENABLED(DM_REGULATOR)
839 if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
840 ret = regulator_set_value(priv->vqmmc_dev, 1800000);
842 printf("Setting to 1.8V error");
847 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
848 if (esdhc_read32(®s->vendorspec) & ESDHC_VENDORSPEC_VSELECT)
852 case MMC_SIGNAL_VOLTAGE_120:
859 static void esdhc_stop_tuning(struct mmc *mmc)
863 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
865 cmd.resp_type = MMC_RSP_R1b;
867 dm_mmc_send_cmd(mmc->dev, &cmd, NULL);
870 static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
872 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
873 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
874 struct fsl_esdhc *regs = priv->esdhc_regs;
875 struct mmc *mmc = &plat->mmc;
876 u32 irqstaten = readl(®s->irqstaten);
877 u32 irqsigen = readl(®s->irqsigen);
878 int i, ret = -ETIMEDOUT;
881 /* clock tuning is not needed for upto 52MHz */
882 if (mmc->clock <= 52000000)
885 /* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */
886 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
887 val = readl(®s->autoc12err);
888 mixctrl = readl(®s->mixctrl);
889 val &= ~MIX_CTRL_SMPCLK_SEL;
890 mixctrl &= ~(MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN);
892 val |= MIX_CTRL_EXE_TUNE;
893 mixctrl |= MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN;
895 writel(val, ®s->autoc12err);
896 writel(mixctrl, ®s->mixctrl);
899 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); */
900 mixctrl = readl(®s->mixctrl);
901 mixctrl = MIX_CTRL_DTDSEL_READ | (mixctrl & ~MIX_CTRL_SDHCI_MASK);
902 writel(mixctrl, ®s->mixctrl);
904 writel(IRQSTATEN_BRR, ®s->irqstaten);
905 writel(IRQSTATEN_BRR, ®s->irqsigen);
908 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
909 * of loops reaches 40 times.
911 for (i = 0; i < MAX_TUNING_LOOP; i++) {
914 if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) {
915 if (mmc->bus_width == 8)
916 writel(0x7080, ®s->blkattr);
917 else if (mmc->bus_width == 4)
918 writel(0x7040, ®s->blkattr);
920 writel(0x7040, ®s->blkattr);
923 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE) */
924 val = readl(®s->mixctrl);
925 val = MIX_CTRL_DTDSEL_READ | (val & ~MIX_CTRL_SDHCI_MASK);
926 writel(val, ®s->mixctrl);
928 /* We are using STD tuning, no need to check return value */
929 mmc_send_tuning(mmc, opcode, NULL);
931 ctrl = readl(®s->autoc12err);
932 if ((!(ctrl & MIX_CTRL_EXE_TUNE)) &&
933 (ctrl & MIX_CTRL_SMPCLK_SEL)) {
935 * need to wait some time, make sure sd/mmc fininsh
936 * send out tuning data, otherwise, the sd/mmc can't
937 * response to any command when the card still out
938 * put the tuning data.
945 /* Add 1ms delay for SD and eMMC */
949 writel(irqstaten, ®s->irqstaten);
950 writel(irqsigen, ®s->irqsigen);
952 esdhc_stop_tuning(mmc);
958 static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
960 struct fsl_esdhc *regs = priv->esdhc_regs;
961 int ret __maybe_unused;
964 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
965 /* Select to use peripheral clock */
966 esdhc_clock_control(priv, false);
967 esdhc_setbits32(®s->scr, ESDHCCTL_PCS);
968 esdhc_clock_control(priv, true);
970 /* Set the clock speed */
972 if (clock < mmc->cfg->f_min)
973 clock = mmc->cfg->f_min;
975 if (priv->clock != clock)
976 set_sysctl(priv, mmc, clock);
978 #ifdef MMC_SUPPORTS_TUNING
979 if (mmc->clk_disable) {
980 #ifdef CONFIG_FSL_USDHC
981 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
983 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
986 #ifdef CONFIG_FSL_USDHC
987 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
990 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
994 if (priv->mode != mmc->selected_mode) {
995 ret = esdhc_set_timing(mmc);
997 printf("esdhc_set_timing error %d\n", ret);
1002 if (priv->signal_voltage != mmc->signal_voltage) {
1003 ret = esdhc_set_voltage(mmc);
1005 printf("esdhc_set_voltage error %d\n", ret);
1011 /* Set the bus width */
1012 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
1014 if (mmc->bus_width == 4)
1015 esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
1016 else if (mmc->bus_width == 8)
1017 esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
1022 static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
1024 struct fsl_esdhc *regs = priv->esdhc_regs;
1027 /* Reset the entire host controller */
1028 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
1030 /* Wait until the controller is available */
1031 start = get_timer(0);
1032 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
1033 if (get_timer(start) > 1000)
1037 #if defined(CONFIG_FSL_USDHC)
1038 /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
1039 esdhc_write32(®s->mmcboot, 0x0);
1040 /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
1041 esdhc_write32(®s->mixctrl, 0x0);
1042 esdhc_write32(®s->clktunectrlstatus, 0x0);
1044 /* Put VEND_SPEC to default value */
1045 if (priv->vs18_enable)
1046 esdhc_write32(®s->vendorspec, (VENDORSPEC_INIT |
1047 ESDHC_VENDORSPEC_VSELECT));
1049 esdhc_write32(®s->vendorspec, VENDORSPEC_INIT);
1051 /* Disable DLL_CTRL delay line */
1052 esdhc_write32(®s->dllctrl, 0x0);
1056 /* Enable cache snooping */
1057 esdhc_write32(®s->scr, 0x00000040);
1060 #ifndef CONFIG_FSL_USDHC
1061 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
1063 esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
1066 /* Set the initial clock speed */
1067 mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
1069 /* Disable the BRR and BWR bits in IRQSTAT */
1070 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
1072 #ifdef CONFIG_MCF5441x
1073 esdhc_write32(®s->proctl, PROCTL_INIT | PROCTL_D3CD);
1075 /* Put the PROCTL reg back to the default */
1076 esdhc_write32(®s->proctl, PROCTL_INIT);
1079 /* Set timout to the maximum value */
1080 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
1085 static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
1087 struct fsl_esdhc *regs = priv->esdhc_regs;
1090 #ifdef CONFIG_ESDHC_DETECT_QUIRK
1091 if (CONFIG_ESDHC_DETECT_QUIRK)
1095 #if CONFIG_IS_ENABLED(DM_MMC)
1096 if (priv->non_removable)
1099 if (priv->broken_cd)
1101 #if CONFIG_IS_ENABLED(DM_GPIO)
1102 if (dm_gpio_is_valid(&priv->cd_gpio))
1103 return dm_gpio_get_value(&priv->cd_gpio);
1107 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
1113 static int esdhc_reset(struct fsl_esdhc *regs)
1117 /* reset the controller */
1118 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
1120 /* hardware clears the bit when it is done */
1121 start = get_timer(0);
1122 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
1123 if (get_timer(start) > 100) {
1124 printf("MMC/SD: Reset never completed.\n");
1132 #if !CONFIG_IS_ENABLED(DM_MMC)
1133 static int esdhc_getcd(struct mmc *mmc)
1135 struct fsl_esdhc_priv *priv = mmc->priv;
1137 return esdhc_getcd_common(priv);
1140 static int esdhc_init(struct mmc *mmc)
1142 struct fsl_esdhc_priv *priv = mmc->priv;
1144 return esdhc_init_common(priv, mmc);
1147 static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
1148 struct mmc_data *data)
1150 struct fsl_esdhc_priv *priv = mmc->priv;
1152 return esdhc_send_cmd_common(priv, mmc, cmd, data);
1155 static int esdhc_set_ios(struct mmc *mmc)
1157 struct fsl_esdhc_priv *priv = mmc->priv;
1159 return esdhc_set_ios_common(priv, mmc);
1162 static const struct mmc_ops esdhc_ops = {
1163 .getcd = esdhc_getcd,
1165 .send_cmd = esdhc_send_cmd,
1166 .set_ios = esdhc_set_ios,
1170 static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
1171 struct fsl_esdhc_plat *plat)
1173 struct mmc_config *cfg;
1174 struct fsl_esdhc *regs;
1175 u32 caps, voltage_caps;
1181 regs = priv->esdhc_regs;
1183 /* First reset the eSDHC controller */
1184 ret = esdhc_reset(regs);
1188 #ifdef CONFIG_MCF5441x
1189 /* ColdFire, using SDHC_DATA[3] for card detection */
1190 esdhc_write32(®s->proctl, PROCTL_INIT | PROCTL_D3CD);
1193 #ifndef CONFIG_FSL_USDHC
1194 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
1195 | SYSCTL_IPGEN | SYSCTL_CKEN);
1196 /* Clearing tuning bits in case ROM has set it already */
1197 esdhc_write32(®s->mixctrl, 0);
1198 esdhc_write32(®s->autoc12err, 0);
1199 esdhc_write32(®s->clktunectrlstatus, 0);
1201 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
1202 VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
1205 if (priv->vs18_enable)
1206 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
1208 writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
1210 #ifndef CONFIG_DM_MMC
1211 memset(cfg, '\0', sizeof(*cfg));
1215 caps = esdhc_read32(®s->hostcapblt);
1217 #ifdef CONFIG_MCF5441x
1219 * MCF5441x RM declares in more points that sdhc clock speed must
1220 * never exceed 25 Mhz. From this, the HS bit needs to be disabled
1221 * from host capabilities.
1223 caps &= ~ESDHC_HOSTCAPBLT_HSS;
1226 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
1227 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
1228 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
1231 /* T4240 host controller capabilities register should have VS33 bit */
1232 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
1233 caps = caps | ESDHC_HOSTCAPBLT_VS33;
1236 if (caps & ESDHC_HOSTCAPBLT_VS18)
1237 voltage_caps |= MMC_VDD_165_195;
1238 if (caps & ESDHC_HOSTCAPBLT_VS30)
1239 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
1240 if (caps & ESDHC_HOSTCAPBLT_VS33)
1241 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
1243 cfg->name = "FSL_SDHC";
1244 #if !CONFIG_IS_ENABLED(DM_MMC)
1245 cfg->ops = &esdhc_ops;
1247 #ifdef CONFIG_SYS_SD_VOLTAGE
1248 cfg->voltages = CONFIG_SYS_SD_VOLTAGE;
1250 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
1252 if ((cfg->voltages & voltage_caps) == 0) {
1253 printf("voltage not supported by controller\n");
1257 if (priv->bus_width == 8)
1258 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
1259 else if (priv->bus_width == 4)
1260 cfg->host_caps = MMC_MODE_4BIT;
1262 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
1263 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
1264 cfg->host_caps |= MMC_MODE_DDR_52MHz;
1267 if (priv->bus_width > 0) {
1268 if (priv->bus_width < 8)
1269 cfg->host_caps &= ~MMC_MODE_8BIT;
1270 if (priv->bus_width < 4)
1271 cfg->host_caps &= ~MMC_MODE_4BIT;
1274 if (caps & ESDHC_HOSTCAPBLT_HSS)
1275 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1277 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
1278 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
1279 cfg->host_caps &= ~MMC_MODE_8BIT;
1282 cfg->host_caps |= priv->caps;
1284 cfg->f_min = 400000;
1285 cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
1287 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1289 writel(0, ®s->dllctrl);
1290 if (priv->flags & ESDHC_FLAG_USDHC) {
1291 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
1292 u32 val = readl(®s->tuning_ctrl);
1294 val |= ESDHC_STD_TUNING_EN;
1295 val &= ~ESDHC_TUNING_START_TAP_MASK;
1296 val |= priv->tuning_start_tap;
1297 val &= ~ESDHC_TUNING_STEP_MASK;
1298 val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT;
1299 writel(val, ®s->tuning_ctrl);
1306 #if !CONFIG_IS_ENABLED(DM_MMC)
1307 static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
1308 struct fsl_esdhc_priv *priv)
1313 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
1314 priv->bus_width = cfg->max_bus_width;
1315 priv->sdhc_clk = cfg->sdhc_clk;
1316 priv->wp_enable = cfg->wp_enable;
1317 priv->vs18_enable = cfg->vs18_enable;
1322 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
1324 struct fsl_esdhc_plat *plat;
1325 struct fsl_esdhc_priv *priv;
1332 priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
1335 plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
1341 ret = fsl_esdhc_cfg_to_priv(cfg, priv);
1343 debug("%s xlate failure\n", __func__);
1349 ret = fsl_esdhc_init(priv, plat);
1351 debug("%s init failure\n", __func__);
1357 mmc = mmc_create(&plat->cfg, priv);
1366 int fsl_esdhc_mmc_init(bd_t *bis)
1368 struct fsl_esdhc_cfg *cfg;
1370 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
1371 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
1372 cfg->sdhc_clk = gd->arch.sdhc_clk;
1373 return fsl_esdhc_initialize(bis, cfg);
1377 #ifdef CONFIG_OF_LIBFDT
1378 __weak int esdhc_status_fixup(void *blob, const char *compat)
1380 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
1381 if (!hwconfig("esdhc")) {
1382 do_fixup_by_compat(blob, compat, "status", "disabled",
1383 sizeof("disabled"), 1);
1390 void fdt_fixup_esdhc(void *blob, bd_t *bd)
1392 const char *compat = "fsl,esdhc";
1394 if (esdhc_status_fixup(blob, compat))
1397 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
1398 do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
1399 gd->arch.sdhc_clk, 1);
1401 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
1402 gd->arch.sdhc_clk, 1);
1407 #if CONFIG_IS_ENABLED(DM_MMC)
1408 #include <asm/arch/clock.h>
1409 __weak void init_clk_usdhc(u32 index)
1413 static int fsl_esdhc_probe(struct udevice *dev)
1415 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1416 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1417 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1418 const void *fdt = gd->fdt_blob;
1419 int node = dev_of_offset(dev);
1420 struct esdhc_soc_data *data =
1421 (struct esdhc_soc_data *)dev_get_driver_data(dev);
1422 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1423 struct udevice *vqmmc_dev;
1428 #if !CONFIG_IS_ENABLED(BLK)
1429 struct blk_desc *bdesc;
1433 addr = dev_read_addr(dev);
1434 if (addr == FDT_ADDR_T_NONE)
1436 priv->esdhc_regs = (struct fsl_esdhc *)addr;
1440 priv->flags = data->flags;
1442 val = dev_read_u32_default(dev, "bus-width", -1);
1444 priv->bus_width = 8;
1446 priv->bus_width = 4;
1448 priv->bus_width = 1;
1450 val = fdtdec_get_int(fdt, node, "fsl,tuning-step", 1);
1451 priv->tuning_step = val;
1452 val = fdtdec_get_int(fdt, node, "fsl,tuning-start-tap",
1453 ESDHC_TUNING_START_TAP_DEFAULT);
1454 priv->tuning_start_tap = val;
1455 val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target",
1456 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT);
1457 priv->strobe_dll_delay_target = val;
1459 if (dev_read_bool(dev, "broken-cd"))
1460 priv->broken_cd = 1;
1462 if (dev_read_bool(dev, "non-removable")) {
1463 priv->non_removable = 1;
1465 priv->non_removable = 0;
1466 #if CONFIG_IS_ENABLED(DM_GPIO)
1467 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
1472 if (dev_read_prop(dev, "fsl,wp-controller", NULL)) {
1473 priv->wp_enable = 1;
1475 priv->wp_enable = 0;
1476 #if CONFIG_IS_ENABLED(DM_GPIO)
1477 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
1482 priv->vs18_enable = 0;
1484 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1486 * If emmc I/O has a fixed voltage at 1.8V, this must be provided,
1487 * otherwise, emmc will work abnormally.
1489 ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
1491 dev_dbg(dev, "no vqmmc-supply\n");
1493 ret = regulator_set_enable(vqmmc_dev, true);
1495 dev_err(dev, "fail to enable vqmmc-supply\n");
1499 if (regulator_get_value(vqmmc_dev) == 1800000)
1500 priv->vs18_enable = 1;
1506 * Because lack of clk driver, if SDHC clk is not enabled,
1507 * need to enable it first before this driver is invoked.
1509 * we use MXC_ESDHC_CLK to get clk freq.
1510 * If one would like to make this function work,
1511 * the aliases should be provided in dts as this:
1519 * Then if your board only supports mmc2 and mmc3, but we can
1520 * correctly get the seq as 2 and 3, then let mxc_get_clock
1524 init_clk_usdhc(dev->seq);
1526 if (CONFIG_IS_ENABLED(CLK)) {
1527 /* Assigned clock already set clock */
1528 ret = clk_get_by_name(dev, "per", &priv->per_clk);
1530 printf("Failed to get per_clk\n");
1533 ret = clk_enable(&priv->per_clk);
1535 printf("Failed to enable per_clk\n");
1539 priv->sdhc_clk = clk_get_rate(&priv->per_clk);
1541 priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
1542 if (priv->sdhc_clk <= 0) {
1543 dev_err(dev, "Unable to get clk for %s\n", dev->name);
1548 ret = fsl_esdhc_init(priv, plat);
1550 dev_err(dev, "fsl_esdhc_init failure\n");
1554 ret = mmc_of_parse(dev, &plat->cfg);
1559 mmc->cfg = &plat->cfg;
1561 #if !CONFIG_IS_ENABLED(BLK)
1564 /* Setup dsr related values */
1566 mmc->dsr = ESDHC_DRIVER_STAGE_VALUE;
1567 /* Setup the universal parts of the block interface just once */
1568 bdesc = mmc_get_blk_desc(mmc);
1569 bdesc->if_type = IF_TYPE_MMC;
1570 bdesc->removable = 1;
1571 bdesc->devnum = mmc_get_next_devnum();
1572 bdesc->block_read = mmc_bread;
1573 bdesc->block_write = mmc_bwrite;
1574 bdesc->block_erase = mmc_berase;
1576 /* setup initial part type */
1577 bdesc->part_type = mmc->cfg->part_type;
1583 return esdhc_init_common(priv, mmc);
1586 #if CONFIG_IS_ENABLED(DM_MMC)
1587 static int fsl_esdhc_get_cd(struct udevice *dev)
1589 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1591 return esdhc_getcd_common(priv);
1594 static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1595 struct mmc_data *data)
1597 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1598 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1600 return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
1603 static int fsl_esdhc_set_ios(struct udevice *dev)
1605 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1606 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1608 return esdhc_set_ios_common(priv, &plat->mmc);
1611 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
1612 static int fsl_esdhc_set_enhanced_strobe(struct udevice *dev)
1614 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1615 struct fsl_esdhc *regs = priv->esdhc_regs;
1618 m = readl(®s->mixctrl);
1619 m |= MIX_CTRL_HS400_ES;
1620 writel(m, ®s->mixctrl);
1626 static const struct dm_mmc_ops fsl_esdhc_ops = {
1627 .get_cd = fsl_esdhc_get_cd,
1628 .send_cmd = fsl_esdhc_send_cmd,
1629 .set_ios = fsl_esdhc_set_ios,
1630 #ifdef MMC_SUPPORTS_TUNING
1631 .execute_tuning = fsl_esdhc_execute_tuning,
1633 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
1634 .set_enhanced_strobe = fsl_esdhc_set_enhanced_strobe,
1639 static struct esdhc_soc_data usdhc_imx7d_data = {
1640 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
1641 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
1645 static struct esdhc_soc_data usdhc_imx8qm_data = {
1646 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING |
1647 ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 |
1648 ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES,
1651 static const struct udevice_id fsl_esdhc_ids[] = {
1652 { .compatible = "fsl,imx53-esdhc", },
1653 { .compatible = "fsl,imx6ul-usdhc", },
1654 { .compatible = "fsl,imx6sx-usdhc", },
1655 { .compatible = "fsl,imx6sl-usdhc", },
1656 { .compatible = "fsl,imx6q-usdhc", },
1657 { .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,},
1658 { .compatible = "fsl,imx7ulp-usdhc", },
1659 { .compatible = "fsl,imx8qm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
1660 { .compatible = "fsl,imx8mm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
1661 { .compatible = "fsl,imx8mn-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
1662 { .compatible = "fsl,imx8mq-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
1663 { .compatible = "fsl,esdhc", },
1667 #if CONFIG_IS_ENABLED(BLK)
1668 static int fsl_esdhc_bind(struct udevice *dev)
1670 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1672 return mmc_bind(dev, &plat->mmc, &plat->cfg);
1676 U_BOOT_DRIVER(fsl_esdhc) = {
1677 .name = "fsl-esdhc-mmc",
1679 .of_match = fsl_esdhc_ids,
1680 .ops = &fsl_esdhc_ops,
1681 #if CONFIG_IS_ENABLED(BLK)
1682 .bind = fsl_esdhc_bind,
1684 .probe = fsl_esdhc_probe,
1685 .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
1686 .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),