1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
4 * Copyright 2019, 2021 NXP
6 * Yangbo Lu <yangbo.lu@nxp.com>
8 * Based vaguely on the pxa mmc code:
10 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
23 #include <asm/cache.h>
24 #include <asm/global_data.h>
25 #include <dm/device_compat.h>
26 #include <linux/bitops.h>
27 #include <linux/delay.h>
28 #include <linux/err.h>
29 #include <power/regulator.h>
31 #include <fsl_esdhc_imx.h>
32 #include <fdt_support.h>
35 #include <asm-generic/gpio.h>
36 #include <dm/pinctrl.h>
37 #include <dt-structs.h>
39 #include <dm/ofnode.h>
40 #include <linux/iopoll.h>
42 #if !CONFIG_IS_ENABLED(BLK)
43 #include "mmc_private.h"
46 #ifndef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
47 #ifdef CONFIG_FSL_USDHC
48 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1
52 DECLARE_GLOBAL_DATA_PTR;
54 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
56 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
57 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
58 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
60 #define MAX_TUNING_LOOP 40
61 #define ESDHC_DRIVER_STAGE_VALUE 0xffffffff
64 uint dsaddr; /* SDMA system address register */
65 uint blkattr; /* Block attributes register */
66 uint cmdarg; /* Command argument register */
67 uint xfertyp; /* Transfer type register */
68 uint cmdrsp0; /* Command response 0 register */
69 uint cmdrsp1; /* Command response 1 register */
70 uint cmdrsp2; /* Command response 2 register */
71 uint cmdrsp3; /* Command response 3 register */
72 uint datport; /* Buffer data port register */
73 uint prsstat; /* Present state register */
74 uint proctl; /* Protocol control register */
75 uint sysctl; /* System Control Register */
76 uint irqstat; /* Interrupt status register */
77 uint irqstaten; /* Interrupt status enable register */
78 uint irqsigen; /* Interrupt signal enable register */
79 uint autoc12err; /* Auto CMD error status register */
80 uint hostcapblt; /* Host controller capabilities register */
81 uint wml; /* Watermark level register */
82 uint mixctrl; /* For USDHC */
83 char reserved1[4]; /* reserved */
84 uint fevt; /* Force event register */
85 uint admaes; /* ADMA error status register */
86 uint adsaddr; /* ADMA system address register */
90 uint clktunectrlstatus;
98 uint tuning_ctrl; /* on i.MX6/7/8/RT */
100 uint hostver; /* Host controller version register */
101 char reserved6[4]; /* reserved */
102 uint dmaerraddr; /* DMA error address register */
103 char reserved7[4]; /* reserved */
104 uint dmaerrattr; /* DMA error attribute register */
105 char reserved8[4]; /* reserved */
106 uint hostcapblt2; /* Host controller capabilities register 2 */
107 char reserved9[8]; /* reserved */
108 uint tcr; /* Tuning control register */
109 char reserved10[28]; /* reserved */
110 uint sddirctl; /* SD direction control register */
111 char reserved11[712];/* reserved */
112 uint scr; /* eSDHC control register */
115 struct fsl_esdhc_plat {
116 #if CONFIG_IS_ENABLED(OF_PLATDATA)
117 /* Put this first since driver model will copy the data here */
118 struct dtd_fsl_esdhc dtplat;
121 struct mmc_config cfg;
125 struct esdhc_soc_data {
130 * struct fsl_esdhc_priv
132 * @esdhc_regs: registers of the sdhc controller
133 * @sdhc_clk: Current clk of the sdhc controller
134 * @bus_width: bus width, 1bit, 4bit or 8bit
137 * Following is used when Driver Model is enabled for MMC
138 * @dev: pointer for the device
139 * @non_removable: 0: removable; 1: non-removable
140 * @broken_cd: 0: use GPIO for card detect; 1: Do not use GPIO for card detect
141 * @wp_enable: 1: enable checking wp; 0: no check
142 * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
143 * @flags: ESDHC_FLAG_xx in include/fsl_esdhc_imx.h
144 * @caps: controller capabilities
145 * @tuning_step: tuning step setting in tuning_ctrl register
146 * @start_tuning_tap: the start point for tuning in tuning_ctrl register
147 * @strobe_dll_delay_target: settings in strobe_dllctrl
148 * @signal_voltage: indicating the current voltage
149 * @signal_voltage_switch_extra_delay_ms: extra delay for IO voltage switch
150 * @cd_gpio: gpio for card detection
151 * @wp_gpio: gpio for write protection
153 struct fsl_esdhc_priv {
154 struct fsl_esdhc *esdhc_regs;
155 unsigned int sdhc_clk;
159 unsigned int bus_width;
160 #if !CONFIG_IS_ENABLED(BLK)
171 u32 tuning_start_tap;
172 u32 strobe_dll_delay_target;
174 u32 signal_voltage_switch_extra_delay_ms;
175 #if CONFIG_IS_ENABLED(DM_REGULATOR)
176 struct udevice *vqmmc_dev;
177 struct udevice *vmmc_dev;
179 #if CONFIG_IS_ENABLED(DM_GPIO)
180 struct gpio_desc cd_gpio;
181 struct gpio_desc wp_gpio;
185 /* Return the XFERTYP flags for a given command and data packet */
186 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
191 xfertyp |= XFERTYP_DPSEL;
192 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
193 xfertyp |= XFERTYP_DMAEN;
195 if (data->blocks > 1) {
196 xfertyp |= XFERTYP_MSBSEL;
197 xfertyp |= XFERTYP_BCEN;
198 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
199 xfertyp |= XFERTYP_AC12EN;
203 if (data->flags & MMC_DATA_READ)
204 xfertyp |= XFERTYP_DTDSEL;
207 if (cmd->resp_type & MMC_RSP_CRC)
208 xfertyp |= XFERTYP_CCCEN;
209 if (cmd->resp_type & MMC_RSP_OPCODE)
210 xfertyp |= XFERTYP_CICEN;
211 if (cmd->resp_type & MMC_RSP_136)
212 xfertyp |= XFERTYP_RSPTYP_136;
213 else if (cmd->resp_type & MMC_RSP_BUSY)
214 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
215 else if (cmd->resp_type & MMC_RSP_PRESENT)
216 xfertyp |= XFERTYP_RSPTYP_48;
218 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
219 xfertyp |= XFERTYP_CMDTYP_ABORT;
221 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
224 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
226 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
228 static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
229 struct mmc_data *data)
231 struct fsl_esdhc *regs = priv->esdhc_regs;
239 if (data->flags & MMC_DATA_READ) {
240 blocks = data->blocks;
243 start = get_timer(0);
244 size = data->blocksize;
245 irqstat = esdhc_read32(®s->irqstat);
246 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)) {
247 if (get_timer(start) > PIO_TIMEOUT) {
248 printf("\nData Read Failed in PIO Mode.");
252 while (size && (!(irqstat & IRQSTAT_TC))) {
253 udelay(100); /* Wait before last byte transfer complete */
254 irqstat = esdhc_read32(®s->irqstat);
255 databuf = in_le32(®s->datport);
256 *((uint *)buffer) = databuf;
263 blocks = data->blocks;
264 buffer = (char *)data->src;
266 start = get_timer(0);
267 size = data->blocksize;
268 irqstat = esdhc_read32(®s->irqstat);
269 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)) {
270 if (get_timer(start) > PIO_TIMEOUT) {
271 printf("\nData Write Failed in PIO Mode.");
275 while (size && (!(irqstat & IRQSTAT_TC))) {
276 udelay(100); /* Wait before last byte transfer complete */
277 databuf = *((uint *)buffer);
280 irqstat = esdhc_read32(®s->irqstat);
281 out_le32(®s->datport, databuf);
289 static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
290 struct mmc_data *data)
293 struct fsl_esdhc *regs = priv->esdhc_regs;
294 #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) || \
295 defined(CONFIG_IMX8ULP)
300 wml_value = data->blocksize/4;
302 if (data->flags & MMC_DATA_READ) {
303 if (wml_value > WML_RD_WML_MAX)
304 wml_value = WML_RD_WML_MAX_VAL;
306 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
307 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
308 #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) || \
309 defined(CONFIG_IMX8ULP)
310 addr = virt_to_phys((void *)(data->dest));
311 if (upper_32_bits(addr))
312 printf("Error found for upper 32 bits\n");
314 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
316 esdhc_write32(®s->dsaddr, (u32)data->dest);
320 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
321 flush_dcache_range((ulong)data->src,
322 (ulong)data->src+data->blocks
325 if (wml_value > WML_WR_WML_MAX)
326 wml_value = WML_WR_WML_MAX_VAL;
327 if (priv->wp_enable) {
328 if ((esdhc_read32(®s->prsstat) &
329 PRSSTAT_WPSPL) == 0) {
330 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
334 #if CONFIG_IS_ENABLED(DM_GPIO)
335 if (dm_gpio_is_valid(&priv->wp_gpio) &&
336 dm_gpio_get_value(&priv->wp_gpio)) {
337 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
343 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
345 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
346 #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) || \
347 defined(CONFIG_IMX8ULP)
348 addr = virt_to_phys((void *)(data->src));
349 if (upper_32_bits(addr))
350 printf("Error found for upper 32 bits\n");
352 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
354 esdhc_write32(®s->dsaddr, (u32)data->src);
359 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
361 /* Calculate the timeout period for data transactions */
363 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
364 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
365 * So, Number of SD Clock cycles for 0.25sec should be minimum
366 * (SD Clock/sec * 0.25 sec) SD Clock cycles
367 * = (mmc->clock * 1/4) SD Clock cycles
369 * => (2^(timeout+13)) >= mmc->clock * 1/4
370 * Taking log2 both the sides
371 * => timeout + 13 >= log2(mmc->clock/4)
372 * Rounding up to next power of 2
373 * => timeout + 13 = log2(mmc->clock/4) + 1
374 * => timeout + 13 = fls(mmc->clock/4)
376 * However, the MMC spec "It is strongly recommended for hosts to
377 * implement more than 500ms timeout value even if the card
378 * indicates the 250ms maximum busy length." Even the previous
379 * value of 300ms is known to be insufficient for some cards.
381 * => timeout + 13 = fls(mmc->clock/2)
383 timeout = fls(mmc->clock/2);
392 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
393 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
397 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
400 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
405 static void check_and_invalidate_dcache_range
406 (struct mmc_cmd *cmd,
407 struct mmc_data *data) {
410 unsigned size = roundup(ARCH_DMA_MINALIGN,
411 data->blocks*data->blocksize);
412 #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) || \
413 defined(CONFIG_IMX8ULP)
416 addr = virt_to_phys((void *)(data->dest));
417 if (upper_32_bits(addr))
418 printf("Error found for upper 32 bits\n");
420 start = lower_32_bits(addr);
422 start = (unsigned)data->dest;
425 invalidate_dcache_range(start, end);
428 #ifdef CONFIG_MCF5441x
430 * Swaps 32-bit words to little-endian byte order.
432 static inline void sd_swap_dma_buff(struct mmc_data *data)
434 int i, size = data->blocksize >> 2;
435 u32 *buffer = (u32 *)data->dest;
438 while (data->blocks--) {
439 for (i = 0; i < size; i++) {
440 sw = __sw32(*buffer);
448 * Sends a command out on the bus. Takes the mmc pointer,
449 * a command pointer, and an optional data pointer.
451 static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
452 struct mmc_cmd *cmd, struct mmc_data *data)
457 u32 flags = IRQSTAT_CC | IRQSTAT_CTOE;
458 struct fsl_esdhc *regs = priv->esdhc_regs;
461 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
462 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
466 esdhc_write32(®s->irqstat, -1);
470 /* Wait for the bus to be idle */
471 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
472 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
475 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
478 /* Set up for a data transfer if we have one */
480 err = esdhc_setup_data(priv, mmc, data);
484 if (data->flags & MMC_DATA_READ)
485 check_and_invalidate_dcache_range(cmd, data);
488 /* Figure out the transfer arguments */
489 xfertyp = esdhc_xfertyp(cmd, data);
492 esdhc_write32(®s->irqsigen, 0);
494 /* Send the command */
495 esdhc_write32(®s->cmdarg, cmd->cmdarg);
496 #if defined(CONFIG_FSL_USDHC)
497 esdhc_write32(®s->mixctrl,
498 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
499 | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
500 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000);
502 esdhc_write32(®s->xfertyp, xfertyp);
505 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
506 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))
509 /* Wait for the command to complete */
510 start = get_timer(0);
511 while (!(esdhc_read32(®s->irqstat) & flags)) {
512 if (get_timer(start) > 1000) {
518 irqstat = esdhc_read32(®s->irqstat);
520 if (irqstat & CMD_ERR) {
525 if (irqstat & IRQSTAT_CTOE) {
530 /* Workaround for ESDHC errata ENGcm03648 */
531 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
534 /* Poll on DATA0 line for cmd with busy signal for 5000 ms */
535 while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
542 printf("Timeout waiting for DAT0 to go high!\n");
548 /* Copy the response to the response buffer */
549 if (cmd->resp_type & MMC_RSP_136) {
550 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
552 cmdrsp3 = esdhc_read32(®s->cmdrsp3);
553 cmdrsp2 = esdhc_read32(®s->cmdrsp2);
554 cmdrsp1 = esdhc_read32(®s->cmdrsp1);
555 cmdrsp0 = esdhc_read32(®s->cmdrsp0);
556 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
557 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
558 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
559 cmd->response[3] = (cmdrsp0 << 8);
561 cmd->response[0] = esdhc_read32(®s->cmdrsp0);
563 /* Wait until all of the blocks are transferred */
565 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
566 esdhc_pio_read_write(priv, data);
568 flags = DATA_COMPLETE;
569 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
570 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) {
575 irqstat = esdhc_read32(®s->irqstat);
577 if (irqstat & IRQSTAT_DTOE) {
582 if (irqstat & DATA_ERR) {
586 } while ((irqstat & flags) != flags);
589 * Need invalidate the dcache here again to avoid any
590 * cache-fill during the DMA operations such as the
591 * speculative pre-fetching etc.
593 if (data->flags & MMC_DATA_READ) {
594 check_and_invalidate_dcache_range(cmd, data);
595 #ifdef CONFIG_MCF5441x
596 sd_swap_dma_buff(data);
603 /* Reset CMD and DATA portions on error */
605 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
607 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC)
611 esdhc_write32(®s->sysctl,
612 esdhc_read32(®s->sysctl) |
614 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
618 /* If this was CMD11, then notify that power cycle is needed */
619 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
620 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
623 esdhc_write32(®s->irqstat, -1);
628 static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
630 struct fsl_esdhc *regs = priv->esdhc_regs;
636 /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
637 int pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1;
644 int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
645 int sdhc_clk = priv->sdhc_clk;
648 while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
651 while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
657 clk = (pre_div << 8) | (div << 4);
659 #ifdef CONFIG_FSL_USDHC
660 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
662 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
665 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
667 ret = readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp, tmp & PRSSTAT_SDSTB, 100);
669 pr_warn("fsl_esdhc_imx: Internal clock never stabilised.\n");
671 #ifdef CONFIG_FSL_USDHC
672 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
674 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
680 #ifdef MMC_SUPPORTS_TUNING
681 static int esdhc_change_pinstate(struct udevice *dev)
683 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
686 switch (priv->mode) {
689 ret = pinctrl_select_state(dev, "state_100mhz");
695 ret = pinctrl_select_state(dev, "state_200mhz");
698 ret = pinctrl_select_state(dev, "default");
703 printf("%s %d error\n", __func__, priv->mode);
708 static void esdhc_reset_tuning(struct mmc *mmc)
710 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
711 struct fsl_esdhc *regs = priv->esdhc_regs;
713 if (priv->flags & ESDHC_FLAG_USDHC) {
714 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
715 esdhc_clrbits32(®s->autoc12err,
716 MIX_CTRL_SMPCLK_SEL |
722 static void esdhc_set_strobe_dll(struct mmc *mmc)
724 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
725 struct fsl_esdhc *regs = priv->esdhc_regs;
728 if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
729 esdhc_write32(®s->strobe_dllctrl, ESDHC_STROBE_DLL_CTRL_RESET);
732 * enable strobe dll ctrl and adjust the delay target
733 * for the uSDHC loopback read clock
735 val = ESDHC_STROBE_DLL_CTRL_ENABLE |
736 (priv->strobe_dll_delay_target <<
737 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
738 esdhc_write32(®s->strobe_dllctrl, val);
739 /* wait 1us to make sure strobe dll status register stable */
741 val = esdhc_read32(®s->strobe_dllstat);
742 if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK))
743 pr_warn("HS400 strobe DLL status REF not lock!\n");
744 if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK))
745 pr_warn("HS400 strobe DLL status SLV not lock!\n");
749 static int esdhc_set_timing(struct mmc *mmc)
751 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
752 struct fsl_esdhc *regs = priv->esdhc_regs;
755 mixctrl = esdhc_read32(®s->mixctrl);
756 mixctrl &= ~(MIX_CTRL_DDREN | MIX_CTRL_HS400_EN);
758 switch (mmc->selected_mode) {
760 esdhc_reset_tuning(mmc);
761 esdhc_write32(®s->mixctrl, mixctrl);
765 mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN;
766 esdhc_write32(®s->mixctrl, mixctrl);
776 esdhc_write32(®s->mixctrl, mixctrl);
780 mixctrl |= MIX_CTRL_DDREN;
781 esdhc_write32(®s->mixctrl, mixctrl);
784 printf("Not supported %d\n", mmc->selected_mode);
788 priv->mode = mmc->selected_mode;
790 return esdhc_change_pinstate(mmc->dev);
793 static int esdhc_set_voltage(struct mmc *mmc)
795 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
796 struct fsl_esdhc *regs = priv->esdhc_regs;
797 #if CONFIG_IS_ENABLED(DM_REGULATOR)
801 priv->signal_voltage = mmc->signal_voltage;
802 switch (mmc->signal_voltage) {
803 case MMC_SIGNAL_VOLTAGE_330:
804 if (priv->vs18_enable)
806 #if CONFIG_IS_ENABLED(DM_REGULATOR)
807 if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
808 ret = regulator_set_value(priv->vqmmc_dev, 3300000);
810 printf("Setting to 3.3V error");
818 esdhc_clrbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
819 if (!(esdhc_read32(®s->vendorspec) &
820 ESDHC_VENDORSPEC_VSELECT))
824 case MMC_SIGNAL_VOLTAGE_180:
825 #if CONFIG_IS_ENABLED(DM_REGULATOR)
826 if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
827 ret = regulator_set_value(priv->vqmmc_dev, 1800000);
829 printf("Setting to 1.8V error");
834 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
836 * some board like imx8mm-evk need about 18ms to switch
837 * the IO voltage from 3.3v to 1.8v, common code only
838 * delay 10ms, so need to delay extra time to make sure
839 * the IO voltage change to 1.8v.
841 if (priv->signal_voltage_switch_extra_delay_ms)
842 mdelay(priv->signal_voltage_switch_extra_delay_ms);
843 if (esdhc_read32(®s->vendorspec) & ESDHC_VENDORSPEC_VSELECT)
847 case MMC_SIGNAL_VOLTAGE_120:
854 static void esdhc_stop_tuning(struct mmc *mmc)
858 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
860 cmd.resp_type = MMC_RSP_R1b;
862 mmc_send_cmd(mmc, &cmd, NULL);
865 static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
867 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
868 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
869 struct fsl_esdhc *regs = priv->esdhc_regs;
870 struct mmc *mmc = &plat->mmc;
871 u32 irqstaten = esdhc_read32(®s->irqstaten);
872 u32 irqsigen = esdhc_read32(®s->irqsigen);
873 int i, ret = -ETIMEDOUT;
876 /* clock tuning is not needed for upto 52MHz */
877 if (mmc->clock <= 52000000)
880 /* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */
881 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
882 val = esdhc_read32(®s->autoc12err);
883 mixctrl = esdhc_read32(®s->mixctrl);
884 val &= ~MIX_CTRL_SMPCLK_SEL;
885 mixctrl &= ~(MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN);
887 val |= MIX_CTRL_EXE_TUNE;
888 mixctrl |= MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN;
890 esdhc_write32(®s->autoc12err, val);
891 esdhc_write32(®s->mixctrl, mixctrl);
894 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); */
895 mixctrl = esdhc_read32(®s->mixctrl);
896 mixctrl = MIX_CTRL_DTDSEL_READ | (mixctrl & ~MIX_CTRL_SDHCI_MASK);
897 esdhc_write32(®s->mixctrl, mixctrl);
899 esdhc_write32(®s->irqstaten, IRQSTATEN_BRR);
900 esdhc_write32(®s->irqsigen, IRQSTATEN_BRR);
903 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
904 * of loops reaches 40 times.
906 for (i = 0; i < MAX_TUNING_LOOP; i++) {
909 if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) {
910 if (mmc->bus_width == 8)
911 esdhc_write32(®s->blkattr, 0x7080);
912 else if (mmc->bus_width == 4)
913 esdhc_write32(®s->blkattr, 0x7040);
915 esdhc_write32(®s->blkattr, 0x7040);
918 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE) */
919 val = esdhc_read32(®s->mixctrl);
920 val = MIX_CTRL_DTDSEL_READ | (val & ~MIX_CTRL_SDHCI_MASK);
921 esdhc_write32(®s->mixctrl, val);
923 /* We are using STD tuning, no need to check return value */
924 mmc_send_tuning(mmc, opcode, NULL);
926 ctrl = esdhc_read32(®s->autoc12err);
927 if ((!(ctrl & MIX_CTRL_EXE_TUNE)) &&
928 (ctrl & MIX_CTRL_SMPCLK_SEL)) {
934 esdhc_write32(®s->irqstaten, irqstaten);
935 esdhc_write32(®s->irqsigen, irqsigen);
937 esdhc_stop_tuning(mmc);
943 static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
945 struct fsl_esdhc *regs = priv->esdhc_regs;
946 int ret __maybe_unused;
949 #ifdef MMC_SUPPORTS_TUNING
951 * call esdhc_set_timing() before update the clock rate,
952 * This is because current we support DDR and SDR mode,
953 * Once the DDR_EN bit is set, the card clock will be
954 * divide by 2 automatically. So need to do this before
955 * setting clock rate.
957 if (priv->mode != mmc->selected_mode) {
958 ret = esdhc_set_timing(mmc);
960 printf("esdhc_set_timing error %d\n", ret);
966 /* Set the clock speed */
968 if (clock < mmc->cfg->f_min)
969 clock = mmc->cfg->f_min;
971 if (priv->clock != clock)
972 set_sysctl(priv, mmc, clock);
974 #ifdef MMC_SUPPORTS_TUNING
975 if (mmc->clk_disable) {
976 #ifdef CONFIG_FSL_USDHC
977 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
979 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
982 #ifdef CONFIG_FSL_USDHC
983 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
986 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
991 * For HS400/HS400ES mode, make sure set the strobe dll in the
992 * target clock rate. So call esdhc_set_strobe_dll() after the
995 if (mmc->selected_mode == MMC_HS_400 || mmc->selected_mode == MMC_HS_400_ES)
996 esdhc_set_strobe_dll(mmc);
998 if (priv->signal_voltage != mmc->signal_voltage) {
999 ret = esdhc_set_voltage(mmc);
1001 if (ret != -ENOTSUPP)
1002 printf("esdhc_set_voltage error %d\n", ret);
1008 /* Set the bus width */
1009 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
1011 if (mmc->bus_width == 4)
1012 esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
1013 else if (mmc->bus_width == 8)
1014 esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
1019 static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
1021 struct fsl_esdhc *regs = priv->esdhc_regs;
1024 /* Reset the entire host controller */
1025 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
1027 /* Wait until the controller is available */
1028 start = get_timer(0);
1029 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
1030 if (get_timer(start) > 1000)
1034 #if defined(CONFIG_FSL_USDHC)
1035 /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
1036 esdhc_write32(®s->mmcboot, 0x0);
1037 /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
1038 esdhc_write32(®s->mixctrl, 0x0);
1039 esdhc_write32(®s->clktunectrlstatus, 0x0);
1041 /* Put VEND_SPEC to default value */
1042 if (priv->vs18_enable)
1043 esdhc_write32(®s->vendorspec, (VENDORSPEC_INIT |
1044 ESDHC_VENDORSPEC_VSELECT));
1046 esdhc_write32(®s->vendorspec, VENDORSPEC_INIT);
1048 /* Disable DLL_CTRL delay line */
1049 esdhc_write32(®s->dllctrl, 0x0);
1053 /* Enable cache snooping */
1054 esdhc_write32(®s->scr, 0x00000040);
1057 #ifndef CONFIG_FSL_USDHC
1058 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
1060 esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
1063 /* Set the initial clock speed */
1064 mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
1066 /* Disable the BRR and BWR bits in IRQSTAT */
1067 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
1069 #ifdef CONFIG_MCF5441x
1070 esdhc_write32(®s->proctl, PROCTL_INIT | PROCTL_D3CD);
1072 /* Put the PROCTL reg back to the default */
1073 esdhc_write32(®s->proctl, PROCTL_INIT);
1076 /* Set timout to the maximum value */
1077 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
1082 static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
1084 struct fsl_esdhc *regs = priv->esdhc_regs;
1087 #ifdef CONFIG_ESDHC_DETECT_QUIRK
1088 if (CONFIG_ESDHC_DETECT_QUIRK)
1092 #if CONFIG_IS_ENABLED(DM_MMC)
1093 if (priv->non_removable)
1096 if (priv->broken_cd)
1098 #if CONFIG_IS_ENABLED(DM_GPIO)
1099 if (dm_gpio_is_valid(&priv->cd_gpio))
1100 return dm_gpio_get_value(&priv->cd_gpio);
1104 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
1110 static int esdhc_reset(struct fsl_esdhc *regs)
1114 /* reset the controller */
1115 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
1117 /* hardware clears the bit when it is done */
1118 start = get_timer(0);
1119 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
1120 if (get_timer(start) > 100) {
1121 printf("MMC/SD: Reset never completed.\n");
1129 #if !CONFIG_IS_ENABLED(DM_MMC)
1130 static int esdhc_getcd(struct mmc *mmc)
1132 struct fsl_esdhc_priv *priv = mmc->priv;
1134 return esdhc_getcd_common(priv);
1137 static int esdhc_init(struct mmc *mmc)
1139 struct fsl_esdhc_priv *priv = mmc->priv;
1141 return esdhc_init_common(priv, mmc);
1144 static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
1145 struct mmc_data *data)
1147 struct fsl_esdhc_priv *priv = mmc->priv;
1149 return esdhc_send_cmd_common(priv, mmc, cmd, data);
1152 static int esdhc_set_ios(struct mmc *mmc)
1154 struct fsl_esdhc_priv *priv = mmc->priv;
1156 return esdhc_set_ios_common(priv, mmc);
1159 static const struct mmc_ops esdhc_ops = {
1160 .getcd = esdhc_getcd,
1162 .send_cmd = esdhc_send_cmd,
1163 .set_ios = esdhc_set_ios,
1167 static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
1168 struct fsl_esdhc_plat *plat)
1170 struct mmc_config *cfg;
1171 struct fsl_esdhc *regs;
1172 u32 caps, voltage_caps;
1178 regs = priv->esdhc_regs;
1180 /* First reset the eSDHC controller */
1181 ret = esdhc_reset(regs);
1185 #ifdef CONFIG_MCF5441x
1186 /* ColdFire, using SDHC_DATA[3] for card detection */
1187 esdhc_write32(®s->proctl, PROCTL_INIT | PROCTL_D3CD);
1190 #ifndef CONFIG_FSL_USDHC
1191 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
1192 | SYSCTL_IPGEN | SYSCTL_CKEN);
1193 /* Clearing tuning bits in case ROM has set it already */
1194 esdhc_write32(®s->mixctrl, 0);
1195 esdhc_write32(®s->autoc12err, 0);
1196 esdhc_write32(®s->clktunectrlstatus, 0);
1198 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
1199 VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
1202 if (priv->vs18_enable)
1203 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
1205 esdhc_write32(®s->irqstaten, SDHCI_IRQ_EN_BITS);
1207 #ifndef CONFIG_DM_MMC
1208 memset(cfg, '\0', sizeof(*cfg));
1212 caps = esdhc_read32(®s->hostcapblt);
1214 #ifdef CONFIG_MCF5441x
1216 * MCF5441x RM declares in more points that sdhc clock speed must
1217 * never exceed 25 Mhz. From this, the HS bit needs to be disabled
1218 * from host capabilities.
1220 caps &= ~ESDHC_HOSTCAPBLT_HSS;
1223 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
1224 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
1225 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
1228 if (caps & ESDHC_HOSTCAPBLT_VS18)
1229 voltage_caps |= MMC_VDD_165_195;
1230 if (caps & ESDHC_HOSTCAPBLT_VS30)
1231 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
1232 if (caps & ESDHC_HOSTCAPBLT_VS33)
1233 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
1235 cfg->name = "FSL_SDHC";
1236 #if !CONFIG_IS_ENABLED(DM_MMC)
1237 cfg->ops = &esdhc_ops;
1239 #ifdef CONFIG_SYS_SD_VOLTAGE
1240 cfg->voltages = CONFIG_SYS_SD_VOLTAGE;
1242 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
1244 if ((cfg->voltages & voltage_caps) == 0) {
1245 printf("voltage not supported by controller\n");
1249 if (priv->bus_width == 8)
1250 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
1251 else if (priv->bus_width == 4)
1252 cfg->host_caps = MMC_MODE_4BIT;
1254 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
1255 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
1256 cfg->host_caps |= MMC_MODE_DDR_52MHz;
1259 if (priv->bus_width > 0) {
1260 if (priv->bus_width < 8)
1261 cfg->host_caps &= ~MMC_MODE_8BIT;
1262 if (priv->bus_width < 4)
1263 cfg->host_caps &= ~MMC_MODE_4BIT;
1266 if (caps & ESDHC_HOSTCAPBLT_HSS)
1267 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1269 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
1270 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
1271 cfg->host_caps &= ~MMC_MODE_8BIT;
1274 cfg->host_caps |= priv->caps;
1276 cfg->f_min = 400000;
1277 cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
1279 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1281 esdhc_write32(®s->dllctrl, 0);
1282 if (priv->flags & ESDHC_FLAG_USDHC) {
1283 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
1284 u32 val = esdhc_read32(®s->tuning_ctrl);
1286 val |= ESDHC_STD_TUNING_EN;
1287 val &= ~ESDHC_TUNING_START_TAP_MASK;
1288 val |= priv->tuning_start_tap;
1289 val &= ~ESDHC_TUNING_STEP_MASK;
1290 val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT;
1292 /* Disable the CMD CRC check for tuning, if not, need to
1293 * add some delay after every tuning command, because
1294 * hardware standard tuning logic will directly go to next
1295 * step once it detect the CMD CRC error, will not wait for
1296 * the card side to finally send out the tuning data, trigger
1297 * the buffer read ready interrupt immediately. If usdhc send
1298 * the next tuning command some eMMC card will stuck, can't
1299 * response, block the tuning procedure or the first command
1300 * after the whole tuning procedure always can't get any response.
1302 val |= ESDHC_TUNING_CMD_CRC_CHECK_DISABLE;
1303 esdhc_write32(®s->tuning_ctrl, val);
1310 #if !CONFIG_IS_ENABLED(DM_MMC)
1311 static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
1312 struct fsl_esdhc_priv *priv)
1317 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
1318 priv->bus_width = cfg->max_bus_width;
1319 priv->sdhc_clk = cfg->sdhc_clk;
1320 priv->wp_enable = cfg->wp_enable;
1321 priv->vs18_enable = cfg->vs18_enable;
1326 int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg)
1328 struct fsl_esdhc_plat *plat;
1329 struct fsl_esdhc_priv *priv;
1336 priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
1339 plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
1345 ret = fsl_esdhc_cfg_to_priv(cfg, priv);
1347 debug("%s xlate failure\n", __func__);
1353 ret = fsl_esdhc_init(priv, plat);
1355 debug("%s init failure\n", __func__);
1361 mmc = mmc_create(&plat->cfg, priv);
1370 int fsl_esdhc_mmc_init(struct bd_info *bis)
1372 struct fsl_esdhc_cfg *cfg;
1374 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
1375 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
1376 cfg->sdhc_clk = gd->arch.sdhc_clk;
1377 return fsl_esdhc_initialize(bis, cfg);
1381 #ifdef CONFIG_OF_LIBFDT
1382 __weak int esdhc_status_fixup(void *blob, const char *compat)
1384 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
1385 if (!hwconfig("esdhc")) {
1386 do_fixup_by_compat(blob, compat, "status", "disabled",
1387 sizeof("disabled"), 1);
1394 void fdt_fixup_esdhc(void *blob, struct bd_info *bd)
1396 const char *compat = "fsl,esdhc";
1398 if (esdhc_status_fixup(blob, compat))
1401 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
1402 gd->arch.sdhc_clk, 1);
1406 #if CONFIG_IS_ENABLED(DM_MMC)
1407 #include <asm/arch/clock.h>
1408 __weak void init_clk_usdhc(u32 index)
1412 static int fsl_esdhc_of_to_plat(struct udevice *dev)
1414 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1415 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1416 struct udevice *vqmmc_dev;
1419 const void *fdt = gd->fdt_blob;
1420 int node = dev_of_offset(dev);
1424 if (!CONFIG_IS_ENABLED(OF_REAL))
1427 addr = dev_read_addr(dev);
1428 if (addr == FDT_ADDR_T_NONE)
1430 priv->esdhc_regs = (struct fsl_esdhc *)addr;
1434 val = dev_read_u32_default(dev, "bus-width", -1);
1436 priv->bus_width = 8;
1438 priv->bus_width = 4;
1440 priv->bus_width = 1;
1442 val = fdtdec_get_int(fdt, node, "fsl,tuning-step", 1);
1443 priv->tuning_step = val;
1444 val = fdtdec_get_int(fdt, node, "fsl,tuning-start-tap",
1445 ESDHC_TUNING_START_TAP_DEFAULT);
1446 priv->tuning_start_tap = val;
1447 val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target",
1448 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT);
1449 priv->strobe_dll_delay_target = val;
1450 val = fdtdec_get_int(fdt, node, "fsl,signal-voltage-switch-extra-delay-ms", 0);
1451 priv->signal_voltage_switch_extra_delay_ms = val;
1453 if (dev_read_bool(dev, "broken-cd"))
1454 priv->broken_cd = 1;
1456 if (dev_read_bool(dev, "non-removable")) {
1457 priv->non_removable = 1;
1459 priv->non_removable = 0;
1460 #if CONFIG_IS_ENABLED(DM_GPIO)
1461 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
1466 if (dev_read_prop(dev, "fsl,wp-controller", NULL)) {
1467 priv->wp_enable = 1;
1469 priv->wp_enable = 0;
1470 #if CONFIG_IS_ENABLED(DM_GPIO)
1471 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
1476 priv->vs18_enable = 0;
1478 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1480 * If emmc I/O has a fixed voltage at 1.8V, this must be provided,
1481 * otherwise, emmc will work abnormally.
1483 ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
1485 dev_dbg(dev, "no vqmmc-supply\n");
1487 priv->vqmmc_dev = vqmmc_dev;
1488 ret = regulator_set_enable(vqmmc_dev, true);
1490 dev_err(dev, "fail to enable vqmmc-supply\n");
1494 if (regulator_get_value(vqmmc_dev) == 1800000)
1495 priv->vs18_enable = 1;
1502 static int fsl_esdhc_probe(struct udevice *dev)
1504 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1505 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
1506 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1507 struct esdhc_soc_data *data =
1508 (struct esdhc_soc_data *)dev_get_driver_data(dev);
1510 #if !CONFIG_IS_ENABLED(BLK)
1511 struct blk_desc *bdesc;
1515 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1516 struct dtd_fsl_esdhc *dtplat = &plat->dtplat;
1519 priv->esdhc_regs = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
1520 val = plat->dtplat.bus_width;
1522 priv->bus_width = 8;
1524 priv->bus_width = 4;
1526 priv->bus_width = 1;
1528 if (dtplat->non_removable)
1529 priv->non_removable = 1;
1531 priv->non_removable = 0;
1533 if (CONFIG_IS_ENABLED(DM_GPIO) && !priv->non_removable) {
1534 struct udevice *gpiodev;
1536 ret = device_get_by_ofplat_idx(dtplat->cd_gpios->idx, &gpiodev);
1540 ret = gpio_dev_request_index(gpiodev, gpiodev->name, "cd-gpios",
1541 dtplat->cd_gpios->arg[0], GPIOD_IS_IN,
1542 dtplat->cd_gpios->arg[1], &priv->cd_gpio);
1550 priv->flags = data->flags;
1554 * Because lack of clk driver, if SDHC clk is not enabled,
1555 * need to enable it first before this driver is invoked.
1557 * we use MXC_ESDHC_CLK to get clk freq.
1558 * If one would like to make this function work,
1559 * the aliases should be provided in dts as this:
1567 * Then if your board only supports mmc2 and mmc3, but we can
1568 * correctly get the seq as 2 and 3, then let mxc_get_clock
1572 init_clk_usdhc(dev_seq(dev));
1574 #if CONFIG_IS_ENABLED(CLK)
1575 /* Assigned clock already set clock */
1576 ret = clk_get_by_name(dev, "per", &priv->per_clk);
1578 printf("Failed to get per_clk\n");
1581 ret = clk_enable(&priv->per_clk);
1583 printf("Failed to enable per_clk\n");
1587 priv->sdhc_clk = clk_get_rate(&priv->per_clk);
1589 priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev_seq(dev));
1590 if (priv->sdhc_clk <= 0) {
1591 dev_err(dev, "Unable to get clk for %s\n", dev->name);
1596 ret = fsl_esdhc_init(priv, plat);
1598 dev_err(dev, "fsl_esdhc_init failure\n");
1602 if (CONFIG_IS_ENABLED(OF_REAL)) {
1603 ret = mmc_of_parse(dev, &plat->cfg);
1609 mmc->cfg = &plat->cfg;
1611 #if !CONFIG_IS_ENABLED(BLK)
1614 /* Setup dsr related values */
1616 mmc->dsr = ESDHC_DRIVER_STAGE_VALUE;
1617 /* Setup the universal parts of the block interface just once */
1618 bdesc = mmc_get_blk_desc(mmc);
1619 bdesc->if_type = IF_TYPE_MMC;
1620 bdesc->removable = 1;
1621 bdesc->devnum = mmc_get_next_devnum();
1622 bdesc->block_read = mmc_bread;
1623 bdesc->block_write = mmc_bwrite;
1624 bdesc->block_erase = mmc_berase;
1626 /* setup initial part type */
1627 bdesc->part_type = mmc->cfg->part_type;
1633 return esdhc_init_common(priv, mmc);
1636 #if CONFIG_IS_ENABLED(DM_MMC)
1637 static int fsl_esdhc_get_cd(struct udevice *dev)
1639 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1641 return esdhc_getcd_common(priv);
1644 static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1645 struct mmc_data *data)
1647 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
1648 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1650 return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
1653 static int fsl_esdhc_set_ios(struct udevice *dev)
1655 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
1656 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1658 return esdhc_set_ios_common(priv, &plat->mmc);
1661 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
1662 static int fsl_esdhc_set_enhanced_strobe(struct udevice *dev)
1664 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1665 struct fsl_esdhc *regs = priv->esdhc_regs;
1668 m = esdhc_read32(®s->mixctrl);
1669 m |= MIX_CTRL_HS400_ES;
1670 esdhc_write32(®s->mixctrl, m);
1676 static int fsl_esdhc_wait_dat0(struct udevice *dev, int state,
1681 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1682 struct fsl_esdhc *regs = priv->esdhc_regs;
1684 ret = readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp,
1685 !!(tmp & PRSSTAT_DAT0) == !!state,
1690 static const struct dm_mmc_ops fsl_esdhc_ops = {
1691 .get_cd = fsl_esdhc_get_cd,
1692 .send_cmd = fsl_esdhc_send_cmd,
1693 .set_ios = fsl_esdhc_set_ios,
1694 #ifdef MMC_SUPPORTS_TUNING
1695 .execute_tuning = fsl_esdhc_execute_tuning,
1697 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
1698 .set_enhanced_strobe = fsl_esdhc_set_enhanced_strobe,
1700 .wait_dat0 = fsl_esdhc_wait_dat0,
1704 static struct esdhc_soc_data usdhc_imx7d_data = {
1705 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
1706 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
1710 static struct esdhc_soc_data usdhc_imx8qm_data = {
1711 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING |
1712 ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 |
1713 ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES,
1716 static const struct udevice_id fsl_esdhc_ids[] = {
1717 { .compatible = "fsl,imx51-esdhc", },
1718 { .compatible = "fsl,imx53-esdhc", },
1719 { .compatible = "fsl,imx6ul-usdhc", },
1720 { .compatible = "fsl,imx6sx-usdhc", },
1721 { .compatible = "fsl,imx6sl-usdhc", },
1722 { .compatible = "fsl,imx6q-usdhc", },
1723 { .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,},
1724 { .compatible = "fsl,imx7ulp-usdhc", },
1725 { .compatible = "fsl,imx8qm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
1726 { .compatible = "fsl,imx8mm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
1727 { .compatible = "fsl,imx8mn-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
1728 { .compatible = "fsl,imx8mq-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
1729 { .compatible = "fsl,imxrt-usdhc", },
1730 { .compatible = "fsl,esdhc", },
1734 #if CONFIG_IS_ENABLED(BLK)
1735 static int fsl_esdhc_bind(struct udevice *dev)
1737 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
1739 return mmc_bind(dev, &plat->mmc, &plat->cfg);
1743 U_BOOT_DRIVER(fsl_esdhc) = {
1744 .name = "fsl_esdhc",
1746 .of_match = fsl_esdhc_ids,
1747 .of_to_plat = fsl_esdhc_of_to_plat,
1748 .ops = &fsl_esdhc_ops,
1749 #if CONFIG_IS_ENABLED(BLK)
1750 .bind = fsl_esdhc_bind,
1752 .probe = fsl_esdhc_probe,
1753 .plat_auto = sizeof(struct fsl_esdhc_plat),
1754 .priv_auto = sizeof(struct fsl_esdhc_priv),
1757 DM_DRIVER_ALIAS(fsl_esdhc, fsl_imx6q_usdhc)