2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
5 * Based vaguely on the pxa mmc code:
7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
36 #include <fsl_esdhc.h>
37 #include <fdt_support.h>
40 DECLARE_GLOBAL_DATA_PTR;
69 /* Return the XFERTYP flags for a given command and data packet */
70 uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
75 xfertyp |= XFERTYP_DPSEL;
76 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
77 xfertyp |= XFERTYP_DMAEN;
79 if (data->blocks > 1) {
80 xfertyp |= XFERTYP_MSBSEL;
81 xfertyp |= XFERTYP_BCEN;
82 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
83 xfertyp |= XFERTYP_AC12EN;
87 if (data->flags & MMC_DATA_READ)
88 xfertyp |= XFERTYP_DTDSEL;
91 if (cmd->resp_type & MMC_RSP_CRC)
92 xfertyp |= XFERTYP_CCCEN;
93 if (cmd->resp_type & MMC_RSP_OPCODE)
94 xfertyp |= XFERTYP_CICEN;
95 if (cmd->resp_type & MMC_RSP_136)
96 xfertyp |= XFERTYP_RSPTYP_136;
97 else if (cmd->resp_type & MMC_RSP_BUSY)
98 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
99 else if (cmd->resp_type & MMC_RSP_PRESENT)
100 xfertyp |= XFERTYP_RSPTYP_48;
102 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
105 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
107 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
110 esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
112 struct fsl_esdhc *regs = mmc->priv;
120 if (data->flags & MMC_DATA_READ) {
121 blocks = data->blocks;
124 timeout = PIO_TIMEOUT;
125 size = data->blocksize;
126 irqstat = esdhc_read32(®s->irqstat);
127 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)
130 printf("\nData Read Failed in PIO Mode.");
133 while (size && (!(irqstat & IRQSTAT_TC))) {
134 udelay(100); /* Wait before last byte transfer complete */
135 irqstat = esdhc_read32(®s->irqstat);
136 databuf = in_le32(®s->datport);
137 *((uint *)buffer) = databuf;
144 blocks = data->blocks;
145 buffer = (char *)data->src;
147 timeout = PIO_TIMEOUT;
148 size = data->blocksize;
149 irqstat = esdhc_read32(®s->irqstat);
150 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)
153 printf("\nData Write Failed in PIO Mode.");
156 while (size && (!(irqstat & IRQSTAT_TC))) {
157 udelay(100); /* Wait before last byte transfer complete */
158 databuf = *((uint *)buffer);
161 irqstat = esdhc_read32(®s->irqstat);
162 out_le32(®s->datport, databuf);
170 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
173 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
174 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
175 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
178 wml_value = data->blocksize/4;
180 if (data->flags & MMC_DATA_READ) {
181 if (wml_value > 0x10)
184 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
185 esdhc_write32(®s->dsaddr, (u32)data->dest);
187 if (wml_value > 0x80)
189 if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) {
190 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
194 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
196 esdhc_write32(®s->dsaddr, (u32)data->src);
198 #else /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
199 if (!(data->flags & MMC_DATA_READ)) {
200 if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) {
201 printf("\nThe SD card is locked. "
202 "Can not write to a locked card.\n\n");
205 esdhc_write32(®s->dsaddr, (u32)data->src);
207 esdhc_write32(®s->dsaddr, (u32)data->dest);
208 #endif /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
210 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
212 /* Calculate the timeout period for data transactions */
213 timeout = fls(mmc->tran_speed/10) - 1;
222 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
229 * Sends a command out on the bus. Takes the mmc pointer,
230 * a command pointer, and an optional data pointer.
233 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
237 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
238 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
240 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
241 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
245 esdhc_write32(®s->irqstat, -1);
249 /* Wait for the bus to be idle */
250 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
251 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
254 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
257 /* Wait at least 8 SD clock cycles before the next command */
259 * Note: This is way more than 8 cycles, but 1ms seems to
260 * resolve timing issues with some cards
264 /* Set up for a data transfer if we have one */
268 err = esdhc_setup_data(mmc, data);
273 /* Figure out the transfer arguments */
274 xfertyp = esdhc_xfertyp(cmd, data);
276 /* Send the command */
277 esdhc_write32(®s->cmdarg, cmd->cmdarg);
278 esdhc_write32(®s->xfertyp, xfertyp);
280 /* Wait for the command to complete */
281 while (!(esdhc_read32(®s->irqstat) & IRQSTAT_CC))
284 irqstat = esdhc_read32(®s->irqstat);
285 esdhc_write32(®s->irqstat, irqstat);
287 if (irqstat & CMD_ERR)
290 if (irqstat & IRQSTAT_CTOE)
293 /* Copy the response to the response buffer */
294 if (cmd->resp_type & MMC_RSP_136) {
295 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
297 cmdrsp3 = esdhc_read32(®s->cmdrsp3);
298 cmdrsp2 = esdhc_read32(®s->cmdrsp2);
299 cmdrsp1 = esdhc_read32(®s->cmdrsp1);
300 cmdrsp0 = esdhc_read32(®s->cmdrsp0);
301 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
302 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
303 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
304 cmd->response[3] = (cmdrsp0 << 8);
306 cmd->response[0] = esdhc_read32(®s->cmdrsp0);
308 /* Wait until all of the blocks are transferred */
310 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
311 esdhc_pio_read_write(mmc, data);
314 irqstat = esdhc_read32(®s->irqstat);
316 if (irqstat & DATA_ERR)
319 if (irqstat & IRQSTAT_DTOE)
321 } while (!(irqstat & IRQSTAT_TC) &&
322 (esdhc_read32(®s->prsstat) & PRSSTAT_DLA));
326 esdhc_write32(®s->irqstat, -1);
331 void set_sysctl(struct mmc *mmc, uint clock)
333 int sdhc_clk = gd->sdhc_clk;
335 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
336 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
339 if (clock < mmc->f_min)
342 if (sdhc_clk / 16 > clock) {
343 for (pre_div = 2; pre_div < 256; pre_div *= 2)
344 if ((sdhc_clk / pre_div) <= (clock * 16))
349 for (div = 1; div <= 16; div++)
350 if ((sdhc_clk / (div * pre_div)) <= clock)
356 clk = (pre_div << 8) | (div << 4);
358 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
360 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
364 clk = SYSCTL_PEREN | SYSCTL_CKEN;
366 esdhc_setbits32(®s->sysctl, clk);
369 static void esdhc_set_ios(struct mmc *mmc)
371 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
372 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
374 /* Set the clock speed */
375 set_sysctl(mmc, mmc->clock);
377 /* Set the bus width */
378 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
380 if (mmc->bus_width == 4)
381 esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
382 else if (mmc->bus_width == 8)
383 esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
387 static int esdhc_init(struct mmc *mmc)
389 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
390 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
395 /* Reset the entire host controller */
396 esdhc_write32(®s->sysctl, SYSCTL_RSTA);
398 /* Wait until the controller is available */
399 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
402 /* Enable cache snooping */
403 if (cfg && !cfg->no_snoop)
404 esdhc_write32(®s->scr, 0x00000040);
406 esdhc_write32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
408 /* Set the initial clock speed */
409 mmc_set_clock(mmc, 400000);
411 /* Disable the BRR and BWR bits in IRQSTAT */
412 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
414 /* Put the PROCTL reg back to the default */
415 esdhc_write32(®s->proctl, PROCTL_INIT);
417 /* Set timout to the maximum value */
418 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
420 /* Check if there is a callback for detecting the card */
421 if (board_mmc_getcd(&card_absent, mmc)) {
423 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) &&
437 static void esdhc_reset(struct fsl_esdhc *regs)
439 unsigned long timeout = 100; /* wait max 100 ms */
441 /* reset the controller */
442 esdhc_write32(®s->sysctl, SYSCTL_RSTA);
444 /* hardware clears the bit when it is done */
445 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
448 printf("MMC/SD: Reset never completed.\n");
451 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
453 struct fsl_esdhc *regs;
455 u32 caps, voltage_caps;
460 mmc = malloc(sizeof(struct mmc));
462 sprintf(mmc->name, "FSL_ESDHC");
463 regs = (struct fsl_esdhc *)cfg->esdhc_base;
465 /* First reset the eSDHC controller */
469 mmc->send_cmd = esdhc_send_cmd;
470 mmc->set_ios = esdhc_set_ios;
471 mmc->init = esdhc_init;
474 caps = regs->hostcapblt;
476 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
477 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
478 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
480 if (caps & ESDHC_HOSTCAPBLT_VS18)
481 voltage_caps |= MMC_VDD_165_195;
482 if (caps & ESDHC_HOSTCAPBLT_VS30)
483 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
484 if (caps & ESDHC_HOSTCAPBLT_VS33)
485 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
487 #ifdef CONFIG_SYS_SD_VOLTAGE
488 mmc->voltages = CONFIG_SYS_SD_VOLTAGE;
490 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
492 if ((mmc->voltages & voltage_caps) == 0) {
493 printf("voltage not supported by controller\n");
497 mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
499 if (caps & ESDHC_HOSTCAPBLT_HSS)
500 mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
503 mmc->f_max = MIN(gd->sdhc_clk, 52000000);
510 int fsl_esdhc_mmc_init(bd_t *bis)
512 struct fsl_esdhc_cfg *cfg;
514 cfg = malloc(sizeof(struct fsl_esdhc_cfg));
515 memset(cfg, 0, sizeof(struct fsl_esdhc_cfg));
516 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
517 return fsl_esdhc_initialize(bis, cfg);
520 #ifdef CONFIG_OF_LIBFDT
521 void fdt_fixup_esdhc(void *blob, bd_t *bd)
523 const char *compat = "fsl,esdhc";
525 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
526 if (!hwconfig("esdhc")) {
527 do_fixup_by_compat(blob, compat, "status", "disabled",
533 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
536 do_fixup_by_compat(blob, compat, "status", "okay",