2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
5 * Based vaguely on the pxa mmc code:
7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
9 * SPDX-License-Identifier: GPL-2.0+
19 #include <power/regulator.h>
21 #include <fsl_esdhc.h>
22 #include <fdt_support.h>
25 #include <asm-generic/gpio.h>
27 DECLARE_GLOBAL_DATA_PTR;
29 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
31 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
32 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
33 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
37 uint dsaddr; /* SDMA system address register */
38 uint blkattr; /* Block attributes register */
39 uint cmdarg; /* Command argument register */
40 uint xfertyp; /* Transfer type register */
41 uint cmdrsp0; /* Command response 0 register */
42 uint cmdrsp1; /* Command response 1 register */
43 uint cmdrsp2; /* Command response 2 register */
44 uint cmdrsp3; /* Command response 3 register */
45 uint datport; /* Buffer data port register */
46 uint prsstat; /* Present state register */
47 uint proctl; /* Protocol control register */
48 uint sysctl; /* System Control Register */
49 uint irqstat; /* Interrupt status register */
50 uint irqstaten; /* Interrupt status enable register */
51 uint irqsigen; /* Interrupt signal enable register */
52 uint autoc12err; /* Auto CMD error status register */
53 uint hostcapblt; /* Host controller capabilities register */
54 uint wml; /* Watermark level register */
55 uint mixctrl; /* For USDHC */
56 char reserved1[4]; /* reserved */
57 uint fevt; /* Force event register */
58 uint admaes; /* ADMA error status register */
59 uint adsaddr; /* ADMA system address register */
63 uint clktunectrlstatus;
71 uint tuning_ctrl; /* on i.MX6/7/8 */
73 uint hostver; /* Host controller version register */
74 char reserved6[4]; /* reserved */
75 uint dmaerraddr; /* DMA error address register */
76 char reserved7[4]; /* reserved */
77 uint dmaerrattr; /* DMA error attribute register */
78 char reserved8[4]; /* reserved */
79 uint hostcapblt2; /* Host controller capabilities register 2 */
80 char reserved9[8]; /* reserved */
81 uint tcr; /* Tuning control register */
82 char reserved10[28]; /* reserved */
83 uint sddirctl; /* SD direction control register */
84 char reserved11[712];/* reserved */
85 uint scr; /* eSDHC control register */
88 struct fsl_esdhc_plat {
89 struct mmc_config cfg;
94 * struct fsl_esdhc_priv
96 * @esdhc_regs: registers of the sdhc controller
97 * @sdhc_clk: Current clk of the sdhc controller
98 * @bus_width: bus width, 1bit, 4bit or 8bit
101 * Following is used when Driver Model is enabled for MMC
102 * @dev: pointer for the device
103 * @non_removable: 0: removable; 1: non-removable
104 * @wp_enable: 1: enable checking wp; 0: no check
105 * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
106 * @cd_gpio: gpio for card detection
107 * @wp_gpio: gpio for write protection
109 struct fsl_esdhc_priv {
110 struct fsl_esdhc *esdhc_regs;
111 unsigned int sdhc_clk;
112 unsigned int bus_width;
113 #if !CONFIG_IS_ENABLED(BLK)
120 #ifdef CONFIG_DM_GPIO
121 struct gpio_desc cd_gpio;
122 struct gpio_desc wp_gpio;
126 /* Return the XFERTYP flags for a given command and data packet */
127 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
132 xfertyp |= XFERTYP_DPSEL;
133 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
134 xfertyp |= XFERTYP_DMAEN;
136 if (data->blocks > 1) {
137 xfertyp |= XFERTYP_MSBSEL;
138 xfertyp |= XFERTYP_BCEN;
139 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
140 xfertyp |= XFERTYP_AC12EN;
144 if (data->flags & MMC_DATA_READ)
145 xfertyp |= XFERTYP_DTDSEL;
148 if (cmd->resp_type & MMC_RSP_CRC)
149 xfertyp |= XFERTYP_CCCEN;
150 if (cmd->resp_type & MMC_RSP_OPCODE)
151 xfertyp |= XFERTYP_CICEN;
152 if (cmd->resp_type & MMC_RSP_136)
153 xfertyp |= XFERTYP_RSPTYP_136;
154 else if (cmd->resp_type & MMC_RSP_BUSY)
155 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
156 else if (cmd->resp_type & MMC_RSP_PRESENT)
157 xfertyp |= XFERTYP_RSPTYP_48;
159 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
160 xfertyp |= XFERTYP_CMDTYP_ABORT;
162 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
165 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
167 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
169 static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
170 struct mmc_data *data)
172 struct fsl_esdhc *regs = priv->esdhc_regs;
180 if (data->flags & MMC_DATA_READ) {
181 blocks = data->blocks;
184 start = get_timer(0);
185 size = data->blocksize;
186 irqstat = esdhc_read32(®s->irqstat);
187 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)) {
188 if (get_timer(start) > PIO_TIMEOUT) {
189 printf("\nData Read Failed in PIO Mode.");
193 while (size && (!(irqstat & IRQSTAT_TC))) {
194 udelay(100); /* Wait before last byte transfer complete */
195 irqstat = esdhc_read32(®s->irqstat);
196 databuf = in_le32(®s->datport);
197 *((uint *)buffer) = databuf;
204 blocks = data->blocks;
205 buffer = (char *)data->src;
207 start = get_timer(0);
208 size = data->blocksize;
209 irqstat = esdhc_read32(®s->irqstat);
210 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)) {
211 if (get_timer(start) > PIO_TIMEOUT) {
212 printf("\nData Write Failed in PIO Mode.");
216 while (size && (!(irqstat & IRQSTAT_TC))) {
217 udelay(100); /* Wait before last byte transfer complete */
218 databuf = *((uint *)buffer);
221 irqstat = esdhc_read32(®s->irqstat);
222 out_le32(®s->datport, databuf);
230 static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
231 struct mmc_data *data)
234 struct fsl_esdhc *regs = priv->esdhc_regs;
235 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
241 wml_value = data->blocksize/4;
243 if (data->flags & MMC_DATA_READ) {
244 if (wml_value > WML_RD_WML_MAX)
245 wml_value = WML_RD_WML_MAX_VAL;
247 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
248 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
249 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
251 addr = virt_to_phys((void *)(data->dest));
252 if (upper_32_bits(addr))
253 printf("Error found for upper 32 bits\n");
255 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
257 esdhc_write32(®s->dsaddr, (u32)data->dest);
261 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
262 flush_dcache_range((ulong)data->src,
263 (ulong)data->src+data->blocks
266 if (wml_value > WML_WR_WML_MAX)
267 wml_value = WML_WR_WML_MAX_VAL;
268 if (priv->wp_enable) {
269 if ((esdhc_read32(®s->prsstat) &
270 PRSSTAT_WPSPL) == 0) {
271 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
276 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
278 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
279 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
281 addr = virt_to_phys((void *)(data->src));
282 if (upper_32_bits(addr))
283 printf("Error found for upper 32 bits\n");
285 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
287 esdhc_write32(®s->dsaddr, (u32)data->src);
292 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
294 /* Calculate the timeout period for data transactions */
296 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
297 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
298 * So, Number of SD Clock cycles for 0.25sec should be minimum
299 * (SD Clock/sec * 0.25 sec) SD Clock cycles
300 * = (mmc->clock * 1/4) SD Clock cycles
302 * => (2^(timeout+13)) >= mmc->clock * 1/4
303 * Taking log2 both the sides
304 * => timeout + 13 >= log2(mmc->clock/4)
305 * Rounding up to next power of 2
306 * => timeout + 13 = log2(mmc->clock/4) + 1
307 * => timeout + 13 = fls(mmc->clock/4)
309 * However, the MMC spec "It is strongly recommended for hosts to
310 * implement more than 500ms timeout value even if the card
311 * indicates the 250ms maximum busy length." Even the previous
312 * value of 300ms is known to be insufficient for some cards.
314 * => timeout + 13 = fls(mmc->clock/2)
316 timeout = fls(mmc->clock/2);
325 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
326 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
330 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
333 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
338 static void check_and_invalidate_dcache_range
339 (struct mmc_cmd *cmd,
340 struct mmc_data *data) {
343 unsigned size = roundup(ARCH_DMA_MINALIGN,
344 data->blocks*data->blocksize);
345 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
349 addr = virt_to_phys((void *)(data->dest));
350 if (upper_32_bits(addr))
351 printf("Error found for upper 32 bits\n");
353 start = lower_32_bits(addr);
355 start = (unsigned)data->dest;
358 invalidate_dcache_range(start, end);
362 * Sends a command out on the bus. Takes the mmc pointer,
363 * a command pointer, and an optional data pointer.
365 static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
366 struct mmc_cmd *cmd, struct mmc_data *data)
371 struct fsl_esdhc *regs = priv->esdhc_regs;
373 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
374 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
378 esdhc_write32(®s->irqstat, -1);
382 /* Wait for the bus to be idle */
383 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
384 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
387 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
390 /* Wait at least 8 SD clock cycles before the next command */
392 * Note: This is way more than 8 cycles, but 1ms seems to
393 * resolve timing issues with some cards
397 /* Set up for a data transfer if we have one */
399 err = esdhc_setup_data(priv, mmc, data);
403 if (data->flags & MMC_DATA_READ)
404 check_and_invalidate_dcache_range(cmd, data);
407 /* Figure out the transfer arguments */
408 xfertyp = esdhc_xfertyp(cmd, data);
411 esdhc_write32(®s->irqsigen, 0);
413 /* Send the command */
414 esdhc_write32(®s->cmdarg, cmd->cmdarg);
415 #if defined(CONFIG_FSL_USDHC)
416 esdhc_write32(®s->mixctrl,
417 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
418 | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
419 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000);
421 esdhc_write32(®s->xfertyp, xfertyp);
424 /* Wait for the command to complete */
425 while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE)))
428 irqstat = esdhc_read32(®s->irqstat);
430 if (irqstat & CMD_ERR) {
435 if (irqstat & IRQSTAT_CTOE) {
440 /* Switch voltage to 1.8V if CMD11 succeeded */
441 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
442 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
444 printf("Run CMD11 1.8V switch\n");
445 /* Sleep for 5 ms - max time for card to switch to 1.8V */
449 /* Workaround for ESDHC errata ENGcm03648 */
450 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
453 /* Poll on DATA0 line for cmd with busy signal for 600 ms */
454 while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
461 printf("Timeout waiting for DAT0 to go high!\n");
467 /* Copy the response to the response buffer */
468 if (cmd->resp_type & MMC_RSP_136) {
469 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
471 cmdrsp3 = esdhc_read32(®s->cmdrsp3);
472 cmdrsp2 = esdhc_read32(®s->cmdrsp2);
473 cmdrsp1 = esdhc_read32(®s->cmdrsp1);
474 cmdrsp0 = esdhc_read32(®s->cmdrsp0);
475 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
476 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
477 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
478 cmd->response[3] = (cmdrsp0 << 8);
480 cmd->response[0] = esdhc_read32(®s->cmdrsp0);
482 /* Wait until all of the blocks are transferred */
484 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
485 esdhc_pio_read_write(priv, data);
488 irqstat = esdhc_read32(®s->irqstat);
490 if (irqstat & IRQSTAT_DTOE) {
495 if (irqstat & DATA_ERR) {
499 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
502 * Need invalidate the dcache here again to avoid any
503 * cache-fill during the DMA operations such as the
504 * speculative pre-fetching etc.
506 if (data->flags & MMC_DATA_READ)
507 check_and_invalidate_dcache_range(cmd, data);
512 /* Reset CMD and DATA portions on error */
514 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
516 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC)
520 esdhc_write32(®s->sysctl,
521 esdhc_read32(®s->sysctl) |
523 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
527 /* If this was CMD11, then notify that power cycle is needed */
528 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
529 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
532 esdhc_write32(®s->irqstat, -1);
537 static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
539 struct fsl_esdhc *regs = priv->esdhc_regs;
543 /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
544 int pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1;
551 int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
552 int sdhc_clk = priv->sdhc_clk;
555 if (clock < mmc->cfg->f_min)
556 clock = mmc->cfg->f_min;
558 while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
561 while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
567 clk = (pre_div << 8) | (div << 4);
569 #ifdef CONFIG_FSL_USDHC
570 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
572 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
575 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
579 #ifdef CONFIG_FSL_USDHC
580 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
582 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
587 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
588 static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
590 struct fsl_esdhc *regs = priv->esdhc_regs;
594 value = esdhc_read32(®s->sysctl);
597 value |= SYSCTL_CKEN;
599 value &= ~SYSCTL_CKEN;
601 esdhc_write32(®s->sysctl, value);
604 value = PRSSTAT_SDSTB;
605 while (!(esdhc_read32(®s->prsstat) & value)) {
607 printf("fsl_esdhc: Internal clock never stabilised.\n");
616 static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
618 struct fsl_esdhc *regs = priv->esdhc_regs;
620 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
621 /* Select to use peripheral clock */
622 esdhc_clock_control(priv, false);
623 esdhc_setbits32(®s->scr, ESDHCCTL_PCS);
624 esdhc_clock_control(priv, true);
626 /* Set the clock speed */
627 set_sysctl(priv, mmc, mmc->clock);
629 /* Set the bus width */
630 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
632 if (mmc->bus_width == 4)
633 esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
634 else if (mmc->bus_width == 8)
635 esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
640 static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
642 struct fsl_esdhc *regs = priv->esdhc_regs;
645 /* Reset the entire host controller */
646 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
648 /* Wait until the controller is available */
649 start = get_timer(0);
650 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
651 if (get_timer(start) > 1000)
655 #if defined(CONFIG_FSL_USDHC)
656 /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
657 esdhc_write32(®s->mmcboot, 0x0);
658 /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
659 esdhc_write32(®s->mixctrl, 0x0);
660 esdhc_write32(®s->clktunectrlstatus, 0x0);
662 /* Put VEND_SPEC to default value */
663 if (priv->vs18_enable)
664 esdhc_write32(®s->vendorspec, (VENDORSPEC_INIT |
665 ESDHC_VENDORSPEC_VSELECT));
667 esdhc_write32(®s->vendorspec, VENDORSPEC_INIT);
669 /* Disable DLL_CTRL delay line */
670 esdhc_write32(®s->dllctrl, 0x0);
674 /* Enable cache snooping */
675 esdhc_write32(®s->scr, 0x00000040);
678 #ifndef CONFIG_FSL_USDHC
679 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
681 esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
684 /* Set the initial clock speed */
685 mmc_set_clock(mmc, 400000, false);
687 /* Disable the BRR and BWR bits in IRQSTAT */
688 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
690 /* Put the PROCTL reg back to the default */
691 esdhc_write32(®s->proctl, PROCTL_INIT);
693 /* Set timout to the maximum value */
694 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
699 static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
701 struct fsl_esdhc *regs = priv->esdhc_regs;
704 #ifdef CONFIG_ESDHC_DETECT_QUIRK
705 if (CONFIG_ESDHC_DETECT_QUIRK)
709 #if CONFIG_IS_ENABLED(DM_MMC)
710 if (priv->non_removable)
712 #ifdef CONFIG_DM_GPIO
713 if (dm_gpio_is_valid(&priv->cd_gpio))
714 return dm_gpio_get_value(&priv->cd_gpio);
718 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
724 static int esdhc_reset(struct fsl_esdhc *regs)
728 /* reset the controller */
729 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
731 /* hardware clears the bit when it is done */
732 start = get_timer(0);
733 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
734 if (get_timer(start) > 100) {
735 printf("MMC/SD: Reset never completed.\n");
743 #if !CONFIG_IS_ENABLED(DM_MMC)
744 static int esdhc_getcd(struct mmc *mmc)
746 struct fsl_esdhc_priv *priv = mmc->priv;
748 return esdhc_getcd_common(priv);
751 static int esdhc_init(struct mmc *mmc)
753 struct fsl_esdhc_priv *priv = mmc->priv;
755 return esdhc_init_common(priv, mmc);
758 static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
759 struct mmc_data *data)
761 struct fsl_esdhc_priv *priv = mmc->priv;
763 return esdhc_send_cmd_common(priv, mmc, cmd, data);
766 static int esdhc_set_ios(struct mmc *mmc)
768 struct fsl_esdhc_priv *priv = mmc->priv;
770 return esdhc_set_ios_common(priv, mmc);
773 static const struct mmc_ops esdhc_ops = {
774 .getcd = esdhc_getcd,
776 .send_cmd = esdhc_send_cmd,
777 .set_ios = esdhc_set_ios,
781 static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
782 struct fsl_esdhc_plat *plat)
784 struct mmc_config *cfg;
785 struct fsl_esdhc *regs;
786 u32 caps, voltage_caps;
792 regs = priv->esdhc_regs;
794 /* First reset the eSDHC controller */
795 ret = esdhc_reset(regs);
799 #ifndef CONFIG_FSL_USDHC
800 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
801 | SYSCTL_IPGEN | SYSCTL_CKEN);
803 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
804 VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
807 if (priv->vs18_enable)
808 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
810 writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
812 #ifndef CONFIG_DM_MMC
813 memset(cfg, '\0', sizeof(*cfg));
817 caps = esdhc_read32(®s->hostcapblt);
819 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
820 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
821 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
824 /* T4240 host controller capabilities register should have VS33 bit */
825 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
826 caps = caps | ESDHC_HOSTCAPBLT_VS33;
829 if (caps & ESDHC_HOSTCAPBLT_VS18)
830 voltage_caps |= MMC_VDD_165_195;
831 if (caps & ESDHC_HOSTCAPBLT_VS30)
832 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
833 if (caps & ESDHC_HOSTCAPBLT_VS33)
834 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
836 cfg->name = "FSL_SDHC";
837 #if !CONFIG_IS_ENABLED(DM_MMC)
838 cfg->ops = &esdhc_ops;
840 #ifdef CONFIG_SYS_SD_VOLTAGE
841 cfg->voltages = CONFIG_SYS_SD_VOLTAGE;
843 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
845 if ((cfg->voltages & voltage_caps) == 0) {
846 printf("voltage not supported by controller\n");
850 if (priv->bus_width == 8)
851 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
852 else if (priv->bus_width == 4)
853 cfg->host_caps = MMC_MODE_4BIT;
855 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
856 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
857 cfg->host_caps |= MMC_MODE_DDR_52MHz;
860 if (priv->bus_width > 0) {
861 if (priv->bus_width < 8)
862 cfg->host_caps &= ~MMC_MODE_8BIT;
863 if (priv->bus_width < 4)
864 cfg->host_caps &= ~MMC_MODE_4BIT;
867 if (caps & ESDHC_HOSTCAPBLT_HSS)
868 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
870 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
871 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
872 cfg->host_caps &= ~MMC_MODE_8BIT;
876 cfg->f_max = min(priv->sdhc_clk, (u32)52000000);
878 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
883 #if !CONFIG_IS_ENABLED(DM_MMC)
884 static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
885 struct fsl_esdhc_priv *priv)
890 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
891 priv->bus_width = cfg->max_bus_width;
892 priv->sdhc_clk = cfg->sdhc_clk;
893 priv->wp_enable = cfg->wp_enable;
894 priv->vs18_enable = cfg->vs18_enable;
899 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
901 struct fsl_esdhc_plat *plat;
902 struct fsl_esdhc_priv *priv;
909 priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
912 plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
918 ret = fsl_esdhc_cfg_to_priv(cfg, priv);
920 debug("%s xlate failure\n", __func__);
926 ret = fsl_esdhc_init(priv, plat);
928 debug("%s init failure\n", __func__);
934 mmc = mmc_create(&plat->cfg, priv);
943 int fsl_esdhc_mmc_init(bd_t *bis)
945 struct fsl_esdhc_cfg *cfg;
947 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
948 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
949 cfg->sdhc_clk = gd->arch.sdhc_clk;
950 return fsl_esdhc_initialize(bis, cfg);
954 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
955 void mmc_adapter_card_type_ident(void)
960 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
961 gd->arch.sdhc_adapter = card_id;
964 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
965 value = QIXIS_READ(brdcfg[5]);
966 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
967 QIXIS_WRITE(brdcfg[5], value);
969 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
970 value = QIXIS_READ(pwr_ctl[1]);
971 value |= QIXIS_EVDD_BY_SDHC_VS;
972 QIXIS_WRITE(pwr_ctl[1], value);
974 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
975 value = QIXIS_READ(brdcfg[5]);
976 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
977 QIXIS_WRITE(brdcfg[5], value);
979 case QIXIS_ESDHC_ADAPTER_TYPE_RSV:
981 case QIXIS_ESDHC_ADAPTER_TYPE_MMC:
983 case QIXIS_ESDHC_ADAPTER_TYPE_SD:
985 case QIXIS_ESDHC_NO_ADAPTER:
993 #ifdef CONFIG_OF_LIBFDT
994 __weak int esdhc_status_fixup(void *blob, const char *compat)
996 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
997 if (!hwconfig("esdhc")) {
998 do_fixup_by_compat(blob, compat, "status", "disabled",
999 sizeof("disabled"), 1);
1006 void fdt_fixup_esdhc(void *blob, bd_t *bd)
1008 const char *compat = "fsl,esdhc";
1010 if (esdhc_status_fixup(blob, compat))
1013 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
1014 do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
1015 gd->arch.sdhc_clk, 1);
1017 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
1018 gd->arch.sdhc_clk, 1);
1020 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1021 do_fixup_by_compat_u32(blob, compat, "adapter-type",
1022 (u32)(gd->arch.sdhc_adapter), 1);
1027 #if CONFIG_IS_ENABLED(DM_MMC)
1028 #include <asm/arch/clock.h>
1029 __weak void init_clk_usdhc(u32 index)
1033 static int fsl_esdhc_probe(struct udevice *dev)
1035 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1036 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1037 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1038 #ifdef CONFIG_DM_REGULATOR
1039 struct udevice *vqmmc_dev;
1046 addr = dev_read_addr(dev);
1047 if (addr == FDT_ADDR_T_NONE)
1050 priv->esdhc_regs = (struct fsl_esdhc *)addr;
1053 val = dev_read_u32_default(dev, "bus-width", -1);
1055 priv->bus_width = 8;
1057 priv->bus_width = 4;
1059 priv->bus_width = 1;
1061 if (dev_read_bool(dev, "non-removable")) {
1062 priv->non_removable = 1;
1064 priv->non_removable = 0;
1065 #ifdef CONFIG_DM_GPIO
1066 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
1071 priv->wp_enable = 1;
1073 #ifdef CONFIG_DM_GPIO
1074 ret = gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
1077 priv->wp_enable = 0;
1080 priv->vs18_enable = 0;
1082 #ifdef CONFIG_DM_REGULATOR
1084 * If emmc I/O has a fixed voltage at 1.8V, this must be provided,
1085 * otherwise, emmc will work abnormally.
1087 ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
1089 dev_dbg(dev, "no vqmmc-supply\n");
1091 ret = regulator_set_enable(vqmmc_dev, true);
1093 dev_err(dev, "fail to enable vqmmc-supply\n");
1097 if (regulator_get_value(vqmmc_dev) == 1800000)
1098 priv->vs18_enable = 1;
1104 * Because lack of clk driver, if SDHC clk is not enabled,
1105 * need to enable it first before this driver is invoked.
1107 * we use MXC_ESDHC_CLK to get clk freq.
1108 * If one would like to make this function work,
1109 * the aliases should be provided in dts as this:
1117 * Then if your board only supports mmc2 and mmc3, but we can
1118 * correctly get the seq as 2 and 3, then let mxc_get_clock
1122 init_clk_usdhc(dev->seq);
1124 priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
1125 if (priv->sdhc_clk <= 0) {
1126 dev_err(dev, "Unable to get clk for %s\n", dev->name);
1130 ret = fsl_esdhc_init(priv, plat);
1132 dev_err(dev, "fsl_esdhc_init failure\n");
1137 mmc->cfg = &plat->cfg;
1141 return esdhc_init_common(priv, mmc);
1144 #if CONFIG_IS_ENABLED(DM_MMC)
1145 static int fsl_esdhc_get_cd(struct udevice *dev)
1147 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1150 return esdhc_getcd_common(priv);
1153 static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1154 struct mmc_data *data)
1156 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1157 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1159 return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
1162 static int fsl_esdhc_set_ios(struct udevice *dev)
1164 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1165 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1167 return esdhc_set_ios_common(priv, &plat->mmc);
1170 static const struct dm_mmc_ops fsl_esdhc_ops = {
1171 .get_cd = fsl_esdhc_get_cd,
1172 .send_cmd = fsl_esdhc_send_cmd,
1173 .set_ios = fsl_esdhc_set_ios,
1177 static const struct udevice_id fsl_esdhc_ids[] = {
1178 { .compatible = "fsl,imx6ul-usdhc", },
1179 { .compatible = "fsl,imx6sx-usdhc", },
1180 { .compatible = "fsl,imx6sl-usdhc", },
1181 { .compatible = "fsl,imx6q-usdhc", },
1182 { .compatible = "fsl,imx7d-usdhc", },
1183 { .compatible = "fsl,imx7ulp-usdhc", },
1184 { .compatible = "fsl,esdhc", },
1188 #if CONFIG_IS_ENABLED(BLK)
1189 static int fsl_esdhc_bind(struct udevice *dev)
1191 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1193 return mmc_bind(dev, &plat->mmc, &plat->cfg);
1197 U_BOOT_DRIVER(fsl_esdhc) = {
1198 .name = "fsl-esdhc-mmc",
1200 .of_match = fsl_esdhc_ids,
1201 .ops = &fsl_esdhc_ops,
1202 #if CONFIG_IS_ENABLED(BLK)
1203 .bind = fsl_esdhc_bind,
1205 .probe = fsl_esdhc_probe,
1206 .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
1207 .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),