2 * Copyright 2007,2010 Freescale Semiconductor, Inc
5 * Based vaguely on the pxa mmc code:
7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
36 #include <fsl_esdhc.h>
37 #include <fdt_support.h>
40 DECLARE_GLOBAL_DATA_PTR;
69 /* Return the XFERTYP flags for a given command and data packet */
70 uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
75 xfertyp |= XFERTYP_DPSEL | XFERTYP_DMAEN;
77 if (data->blocks > 1) {
78 xfertyp |= XFERTYP_MSBSEL;
79 xfertyp |= XFERTYP_BCEN;
82 if (data->flags & MMC_DATA_READ)
83 xfertyp |= XFERTYP_DTDSEL;
86 if (cmd->resp_type & MMC_RSP_CRC)
87 xfertyp |= XFERTYP_CCCEN;
88 if (cmd->resp_type & MMC_RSP_OPCODE)
89 xfertyp |= XFERTYP_CICEN;
90 if (cmd->resp_type & MMC_RSP_136)
91 xfertyp |= XFERTYP_RSPTYP_136;
92 else if (cmd->resp_type & MMC_RSP_BUSY)
93 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
94 else if (cmd->resp_type & MMC_RSP_PRESENT)
95 xfertyp |= XFERTYP_RSPTYP_48;
97 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
100 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
104 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
105 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
107 wml_value = data->blocksize/4;
109 if (data->flags & MMC_DATA_READ) {
110 if (wml_value > 0x10)
113 wml_value = 0x100000 | wml_value;
115 esdhc_write32(®s->dsaddr, (u32)data->dest);
117 if (wml_value > 0x80)
119 if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) {
120 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
123 wml_value = wml_value << 16 | 0x10;
124 esdhc_write32(®s->dsaddr, (u32)data->src);
127 esdhc_write32(®s->wml, wml_value);
129 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
131 /* Calculate the timeout period for data transactions */
132 timeout = fls(mmc->tran_speed/10) - 1;
141 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
148 * Sends a command out on the bus. Takes the mmc pointer,
149 * a command pointer, and an optional data pointer.
152 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
156 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
157 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
159 esdhc_write32(®s->irqstat, -1);
163 /* Wait for the bus to be idle */
164 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
165 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
168 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
171 /* Wait at least 8 SD clock cycles before the next command */
173 * Note: This is way more than 8 cycles, but 1ms seems to
174 * resolve timing issues with some cards
178 /* Set up for a data transfer if we have one */
182 err = esdhc_setup_data(mmc, data);
187 /* Figure out the transfer arguments */
188 xfertyp = esdhc_xfertyp(cmd, data);
190 /* Send the command */
191 esdhc_write32(®s->cmdarg, cmd->cmdarg);
192 esdhc_write32(®s->xfertyp, xfertyp);
194 /* Wait for the command to complete */
195 while (!(esdhc_read32(®s->irqstat) & IRQSTAT_CC))
198 irqstat = esdhc_read32(®s->irqstat);
199 esdhc_write32(®s->irqstat, irqstat);
201 if (irqstat & CMD_ERR)
204 if (irqstat & IRQSTAT_CTOE)
207 /* Copy the response to the response buffer */
208 if (cmd->resp_type & MMC_RSP_136) {
209 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
211 cmdrsp3 = esdhc_read32(®s->cmdrsp3);
212 cmdrsp2 = esdhc_read32(®s->cmdrsp2);
213 cmdrsp1 = esdhc_read32(®s->cmdrsp1);
214 cmdrsp0 = esdhc_read32(®s->cmdrsp0);
215 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
216 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
217 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
218 cmd->response[3] = (cmdrsp0 << 8);
220 cmd->response[0] = esdhc_read32(®s->cmdrsp0);
222 /* Wait until all of the blocks are transferred */
225 irqstat = esdhc_read32(®s->irqstat);
227 if (irqstat & DATA_ERR)
230 if (irqstat & IRQSTAT_DTOE)
232 } while (!(irqstat & IRQSTAT_TC) &&
233 (esdhc_read32(®s->prsstat) & PRSSTAT_DLA));
236 esdhc_write32(®s->irqstat, -1);
241 void set_sysctl(struct mmc *mmc, uint clock)
243 int sdhc_clk = gd->sdhc_clk;
245 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
246 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
249 if (clock < mmc->f_min)
252 if (sdhc_clk / 16 > clock) {
253 for (pre_div = 2; pre_div < 256; pre_div *= 2)
254 if ((sdhc_clk / pre_div) <= (clock * 16))
259 for (div = 1; div <= 16; div++)
260 if ((sdhc_clk / (div * pre_div)) <= clock)
266 clk = (pre_div << 8) | (div << 4);
268 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
270 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
274 clk = SYSCTL_PEREN | SYSCTL_CKEN;
276 esdhc_setbits32(®s->sysctl, clk);
279 static void esdhc_set_ios(struct mmc *mmc)
281 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
282 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
284 /* Set the clock speed */
285 set_sysctl(mmc, mmc->clock);
287 /* Set the bus width */
288 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
290 if (mmc->bus_width == 4)
291 esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
292 else if (mmc->bus_width == 8)
293 esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
297 static int esdhc_init(struct mmc *mmc)
299 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
300 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
305 /* Enable cache snooping */
306 if (cfg && !cfg->no_snoop)
307 esdhc_write32(®s->scr, 0x00000040);
309 /* Reset the entire host controller */
310 esdhc_write32(®s->sysctl, SYSCTL_RSTA);
312 /* Wait until the controller is available */
313 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
316 esdhc_write32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
318 /* Set the initial clock speed */
319 set_sysctl(mmc, 400000);
321 /* Disable the BRR and BWR bits in IRQSTAT */
322 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
324 /* Put the PROCTL reg back to the default */
325 esdhc_write32(®s->proctl, PROCTL_INIT);
327 /* Set timout to the maximum value */
328 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
330 /* Check if there is a callback for detecting the card */
331 if (board_mmc_getcd(&card_absent, mmc)) {
333 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) &&
347 static void esdhc_reset(struct fsl_esdhc *regs)
349 unsigned long timeout = 100; /* wait max 100 ms */
351 /* reset the controller */
352 esdhc_write32(®s->sysctl, SYSCTL_RSTA);
354 /* hardware clears the bit when it is done */
355 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
358 printf("MMC/SD: Reset never completed.\n");
361 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
363 struct fsl_esdhc *regs;
370 mmc = malloc(sizeof(struct mmc));
372 sprintf(mmc->name, "FSL_ESDHC");
373 regs = (struct fsl_esdhc *)cfg->esdhc_base;
375 /* First reset the eSDHC controller */
379 mmc->send_cmd = esdhc_send_cmd;
380 mmc->set_ios = esdhc_set_ios;
381 mmc->init = esdhc_init;
383 caps = regs->hostcapblt;
385 if (caps & ESDHC_HOSTCAPBLT_VS18)
386 mmc->voltages |= MMC_VDD_165_195;
387 if (caps & ESDHC_HOSTCAPBLT_VS30)
388 mmc->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
389 if (caps & ESDHC_HOSTCAPBLT_VS33)
390 mmc->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
392 mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
394 if (caps & ESDHC_HOSTCAPBLT_HSS)
395 mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
398 mmc->f_max = MIN(gd->sdhc_clk, 50000000);
405 int fsl_esdhc_mmc_init(bd_t *bis)
407 struct fsl_esdhc_cfg *cfg;
409 cfg = malloc(sizeof(struct fsl_esdhc_cfg));
410 memset(cfg, 0, sizeof(struct fsl_esdhc_cfg));
411 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
412 return fsl_esdhc_initialize(bis, cfg);
415 #ifdef CONFIG_OF_LIBFDT
416 void fdt_fixup_esdhc(void *blob, bd_t *bd)
418 const char *compat = "fsl,esdhc";
419 const char *status = "okay";
421 if (!hwconfig("esdhc")) {
426 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
429 do_fixup_by_compat(blob, compat, "status", status,
430 strlen(status) + 1, 1);