2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
5 * Based vaguely on the pxa mmc code:
7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
9 * SPDX-License-Identifier: GPL-2.0+
19 #include <power/regulator.h>
21 #include <fsl_esdhc.h>
22 #include <fdt_support.h>
25 #include <asm-generic/gpio.h>
27 DECLARE_GLOBAL_DATA_PTR;
29 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
31 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
32 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
33 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
37 uint dsaddr; /* SDMA system address register */
38 uint blkattr; /* Block attributes register */
39 uint cmdarg; /* Command argument register */
40 uint xfertyp; /* Transfer type register */
41 uint cmdrsp0; /* Command response 0 register */
42 uint cmdrsp1; /* Command response 1 register */
43 uint cmdrsp2; /* Command response 2 register */
44 uint cmdrsp3; /* Command response 3 register */
45 uint datport; /* Buffer data port register */
46 uint prsstat; /* Present state register */
47 uint proctl; /* Protocol control register */
48 uint sysctl; /* System Control Register */
49 uint irqstat; /* Interrupt status register */
50 uint irqstaten; /* Interrupt status enable register */
51 uint irqsigen; /* Interrupt signal enable register */
52 uint autoc12err; /* Auto CMD error status register */
53 uint hostcapblt; /* Host controller capabilities register */
54 uint wml; /* Watermark level register */
55 uint mixctrl; /* For USDHC */
56 char reserved1[4]; /* reserved */
57 uint fevt; /* Force event register */
58 uint admaes; /* ADMA error status register */
59 uint adsaddr; /* ADMA system address register */
63 uint clktunectrlstatus;
69 uint hostver; /* Host controller version register */
70 char reserved5[4]; /* reserved */
71 uint dmaerraddr; /* DMA error address register */
72 char reserved6[4]; /* reserved */
73 uint dmaerrattr; /* DMA error attribute register */
74 char reserved7[4]; /* reserved */
75 uint hostcapblt2; /* Host controller capabilities register 2 */
76 char reserved8[8]; /* reserved */
77 uint tcr; /* Tuning control register */
78 char reserved9[28]; /* reserved */
79 uint sddirctl; /* SD direction control register */
80 char reserved10[712];/* reserved */
81 uint scr; /* eSDHC control register */
85 * struct fsl_esdhc_priv
87 * @esdhc_regs: registers of the sdhc controller
88 * @sdhc_clk: Current clk of the sdhc controller
89 * @bus_width: bus width, 1bit, 4bit or 8bit
92 * Following is used when Driver Model is enabled for MMC
93 * @dev: pointer for the device
94 * @non_removable: 0: removable; 1: non-removable
95 * @wp_enable: 1: enable checking wp; 0: no check
96 * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
97 * @cd_gpio: gpio for card detection
98 * @wp_gpio: gpio for write protection
100 struct fsl_esdhc_priv {
101 struct fsl_esdhc *esdhc_regs;
102 unsigned int sdhc_clk;
103 unsigned int bus_width;
104 struct mmc_config cfg;
110 #ifdef CONFIG_DM_GPIO
111 struct gpio_desc cd_gpio;
112 struct gpio_desc wp_gpio;
116 /* Return the XFERTYP flags for a given command and data packet */
117 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
122 xfertyp |= XFERTYP_DPSEL;
123 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
124 xfertyp |= XFERTYP_DMAEN;
126 if (data->blocks > 1) {
127 xfertyp |= XFERTYP_MSBSEL;
128 xfertyp |= XFERTYP_BCEN;
129 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
130 xfertyp |= XFERTYP_AC12EN;
134 if (data->flags & MMC_DATA_READ)
135 xfertyp |= XFERTYP_DTDSEL;
138 if (cmd->resp_type & MMC_RSP_CRC)
139 xfertyp |= XFERTYP_CCCEN;
140 if (cmd->resp_type & MMC_RSP_OPCODE)
141 xfertyp |= XFERTYP_CICEN;
142 if (cmd->resp_type & MMC_RSP_136)
143 xfertyp |= XFERTYP_RSPTYP_136;
144 else if (cmd->resp_type & MMC_RSP_BUSY)
145 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
146 else if (cmd->resp_type & MMC_RSP_PRESENT)
147 xfertyp |= XFERTYP_RSPTYP_48;
149 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
150 xfertyp |= XFERTYP_CMDTYP_ABORT;
152 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
155 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
157 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
160 esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
162 struct fsl_esdhc_priv *priv = mmc->priv;
163 struct fsl_esdhc *regs = priv->esdhc_regs;
171 if (data->flags & MMC_DATA_READ) {
172 blocks = data->blocks;
175 timeout = PIO_TIMEOUT;
176 size = data->blocksize;
177 irqstat = esdhc_read32(®s->irqstat);
178 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)
181 printf("\nData Read Failed in PIO Mode.");
184 while (size && (!(irqstat & IRQSTAT_TC))) {
185 udelay(100); /* Wait before last byte transfer complete */
186 irqstat = esdhc_read32(®s->irqstat);
187 databuf = in_le32(®s->datport);
188 *((uint *)buffer) = databuf;
195 blocks = data->blocks;
196 buffer = (char *)data->src;
198 timeout = PIO_TIMEOUT;
199 size = data->blocksize;
200 irqstat = esdhc_read32(®s->irqstat);
201 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)
204 printf("\nData Write Failed in PIO Mode.");
207 while (size && (!(irqstat & IRQSTAT_TC))) {
208 udelay(100); /* Wait before last byte transfer complete */
209 databuf = *((uint *)buffer);
212 irqstat = esdhc_read32(®s->irqstat);
213 out_le32(®s->datport, databuf);
221 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
224 struct fsl_esdhc_priv *priv = mmc->priv;
225 struct fsl_esdhc *regs = priv->esdhc_regs;
226 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
231 wml_value = data->blocksize/4;
233 if (data->flags & MMC_DATA_READ) {
234 if (wml_value > WML_RD_WML_MAX)
235 wml_value = WML_RD_WML_MAX_VAL;
237 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
238 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
239 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
240 addr = virt_to_phys((void *)(data->dest));
241 if (upper_32_bits(addr))
242 printf("Error found for upper 32 bits\n");
244 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
246 esdhc_write32(®s->dsaddr, (u32)data->dest);
250 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
251 flush_dcache_range((ulong)data->src,
252 (ulong)data->src+data->blocks
255 if (wml_value > WML_WR_WML_MAX)
256 wml_value = WML_WR_WML_MAX_VAL;
257 if (priv->wp_enable) {
258 if ((esdhc_read32(®s->prsstat) &
259 PRSSTAT_WPSPL) == 0) {
260 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
265 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
267 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
268 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
269 addr = virt_to_phys((void *)(data->src));
270 if (upper_32_bits(addr))
271 printf("Error found for upper 32 bits\n");
273 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
275 esdhc_write32(®s->dsaddr, (u32)data->src);
280 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
282 /* Calculate the timeout period for data transactions */
284 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
285 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
286 * So, Number of SD Clock cycles for 0.25sec should be minimum
287 * (SD Clock/sec * 0.25 sec) SD Clock cycles
288 * = (mmc->clock * 1/4) SD Clock cycles
290 * => (2^(timeout+13)) >= mmc->clock * 1/4
291 * Taking log2 both the sides
292 * => timeout + 13 >= log2(mmc->clock/4)
293 * Rounding up to next power of 2
294 * => timeout + 13 = log2(mmc->clock/4) + 1
295 * => timeout + 13 = fls(mmc->clock/4)
297 * However, the MMC spec "It is strongly recommended for hosts to
298 * implement more than 500ms timeout value even if the card
299 * indicates the 250ms maximum busy length." Even the previous
300 * value of 300ms is known to be insufficient for some cards.
302 * => timeout + 13 = fls(mmc->clock/2)
304 timeout = fls(mmc->clock/2);
313 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
314 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
318 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
321 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
326 static void check_and_invalidate_dcache_range
327 (struct mmc_cmd *cmd,
328 struct mmc_data *data) {
331 unsigned size = roundup(ARCH_DMA_MINALIGN,
332 data->blocks*data->blocksize);
333 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
336 addr = virt_to_phys((void *)(data->dest));
337 if (upper_32_bits(addr))
338 printf("Error found for upper 32 bits\n");
340 start = lower_32_bits(addr);
342 start = (unsigned)data->dest;
345 invalidate_dcache_range(start, end);
349 * Sends a command out on the bus. Takes the mmc pointer,
350 * a command pointer, and an optional data pointer.
353 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
358 struct fsl_esdhc_priv *priv = mmc->priv;
359 struct fsl_esdhc *regs = priv->esdhc_regs;
361 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
362 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
366 esdhc_write32(®s->irqstat, -1);
370 /* Wait for the bus to be idle */
371 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
372 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
375 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
378 /* Wait at least 8 SD clock cycles before the next command */
380 * Note: This is way more than 8 cycles, but 1ms seems to
381 * resolve timing issues with some cards
385 /* Set up for a data transfer if we have one */
387 err = esdhc_setup_data(mmc, data);
391 if (data->flags & MMC_DATA_READ)
392 check_and_invalidate_dcache_range(cmd, data);
395 /* Figure out the transfer arguments */
396 xfertyp = esdhc_xfertyp(cmd, data);
399 esdhc_write32(®s->irqsigen, 0);
401 /* Send the command */
402 esdhc_write32(®s->cmdarg, cmd->cmdarg);
403 #if defined(CONFIG_FSL_USDHC)
404 esdhc_write32(®s->mixctrl,
405 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
406 | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
407 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000);
409 esdhc_write32(®s->xfertyp, xfertyp);
412 /* Wait for the command to complete */
413 while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE)))
416 irqstat = esdhc_read32(®s->irqstat);
418 if (irqstat & CMD_ERR) {
423 if (irqstat & IRQSTAT_CTOE) {
428 /* Switch voltage to 1.8V if CMD11 succeeded */
429 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
430 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
432 printf("Run CMD11 1.8V switch\n");
433 /* Sleep for 5 ms - max time for card to switch to 1.8V */
437 /* Workaround for ESDHC errata ENGcm03648 */
438 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
441 /* Poll on DATA0 line for cmd with busy signal for 600 ms */
442 while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
449 printf("Timeout waiting for DAT0 to go high!\n");
455 /* Copy the response to the response buffer */
456 if (cmd->resp_type & MMC_RSP_136) {
457 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
459 cmdrsp3 = esdhc_read32(®s->cmdrsp3);
460 cmdrsp2 = esdhc_read32(®s->cmdrsp2);
461 cmdrsp1 = esdhc_read32(®s->cmdrsp1);
462 cmdrsp0 = esdhc_read32(®s->cmdrsp0);
463 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
464 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
465 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
466 cmd->response[3] = (cmdrsp0 << 8);
468 cmd->response[0] = esdhc_read32(®s->cmdrsp0);
470 /* Wait until all of the blocks are transferred */
472 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
473 esdhc_pio_read_write(mmc, data);
476 irqstat = esdhc_read32(®s->irqstat);
478 if (irqstat & IRQSTAT_DTOE) {
483 if (irqstat & DATA_ERR) {
487 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
490 * Need invalidate the dcache here again to avoid any
491 * cache-fill during the DMA operations such as the
492 * speculative pre-fetching etc.
494 if (data->flags & MMC_DATA_READ)
495 check_and_invalidate_dcache_range(cmd, data);
500 /* Reset CMD and DATA portions on error */
502 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
504 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC)
508 esdhc_write32(®s->sysctl,
509 esdhc_read32(®s->sysctl) |
511 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
515 /* If this was CMD11, then notify that power cycle is needed */
516 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
517 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
520 esdhc_write32(®s->irqstat, -1);
525 static void set_sysctl(struct mmc *mmc, uint clock)
533 int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
534 struct fsl_esdhc_priv *priv = mmc->priv;
535 struct fsl_esdhc *regs = priv->esdhc_regs;
536 int sdhc_clk = priv->sdhc_clk;
539 if (clock < mmc->cfg->f_min)
540 clock = mmc->cfg->f_min;
542 while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
545 while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
551 clk = (pre_div << 8) | (div << 4);
553 #ifdef CONFIG_FSL_USDHC
554 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
556 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
559 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
563 #ifdef CONFIG_FSL_USDHC
564 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
566 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
571 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
572 static void esdhc_clock_control(struct mmc *mmc, bool enable)
574 struct fsl_esdhc_priv *priv = mmc->priv;
575 struct fsl_esdhc *regs = priv->esdhc_regs;
579 value = esdhc_read32(®s->sysctl);
582 value |= SYSCTL_CKEN;
584 value &= ~SYSCTL_CKEN;
586 esdhc_write32(®s->sysctl, value);
589 value = PRSSTAT_SDSTB;
590 while (!(esdhc_read32(®s->prsstat) & value)) {
592 printf("fsl_esdhc: Internal clock never stabilised.\n");
601 static int esdhc_set_ios(struct mmc *mmc)
603 struct fsl_esdhc_priv *priv = mmc->priv;
604 struct fsl_esdhc *regs = priv->esdhc_regs;
606 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
607 /* Select to use peripheral clock */
608 esdhc_clock_control(mmc, false);
609 esdhc_setbits32(®s->scr, ESDHCCTL_PCS);
610 esdhc_clock_control(mmc, true);
612 /* Set the clock speed */
613 set_sysctl(mmc, mmc->clock);
615 /* Set the bus width */
616 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
618 if (mmc->bus_width == 4)
619 esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
620 else if (mmc->bus_width == 8)
621 esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
626 static int esdhc_init(struct mmc *mmc)
628 struct fsl_esdhc_priv *priv = mmc->priv;
629 struct fsl_esdhc *regs = priv->esdhc_regs;
632 /* Reset the entire host controller */
633 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
635 /* Wait until the controller is available */
636 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
639 #if defined(CONFIG_FSL_USDHC)
640 /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
641 esdhc_write32(®s->mmcboot, 0x0);
642 /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
643 esdhc_write32(®s->mixctrl, 0x0);
644 esdhc_write32(®s->clktunectrlstatus, 0x0);
646 /* Put VEND_SPEC to default value */
647 esdhc_write32(®s->vendorspec, VENDORSPEC_INIT);
649 /* Disable DLL_CTRL delay line */
650 esdhc_write32(®s->dllctrl, 0x0);
654 /* Enable cache snooping */
655 esdhc_write32(®s->scr, 0x00000040);
658 #ifndef CONFIG_FSL_USDHC
659 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
661 esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
664 /* Set the initial clock speed */
665 mmc_set_clock(mmc, 400000);
667 /* Disable the BRR and BWR bits in IRQSTAT */
668 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
670 /* Put the PROCTL reg back to the default */
671 esdhc_write32(®s->proctl, PROCTL_INIT);
673 /* Set timout to the maximum value */
674 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
676 if (priv->vs18_enable)
677 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
682 static int esdhc_getcd(struct mmc *mmc)
684 struct fsl_esdhc_priv *priv = mmc->priv;
685 struct fsl_esdhc *regs = priv->esdhc_regs;
688 #ifdef CONFIG_ESDHC_DETECT_QUIRK
689 if (CONFIG_ESDHC_DETECT_QUIRK)
694 if (priv->non_removable)
696 #ifdef CONFIG_DM_GPIO
697 if (dm_gpio_is_valid(&priv->cd_gpio))
698 return dm_gpio_get_value(&priv->cd_gpio);
702 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
708 static void esdhc_reset(struct fsl_esdhc *regs)
710 unsigned long timeout = 100; /* wait max 100 ms */
712 /* reset the controller */
713 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
715 /* hardware clears the bit when it is done */
716 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
719 printf("MMC/SD: Reset never completed.\n");
722 static const struct mmc_ops esdhc_ops = {
723 .send_cmd = esdhc_send_cmd,
724 .set_ios = esdhc_set_ios,
726 .getcd = esdhc_getcd,
729 static int fsl_esdhc_init(struct fsl_esdhc_priv *priv)
731 struct fsl_esdhc *regs;
733 u32 caps, voltage_caps;
738 regs = priv->esdhc_regs;
740 /* First reset the eSDHC controller */
743 #ifndef CONFIG_FSL_USDHC
744 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
745 | SYSCTL_IPGEN | SYSCTL_CKEN);
747 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
748 VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
751 if (priv->vs18_enable)
752 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
754 writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
755 memset(&priv->cfg, 0, sizeof(priv->cfg));
758 caps = esdhc_read32(®s->hostcapblt);
760 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
761 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
762 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
765 /* T4240 host controller capabilities register should have VS33 bit */
766 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
767 caps = caps | ESDHC_HOSTCAPBLT_VS33;
770 if (caps & ESDHC_HOSTCAPBLT_VS18)
771 voltage_caps |= MMC_VDD_165_195;
772 if (caps & ESDHC_HOSTCAPBLT_VS30)
773 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
774 if (caps & ESDHC_HOSTCAPBLT_VS33)
775 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
777 priv->cfg.name = "FSL_SDHC";
778 priv->cfg.ops = &esdhc_ops;
779 #ifdef CONFIG_SYS_SD_VOLTAGE
780 priv->cfg.voltages = CONFIG_SYS_SD_VOLTAGE;
782 priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
784 if ((priv->cfg.voltages & voltage_caps) == 0) {
785 printf("voltage not supported by controller\n");
789 if (priv->bus_width == 8)
790 priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
791 else if (priv->bus_width == 4)
792 priv->cfg.host_caps = MMC_MODE_4BIT;
794 priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
795 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
796 priv->cfg.host_caps |= MMC_MODE_DDR_52MHz;
799 if (priv->bus_width > 0) {
800 if (priv->bus_width < 8)
801 priv->cfg.host_caps &= ~MMC_MODE_8BIT;
802 if (priv->bus_width < 4)
803 priv->cfg.host_caps &= ~MMC_MODE_4BIT;
806 if (caps & ESDHC_HOSTCAPBLT_HSS)
807 priv->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
809 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
810 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
811 priv->cfg.host_caps &= ~MMC_MODE_8BIT;
814 priv->cfg.f_min = 400000;
815 priv->cfg.f_max = min(priv->sdhc_clk, (u32)52000000);
817 priv->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
819 mmc = mmc_create(&priv->cfg, priv);
828 #ifndef CONFIG_DM_MMC
829 static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
830 struct fsl_esdhc_priv *priv)
835 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
836 priv->bus_width = cfg->max_bus_width;
837 priv->sdhc_clk = cfg->sdhc_clk;
838 priv->wp_enable = cfg->wp_enable;
839 priv->vs18_enable = cfg->vs18_enable;
844 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
846 struct fsl_esdhc_priv *priv;
852 priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
856 ret = fsl_esdhc_cfg_to_priv(cfg, priv);
858 debug("%s xlate failure\n", __func__);
863 ret = fsl_esdhc_init(priv);
865 debug("%s init failure\n", __func__);
873 int fsl_esdhc_mmc_init(bd_t *bis)
875 struct fsl_esdhc_cfg *cfg;
877 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
878 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
879 cfg->sdhc_clk = gd->arch.sdhc_clk;
880 return fsl_esdhc_initialize(bis, cfg);
884 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
885 void mmc_adapter_card_type_ident(void)
890 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
891 gd->arch.sdhc_adapter = card_id;
894 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
895 value = QIXIS_READ(brdcfg[5]);
896 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
897 QIXIS_WRITE(brdcfg[5], value);
899 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
900 value = QIXIS_READ(pwr_ctl[1]);
901 value |= QIXIS_EVDD_BY_SDHC_VS;
902 QIXIS_WRITE(pwr_ctl[1], value);
904 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
905 value = QIXIS_READ(brdcfg[5]);
906 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
907 QIXIS_WRITE(brdcfg[5], value);
909 case QIXIS_ESDHC_ADAPTER_TYPE_RSV:
911 case QIXIS_ESDHC_ADAPTER_TYPE_MMC:
913 case QIXIS_ESDHC_ADAPTER_TYPE_SD:
915 case QIXIS_ESDHC_NO_ADAPTER:
923 #ifdef CONFIG_OF_LIBFDT
924 __weak int esdhc_status_fixup(void *blob, const char *compat)
926 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
927 if (!hwconfig("esdhc")) {
928 do_fixup_by_compat(blob, compat, "status", "disabled",
929 sizeof("disabled"), 1);
933 do_fixup_by_compat(blob, compat, "status", "okay",
938 void fdt_fixup_esdhc(void *blob, bd_t *bd)
940 const char *compat = "fsl,esdhc";
942 if (esdhc_status_fixup(blob, compat))
945 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
946 do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
947 gd->arch.sdhc_clk, 1);
949 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
950 gd->arch.sdhc_clk, 1);
952 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
953 do_fixup_by_compat_u32(blob, compat, "adapter-type",
954 (u32)(gd->arch.sdhc_adapter), 1);
960 #include <asm/arch/clock.h>
961 __weak void init_clk_usdhc(u32 index)
965 static int fsl_esdhc_probe(struct udevice *dev)
967 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
968 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
969 const void *fdt = gd->fdt_blob;
970 int node = dev_of_offset(dev);
971 struct udevice *vqmmc_dev;
976 addr = devfdt_get_addr(dev);
977 if (addr == FDT_ADDR_T_NONE)
980 priv->esdhc_regs = (struct fsl_esdhc *)addr;
983 val = fdtdec_get_int(fdt, node, "bus-width", -1);
991 if (fdt_get_property(fdt, node, "non-removable", NULL)) {
992 priv->non_removable = 1;
994 priv->non_removable = 0;
995 #ifdef CONFIG_DM_GPIO
996 gpio_request_by_name_nodev(offset_to_ofnode(node), "cd-gpios",
997 0, &priv->cd_gpio, GPIOD_IS_IN);
1001 priv->wp_enable = 1;
1003 #ifdef CONFIG_DM_GPIO
1004 ret = gpio_request_by_name_nodev(offset_to_ofnode(node), "wp-gpios", 0,
1005 &priv->wp_gpio, GPIOD_IS_IN);
1007 priv->wp_enable = 0;
1010 priv->vs18_enable = 0;
1012 #ifdef CONFIG_DM_REGULATOR
1014 * If emmc I/O has a fixed voltage at 1.8V, this must be provided,
1015 * otherwise, emmc will work abnormally.
1017 ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
1019 dev_dbg(dev, "no vqmmc-supply\n");
1021 ret = regulator_set_enable(vqmmc_dev, true);
1023 dev_err(dev, "fail to enable vqmmc-supply\n");
1027 if (regulator_get_value(vqmmc_dev) == 1800000)
1028 priv->vs18_enable = 1;
1034 * Because lack of clk driver, if SDHC clk is not enabled,
1035 * need to enable it first before this driver is invoked.
1037 * we use MXC_ESDHC_CLK to get clk freq.
1038 * If one would like to make this function work,
1039 * the aliases should be provided in dts as this:
1047 * Then if your board only supports mmc2 and mmc3, but we can
1048 * correctly get the seq as 2 and 3, then let mxc_get_clock
1052 init_clk_usdhc(dev->seq);
1054 priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
1055 if (priv->sdhc_clk <= 0) {
1056 dev_err(dev, "Unable to get clk for %s\n", dev->name);
1060 ret = fsl_esdhc_init(priv);
1062 dev_err(dev, "fsl_esdhc_init failure\n");
1066 upriv->mmc = priv->mmc;
1067 priv->mmc->dev = dev;
1072 static const struct udevice_id fsl_esdhc_ids[] = {
1073 { .compatible = "fsl,imx6ul-usdhc", },
1074 { .compatible = "fsl,imx6sx-usdhc", },
1075 { .compatible = "fsl,imx6sl-usdhc", },
1076 { .compatible = "fsl,imx6q-usdhc", },
1077 { .compatible = "fsl,imx7d-usdhc", },
1078 { .compatible = "fsl,imx7ulp-usdhc", },
1079 { .compatible = "fsl,esdhc", },
1083 U_BOOT_DRIVER(fsl_esdhc) = {
1084 .name = "fsl-esdhc-mmc",
1086 .of_match = fsl_esdhc_ids,
1087 .probe = fsl_esdhc_probe,
1088 .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),