2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
5 * Based vaguely on the pxa mmc code:
7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
9 * SPDX-License-Identifier: GPL-2.0+
19 #include <power/regulator.h>
21 #include <fsl_esdhc.h>
22 #include <fdt_support.h>
25 #include <asm-generic/gpio.h>
27 DECLARE_GLOBAL_DATA_PTR;
29 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
31 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
32 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
33 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
37 uint dsaddr; /* SDMA system address register */
38 uint blkattr; /* Block attributes register */
39 uint cmdarg; /* Command argument register */
40 uint xfertyp; /* Transfer type register */
41 uint cmdrsp0; /* Command response 0 register */
42 uint cmdrsp1; /* Command response 1 register */
43 uint cmdrsp2; /* Command response 2 register */
44 uint cmdrsp3; /* Command response 3 register */
45 uint datport; /* Buffer data port register */
46 uint prsstat; /* Present state register */
47 uint proctl; /* Protocol control register */
48 uint sysctl; /* System Control Register */
49 uint irqstat; /* Interrupt status register */
50 uint irqstaten; /* Interrupt status enable register */
51 uint irqsigen; /* Interrupt signal enable register */
52 uint autoc12err; /* Auto CMD error status register */
53 uint hostcapblt; /* Host controller capabilities register */
54 uint wml; /* Watermark level register */
55 uint mixctrl; /* For USDHC */
56 char reserved1[4]; /* reserved */
57 uint fevt; /* Force event register */
58 uint admaes; /* ADMA error status register */
59 uint adsaddr; /* ADMA system address register */
63 uint clktunectrlstatus;
69 uint hostver; /* Host controller version register */
70 char reserved5[4]; /* reserved */
71 uint dmaerraddr; /* DMA error address register */
72 char reserved6[4]; /* reserved */
73 uint dmaerrattr; /* DMA error attribute register */
74 char reserved7[4]; /* reserved */
75 uint hostcapblt2; /* Host controller capabilities register 2 */
76 char reserved8[8]; /* reserved */
77 uint tcr; /* Tuning control register */
78 char reserved9[28]; /* reserved */
79 uint sddirctl; /* SD direction control register */
80 char reserved10[712];/* reserved */
81 uint scr; /* eSDHC control register */
85 * struct fsl_esdhc_priv
87 * @esdhc_regs: registers of the sdhc controller
88 * @sdhc_clk: Current clk of the sdhc controller
89 * @bus_width: bus width, 1bit, 4bit or 8bit
92 * Following is used when Driver Model is enabled for MMC
93 * @dev: pointer for the device
94 * @non_removable: 0: removable; 1: non-removable
95 * @wp_enable: 1: enable checking wp; 0: no check
96 * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
97 * @cd_gpio: gpio for card detection
98 * @wp_gpio: gpio for write protection
100 struct fsl_esdhc_priv {
101 struct fsl_esdhc *esdhc_regs;
102 unsigned int sdhc_clk;
103 unsigned int bus_width;
104 struct mmc_config cfg;
110 #ifdef CONFIG_DM_GPIO
111 struct gpio_desc cd_gpio;
112 struct gpio_desc wp_gpio;
116 /* Return the XFERTYP flags for a given command and data packet */
117 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
122 xfertyp |= XFERTYP_DPSEL;
123 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
124 xfertyp |= XFERTYP_DMAEN;
126 if (data->blocks > 1) {
127 xfertyp |= XFERTYP_MSBSEL;
128 xfertyp |= XFERTYP_BCEN;
129 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
130 xfertyp |= XFERTYP_AC12EN;
134 if (data->flags & MMC_DATA_READ)
135 xfertyp |= XFERTYP_DTDSEL;
138 if (cmd->resp_type & MMC_RSP_CRC)
139 xfertyp |= XFERTYP_CCCEN;
140 if (cmd->resp_type & MMC_RSP_OPCODE)
141 xfertyp |= XFERTYP_CICEN;
142 if (cmd->resp_type & MMC_RSP_136)
143 xfertyp |= XFERTYP_RSPTYP_136;
144 else if (cmd->resp_type & MMC_RSP_BUSY)
145 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
146 else if (cmd->resp_type & MMC_RSP_PRESENT)
147 xfertyp |= XFERTYP_RSPTYP_48;
149 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
150 xfertyp |= XFERTYP_CMDTYP_ABORT;
152 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
155 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
157 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
159 static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
160 struct mmc_data *data)
162 struct fsl_esdhc *regs = priv->esdhc_regs;
170 if (data->flags & MMC_DATA_READ) {
171 blocks = data->blocks;
174 timeout = PIO_TIMEOUT;
175 size = data->blocksize;
176 irqstat = esdhc_read32(®s->irqstat);
177 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)
180 printf("\nData Read Failed in PIO Mode.");
183 while (size && (!(irqstat & IRQSTAT_TC))) {
184 udelay(100); /* Wait before last byte transfer complete */
185 irqstat = esdhc_read32(®s->irqstat);
186 databuf = in_le32(®s->datport);
187 *((uint *)buffer) = databuf;
194 blocks = data->blocks;
195 buffer = (char *)data->src;
197 timeout = PIO_TIMEOUT;
198 size = data->blocksize;
199 irqstat = esdhc_read32(®s->irqstat);
200 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)
203 printf("\nData Write Failed in PIO Mode.");
206 while (size && (!(irqstat & IRQSTAT_TC))) {
207 udelay(100); /* Wait before last byte transfer complete */
208 databuf = *((uint *)buffer);
211 irqstat = esdhc_read32(®s->irqstat);
212 out_le32(®s->datport, databuf);
220 static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
221 struct mmc_data *data)
224 struct fsl_esdhc *regs = priv->esdhc_regs;
225 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
230 wml_value = data->blocksize/4;
232 if (data->flags & MMC_DATA_READ) {
233 if (wml_value > WML_RD_WML_MAX)
234 wml_value = WML_RD_WML_MAX_VAL;
236 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
237 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
238 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
239 addr = virt_to_phys((void *)(data->dest));
240 if (upper_32_bits(addr))
241 printf("Error found for upper 32 bits\n");
243 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
245 esdhc_write32(®s->dsaddr, (u32)data->dest);
249 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
250 flush_dcache_range((ulong)data->src,
251 (ulong)data->src+data->blocks
254 if (wml_value > WML_WR_WML_MAX)
255 wml_value = WML_WR_WML_MAX_VAL;
256 if (priv->wp_enable) {
257 if ((esdhc_read32(®s->prsstat) &
258 PRSSTAT_WPSPL) == 0) {
259 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
264 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
266 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
267 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
268 addr = virt_to_phys((void *)(data->src));
269 if (upper_32_bits(addr))
270 printf("Error found for upper 32 bits\n");
272 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
274 esdhc_write32(®s->dsaddr, (u32)data->src);
279 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
281 /* Calculate the timeout period for data transactions */
283 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
284 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
285 * So, Number of SD Clock cycles for 0.25sec should be minimum
286 * (SD Clock/sec * 0.25 sec) SD Clock cycles
287 * = (mmc->clock * 1/4) SD Clock cycles
289 * => (2^(timeout+13)) >= mmc->clock * 1/4
290 * Taking log2 both the sides
291 * => timeout + 13 >= log2(mmc->clock/4)
292 * Rounding up to next power of 2
293 * => timeout + 13 = log2(mmc->clock/4) + 1
294 * => timeout + 13 = fls(mmc->clock/4)
296 * However, the MMC spec "It is strongly recommended for hosts to
297 * implement more than 500ms timeout value even if the card
298 * indicates the 250ms maximum busy length." Even the previous
299 * value of 300ms is known to be insufficient for some cards.
301 * => timeout + 13 = fls(mmc->clock/2)
303 timeout = fls(mmc->clock/2);
312 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
313 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
317 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
320 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
325 static void check_and_invalidate_dcache_range
326 (struct mmc_cmd *cmd,
327 struct mmc_data *data) {
330 unsigned size = roundup(ARCH_DMA_MINALIGN,
331 data->blocks*data->blocksize);
332 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
335 addr = virt_to_phys((void *)(data->dest));
336 if (upper_32_bits(addr))
337 printf("Error found for upper 32 bits\n");
339 start = lower_32_bits(addr);
341 start = (unsigned)data->dest;
344 invalidate_dcache_range(start, end);
348 * Sends a command out on the bus. Takes the mmc pointer,
349 * a command pointer, and an optional data pointer.
351 static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
352 struct mmc_cmd *cmd, struct mmc_data *data)
357 struct fsl_esdhc *regs = priv->esdhc_regs;
359 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
360 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
364 esdhc_write32(®s->irqstat, -1);
368 /* Wait for the bus to be idle */
369 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
370 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
373 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
376 /* Wait at least 8 SD clock cycles before the next command */
378 * Note: This is way more than 8 cycles, but 1ms seems to
379 * resolve timing issues with some cards
383 /* Set up for a data transfer if we have one */
385 err = esdhc_setup_data(priv, mmc, data);
389 if (data->flags & MMC_DATA_READ)
390 check_and_invalidate_dcache_range(cmd, data);
393 /* Figure out the transfer arguments */
394 xfertyp = esdhc_xfertyp(cmd, data);
397 esdhc_write32(®s->irqsigen, 0);
399 /* Send the command */
400 esdhc_write32(®s->cmdarg, cmd->cmdarg);
401 #if defined(CONFIG_FSL_USDHC)
402 esdhc_write32(®s->mixctrl,
403 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
404 | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
405 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000);
407 esdhc_write32(®s->xfertyp, xfertyp);
410 /* Wait for the command to complete */
411 while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE)))
414 irqstat = esdhc_read32(®s->irqstat);
416 if (irqstat & CMD_ERR) {
421 if (irqstat & IRQSTAT_CTOE) {
426 /* Switch voltage to 1.8V if CMD11 succeeded */
427 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
428 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
430 printf("Run CMD11 1.8V switch\n");
431 /* Sleep for 5 ms - max time for card to switch to 1.8V */
435 /* Workaround for ESDHC errata ENGcm03648 */
436 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
439 /* Poll on DATA0 line for cmd with busy signal for 600 ms */
440 while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
447 printf("Timeout waiting for DAT0 to go high!\n");
453 /* Copy the response to the response buffer */
454 if (cmd->resp_type & MMC_RSP_136) {
455 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
457 cmdrsp3 = esdhc_read32(®s->cmdrsp3);
458 cmdrsp2 = esdhc_read32(®s->cmdrsp2);
459 cmdrsp1 = esdhc_read32(®s->cmdrsp1);
460 cmdrsp0 = esdhc_read32(®s->cmdrsp0);
461 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
462 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
463 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
464 cmd->response[3] = (cmdrsp0 << 8);
466 cmd->response[0] = esdhc_read32(®s->cmdrsp0);
468 /* Wait until all of the blocks are transferred */
470 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
471 esdhc_pio_read_write(priv, data);
474 irqstat = esdhc_read32(®s->irqstat);
476 if (irqstat & IRQSTAT_DTOE) {
481 if (irqstat & DATA_ERR) {
485 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
488 * Need invalidate the dcache here again to avoid any
489 * cache-fill during the DMA operations such as the
490 * speculative pre-fetching etc.
492 if (data->flags & MMC_DATA_READ)
493 check_and_invalidate_dcache_range(cmd, data);
498 /* Reset CMD and DATA portions on error */
500 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
502 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC)
506 esdhc_write32(®s->sysctl,
507 esdhc_read32(®s->sysctl) |
509 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
513 /* If this was CMD11, then notify that power cycle is needed */
514 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
515 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
518 esdhc_write32(®s->irqstat, -1);
523 static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
531 int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
532 struct fsl_esdhc *regs = priv->esdhc_regs;
533 int sdhc_clk = priv->sdhc_clk;
536 if (clock < mmc->cfg->f_min)
537 clock = mmc->cfg->f_min;
539 while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
542 while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
548 clk = (pre_div << 8) | (div << 4);
550 #ifdef CONFIG_FSL_USDHC
551 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
553 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
556 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
560 #ifdef CONFIG_FSL_USDHC
561 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
563 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
568 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
569 static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
571 struct fsl_esdhc *regs = priv->esdhc_regs;
575 value = esdhc_read32(®s->sysctl);
578 value |= SYSCTL_CKEN;
580 value &= ~SYSCTL_CKEN;
582 esdhc_write32(®s->sysctl, value);
585 value = PRSSTAT_SDSTB;
586 while (!(esdhc_read32(®s->prsstat) & value)) {
588 printf("fsl_esdhc: Internal clock never stabilised.\n");
597 static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
599 struct fsl_esdhc *regs = priv->esdhc_regs;
601 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
602 /* Select to use peripheral clock */
603 esdhc_clock_control(priv, false);
604 esdhc_setbits32(®s->scr, ESDHCCTL_PCS);
605 esdhc_clock_control(priv, true);
607 /* Set the clock speed */
608 set_sysctl(priv, mmc, mmc->clock);
610 /* Set the bus width */
611 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
613 if (mmc->bus_width == 4)
614 esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
615 else if (mmc->bus_width == 8)
616 esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
621 static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
623 struct fsl_esdhc *regs = priv->esdhc_regs;
626 /* Reset the entire host controller */
627 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
629 /* Wait until the controller is available */
630 start = get_timer(0);
631 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
632 if (get_timer(start) > 1000)
636 #if defined(CONFIG_FSL_USDHC)
637 /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
638 esdhc_write32(®s->mmcboot, 0x0);
639 /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
640 esdhc_write32(®s->mixctrl, 0x0);
641 esdhc_write32(®s->clktunectrlstatus, 0x0);
643 /* Put VEND_SPEC to default value */
644 esdhc_write32(®s->vendorspec, VENDORSPEC_INIT);
646 /* Disable DLL_CTRL delay line */
647 esdhc_write32(®s->dllctrl, 0x0);
651 /* Enable cache snooping */
652 esdhc_write32(®s->scr, 0x00000040);
655 #ifndef CONFIG_FSL_USDHC
656 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
658 esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
661 /* Set the initial clock speed */
662 mmc_set_clock(mmc, 400000);
664 /* Disable the BRR and BWR bits in IRQSTAT */
665 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
667 /* Put the PROCTL reg back to the default */
668 esdhc_write32(®s->proctl, PROCTL_INIT);
670 /* Set timout to the maximum value */
671 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
673 if (priv->vs18_enable)
674 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
679 static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
681 struct fsl_esdhc *regs = priv->esdhc_regs;
684 #ifdef CONFIG_ESDHC_DETECT_QUIRK
685 if (CONFIG_ESDHC_DETECT_QUIRK)
690 if (priv->non_removable)
692 #ifdef CONFIG_DM_GPIO
693 if (dm_gpio_is_valid(&priv->cd_gpio))
694 return dm_gpio_get_value(&priv->cd_gpio);
698 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
704 static int esdhc_reset(struct fsl_esdhc *regs)
708 /* reset the controller */
709 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
711 /* hardware clears the bit when it is done */
712 start = get_timer(0);
713 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
714 if (get_timer(start) > 100) {
715 printf("MMC/SD: Reset never completed.\n");
723 static int esdhc_getcd(struct mmc *mmc)
725 struct fsl_esdhc_priv *priv = mmc->priv;
727 return esdhc_getcd_common(priv);
730 static int esdhc_init(struct mmc *mmc)
732 struct fsl_esdhc_priv *priv = mmc->priv;
734 return esdhc_init_common(priv, mmc);
737 static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
738 struct mmc_data *data)
740 struct fsl_esdhc_priv *priv = mmc->priv;
742 return esdhc_send_cmd_common(priv, mmc, cmd, data);
745 static int esdhc_set_ios(struct mmc *mmc)
747 struct fsl_esdhc_priv *priv = mmc->priv;
749 return esdhc_set_ios_common(priv, mmc);
752 static const struct mmc_ops esdhc_ops = {
753 .getcd = esdhc_getcd,
755 .send_cmd = esdhc_send_cmd,
756 .set_ios = esdhc_set_ios,
759 static int fsl_esdhc_init(struct fsl_esdhc_priv *priv)
761 struct fsl_esdhc *regs;
763 u32 caps, voltage_caps;
769 regs = priv->esdhc_regs;
771 /* First reset the eSDHC controller */
772 ret = esdhc_reset(regs);
776 #ifndef CONFIG_FSL_USDHC
777 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
778 | SYSCTL_IPGEN | SYSCTL_CKEN);
780 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
781 VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
784 if (priv->vs18_enable)
785 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
787 writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
788 memset(&priv->cfg, 0, sizeof(priv->cfg));
791 caps = esdhc_read32(®s->hostcapblt);
793 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
794 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
795 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
798 /* T4240 host controller capabilities register should have VS33 bit */
799 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
800 caps = caps | ESDHC_HOSTCAPBLT_VS33;
803 if (caps & ESDHC_HOSTCAPBLT_VS18)
804 voltage_caps |= MMC_VDD_165_195;
805 if (caps & ESDHC_HOSTCAPBLT_VS30)
806 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
807 if (caps & ESDHC_HOSTCAPBLT_VS33)
808 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
810 priv->cfg.name = "FSL_SDHC";
811 priv->cfg.ops = &esdhc_ops;
812 #ifdef CONFIG_SYS_SD_VOLTAGE
813 priv->cfg.voltages = CONFIG_SYS_SD_VOLTAGE;
815 priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
817 if ((priv->cfg.voltages & voltage_caps) == 0) {
818 printf("voltage not supported by controller\n");
822 if (priv->bus_width == 8)
823 priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
824 else if (priv->bus_width == 4)
825 priv->cfg.host_caps = MMC_MODE_4BIT;
827 priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
828 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
829 priv->cfg.host_caps |= MMC_MODE_DDR_52MHz;
832 if (priv->bus_width > 0) {
833 if (priv->bus_width < 8)
834 priv->cfg.host_caps &= ~MMC_MODE_8BIT;
835 if (priv->bus_width < 4)
836 priv->cfg.host_caps &= ~MMC_MODE_4BIT;
839 if (caps & ESDHC_HOSTCAPBLT_HSS)
840 priv->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
842 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
843 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
844 priv->cfg.host_caps &= ~MMC_MODE_8BIT;
847 priv->cfg.f_min = 400000;
848 priv->cfg.f_max = min(priv->sdhc_clk, (u32)52000000);
850 priv->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
852 mmc = mmc_create(&priv->cfg, priv);
861 #ifndef CONFIG_DM_MMC
862 static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
863 struct fsl_esdhc_priv *priv)
868 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
869 priv->bus_width = cfg->max_bus_width;
870 priv->sdhc_clk = cfg->sdhc_clk;
871 priv->wp_enable = cfg->wp_enable;
872 priv->vs18_enable = cfg->vs18_enable;
877 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
879 struct fsl_esdhc_priv *priv;
885 priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
889 ret = fsl_esdhc_cfg_to_priv(cfg, priv);
891 debug("%s xlate failure\n", __func__);
896 ret = fsl_esdhc_init(priv);
898 debug("%s init failure\n", __func__);
906 int fsl_esdhc_mmc_init(bd_t *bis)
908 struct fsl_esdhc_cfg *cfg;
910 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
911 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
912 cfg->sdhc_clk = gd->arch.sdhc_clk;
913 return fsl_esdhc_initialize(bis, cfg);
917 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
918 void mmc_adapter_card_type_ident(void)
923 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
924 gd->arch.sdhc_adapter = card_id;
927 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
928 value = QIXIS_READ(brdcfg[5]);
929 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
930 QIXIS_WRITE(brdcfg[5], value);
932 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
933 value = QIXIS_READ(pwr_ctl[1]);
934 value |= QIXIS_EVDD_BY_SDHC_VS;
935 QIXIS_WRITE(pwr_ctl[1], value);
937 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
938 value = QIXIS_READ(brdcfg[5]);
939 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
940 QIXIS_WRITE(brdcfg[5], value);
942 case QIXIS_ESDHC_ADAPTER_TYPE_RSV:
944 case QIXIS_ESDHC_ADAPTER_TYPE_MMC:
946 case QIXIS_ESDHC_ADAPTER_TYPE_SD:
948 case QIXIS_ESDHC_NO_ADAPTER:
956 #ifdef CONFIG_OF_LIBFDT
957 __weak int esdhc_status_fixup(void *blob, const char *compat)
959 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
960 if (!hwconfig("esdhc")) {
961 do_fixup_by_compat(blob, compat, "status", "disabled",
962 sizeof("disabled"), 1);
969 void fdt_fixup_esdhc(void *blob, bd_t *bd)
971 const char *compat = "fsl,esdhc";
973 if (esdhc_status_fixup(blob, compat))
976 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
977 do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
978 gd->arch.sdhc_clk, 1);
980 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
981 gd->arch.sdhc_clk, 1);
983 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
984 do_fixup_by_compat_u32(blob, compat, "adapter-type",
985 (u32)(gd->arch.sdhc_adapter), 1);
991 #include <asm/arch/clock.h>
992 __weak void init_clk_usdhc(u32 index)
996 static int fsl_esdhc_probe(struct udevice *dev)
998 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
999 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1000 const void *fdt = gd->fdt_blob;
1001 int node = dev_of_offset(dev);
1002 #ifdef CONFIG_DM_REGULATOR
1003 struct udevice *vqmmc_dev;
1009 addr = devfdt_get_addr(dev);
1010 if (addr == FDT_ADDR_T_NONE)
1013 priv->esdhc_regs = (struct fsl_esdhc *)addr;
1016 val = fdtdec_get_int(fdt, node, "bus-width", -1);
1018 priv->bus_width = 8;
1020 priv->bus_width = 4;
1022 priv->bus_width = 1;
1024 if (fdt_get_property(fdt, node, "non-removable", NULL)) {
1025 priv->non_removable = 1;
1027 priv->non_removable = 0;
1028 #ifdef CONFIG_DM_GPIO
1029 gpio_request_by_name_nodev(offset_to_ofnode(node), "cd-gpios",
1030 0, &priv->cd_gpio, GPIOD_IS_IN);
1034 priv->wp_enable = 1;
1036 #ifdef CONFIG_DM_GPIO
1037 ret = gpio_request_by_name_nodev(offset_to_ofnode(node), "wp-gpios", 0,
1038 &priv->wp_gpio, GPIOD_IS_IN);
1040 priv->wp_enable = 0;
1043 priv->vs18_enable = 0;
1045 #ifdef CONFIG_DM_REGULATOR
1047 * If emmc I/O has a fixed voltage at 1.8V, this must be provided,
1048 * otherwise, emmc will work abnormally.
1050 ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
1052 dev_dbg(dev, "no vqmmc-supply\n");
1054 ret = regulator_set_enable(vqmmc_dev, true);
1056 dev_err(dev, "fail to enable vqmmc-supply\n");
1060 if (regulator_get_value(vqmmc_dev) == 1800000)
1061 priv->vs18_enable = 1;
1067 * Because lack of clk driver, if SDHC clk is not enabled,
1068 * need to enable it first before this driver is invoked.
1070 * we use MXC_ESDHC_CLK to get clk freq.
1071 * If one would like to make this function work,
1072 * the aliases should be provided in dts as this:
1080 * Then if your board only supports mmc2 and mmc3, but we can
1081 * correctly get the seq as 2 and 3, then let mxc_get_clock
1085 init_clk_usdhc(dev->seq);
1087 priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
1088 if (priv->sdhc_clk <= 0) {
1089 dev_err(dev, "Unable to get clk for %s\n", dev->name);
1093 ret = fsl_esdhc_init(priv);
1095 dev_err(dev, "fsl_esdhc_init failure\n");
1099 upriv->mmc = priv->mmc;
1100 priv->mmc->dev = dev;
1105 static const struct udevice_id fsl_esdhc_ids[] = {
1106 { .compatible = "fsl,imx6ul-usdhc", },
1107 { .compatible = "fsl,imx6sx-usdhc", },
1108 { .compatible = "fsl,imx6sl-usdhc", },
1109 { .compatible = "fsl,imx6q-usdhc", },
1110 { .compatible = "fsl,imx7d-usdhc", },
1111 { .compatible = "fsl,imx7ulp-usdhc", },
1112 { .compatible = "fsl,esdhc", },
1116 U_BOOT_DRIVER(fsl_esdhc) = {
1117 .name = "fsl-esdhc-mmc",
1119 .of_match = fsl_esdhc_ids,
1120 .probe = fsl_esdhc_probe,
1121 .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),