1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
6 * Based vaguely on the pxa mmc code:
8 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
19 #include <power/regulator.h>
21 #include <fsl_esdhc.h>
22 #include <fdt_support.h>
25 #include <asm-generic/gpio.h>
26 #include <dm/pinctrl.h>
28 DECLARE_GLOBAL_DATA_PTR;
30 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
32 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
33 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
34 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
36 #define MAX_TUNING_LOOP 40
39 uint dsaddr; /* SDMA system address register */
40 uint blkattr; /* Block attributes register */
41 uint cmdarg; /* Command argument register */
42 uint xfertyp; /* Transfer type register */
43 uint cmdrsp0; /* Command response 0 register */
44 uint cmdrsp1; /* Command response 1 register */
45 uint cmdrsp2; /* Command response 2 register */
46 uint cmdrsp3; /* Command response 3 register */
47 uint datport; /* Buffer data port register */
48 uint prsstat; /* Present state register */
49 uint proctl; /* Protocol control register */
50 uint sysctl; /* System Control Register */
51 uint irqstat; /* Interrupt status register */
52 uint irqstaten; /* Interrupt status enable register */
53 uint irqsigen; /* Interrupt signal enable register */
54 uint autoc12err; /* Auto CMD error status register */
55 uint hostcapblt; /* Host controller capabilities register */
56 uint wml; /* Watermark level register */
57 uint mixctrl; /* For USDHC */
58 char reserved1[4]; /* reserved */
59 uint fevt; /* Force event register */
60 uint admaes; /* ADMA error status register */
61 uint adsaddr; /* ADMA system address register */
65 uint clktunectrlstatus;
73 uint tuning_ctrl; /* on i.MX6/7/8 */
75 uint hostver; /* Host controller version register */
76 char reserved6[4]; /* reserved */
77 uint dmaerraddr; /* DMA error address register */
78 char reserved7[4]; /* reserved */
79 uint dmaerrattr; /* DMA error attribute register */
80 char reserved8[4]; /* reserved */
81 uint hostcapblt2; /* Host controller capabilities register 2 */
82 char reserved9[8]; /* reserved */
83 uint tcr; /* Tuning control register */
84 char reserved10[28]; /* reserved */
85 uint sddirctl; /* SD direction control register */
86 char reserved11[712];/* reserved */
87 uint scr; /* eSDHC control register */
90 struct fsl_esdhc_plat {
91 struct mmc_config cfg;
95 struct esdhc_soc_data {
101 * struct fsl_esdhc_priv
103 * @esdhc_regs: registers of the sdhc controller
104 * @sdhc_clk: Current clk of the sdhc controller
105 * @bus_width: bus width, 1bit, 4bit or 8bit
108 * Following is used when Driver Model is enabled for MMC
109 * @dev: pointer for the device
110 * @non_removable: 0: removable; 1: non-removable
111 * @wp_enable: 1: enable checking wp; 0: no check
112 * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
113 * @flags: ESDHC_FLAG_xx in include/fsl_esdhc.h
114 * @caps: controller capabilities
115 * @tuning_step: tuning step setting in tuning_ctrl register
116 * @start_tuning_tap: the start point for tuning in tuning_ctrl register
117 * @strobe_dll_delay_target: settings in strobe_dllctrl
118 * @signal_voltage: indicating the current voltage
119 * @cd_gpio: gpio for card detection
120 * @wp_gpio: gpio for write protection
122 struct fsl_esdhc_priv {
123 struct fsl_esdhc *esdhc_regs;
124 unsigned int sdhc_clk;
128 unsigned int bus_width;
129 #if !CONFIG_IS_ENABLED(BLK)
139 u32 tuning_start_tap;
140 u32 strobe_dll_delay_target;
142 #if IS_ENABLED(CONFIG_DM_REGULATOR)
143 struct udevice *vqmmc_dev;
144 struct udevice *vmmc_dev;
146 #ifdef CONFIG_DM_GPIO
147 struct gpio_desc cd_gpio;
148 struct gpio_desc wp_gpio;
152 /* Return the XFERTYP flags for a given command and data packet */
153 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
158 xfertyp |= XFERTYP_DPSEL;
159 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
160 xfertyp |= XFERTYP_DMAEN;
162 if (data->blocks > 1) {
163 xfertyp |= XFERTYP_MSBSEL;
164 xfertyp |= XFERTYP_BCEN;
165 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
166 xfertyp |= XFERTYP_AC12EN;
170 if (data->flags & MMC_DATA_READ)
171 xfertyp |= XFERTYP_DTDSEL;
174 if (cmd->resp_type & MMC_RSP_CRC)
175 xfertyp |= XFERTYP_CCCEN;
176 if (cmd->resp_type & MMC_RSP_OPCODE)
177 xfertyp |= XFERTYP_CICEN;
178 if (cmd->resp_type & MMC_RSP_136)
179 xfertyp |= XFERTYP_RSPTYP_136;
180 else if (cmd->resp_type & MMC_RSP_BUSY)
181 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
182 else if (cmd->resp_type & MMC_RSP_PRESENT)
183 xfertyp |= XFERTYP_RSPTYP_48;
185 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
186 xfertyp |= XFERTYP_CMDTYP_ABORT;
188 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
191 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
193 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
195 static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
196 struct mmc_data *data)
198 struct fsl_esdhc *regs = priv->esdhc_regs;
206 if (data->flags & MMC_DATA_READ) {
207 blocks = data->blocks;
210 start = get_timer(0);
211 size = data->blocksize;
212 irqstat = esdhc_read32(®s->irqstat);
213 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)) {
214 if (get_timer(start) > PIO_TIMEOUT) {
215 printf("\nData Read Failed in PIO Mode.");
219 while (size && (!(irqstat & IRQSTAT_TC))) {
220 udelay(100); /* Wait before last byte transfer complete */
221 irqstat = esdhc_read32(®s->irqstat);
222 databuf = in_le32(®s->datport);
223 *((uint *)buffer) = databuf;
230 blocks = data->blocks;
231 buffer = (char *)data->src;
233 start = get_timer(0);
234 size = data->blocksize;
235 irqstat = esdhc_read32(®s->irqstat);
236 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)) {
237 if (get_timer(start) > PIO_TIMEOUT) {
238 printf("\nData Write Failed in PIO Mode.");
242 while (size && (!(irqstat & IRQSTAT_TC))) {
243 udelay(100); /* Wait before last byte transfer complete */
244 databuf = *((uint *)buffer);
247 irqstat = esdhc_read32(®s->irqstat);
248 out_le32(®s->datport, databuf);
256 static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
257 struct mmc_data *data)
260 struct fsl_esdhc *regs = priv->esdhc_regs;
261 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
262 defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
267 wml_value = data->blocksize/4;
269 if (data->flags & MMC_DATA_READ) {
270 if (wml_value > WML_RD_WML_MAX)
271 wml_value = WML_RD_WML_MAX_VAL;
273 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
274 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
275 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
276 defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
277 addr = virt_to_phys((void *)(data->dest));
278 if (upper_32_bits(addr))
279 printf("Error found for upper 32 bits\n");
281 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
283 esdhc_write32(®s->dsaddr, (u32)data->dest);
287 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
288 flush_dcache_range((ulong)data->src,
289 (ulong)data->src+data->blocks
292 if (wml_value > WML_WR_WML_MAX)
293 wml_value = WML_WR_WML_MAX_VAL;
294 if (priv->wp_enable) {
295 if ((esdhc_read32(®s->prsstat) &
296 PRSSTAT_WPSPL) == 0) {
297 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
302 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
304 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
305 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
306 defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
307 addr = virt_to_phys((void *)(data->src));
308 if (upper_32_bits(addr))
309 printf("Error found for upper 32 bits\n");
311 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
313 esdhc_write32(®s->dsaddr, (u32)data->src);
318 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
320 /* Calculate the timeout period for data transactions */
322 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
323 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
324 * So, Number of SD Clock cycles for 0.25sec should be minimum
325 * (SD Clock/sec * 0.25 sec) SD Clock cycles
326 * = (mmc->clock * 1/4) SD Clock cycles
328 * => (2^(timeout+13)) >= mmc->clock * 1/4
329 * Taking log2 both the sides
330 * => timeout + 13 >= log2(mmc->clock/4)
331 * Rounding up to next power of 2
332 * => timeout + 13 = log2(mmc->clock/4) + 1
333 * => timeout + 13 = fls(mmc->clock/4)
335 * However, the MMC spec "It is strongly recommended for hosts to
336 * implement more than 500ms timeout value even if the card
337 * indicates the 250ms maximum busy length." Even the previous
338 * value of 300ms is known to be insufficient for some cards.
340 * => timeout + 13 = fls(mmc->clock/2)
342 timeout = fls(mmc->clock/2);
351 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
352 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
356 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
359 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
364 static void check_and_invalidate_dcache_range
365 (struct mmc_cmd *cmd,
366 struct mmc_data *data) {
369 unsigned size = roundup(ARCH_DMA_MINALIGN,
370 data->blocks*data->blocksize);
371 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
372 defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
375 addr = virt_to_phys((void *)(data->dest));
376 if (upper_32_bits(addr))
377 printf("Error found for upper 32 bits\n");
379 start = lower_32_bits(addr);
381 start = (unsigned)data->dest;
384 invalidate_dcache_range(start, end);
387 #ifdef CONFIG_MCF5441x
389 * Swaps 32-bit words to little-endian byte order.
391 static inline void sd_swap_dma_buff(struct mmc_data *data)
393 int i, size = data->blocksize >> 2;
394 u32 *buffer = (u32 *)data->dest;
397 while (data->blocks--) {
398 for (i = 0; i < size; i++) {
399 sw = __sw32(*buffer);
407 * Sends a command out on the bus. Takes the mmc pointer,
408 * a command pointer, and an optional data pointer.
410 static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
411 struct mmc_cmd *cmd, struct mmc_data *data)
416 u32 flags = IRQSTAT_CC | IRQSTAT_CTOE;
417 struct fsl_esdhc *regs = priv->esdhc_regs;
420 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
421 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
425 esdhc_write32(®s->irqstat, -1);
429 /* Wait for the bus to be idle */
430 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
431 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
434 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
437 /* Wait at least 8 SD clock cycles before the next command */
439 * Note: This is way more than 8 cycles, but 1ms seems to
440 * resolve timing issues with some cards
444 /* Set up for a data transfer if we have one */
446 err = esdhc_setup_data(priv, mmc, data);
450 if (data->flags & MMC_DATA_READ)
451 check_and_invalidate_dcache_range(cmd, data);
454 /* Figure out the transfer arguments */
455 xfertyp = esdhc_xfertyp(cmd, data);
458 esdhc_write32(®s->irqsigen, 0);
460 /* Send the command */
461 esdhc_write32(®s->cmdarg, cmd->cmdarg);
462 #if defined(CONFIG_FSL_USDHC)
463 esdhc_write32(®s->mixctrl,
464 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
465 | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
466 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000);
468 esdhc_write32(®s->xfertyp, xfertyp);
471 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
472 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))
475 /* Wait for the command to complete */
476 start = get_timer(0);
477 while (!(esdhc_read32(®s->irqstat) & flags)) {
478 if (get_timer(start) > 1000) {
484 irqstat = esdhc_read32(®s->irqstat);
486 if (irqstat & CMD_ERR) {
491 if (irqstat & IRQSTAT_CTOE) {
496 /* Switch voltage to 1.8V if CMD11 succeeded */
497 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
498 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
500 printf("Run CMD11 1.8V switch\n");
501 /* Sleep for 5 ms - max time for card to switch to 1.8V */
505 /* Workaround for ESDHC errata ENGcm03648 */
506 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
509 /* Poll on DATA0 line for cmd with busy signal for 600 ms */
510 while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
517 printf("Timeout waiting for DAT0 to go high!\n");
523 /* Copy the response to the response buffer */
524 if (cmd->resp_type & MMC_RSP_136) {
525 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
527 cmdrsp3 = esdhc_read32(®s->cmdrsp3);
528 cmdrsp2 = esdhc_read32(®s->cmdrsp2);
529 cmdrsp1 = esdhc_read32(®s->cmdrsp1);
530 cmdrsp0 = esdhc_read32(®s->cmdrsp0);
531 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
532 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
533 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
534 cmd->response[3] = (cmdrsp0 << 8);
536 cmd->response[0] = esdhc_read32(®s->cmdrsp0);
538 /* Wait until all of the blocks are transferred */
540 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
541 esdhc_pio_read_write(priv, data);
543 flags = DATA_COMPLETE;
544 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
545 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) {
550 irqstat = esdhc_read32(®s->irqstat);
552 if (irqstat & IRQSTAT_DTOE) {
557 if (irqstat & DATA_ERR) {
561 } while ((irqstat & flags) != flags);
564 * Need invalidate the dcache here again to avoid any
565 * cache-fill during the DMA operations such as the
566 * speculative pre-fetching etc.
568 if (data->flags & MMC_DATA_READ) {
569 check_and_invalidate_dcache_range(cmd, data);
570 #ifdef CONFIG_MCF5441x
571 sd_swap_dma_buff(data);
578 /* Reset CMD and DATA portions on error */
580 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
582 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC)
586 esdhc_write32(®s->sysctl,
587 esdhc_read32(®s->sysctl) |
589 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
593 /* If this was CMD11, then notify that power cycle is needed */
594 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
595 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
598 esdhc_write32(®s->irqstat, -1);
603 static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
605 struct fsl_esdhc *regs = priv->esdhc_regs;
609 /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
610 int pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1;
617 int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
618 int sdhc_clk = priv->sdhc_clk;
621 if (clock < mmc->cfg->f_min)
622 clock = mmc->cfg->f_min;
624 while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
627 while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
633 clk = (pre_div << 8) | (div << 4);
635 #ifdef CONFIG_FSL_USDHC
636 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
638 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
641 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
645 #ifdef CONFIG_FSL_USDHC
646 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
648 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
654 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
655 static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
657 struct fsl_esdhc *regs = priv->esdhc_regs;
661 value = esdhc_read32(®s->sysctl);
664 value |= SYSCTL_CKEN;
666 value &= ~SYSCTL_CKEN;
668 esdhc_write32(®s->sysctl, value);
671 value = PRSSTAT_SDSTB;
672 while (!(esdhc_read32(®s->prsstat) & value)) {
674 printf("fsl_esdhc: Internal clock never stabilised.\n");
683 #ifdef MMC_SUPPORTS_TUNING
684 static int esdhc_change_pinstate(struct udevice *dev)
686 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
689 switch (priv->mode) {
692 ret = pinctrl_select_state(dev, "state_100mhz");
697 ret = pinctrl_select_state(dev, "state_200mhz");
700 ret = pinctrl_select_state(dev, "default");
705 printf("%s %d error\n", __func__, priv->mode);
710 static void esdhc_reset_tuning(struct mmc *mmc)
712 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
713 struct fsl_esdhc *regs = priv->esdhc_regs;
715 if (priv->flags & ESDHC_FLAG_USDHC) {
716 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
717 esdhc_clrbits32(®s->autoc12err,
718 MIX_CTRL_SMPCLK_SEL |
724 static void esdhc_set_strobe_dll(struct mmc *mmc)
726 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
727 struct fsl_esdhc *regs = priv->esdhc_regs;
730 if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
731 writel(ESDHC_STROBE_DLL_CTRL_RESET, ®s->strobe_dllctrl);
734 * enable strobe dll ctrl and adjust the delay target
735 * for the uSDHC loopback read clock
737 val = ESDHC_STROBE_DLL_CTRL_ENABLE |
738 (priv->strobe_dll_delay_target <<
739 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
740 writel(val, ®s->strobe_dllctrl);
741 /* wait 1us to make sure strobe dll status register stable */
743 val = readl(®s->strobe_dllstat);
744 if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK))
745 pr_warn("HS400 strobe DLL status REF not lock!\n");
746 if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK))
747 pr_warn("HS400 strobe DLL status SLV not lock!\n");
751 static int esdhc_set_timing(struct mmc *mmc)
753 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
754 struct fsl_esdhc *regs = priv->esdhc_regs;
757 mixctrl = readl(®s->mixctrl);
758 mixctrl &= ~(MIX_CTRL_DDREN | MIX_CTRL_HS400_EN);
760 switch (mmc->selected_mode) {
763 esdhc_reset_tuning(mmc);
764 writel(mixctrl, ®s->mixctrl);
767 mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN;
768 writel(mixctrl, ®s->mixctrl);
769 esdhc_set_strobe_dll(mmc);
779 writel(mixctrl, ®s->mixctrl);
783 mixctrl |= MIX_CTRL_DDREN;
784 writel(mixctrl, ®s->mixctrl);
787 printf("Not supported %d\n", mmc->selected_mode);
791 priv->mode = mmc->selected_mode;
793 return esdhc_change_pinstate(mmc->dev);
796 static int esdhc_set_voltage(struct mmc *mmc)
798 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
799 struct fsl_esdhc *regs = priv->esdhc_regs;
802 priv->signal_voltage = mmc->signal_voltage;
803 switch (mmc->signal_voltage) {
804 case MMC_SIGNAL_VOLTAGE_330:
805 if (priv->vs18_enable)
807 #ifdef CONFIG_DM_REGULATOR
808 if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
809 ret = regulator_set_value(priv->vqmmc_dev, 3300000);
811 printf("Setting to 3.3V error");
819 esdhc_clrbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
820 if (!(esdhc_read32(®s->vendorspec) &
821 ESDHC_VENDORSPEC_VSELECT))
825 case MMC_SIGNAL_VOLTAGE_180:
826 #ifdef CONFIG_DM_REGULATOR
827 if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
828 ret = regulator_set_value(priv->vqmmc_dev, 1800000);
830 printf("Setting to 1.8V error");
835 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
836 if (esdhc_read32(®s->vendorspec) & ESDHC_VENDORSPEC_VSELECT)
840 case MMC_SIGNAL_VOLTAGE_120:
847 static void esdhc_stop_tuning(struct mmc *mmc)
851 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
853 cmd.resp_type = MMC_RSP_R1b;
855 dm_mmc_send_cmd(mmc->dev, &cmd, NULL);
858 static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
860 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
861 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
862 struct fsl_esdhc *regs = priv->esdhc_regs;
863 struct mmc *mmc = &plat->mmc;
864 u32 irqstaten = readl(®s->irqstaten);
865 u32 irqsigen = readl(®s->irqsigen);
866 int i, ret = -ETIMEDOUT;
869 /* clock tuning is not needed for upto 52MHz */
870 if (mmc->clock <= 52000000)
873 /* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */
874 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
875 val = readl(®s->autoc12err);
876 mixctrl = readl(®s->mixctrl);
877 val &= ~MIX_CTRL_SMPCLK_SEL;
878 mixctrl &= ~(MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN);
880 val |= MIX_CTRL_EXE_TUNE;
881 mixctrl |= MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN;
883 writel(val, ®s->autoc12err);
884 writel(mixctrl, ®s->mixctrl);
887 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); */
888 mixctrl = readl(®s->mixctrl);
889 mixctrl = MIX_CTRL_DTDSEL_READ | (mixctrl & ~MIX_CTRL_SDHCI_MASK);
890 writel(mixctrl, ®s->mixctrl);
892 writel(IRQSTATEN_BRR, ®s->irqstaten);
893 writel(IRQSTATEN_BRR, ®s->irqsigen);
896 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
897 * of loops reaches 40 times.
899 for (i = 0; i < MAX_TUNING_LOOP; i++) {
902 if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) {
903 if (mmc->bus_width == 8)
904 writel(0x7080, ®s->blkattr);
905 else if (mmc->bus_width == 4)
906 writel(0x7040, ®s->blkattr);
908 writel(0x7040, ®s->blkattr);
911 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE) */
912 val = readl(®s->mixctrl);
913 val = MIX_CTRL_DTDSEL_READ | (val & ~MIX_CTRL_SDHCI_MASK);
914 writel(val, ®s->mixctrl);
916 /* We are using STD tuning, no need to check return value */
917 mmc_send_tuning(mmc, opcode, NULL);
919 ctrl = readl(®s->autoc12err);
920 if ((!(ctrl & MIX_CTRL_EXE_TUNE)) &&
921 (ctrl & MIX_CTRL_SMPCLK_SEL)) {
923 * need to wait some time, make sure sd/mmc fininsh
924 * send out tuning data, otherwise, the sd/mmc can't
925 * response to any command when the card still out
926 * put the tuning data.
933 /* Add 1ms delay for SD and eMMC */
937 writel(irqstaten, ®s->irqstaten);
938 writel(irqsigen, ®s->irqsigen);
940 esdhc_stop_tuning(mmc);
946 static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
948 struct fsl_esdhc *regs = priv->esdhc_regs;
949 int ret __maybe_unused;
951 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
952 /* Select to use peripheral clock */
953 esdhc_clock_control(priv, false);
954 esdhc_setbits32(®s->scr, ESDHCCTL_PCS);
955 esdhc_clock_control(priv, true);
957 /* Set the clock speed */
958 if (priv->clock != mmc->clock)
959 set_sysctl(priv, mmc, mmc->clock);
961 #ifdef MMC_SUPPORTS_TUNING
962 if (mmc->clk_disable) {
963 #ifdef CONFIG_FSL_USDHC
964 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
966 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
969 #ifdef CONFIG_FSL_USDHC
970 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
973 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
977 if (priv->mode != mmc->selected_mode) {
978 ret = esdhc_set_timing(mmc);
980 printf("esdhc_set_timing error %d\n", ret);
985 if (priv->signal_voltage != mmc->signal_voltage) {
986 ret = esdhc_set_voltage(mmc);
988 printf("esdhc_set_voltage error %d\n", ret);
994 /* Set the bus width */
995 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
997 if (mmc->bus_width == 4)
998 esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
999 else if (mmc->bus_width == 8)
1000 esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
1005 static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
1007 struct fsl_esdhc *regs = priv->esdhc_regs;
1010 /* Reset the entire host controller */
1011 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
1013 /* Wait until the controller is available */
1014 start = get_timer(0);
1015 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
1016 if (get_timer(start) > 1000)
1020 #if defined(CONFIG_FSL_USDHC)
1021 /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
1022 esdhc_write32(®s->mmcboot, 0x0);
1023 /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
1024 esdhc_write32(®s->mixctrl, 0x0);
1025 esdhc_write32(®s->clktunectrlstatus, 0x0);
1027 /* Put VEND_SPEC to default value */
1028 if (priv->vs18_enable)
1029 esdhc_write32(®s->vendorspec, (VENDORSPEC_INIT |
1030 ESDHC_VENDORSPEC_VSELECT));
1032 esdhc_write32(®s->vendorspec, VENDORSPEC_INIT);
1034 /* Disable DLL_CTRL delay line */
1035 esdhc_write32(®s->dllctrl, 0x0);
1039 /* Enable cache snooping */
1040 esdhc_write32(®s->scr, 0x00000040);
1043 #ifndef CONFIG_FSL_USDHC
1044 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
1046 esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
1049 /* Set the initial clock speed */
1050 mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
1052 /* Disable the BRR and BWR bits in IRQSTAT */
1053 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
1055 #ifdef CONFIG_MCF5441x
1056 esdhc_write32(®s->proctl, PROCTL_INIT | PROCTL_D3CD);
1058 /* Put the PROCTL reg back to the default */
1059 esdhc_write32(®s->proctl, PROCTL_INIT);
1062 /* Set timout to the maximum value */
1063 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
1068 static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
1070 struct fsl_esdhc *regs = priv->esdhc_regs;
1073 #ifdef CONFIG_ESDHC_DETECT_QUIRK
1074 if (CONFIG_ESDHC_DETECT_QUIRK)
1078 #if CONFIG_IS_ENABLED(DM_MMC)
1079 if (priv->non_removable)
1081 #ifdef CONFIG_DM_GPIO
1082 if (dm_gpio_is_valid(&priv->cd_gpio))
1083 return dm_gpio_get_value(&priv->cd_gpio);
1087 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
1093 static int esdhc_reset(struct fsl_esdhc *regs)
1097 /* reset the controller */
1098 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
1100 /* hardware clears the bit when it is done */
1101 start = get_timer(0);
1102 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
1103 if (get_timer(start) > 100) {
1104 printf("MMC/SD: Reset never completed.\n");
1112 #if !CONFIG_IS_ENABLED(DM_MMC)
1113 static int esdhc_getcd(struct mmc *mmc)
1115 struct fsl_esdhc_priv *priv = mmc->priv;
1117 return esdhc_getcd_common(priv);
1120 static int esdhc_init(struct mmc *mmc)
1122 struct fsl_esdhc_priv *priv = mmc->priv;
1124 return esdhc_init_common(priv, mmc);
1127 static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
1128 struct mmc_data *data)
1130 struct fsl_esdhc_priv *priv = mmc->priv;
1132 return esdhc_send_cmd_common(priv, mmc, cmd, data);
1135 static int esdhc_set_ios(struct mmc *mmc)
1137 struct fsl_esdhc_priv *priv = mmc->priv;
1139 return esdhc_set_ios_common(priv, mmc);
1142 static const struct mmc_ops esdhc_ops = {
1143 .getcd = esdhc_getcd,
1145 .send_cmd = esdhc_send_cmd,
1146 .set_ios = esdhc_set_ios,
1150 static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
1151 struct fsl_esdhc_plat *plat)
1153 struct mmc_config *cfg;
1154 struct fsl_esdhc *regs;
1155 u32 caps, voltage_caps;
1161 regs = priv->esdhc_regs;
1163 /* First reset the eSDHC controller */
1164 ret = esdhc_reset(regs);
1168 #ifdef CONFIG_MCF5441x
1169 /* ColdFire, using SDHC_DATA[3] for card detection */
1170 esdhc_write32(®s->proctl, PROCTL_INIT | PROCTL_D3CD);
1173 #ifndef CONFIG_FSL_USDHC
1174 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
1175 | SYSCTL_IPGEN | SYSCTL_CKEN);
1176 /* Clearing tuning bits in case ROM has set it already */
1177 esdhc_write32(®s->mixctrl, 0);
1178 esdhc_write32(®s->autoc12err, 0);
1179 esdhc_write32(®s->clktunectrlstatus, 0);
1181 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
1182 VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
1185 if (priv->vs18_enable)
1186 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
1188 writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
1190 #ifndef CONFIG_DM_MMC
1191 memset(cfg, '\0', sizeof(*cfg));
1195 caps = esdhc_read32(®s->hostcapblt);
1197 #ifdef CONFIG_MCF5441x
1199 * MCF5441x RM declares in more points that sdhc clock speed must
1200 * never exceed 25 Mhz. From this, the HS bit needs to be disabled
1201 * from host capabilities.
1203 caps &= ~ESDHC_HOSTCAPBLT_HSS;
1206 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
1207 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
1208 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
1211 /* T4240 host controller capabilities register should have VS33 bit */
1212 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
1213 caps = caps | ESDHC_HOSTCAPBLT_VS33;
1216 if (caps & ESDHC_HOSTCAPBLT_VS18)
1217 voltage_caps |= MMC_VDD_165_195;
1218 if (caps & ESDHC_HOSTCAPBLT_VS30)
1219 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
1220 if (caps & ESDHC_HOSTCAPBLT_VS33)
1221 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
1223 cfg->name = "FSL_SDHC";
1224 #if !CONFIG_IS_ENABLED(DM_MMC)
1225 cfg->ops = &esdhc_ops;
1227 #ifdef CONFIG_SYS_SD_VOLTAGE
1228 cfg->voltages = CONFIG_SYS_SD_VOLTAGE;
1230 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
1232 if ((cfg->voltages & voltage_caps) == 0) {
1233 printf("voltage not supported by controller\n");
1237 if (priv->bus_width == 8)
1238 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
1239 else if (priv->bus_width == 4)
1240 cfg->host_caps = MMC_MODE_4BIT;
1242 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
1243 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
1244 cfg->host_caps |= MMC_MODE_DDR_52MHz;
1247 if (priv->bus_width > 0) {
1248 if (priv->bus_width < 8)
1249 cfg->host_caps &= ~MMC_MODE_8BIT;
1250 if (priv->bus_width < 4)
1251 cfg->host_caps &= ~MMC_MODE_4BIT;
1254 if (caps & ESDHC_HOSTCAPBLT_HSS)
1255 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1257 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
1258 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
1259 cfg->host_caps &= ~MMC_MODE_8BIT;
1262 cfg->host_caps |= priv->caps;
1264 cfg->f_min = 400000;
1265 cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
1267 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1269 writel(0, ®s->dllctrl);
1270 if (priv->flags & ESDHC_FLAG_USDHC) {
1271 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
1272 u32 val = readl(®s->tuning_ctrl);
1274 val |= ESDHC_STD_TUNING_EN;
1275 val &= ~ESDHC_TUNING_START_TAP_MASK;
1276 val |= priv->tuning_start_tap;
1277 val &= ~ESDHC_TUNING_STEP_MASK;
1278 val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT;
1279 writel(val, ®s->tuning_ctrl);
1286 #if !CONFIG_IS_ENABLED(DM_MMC)
1287 static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
1288 struct fsl_esdhc_priv *priv)
1293 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
1294 priv->bus_width = cfg->max_bus_width;
1295 priv->sdhc_clk = cfg->sdhc_clk;
1296 priv->wp_enable = cfg->wp_enable;
1297 priv->vs18_enable = cfg->vs18_enable;
1302 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
1304 struct fsl_esdhc_plat *plat;
1305 struct fsl_esdhc_priv *priv;
1312 priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
1315 plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
1321 ret = fsl_esdhc_cfg_to_priv(cfg, priv);
1323 debug("%s xlate failure\n", __func__);
1329 ret = fsl_esdhc_init(priv, plat);
1331 debug("%s init failure\n", __func__);
1337 mmc = mmc_create(&plat->cfg, priv);
1346 int fsl_esdhc_mmc_init(bd_t *bis)
1348 struct fsl_esdhc_cfg *cfg;
1350 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
1351 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
1352 cfg->sdhc_clk = gd->arch.sdhc_clk;
1353 return fsl_esdhc_initialize(bis, cfg);
1357 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1358 void mmc_adapter_card_type_ident(void)
1363 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
1364 gd->arch.sdhc_adapter = card_id;
1367 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
1368 value = QIXIS_READ(brdcfg[5]);
1369 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
1370 QIXIS_WRITE(brdcfg[5], value);
1372 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
1373 value = QIXIS_READ(pwr_ctl[1]);
1374 value |= QIXIS_EVDD_BY_SDHC_VS;
1375 QIXIS_WRITE(pwr_ctl[1], value);
1377 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
1378 value = QIXIS_READ(brdcfg[5]);
1379 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
1380 QIXIS_WRITE(brdcfg[5], value);
1382 case QIXIS_ESDHC_ADAPTER_TYPE_RSV:
1384 case QIXIS_ESDHC_ADAPTER_TYPE_MMC:
1386 case QIXIS_ESDHC_ADAPTER_TYPE_SD:
1388 case QIXIS_ESDHC_NO_ADAPTER:
1396 #ifdef CONFIG_OF_LIBFDT
1397 __weak int esdhc_status_fixup(void *blob, const char *compat)
1399 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
1400 if (!hwconfig("esdhc")) {
1401 do_fixup_by_compat(blob, compat, "status", "disabled",
1402 sizeof("disabled"), 1);
1409 void fdt_fixup_esdhc(void *blob, bd_t *bd)
1411 const char *compat = "fsl,esdhc";
1413 if (esdhc_status_fixup(blob, compat))
1416 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
1417 do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
1418 gd->arch.sdhc_clk, 1);
1420 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
1421 gd->arch.sdhc_clk, 1);
1423 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1424 do_fixup_by_compat_u32(blob, compat, "adapter-type",
1425 (u32)(gd->arch.sdhc_adapter), 1);
1430 #if CONFIG_IS_ENABLED(DM_MMC)
1431 #include <asm/arch/clock.h>
1432 __weak void init_clk_usdhc(u32 index)
1436 static int fsl_esdhc_probe(struct udevice *dev)
1438 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1439 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1440 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1441 const void *fdt = gd->fdt_blob;
1442 int node = dev_of_offset(dev);
1443 struct esdhc_soc_data *data =
1444 (struct esdhc_soc_data *)dev_get_driver_data(dev);
1445 #ifdef CONFIG_DM_REGULATOR
1446 struct udevice *vqmmc_dev;
1453 addr = dev_read_addr(dev);
1454 if (addr == FDT_ADDR_T_NONE)
1457 priv->esdhc_regs = (struct fsl_esdhc *)addr;
1461 priv->flags = data->flags;
1462 priv->caps = data->caps;
1465 val = dev_read_u32_default(dev, "bus-width", -1);
1467 priv->bus_width = 8;
1469 priv->bus_width = 4;
1471 priv->bus_width = 1;
1473 val = fdtdec_get_int(fdt, node, "fsl,tuning-step", 1);
1474 priv->tuning_step = val;
1475 val = fdtdec_get_int(fdt, node, "fsl,tuning-start-tap",
1476 ESDHC_TUNING_START_TAP_DEFAULT);
1477 priv->tuning_start_tap = val;
1478 val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target",
1479 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT);
1480 priv->strobe_dll_delay_target = val;
1482 if (dev_read_bool(dev, "non-removable")) {
1483 priv->non_removable = 1;
1485 priv->non_removable = 0;
1486 #ifdef CONFIG_DM_GPIO
1487 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
1492 priv->wp_enable = 1;
1494 #ifdef CONFIG_DM_GPIO
1495 ret = gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
1498 priv->wp_enable = 0;
1501 priv->vs18_enable = 0;
1503 #ifdef CONFIG_DM_REGULATOR
1505 * If emmc I/O has a fixed voltage at 1.8V, this must be provided,
1506 * otherwise, emmc will work abnormally.
1508 ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
1510 dev_dbg(dev, "no vqmmc-supply\n");
1512 ret = regulator_set_enable(vqmmc_dev, true);
1514 dev_err(dev, "fail to enable vqmmc-supply\n");
1518 if (regulator_get_value(vqmmc_dev) == 1800000)
1519 priv->vs18_enable = 1;
1523 if (fdt_get_property(fdt, node, "no-1-8-v", NULL))
1524 priv->caps &= ~(UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_HS400);
1528 * Because lack of clk driver, if SDHC clk is not enabled,
1529 * need to enable it first before this driver is invoked.
1531 * we use MXC_ESDHC_CLK to get clk freq.
1532 * If one would like to make this function work,
1533 * the aliases should be provided in dts as this:
1541 * Then if your board only supports mmc2 and mmc3, but we can
1542 * correctly get the seq as 2 and 3, then let mxc_get_clock
1546 init_clk_usdhc(dev->seq);
1548 if (IS_ENABLED(CONFIG_CLK)) {
1549 /* Assigned clock already set clock */
1550 ret = clk_get_by_name(dev, "per", &priv->per_clk);
1552 printf("Failed to get per_clk\n");
1555 ret = clk_enable(&priv->per_clk);
1557 printf("Failed to enable per_clk\n");
1561 priv->sdhc_clk = clk_get_rate(&priv->per_clk);
1563 priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
1564 if (priv->sdhc_clk <= 0) {
1565 dev_err(dev, "Unable to get clk for %s\n", dev->name);
1570 ret = fsl_esdhc_init(priv, plat);
1572 dev_err(dev, "fsl_esdhc_init failure\n");
1577 mmc->cfg = &plat->cfg;
1581 return esdhc_init_common(priv, mmc);
1584 #if CONFIG_IS_ENABLED(DM_MMC)
1585 static int fsl_esdhc_get_cd(struct udevice *dev)
1587 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1589 return esdhc_getcd_common(priv);
1592 static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1593 struct mmc_data *data)
1595 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1596 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1598 return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
1601 static int fsl_esdhc_set_ios(struct udevice *dev)
1603 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1604 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1606 return esdhc_set_ios_common(priv, &plat->mmc);
1609 static const struct dm_mmc_ops fsl_esdhc_ops = {
1610 .get_cd = fsl_esdhc_get_cd,
1611 .send_cmd = fsl_esdhc_send_cmd,
1612 .set_ios = fsl_esdhc_set_ios,
1613 #ifdef MMC_SUPPORTS_TUNING
1614 .execute_tuning = fsl_esdhc_execute_tuning,
1619 static struct esdhc_soc_data usdhc_imx7d_data = {
1620 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
1621 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
1623 .caps = UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_DDR_52MHz |
1624 MMC_MODE_HS_52MHz | MMC_MODE_HS,
1627 static const struct udevice_id fsl_esdhc_ids[] = {
1628 { .compatible = "fsl,imx6ul-usdhc", },
1629 { .compatible = "fsl,imx6sx-usdhc", },
1630 { .compatible = "fsl,imx6sl-usdhc", },
1631 { .compatible = "fsl,imx6q-usdhc", },
1632 { .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,},
1633 { .compatible = "fsl,imx7ulp-usdhc", },
1634 { .compatible = "fsl,esdhc", },
1638 #if CONFIG_IS_ENABLED(BLK)
1639 static int fsl_esdhc_bind(struct udevice *dev)
1641 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1643 return mmc_bind(dev, &plat->mmc, &plat->cfg);
1647 U_BOOT_DRIVER(fsl_esdhc) = {
1648 .name = "fsl-esdhc-mmc",
1650 .of_match = fsl_esdhc_ids,
1651 .ops = &fsl_esdhc_ops,
1652 #if CONFIG_IS_ENABLED(BLK)
1653 .bind = fsl_esdhc_bind,
1655 .probe = fsl_esdhc_probe,
1656 .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
1657 .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),