1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
4 * Copyright 2019 NXP Semiconductors
7 * Based vaguely on the pxa mmc code:
9 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
21 #include <fsl_esdhc.h>
22 #include <fdt_support.h>
23 #include <asm/cache.h>
26 #include <dm/device_compat.h>
27 #include <linux/bitops.h>
28 #include <linux/delay.h>
30 DECLARE_GLOBAL_DATA_PTR;
33 uint dsaddr; /* SDMA system address register */
34 uint blkattr; /* Block attributes register */
35 uint cmdarg; /* Command argument register */
36 uint xfertyp; /* Transfer type register */
37 uint cmdrsp0; /* Command response 0 register */
38 uint cmdrsp1; /* Command response 1 register */
39 uint cmdrsp2; /* Command response 2 register */
40 uint cmdrsp3; /* Command response 3 register */
41 uint datport; /* Buffer data port register */
42 uint prsstat; /* Present state register */
43 uint proctl; /* Protocol control register */
44 uint sysctl; /* System Control Register */
45 uint irqstat; /* Interrupt status register */
46 uint irqstaten; /* Interrupt status enable register */
47 uint irqsigen; /* Interrupt signal enable register */
48 uint autoc12err; /* Auto CMD error status register */
49 uint hostcapblt; /* Host controller capabilities register */
50 uint wml; /* Watermark level register */
51 char reserved1[8]; /* reserved */
52 uint fevt; /* Force event register */
53 uint admaes; /* ADMA error status register */
54 uint adsaddr; /* ADMA system address register */
56 uint hostver; /* Host controller version register */
57 char reserved3[4]; /* reserved */
58 uint dmaerraddr; /* DMA error address register */
59 char reserved4[4]; /* reserved */
60 uint dmaerrattr; /* DMA error attribute register */
61 char reserved5[4]; /* reserved */
62 uint hostcapblt2; /* Host controller capabilities register 2 */
63 char reserved6[756]; /* reserved */
64 uint esdhcctl; /* eSDHC control register */
67 struct fsl_esdhc_plat {
68 struct mmc_config cfg;
73 * struct fsl_esdhc_priv
75 * @esdhc_regs: registers of the sdhc controller
76 * @sdhc_clk: Current clk of the sdhc controller
77 * @bus_width: bus width, 1bit, 4bit or 8bit
80 * Following is used when Driver Model is enabled for MMC
81 * @dev: pointer for the device
82 * @cd_gpio: gpio for card detection
83 * @wp_gpio: gpio for write protection
85 struct fsl_esdhc_priv {
86 struct fsl_esdhc *esdhc_regs;
87 unsigned int sdhc_clk;
90 #if !CONFIG_IS_ENABLED(DM_MMC)
96 /* Return the XFERTYP flags for a given command and data packet */
97 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
102 xfertyp |= XFERTYP_DPSEL;
103 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
104 xfertyp |= XFERTYP_DMAEN;
106 if (data->blocks > 1) {
107 xfertyp |= XFERTYP_MSBSEL;
108 xfertyp |= XFERTYP_BCEN;
109 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
110 xfertyp |= XFERTYP_AC12EN;
114 if (data->flags & MMC_DATA_READ)
115 xfertyp |= XFERTYP_DTDSEL;
118 if (cmd->resp_type & MMC_RSP_CRC)
119 xfertyp |= XFERTYP_CCCEN;
120 if (cmd->resp_type & MMC_RSP_OPCODE)
121 xfertyp |= XFERTYP_CICEN;
122 if (cmd->resp_type & MMC_RSP_136)
123 xfertyp |= XFERTYP_RSPTYP_136;
124 else if (cmd->resp_type & MMC_RSP_BUSY)
125 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
126 else if (cmd->resp_type & MMC_RSP_PRESENT)
127 xfertyp |= XFERTYP_RSPTYP_48;
129 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
130 xfertyp |= XFERTYP_CMDTYP_ABORT;
132 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
135 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
137 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
139 static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
140 struct mmc_data *data)
142 struct fsl_esdhc *regs = priv->esdhc_regs;
150 if (data->flags & MMC_DATA_READ) {
151 blocks = data->blocks;
154 start = get_timer(0);
155 size = data->blocksize;
156 irqstat = esdhc_read32(®s->irqstat);
157 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)) {
158 if (get_timer(start) > PIO_TIMEOUT) {
159 printf("\nData Read Failed in PIO Mode.");
163 while (size && (!(irqstat & IRQSTAT_TC))) {
164 udelay(100); /* Wait before last byte transfer complete */
165 irqstat = esdhc_read32(®s->irqstat);
166 databuf = in_le32(®s->datport);
167 *((uint *)buffer) = databuf;
174 blocks = data->blocks;
175 buffer = (char *)data->src;
177 start = get_timer(0);
178 size = data->blocksize;
179 irqstat = esdhc_read32(®s->irqstat);
180 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)) {
181 if (get_timer(start) > PIO_TIMEOUT) {
182 printf("\nData Write Failed in PIO Mode.");
186 while (size && (!(irqstat & IRQSTAT_TC))) {
187 udelay(100); /* Wait before last byte transfer complete */
188 databuf = *((uint *)buffer);
191 irqstat = esdhc_read32(®s->irqstat);
192 out_le32(®s->datport, databuf);
200 static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
201 struct mmc_data *data)
204 struct fsl_esdhc *regs = priv->esdhc_regs;
205 #if defined(CONFIG_FSL_LAYERSCAPE)
210 wml_value = data->blocksize/4;
212 if (data->flags & MMC_DATA_READ) {
213 if (wml_value > WML_RD_WML_MAX)
214 wml_value = WML_RD_WML_MAX_VAL;
216 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
217 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
218 #if defined(CONFIG_FSL_LAYERSCAPE)
219 addr = virt_to_phys((void *)(data->dest));
220 if (upper_32_bits(addr))
221 printf("Error found for upper 32 bits\n");
223 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
225 esdhc_write32(®s->dsaddr, (u32)data->dest);
229 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
230 flush_dcache_range((ulong)data->src,
231 (ulong)data->src+data->blocks
234 if (wml_value > WML_WR_WML_MAX)
235 wml_value = WML_WR_WML_MAX_VAL;
237 if (!(esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL)) {
238 printf("Can not write to locked SD card.\n");
242 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
244 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
245 #if defined(CONFIG_FSL_LAYERSCAPE)
246 addr = virt_to_phys((void *)(data->src));
247 if (upper_32_bits(addr))
248 printf("Error found for upper 32 bits\n");
250 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
252 esdhc_write32(®s->dsaddr, (u32)data->src);
257 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
259 /* Calculate the timeout period for data transactions */
261 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
262 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
263 * So, Number of SD Clock cycles for 0.25sec should be minimum
264 * (SD Clock/sec * 0.25 sec) SD Clock cycles
265 * = (mmc->clock * 1/4) SD Clock cycles
267 * => (2^(timeout+13)) >= mmc->clock * 1/4
268 * Taking log2 both the sides
269 * => timeout + 13 >= log2(mmc->clock/4)
270 * Rounding up to next power of 2
271 * => timeout + 13 = log2(mmc->clock/4) + 1
272 * => timeout + 13 = fls(mmc->clock/4)
274 * However, the MMC spec "It is strongly recommended for hosts to
275 * implement more than 500ms timeout value even if the card
276 * indicates the 250ms maximum busy length." Even the previous
277 * value of 300ms is known to be insufficient for some cards.
279 * => timeout + 13 = fls(mmc->clock/2)
281 timeout = fls(mmc->clock/2);
290 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
291 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
295 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
298 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
303 static void check_and_invalidate_dcache_range
304 (struct mmc_cmd *cmd,
305 struct mmc_data *data) {
308 unsigned size = roundup(ARCH_DMA_MINALIGN,
309 data->blocks*data->blocksize);
310 #if defined(CONFIG_FSL_LAYERSCAPE)
313 addr = virt_to_phys((void *)(data->dest));
314 if (upper_32_bits(addr))
315 printf("Error found for upper 32 bits\n");
317 start = lower_32_bits(addr);
319 start = (unsigned)data->dest;
322 invalidate_dcache_range(start, end);
326 * Sends a command out on the bus. Takes the mmc pointer,
327 * a command pointer, and an optional data pointer.
329 static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
330 struct mmc_cmd *cmd, struct mmc_data *data)
335 u32 flags = IRQSTAT_CC | IRQSTAT_CTOE;
336 struct fsl_esdhc *regs = priv->esdhc_regs;
339 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
340 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
344 esdhc_write32(®s->irqstat, -1);
348 /* Wait for the bus to be idle */
349 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
350 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
353 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
356 /* Wait at least 8 SD clock cycles before the next command */
358 * Note: This is way more than 8 cycles, but 1ms seems to
359 * resolve timing issues with some cards
363 /* Set up for a data transfer if we have one */
365 err = esdhc_setup_data(priv, mmc, data);
369 if (data->flags & MMC_DATA_READ)
370 check_and_invalidate_dcache_range(cmd, data);
373 /* Figure out the transfer arguments */
374 xfertyp = esdhc_xfertyp(cmd, data);
377 esdhc_write32(®s->irqsigen, 0);
379 /* Send the command */
380 esdhc_write32(®s->cmdarg, cmd->cmdarg);
381 esdhc_write32(®s->xfertyp, xfertyp);
383 /* Wait for the command to complete */
384 start = get_timer(0);
385 while (!(esdhc_read32(®s->irqstat) & flags)) {
386 if (get_timer(start) > 1000) {
392 irqstat = esdhc_read32(®s->irqstat);
394 if (irqstat & CMD_ERR) {
399 if (irqstat & IRQSTAT_CTOE) {
404 /* Workaround for ESDHC errata ENGcm03648 */
405 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
408 /* Poll on DATA0 line for cmd with busy signal for 600 ms */
409 while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
416 printf("Timeout waiting for DAT0 to go high!\n");
422 /* Copy the response to the response buffer */
423 if (cmd->resp_type & MMC_RSP_136) {
424 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
426 cmdrsp3 = esdhc_read32(®s->cmdrsp3);
427 cmdrsp2 = esdhc_read32(®s->cmdrsp2);
428 cmdrsp1 = esdhc_read32(®s->cmdrsp1);
429 cmdrsp0 = esdhc_read32(®s->cmdrsp0);
430 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
431 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
432 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
433 cmd->response[3] = (cmdrsp0 << 8);
435 cmd->response[0] = esdhc_read32(®s->cmdrsp0);
437 /* Wait until all of the blocks are transferred */
439 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
440 esdhc_pio_read_write(priv, data);
443 irqstat = esdhc_read32(®s->irqstat);
445 if (irqstat & IRQSTAT_DTOE) {
450 if (irqstat & DATA_ERR) {
454 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
457 * Need invalidate the dcache here again to avoid any
458 * cache-fill during the DMA operations such as the
459 * speculative pre-fetching etc.
461 if (data->flags & MMC_DATA_READ) {
462 check_and_invalidate_dcache_range(cmd, data);
468 /* Reset CMD and DATA portions on error */
470 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
472 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC)
476 esdhc_write32(®s->sysctl,
477 esdhc_read32(®s->sysctl) |
479 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
484 esdhc_write32(®s->irqstat, -1);
489 static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
491 struct fsl_esdhc *regs = priv->esdhc_regs;
494 unsigned int sdhc_clk = priv->sdhc_clk;
499 if (clock < mmc->cfg->f_min)
500 clock = mmc->cfg->f_min;
502 while (sdhc_clk / (16 * pre_div) > clock && pre_div < 256)
505 while (sdhc_clk / (div * pre_div) > clock && div < 16)
511 clk = (pre_div << 8) | (div << 4);
513 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
515 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
518 value = PRSSTAT_SDSTB;
519 while (!(esdhc_read32(®s->prsstat) & value)) {
521 printf("fsl_esdhc: Internal clock never stabilised.\n");
528 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
531 static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
533 struct fsl_esdhc *regs = priv->esdhc_regs;
537 value = esdhc_read32(®s->sysctl);
540 value |= SYSCTL_CKEN;
542 value &= ~SYSCTL_CKEN;
544 esdhc_write32(®s->sysctl, value);
547 value = PRSSTAT_SDSTB;
548 while (!(esdhc_read32(®s->prsstat) & value)) {
550 printf("fsl_esdhc: Internal clock never stabilised.\n");
558 static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
560 struct fsl_esdhc *regs = priv->esdhc_regs;
562 if (priv->is_sdhc_per_clk) {
563 /* Select to use peripheral clock */
564 esdhc_clock_control(priv, false);
565 esdhc_setbits32(®s->esdhcctl, ESDHCCTL_PCS);
566 esdhc_clock_control(priv, true);
569 /* Set the clock speed */
570 if (priv->clock != mmc->clock)
571 set_sysctl(priv, mmc, mmc->clock);
573 /* Set the bus width */
574 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
576 if (mmc->bus_width == 4)
577 esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
578 else if (mmc->bus_width == 8)
579 esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
584 static void esdhc_enable_cache_snooping(struct fsl_esdhc *regs)
586 #ifdef CONFIG_ARCH_MPC830X
587 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
588 sysconf83xx_t *sysconf = &immr->sysconf;
590 setbits_be32(&sysconf->sdhccr, 0x02000000);
592 esdhc_write32(®s->esdhcctl, 0x00000040);
596 static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
598 struct fsl_esdhc *regs = priv->esdhc_regs;
601 /* Reset the entire host controller */
602 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
604 /* Wait until the controller is available */
605 start = get_timer(0);
606 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
607 if (get_timer(start) > 1000)
611 esdhc_enable_cache_snooping(regs);
613 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
615 /* Set the initial clock speed */
616 mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
618 /* Disable the BRR and BWR bits in IRQSTAT */
619 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
621 /* Put the PROCTL reg back to the default */
622 esdhc_write32(®s->proctl, PROCTL_INIT);
624 /* Set timout to the maximum value */
625 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
630 static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
632 struct fsl_esdhc *regs = priv->esdhc_regs;
635 #ifdef CONFIG_ESDHC_DETECT_QUIRK
636 if (CONFIG_ESDHC_DETECT_QUIRK)
639 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
645 static void fsl_esdhc_get_cfg_common(struct fsl_esdhc_priv *priv,
646 struct mmc_config *cfg)
648 struct fsl_esdhc *regs = priv->esdhc_regs;
651 caps = esdhc_read32(®s->hostcapblt);
652 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
653 caps &= ~(HOSTCAPBLT_SRS | HOSTCAPBLT_VS18 | HOSTCAPBLT_VS30);
655 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
656 caps |= HOSTCAPBLT_VS33;
658 if (caps & HOSTCAPBLT_VS18)
659 cfg->voltages |= MMC_VDD_165_195;
660 if (caps & HOSTCAPBLT_VS30)
661 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
662 if (caps & HOSTCAPBLT_VS33)
663 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
665 cfg->name = "FSL_SDHC";
667 if (caps & HOSTCAPBLT_HSS)
668 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
671 cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
672 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
675 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
676 void mmc_adapter_card_type_ident(void)
681 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
682 gd->arch.sdhc_adapter = card_id;
685 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
686 value = QIXIS_READ(brdcfg[5]);
687 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
688 QIXIS_WRITE(brdcfg[5], value);
690 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
691 value = QIXIS_READ(pwr_ctl[1]);
692 value |= QIXIS_EVDD_BY_SDHC_VS;
693 QIXIS_WRITE(pwr_ctl[1], value);
695 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
696 value = QIXIS_READ(brdcfg[5]);
697 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
698 QIXIS_WRITE(brdcfg[5], value);
700 case QIXIS_ESDHC_ADAPTER_TYPE_RSV:
702 case QIXIS_ESDHC_ADAPTER_TYPE_MMC:
704 case QIXIS_ESDHC_ADAPTER_TYPE_SD:
706 case QIXIS_ESDHC_NO_ADAPTER:
714 #ifdef CONFIG_OF_LIBFDT
715 __weak int esdhc_status_fixup(void *blob, const char *compat)
717 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
718 if (!hwconfig("esdhc")) {
719 do_fixup_by_compat(blob, compat, "status", "disabled",
720 sizeof("disabled"), 1);
727 void fdt_fixup_esdhc(void *blob, bd_t *bd)
729 const char *compat = "fsl,esdhc";
731 if (esdhc_status_fixup(blob, compat))
734 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
735 gd->arch.sdhc_clk, 1);
739 #if !CONFIG_IS_ENABLED(DM_MMC)
740 static int esdhc_getcd(struct mmc *mmc)
742 struct fsl_esdhc_priv *priv = mmc->priv;
744 return esdhc_getcd_common(priv);
747 static int esdhc_init(struct mmc *mmc)
749 struct fsl_esdhc_priv *priv = mmc->priv;
751 return esdhc_init_common(priv, mmc);
754 static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
755 struct mmc_data *data)
757 struct fsl_esdhc_priv *priv = mmc->priv;
759 return esdhc_send_cmd_common(priv, mmc, cmd, data);
762 static int esdhc_set_ios(struct mmc *mmc)
764 struct fsl_esdhc_priv *priv = mmc->priv;
766 return esdhc_set_ios_common(priv, mmc);
769 static const struct mmc_ops esdhc_ops = {
770 .getcd = esdhc_getcd,
772 .send_cmd = esdhc_send_cmd,
773 .set_ios = esdhc_set_ios,
776 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
778 struct fsl_esdhc_plat *plat;
779 struct fsl_esdhc_priv *priv;
780 struct mmc_config *mmc_cfg;
786 priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
789 plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
795 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
796 priv->sdhc_clk = cfg->sdhc_clk;
797 if (gd->arch.sdhc_per_clk)
798 priv->is_sdhc_per_clk = true;
800 mmc_cfg = &plat->cfg;
802 if (cfg->max_bus_width == 8) {
803 mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT |
805 } else if (cfg->max_bus_width == 4) {
806 mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT;
807 } else if (cfg->max_bus_width == 1) {
808 mmc_cfg->host_caps |= MMC_MODE_1BIT;
810 mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT |
812 printf("No max bus width provided. Assume 8-bit supported.\n");
815 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
816 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
817 mmc_cfg->host_caps &= ~MMC_MODE_8BIT;
819 mmc_cfg->ops = &esdhc_ops;
821 fsl_esdhc_get_cfg_common(priv, mmc_cfg);
823 mmc = mmc_create(mmc_cfg, priv);
831 int fsl_esdhc_mmc_init(bd_t *bis)
833 struct fsl_esdhc_cfg *cfg;
835 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
836 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
837 /* Prefer peripheral clock which provides higher frequency. */
838 if (gd->arch.sdhc_per_clk)
839 cfg->sdhc_clk = gd->arch.sdhc_per_clk;
841 cfg->sdhc_clk = gd->arch.sdhc_clk;
842 return fsl_esdhc_initialize(bis, cfg);
845 static int fsl_esdhc_probe(struct udevice *dev)
847 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
848 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
849 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
853 addr = dev_read_addr(dev);
854 if (addr == FDT_ADDR_T_NONE)
857 priv->esdhc_regs = (struct fsl_esdhc *)lower_32_bits(addr);
859 priv->esdhc_regs = (struct fsl_esdhc *)addr;
863 if (gd->arch.sdhc_per_clk) {
864 priv->sdhc_clk = gd->arch.sdhc_per_clk;
865 priv->is_sdhc_per_clk = true;
867 priv->sdhc_clk = gd->arch.sdhc_clk;
870 if (priv->sdhc_clk <= 0) {
871 dev_err(dev, "Unable to get clk for %s\n", dev->name);
875 fsl_esdhc_get_cfg_common(priv, &plat->cfg);
877 mmc_of_parse(dev, &plat->cfg);
880 mmc->cfg = &plat->cfg;
885 return esdhc_init_common(priv, mmc);
888 static int fsl_esdhc_get_cd(struct udevice *dev)
890 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
891 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
893 if (plat->cfg.host_caps & MMC_CAP_NONREMOVABLE)
896 return esdhc_getcd_common(priv);
899 static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
900 struct mmc_data *data)
902 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
903 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
905 return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
908 static int fsl_esdhc_set_ios(struct udevice *dev)
910 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
911 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
913 return esdhc_set_ios_common(priv, &plat->mmc);
916 static const struct dm_mmc_ops fsl_esdhc_ops = {
917 .get_cd = fsl_esdhc_get_cd,
918 .send_cmd = fsl_esdhc_send_cmd,
919 .set_ios = fsl_esdhc_set_ios,
920 #ifdef MMC_SUPPORTS_TUNING
921 .execute_tuning = fsl_esdhc_execute_tuning,
925 static const struct udevice_id fsl_esdhc_ids[] = {
926 { .compatible = "fsl,esdhc", },
930 static int fsl_esdhc_bind(struct udevice *dev)
932 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
934 return mmc_bind(dev, &plat->mmc, &plat->cfg);
937 U_BOOT_DRIVER(fsl_esdhc) = {
938 .name = "fsl-esdhc-mmc",
940 .of_match = fsl_esdhc_ids,
941 .ops = &fsl_esdhc_ops,
942 .bind = fsl_esdhc_bind,
943 .probe = fsl_esdhc_probe,
944 .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
945 .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),