1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
6 * Based vaguely on the pxa mmc code:
8 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
19 #include <power/regulator.h>
21 #include <fsl_esdhc.h>
22 #include <fdt_support.h>
25 #include <asm-generic/gpio.h>
26 #include <dm/pinctrl.h>
28 DECLARE_GLOBAL_DATA_PTR;
30 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
32 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
33 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
34 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
36 #define MAX_TUNING_LOOP 40
39 uint dsaddr; /* SDMA system address register */
40 uint blkattr; /* Block attributes register */
41 uint cmdarg; /* Command argument register */
42 uint xfertyp; /* Transfer type register */
43 uint cmdrsp0; /* Command response 0 register */
44 uint cmdrsp1; /* Command response 1 register */
45 uint cmdrsp2; /* Command response 2 register */
46 uint cmdrsp3; /* Command response 3 register */
47 uint datport; /* Buffer data port register */
48 uint prsstat; /* Present state register */
49 uint proctl; /* Protocol control register */
50 uint sysctl; /* System Control Register */
51 uint irqstat; /* Interrupt status register */
52 uint irqstaten; /* Interrupt status enable register */
53 uint irqsigen; /* Interrupt signal enable register */
54 uint autoc12err; /* Auto CMD error status register */
55 uint hostcapblt; /* Host controller capabilities register */
56 uint wml; /* Watermark level register */
57 uint mixctrl; /* For USDHC */
58 char reserved1[4]; /* reserved */
59 uint fevt; /* Force event register */
60 uint admaes; /* ADMA error status register */
61 uint adsaddr; /* ADMA system address register */
65 uint clktunectrlstatus;
73 uint tuning_ctrl; /* on i.MX6/7/8 */
75 uint hostver; /* Host controller version register */
76 char reserved6[4]; /* reserved */
77 uint dmaerraddr; /* DMA error address register */
78 char reserved7[4]; /* reserved */
79 uint dmaerrattr; /* DMA error attribute register */
80 char reserved8[4]; /* reserved */
81 uint hostcapblt2; /* Host controller capabilities register 2 */
82 char reserved9[8]; /* reserved */
83 uint tcr; /* Tuning control register */
84 char reserved10[28]; /* reserved */
85 uint sddirctl; /* SD direction control register */
86 char reserved11[712];/* reserved */
87 uint scr; /* eSDHC control register */
90 struct fsl_esdhc_plat {
91 struct mmc_config cfg;
95 struct esdhc_soc_data {
101 * struct fsl_esdhc_priv
103 * @esdhc_regs: registers of the sdhc controller
104 * @sdhc_clk: Current clk of the sdhc controller
105 * @bus_width: bus width, 1bit, 4bit or 8bit
108 * Following is used when Driver Model is enabled for MMC
109 * @dev: pointer for the device
110 * @non_removable: 0: removable; 1: non-removable
111 * @wp_enable: 1: enable checking wp; 0: no check
112 * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
113 * @flags: ESDHC_FLAG_xx in include/fsl_esdhc.h
114 * @caps: controller capabilities
115 * @tuning_step: tuning step setting in tuning_ctrl register
116 * @start_tuning_tap: the start point for tuning in tuning_ctrl register
117 * @strobe_dll_delay_target: settings in strobe_dllctrl
118 * @signal_voltage: indicating the current voltage
119 * @cd_gpio: gpio for card detection
120 * @wp_gpio: gpio for write protection
122 struct fsl_esdhc_priv {
123 struct fsl_esdhc *esdhc_regs;
124 unsigned int sdhc_clk;
128 unsigned int bus_width;
129 #if !CONFIG_IS_ENABLED(BLK)
139 u32 tuning_start_tap;
140 u32 strobe_dll_delay_target;
142 #if IS_ENABLED(CONFIG_DM_REGULATOR)
143 struct udevice *vqmmc_dev;
144 struct udevice *vmmc_dev;
146 #ifdef CONFIG_DM_GPIO
147 struct gpio_desc cd_gpio;
148 struct gpio_desc wp_gpio;
152 /* Return the XFERTYP flags for a given command and data packet */
153 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
158 xfertyp |= XFERTYP_DPSEL;
159 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
160 xfertyp |= XFERTYP_DMAEN;
162 if (data->blocks > 1) {
163 xfertyp |= XFERTYP_MSBSEL;
164 xfertyp |= XFERTYP_BCEN;
165 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
166 xfertyp |= XFERTYP_AC12EN;
170 if (data->flags & MMC_DATA_READ)
171 xfertyp |= XFERTYP_DTDSEL;
174 if (cmd->resp_type & MMC_RSP_CRC)
175 xfertyp |= XFERTYP_CCCEN;
176 if (cmd->resp_type & MMC_RSP_OPCODE)
177 xfertyp |= XFERTYP_CICEN;
178 if (cmd->resp_type & MMC_RSP_136)
179 xfertyp |= XFERTYP_RSPTYP_136;
180 else if (cmd->resp_type & MMC_RSP_BUSY)
181 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
182 else if (cmd->resp_type & MMC_RSP_PRESENT)
183 xfertyp |= XFERTYP_RSPTYP_48;
185 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
186 xfertyp |= XFERTYP_CMDTYP_ABORT;
188 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
191 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
193 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
195 static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
196 struct mmc_data *data)
198 struct fsl_esdhc *regs = priv->esdhc_regs;
206 if (data->flags & MMC_DATA_READ) {
207 blocks = data->blocks;
210 start = get_timer(0);
211 size = data->blocksize;
212 irqstat = esdhc_read32(®s->irqstat);
213 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)) {
214 if (get_timer(start) > PIO_TIMEOUT) {
215 printf("\nData Read Failed in PIO Mode.");
219 while (size && (!(irqstat & IRQSTAT_TC))) {
220 udelay(100); /* Wait before last byte transfer complete */
221 irqstat = esdhc_read32(®s->irqstat);
222 databuf = in_le32(®s->datport);
223 *((uint *)buffer) = databuf;
230 blocks = data->blocks;
231 buffer = (char *)data->src;
233 start = get_timer(0);
234 size = data->blocksize;
235 irqstat = esdhc_read32(®s->irqstat);
236 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)) {
237 if (get_timer(start) > PIO_TIMEOUT) {
238 printf("\nData Write Failed in PIO Mode.");
242 while (size && (!(irqstat & IRQSTAT_TC))) {
243 udelay(100); /* Wait before last byte transfer complete */
244 databuf = *((uint *)buffer);
247 irqstat = esdhc_read32(®s->irqstat);
248 out_le32(®s->datport, databuf);
256 static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
257 struct mmc_data *data)
260 struct fsl_esdhc *regs = priv->esdhc_regs;
261 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
262 defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
267 wml_value = data->blocksize/4;
269 if (data->flags & MMC_DATA_READ) {
270 if (wml_value > WML_RD_WML_MAX)
271 wml_value = WML_RD_WML_MAX_VAL;
273 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
274 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
275 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
276 defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
277 addr = virt_to_phys((void *)(data->dest));
278 if (upper_32_bits(addr))
279 printf("Error found for upper 32 bits\n");
281 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
283 esdhc_write32(®s->dsaddr, (u32)data->dest);
287 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
288 flush_dcache_range((ulong)data->src,
289 (ulong)data->src+data->blocks
292 if (wml_value > WML_WR_WML_MAX)
293 wml_value = WML_WR_WML_MAX_VAL;
294 if (priv->wp_enable) {
295 if ((esdhc_read32(®s->prsstat) &
296 PRSSTAT_WPSPL) == 0) {
297 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
302 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
304 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
305 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
306 defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
307 addr = virt_to_phys((void *)(data->src));
308 if (upper_32_bits(addr))
309 printf("Error found for upper 32 bits\n");
311 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
313 esdhc_write32(®s->dsaddr, (u32)data->src);
318 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
320 /* Calculate the timeout period for data transactions */
322 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
323 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
324 * So, Number of SD Clock cycles for 0.25sec should be minimum
325 * (SD Clock/sec * 0.25 sec) SD Clock cycles
326 * = (mmc->clock * 1/4) SD Clock cycles
328 * => (2^(timeout+13)) >= mmc->clock * 1/4
329 * Taking log2 both the sides
330 * => timeout + 13 >= log2(mmc->clock/4)
331 * Rounding up to next power of 2
332 * => timeout + 13 = log2(mmc->clock/4) + 1
333 * => timeout + 13 = fls(mmc->clock/4)
335 * However, the MMC spec "It is strongly recommended for hosts to
336 * implement more than 500ms timeout value even if the card
337 * indicates the 250ms maximum busy length." Even the previous
338 * value of 300ms is known to be insufficient for some cards.
340 * => timeout + 13 = fls(mmc->clock/2)
342 timeout = fls(mmc->clock/2);
351 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
352 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
356 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
359 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
364 static void check_and_invalidate_dcache_range
365 (struct mmc_cmd *cmd,
366 struct mmc_data *data) {
369 unsigned size = roundup(ARCH_DMA_MINALIGN,
370 data->blocks*data->blocksize);
371 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
372 defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
375 addr = virt_to_phys((void *)(data->dest));
376 if (upper_32_bits(addr))
377 printf("Error found for upper 32 bits\n");
379 start = lower_32_bits(addr);
381 start = (unsigned)data->dest;
384 invalidate_dcache_range(start, end);
388 * Sends a command out on the bus. Takes the mmc pointer,
389 * a command pointer, and an optional data pointer.
391 static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
392 struct mmc_cmd *cmd, struct mmc_data *data)
397 u32 flags = IRQSTAT_CC | IRQSTAT_CTOE;
398 struct fsl_esdhc *regs = priv->esdhc_regs;
401 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
402 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
406 esdhc_write32(®s->irqstat, -1);
410 /* Wait for the bus to be idle */
411 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
412 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
415 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
418 /* Wait at least 8 SD clock cycles before the next command */
420 * Note: This is way more than 8 cycles, but 1ms seems to
421 * resolve timing issues with some cards
425 /* Set up for a data transfer if we have one */
427 err = esdhc_setup_data(priv, mmc, data);
431 if (data->flags & MMC_DATA_READ)
432 check_and_invalidate_dcache_range(cmd, data);
435 /* Figure out the transfer arguments */
436 xfertyp = esdhc_xfertyp(cmd, data);
439 esdhc_write32(®s->irqsigen, 0);
441 /* Send the command */
442 esdhc_write32(®s->cmdarg, cmd->cmdarg);
443 #if defined(CONFIG_FSL_USDHC)
444 esdhc_write32(®s->mixctrl,
445 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
446 | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
447 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000);
449 esdhc_write32(®s->xfertyp, xfertyp);
452 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
453 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))
456 /* Wait for the command to complete */
457 start = get_timer(0);
458 while (!(esdhc_read32(®s->irqstat) & flags)) {
459 if (get_timer(start) > 1000) {
465 irqstat = esdhc_read32(®s->irqstat);
467 if (irqstat & CMD_ERR) {
472 if (irqstat & IRQSTAT_CTOE) {
477 /* Switch voltage to 1.8V if CMD11 succeeded */
478 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
479 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
481 printf("Run CMD11 1.8V switch\n");
482 /* Sleep for 5 ms - max time for card to switch to 1.8V */
486 /* Workaround for ESDHC errata ENGcm03648 */
487 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
490 /* Poll on DATA0 line for cmd with busy signal for 600 ms */
491 while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
498 printf("Timeout waiting for DAT0 to go high!\n");
504 /* Copy the response to the response buffer */
505 if (cmd->resp_type & MMC_RSP_136) {
506 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
508 cmdrsp3 = esdhc_read32(®s->cmdrsp3);
509 cmdrsp2 = esdhc_read32(®s->cmdrsp2);
510 cmdrsp1 = esdhc_read32(®s->cmdrsp1);
511 cmdrsp0 = esdhc_read32(®s->cmdrsp0);
512 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
513 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
514 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
515 cmd->response[3] = (cmdrsp0 << 8);
517 cmd->response[0] = esdhc_read32(®s->cmdrsp0);
519 /* Wait until all of the blocks are transferred */
521 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
522 esdhc_pio_read_write(priv, data);
524 flags = DATA_COMPLETE;
525 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
526 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) {
531 irqstat = esdhc_read32(®s->irqstat);
533 if (irqstat & IRQSTAT_DTOE) {
538 if (irqstat & DATA_ERR) {
542 } while ((irqstat & flags) != flags);
545 * Need invalidate the dcache here again to avoid any
546 * cache-fill during the DMA operations such as the
547 * speculative pre-fetching etc.
549 if (data->flags & MMC_DATA_READ)
550 check_and_invalidate_dcache_range(cmd, data);
555 /* Reset CMD and DATA portions on error */
557 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
559 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC)
563 esdhc_write32(®s->sysctl,
564 esdhc_read32(®s->sysctl) |
566 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
570 /* If this was CMD11, then notify that power cycle is needed */
571 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
572 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
575 esdhc_write32(®s->irqstat, -1);
580 static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
582 struct fsl_esdhc *regs = priv->esdhc_regs;
586 /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
587 int pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1;
594 int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
595 int sdhc_clk = priv->sdhc_clk;
598 if (clock < mmc->cfg->f_min)
599 clock = mmc->cfg->f_min;
601 while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
604 while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
610 clk = (pre_div << 8) | (div << 4);
612 #ifdef CONFIG_FSL_USDHC
613 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
615 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
618 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
622 #ifdef CONFIG_FSL_USDHC
623 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
625 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
631 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
632 static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
634 struct fsl_esdhc *regs = priv->esdhc_regs;
638 value = esdhc_read32(®s->sysctl);
641 value |= SYSCTL_CKEN;
643 value &= ~SYSCTL_CKEN;
645 esdhc_write32(®s->sysctl, value);
648 value = PRSSTAT_SDSTB;
649 while (!(esdhc_read32(®s->prsstat) & value)) {
651 printf("fsl_esdhc: Internal clock never stabilised.\n");
660 #ifdef MMC_SUPPORTS_TUNING
661 static int esdhc_change_pinstate(struct udevice *dev)
663 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
666 switch (priv->mode) {
669 ret = pinctrl_select_state(dev, "state_100mhz");
674 ret = pinctrl_select_state(dev, "state_200mhz");
677 ret = pinctrl_select_state(dev, "default");
682 printf("%s %d error\n", __func__, priv->mode);
687 static void esdhc_reset_tuning(struct mmc *mmc)
689 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
690 struct fsl_esdhc *regs = priv->esdhc_regs;
692 if (priv->flags & ESDHC_FLAG_USDHC) {
693 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
694 esdhc_clrbits32(®s->autoc12err,
695 MIX_CTRL_SMPCLK_SEL |
701 static void esdhc_set_strobe_dll(struct mmc *mmc)
703 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
704 struct fsl_esdhc *regs = priv->esdhc_regs;
707 if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
708 writel(ESDHC_STROBE_DLL_CTRL_RESET, ®s->strobe_dllctrl);
711 * enable strobe dll ctrl and adjust the delay target
712 * for the uSDHC loopback read clock
714 val = ESDHC_STROBE_DLL_CTRL_ENABLE |
715 (priv->strobe_dll_delay_target <<
716 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
717 writel(val, ®s->strobe_dllctrl);
718 /* wait 1us to make sure strobe dll status register stable */
720 val = readl(®s->strobe_dllstat);
721 if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK))
722 pr_warn("HS400 strobe DLL status REF not lock!\n");
723 if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK))
724 pr_warn("HS400 strobe DLL status SLV not lock!\n");
728 static int esdhc_set_timing(struct mmc *mmc)
730 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
731 struct fsl_esdhc *regs = priv->esdhc_regs;
734 mixctrl = readl(®s->mixctrl);
735 mixctrl &= ~(MIX_CTRL_DDREN | MIX_CTRL_HS400_EN);
737 switch (mmc->selected_mode) {
740 esdhc_reset_tuning(mmc);
741 writel(mixctrl, ®s->mixctrl);
744 mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN;
745 writel(mixctrl, ®s->mixctrl);
746 esdhc_set_strobe_dll(mmc);
756 writel(mixctrl, ®s->mixctrl);
760 mixctrl |= MIX_CTRL_DDREN;
761 writel(mixctrl, ®s->mixctrl);
764 printf("Not supported %d\n", mmc->selected_mode);
768 priv->mode = mmc->selected_mode;
770 return esdhc_change_pinstate(mmc->dev);
773 static int esdhc_set_voltage(struct mmc *mmc)
775 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
776 struct fsl_esdhc *regs = priv->esdhc_regs;
779 priv->signal_voltage = mmc->signal_voltage;
780 switch (mmc->signal_voltage) {
781 case MMC_SIGNAL_VOLTAGE_330:
782 if (priv->vs18_enable)
784 #ifdef CONFIG_DM_REGULATOR
785 if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
786 ret = regulator_set_value(priv->vqmmc_dev, 3300000);
788 printf("Setting to 3.3V error");
796 esdhc_clrbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
797 if (!(esdhc_read32(®s->vendorspec) &
798 ESDHC_VENDORSPEC_VSELECT))
802 case MMC_SIGNAL_VOLTAGE_180:
803 #ifdef CONFIG_DM_REGULATOR
804 if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
805 ret = regulator_set_value(priv->vqmmc_dev, 1800000);
807 printf("Setting to 1.8V error");
812 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
813 if (esdhc_read32(®s->vendorspec) & ESDHC_VENDORSPEC_VSELECT)
817 case MMC_SIGNAL_VOLTAGE_120:
824 static void esdhc_stop_tuning(struct mmc *mmc)
828 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
830 cmd.resp_type = MMC_RSP_R1b;
832 dm_mmc_send_cmd(mmc->dev, &cmd, NULL);
835 static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
837 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
838 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
839 struct fsl_esdhc *regs = priv->esdhc_regs;
840 struct mmc *mmc = &plat->mmc;
841 u32 irqstaten = readl(®s->irqstaten);
842 u32 irqsigen = readl(®s->irqsigen);
843 int i, ret = -ETIMEDOUT;
846 /* clock tuning is not needed for upto 52MHz */
847 if (mmc->clock <= 52000000)
850 /* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */
851 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
852 val = readl(®s->autoc12err);
853 mixctrl = readl(®s->mixctrl);
854 val &= ~MIX_CTRL_SMPCLK_SEL;
855 mixctrl &= ~(MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN);
857 val |= MIX_CTRL_EXE_TUNE;
858 mixctrl |= MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN;
860 writel(val, ®s->autoc12err);
861 writel(mixctrl, ®s->mixctrl);
864 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); */
865 mixctrl = readl(®s->mixctrl);
866 mixctrl = MIX_CTRL_DTDSEL_READ | (mixctrl & ~MIX_CTRL_SDHCI_MASK);
867 writel(mixctrl, ®s->mixctrl);
869 writel(IRQSTATEN_BRR, ®s->irqstaten);
870 writel(IRQSTATEN_BRR, ®s->irqsigen);
873 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
874 * of loops reaches 40 times.
876 for (i = 0; i < MAX_TUNING_LOOP; i++) {
879 if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) {
880 if (mmc->bus_width == 8)
881 writel(0x7080, ®s->blkattr);
882 else if (mmc->bus_width == 4)
883 writel(0x7040, ®s->blkattr);
885 writel(0x7040, ®s->blkattr);
888 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE) */
889 val = readl(®s->mixctrl);
890 val = MIX_CTRL_DTDSEL_READ | (val & ~MIX_CTRL_SDHCI_MASK);
891 writel(val, ®s->mixctrl);
893 /* We are using STD tuning, no need to check return value */
894 mmc_send_tuning(mmc, opcode, NULL);
896 ctrl = readl(®s->autoc12err);
897 if ((!(ctrl & MIX_CTRL_EXE_TUNE)) &&
898 (ctrl & MIX_CTRL_SMPCLK_SEL)) {
900 * need to wait some time, make sure sd/mmc fininsh
901 * send out tuning data, otherwise, the sd/mmc can't
902 * response to any command when the card still out
903 * put the tuning data.
910 /* Add 1ms delay for SD and eMMC */
914 writel(irqstaten, ®s->irqstaten);
915 writel(irqsigen, ®s->irqsigen);
917 esdhc_stop_tuning(mmc);
923 static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
925 struct fsl_esdhc *regs = priv->esdhc_regs;
926 int ret __maybe_unused;
928 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
929 /* Select to use peripheral clock */
930 esdhc_clock_control(priv, false);
931 esdhc_setbits32(®s->scr, ESDHCCTL_PCS);
932 esdhc_clock_control(priv, true);
934 /* Set the clock speed */
935 if (priv->clock != mmc->clock)
936 set_sysctl(priv, mmc, mmc->clock);
938 #ifdef MMC_SUPPORTS_TUNING
939 if (mmc->clk_disable) {
940 #ifdef CONFIG_FSL_USDHC
941 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
943 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
946 #ifdef CONFIG_FSL_USDHC
947 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
950 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
954 if (priv->mode != mmc->selected_mode) {
955 ret = esdhc_set_timing(mmc);
957 printf("esdhc_set_timing error %d\n", ret);
962 if (priv->signal_voltage != mmc->signal_voltage) {
963 ret = esdhc_set_voltage(mmc);
965 printf("esdhc_set_voltage error %d\n", ret);
971 /* Set the bus width */
972 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
974 if (mmc->bus_width == 4)
975 esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
976 else if (mmc->bus_width == 8)
977 esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
982 static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
984 struct fsl_esdhc *regs = priv->esdhc_regs;
987 /* Reset the entire host controller */
988 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
990 /* Wait until the controller is available */
991 start = get_timer(0);
992 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
993 if (get_timer(start) > 1000)
997 #if defined(CONFIG_FSL_USDHC)
998 /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
999 esdhc_write32(®s->mmcboot, 0x0);
1000 /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
1001 esdhc_write32(®s->mixctrl, 0x0);
1002 esdhc_write32(®s->clktunectrlstatus, 0x0);
1004 /* Put VEND_SPEC to default value */
1005 if (priv->vs18_enable)
1006 esdhc_write32(®s->vendorspec, (VENDORSPEC_INIT |
1007 ESDHC_VENDORSPEC_VSELECT));
1009 esdhc_write32(®s->vendorspec, VENDORSPEC_INIT);
1011 /* Disable DLL_CTRL delay line */
1012 esdhc_write32(®s->dllctrl, 0x0);
1016 /* Enable cache snooping */
1017 esdhc_write32(®s->scr, 0x00000040);
1020 #ifndef CONFIG_FSL_USDHC
1021 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
1023 esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
1026 /* Set the initial clock speed */
1027 mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
1029 /* Disable the BRR and BWR bits in IRQSTAT */
1030 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
1032 /* Put the PROCTL reg back to the default */
1033 esdhc_write32(®s->proctl, PROCTL_INIT);
1035 /* Set timout to the maximum value */
1036 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
1041 static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
1043 struct fsl_esdhc *regs = priv->esdhc_regs;
1046 #ifdef CONFIG_ESDHC_DETECT_QUIRK
1047 if (CONFIG_ESDHC_DETECT_QUIRK)
1051 #if CONFIG_IS_ENABLED(DM_MMC)
1052 if (priv->non_removable)
1054 #ifdef CONFIG_DM_GPIO
1055 if (dm_gpio_is_valid(&priv->cd_gpio))
1056 return dm_gpio_get_value(&priv->cd_gpio);
1060 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
1066 static int esdhc_reset(struct fsl_esdhc *regs)
1070 /* reset the controller */
1071 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
1073 /* hardware clears the bit when it is done */
1074 start = get_timer(0);
1075 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
1076 if (get_timer(start) > 100) {
1077 printf("MMC/SD: Reset never completed.\n");
1085 #if !CONFIG_IS_ENABLED(DM_MMC)
1086 static int esdhc_getcd(struct mmc *mmc)
1088 struct fsl_esdhc_priv *priv = mmc->priv;
1090 return esdhc_getcd_common(priv);
1093 static int esdhc_init(struct mmc *mmc)
1095 struct fsl_esdhc_priv *priv = mmc->priv;
1097 return esdhc_init_common(priv, mmc);
1100 static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
1101 struct mmc_data *data)
1103 struct fsl_esdhc_priv *priv = mmc->priv;
1105 return esdhc_send_cmd_common(priv, mmc, cmd, data);
1108 static int esdhc_set_ios(struct mmc *mmc)
1110 struct fsl_esdhc_priv *priv = mmc->priv;
1112 return esdhc_set_ios_common(priv, mmc);
1115 static const struct mmc_ops esdhc_ops = {
1116 .getcd = esdhc_getcd,
1118 .send_cmd = esdhc_send_cmd,
1119 .set_ios = esdhc_set_ios,
1123 static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
1124 struct fsl_esdhc_plat *plat)
1126 struct mmc_config *cfg;
1127 struct fsl_esdhc *regs;
1128 u32 caps, voltage_caps;
1134 regs = priv->esdhc_regs;
1136 /* First reset the eSDHC controller */
1137 ret = esdhc_reset(regs);
1141 #ifndef CONFIG_FSL_USDHC
1142 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
1143 | SYSCTL_IPGEN | SYSCTL_CKEN);
1144 /* Clearing tuning bits in case ROM has set it already */
1145 esdhc_write32(®s->mixctrl, 0);
1146 esdhc_write32(®s->autoc12err, 0);
1147 esdhc_write32(®s->clktunectrlstatus, 0);
1149 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
1150 VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
1153 if (priv->vs18_enable)
1154 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
1156 writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
1158 #ifndef CONFIG_DM_MMC
1159 memset(cfg, '\0', sizeof(*cfg));
1163 caps = esdhc_read32(®s->hostcapblt);
1165 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
1166 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
1167 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
1170 /* T4240 host controller capabilities register should have VS33 bit */
1171 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
1172 caps = caps | ESDHC_HOSTCAPBLT_VS33;
1175 if (caps & ESDHC_HOSTCAPBLT_VS18)
1176 voltage_caps |= MMC_VDD_165_195;
1177 if (caps & ESDHC_HOSTCAPBLT_VS30)
1178 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
1179 if (caps & ESDHC_HOSTCAPBLT_VS33)
1180 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
1182 cfg->name = "FSL_SDHC";
1183 #if !CONFIG_IS_ENABLED(DM_MMC)
1184 cfg->ops = &esdhc_ops;
1186 #ifdef CONFIG_SYS_SD_VOLTAGE
1187 cfg->voltages = CONFIG_SYS_SD_VOLTAGE;
1189 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
1191 if ((cfg->voltages & voltage_caps) == 0) {
1192 printf("voltage not supported by controller\n");
1196 if (priv->bus_width == 8)
1197 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
1198 else if (priv->bus_width == 4)
1199 cfg->host_caps = MMC_MODE_4BIT;
1201 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
1202 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
1203 cfg->host_caps |= MMC_MODE_DDR_52MHz;
1206 if (priv->bus_width > 0) {
1207 if (priv->bus_width < 8)
1208 cfg->host_caps &= ~MMC_MODE_8BIT;
1209 if (priv->bus_width < 4)
1210 cfg->host_caps &= ~MMC_MODE_4BIT;
1213 if (caps & ESDHC_HOSTCAPBLT_HSS)
1214 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1216 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
1217 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
1218 cfg->host_caps &= ~MMC_MODE_8BIT;
1221 cfg->host_caps |= priv->caps;
1223 cfg->f_min = 400000;
1224 cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
1226 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1228 writel(0, ®s->dllctrl);
1229 if (priv->flags & ESDHC_FLAG_USDHC) {
1230 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
1231 u32 val = readl(®s->tuning_ctrl);
1233 val |= ESDHC_STD_TUNING_EN;
1234 val &= ~ESDHC_TUNING_START_TAP_MASK;
1235 val |= priv->tuning_start_tap;
1236 val &= ~ESDHC_TUNING_STEP_MASK;
1237 val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT;
1238 writel(val, ®s->tuning_ctrl);
1245 #if !CONFIG_IS_ENABLED(DM_MMC)
1246 static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
1247 struct fsl_esdhc_priv *priv)
1252 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
1253 priv->bus_width = cfg->max_bus_width;
1254 priv->sdhc_clk = cfg->sdhc_clk;
1255 priv->wp_enable = cfg->wp_enable;
1256 priv->vs18_enable = cfg->vs18_enable;
1261 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
1263 struct fsl_esdhc_plat *plat;
1264 struct fsl_esdhc_priv *priv;
1271 priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
1274 plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
1280 ret = fsl_esdhc_cfg_to_priv(cfg, priv);
1282 debug("%s xlate failure\n", __func__);
1288 ret = fsl_esdhc_init(priv, plat);
1290 debug("%s init failure\n", __func__);
1296 mmc = mmc_create(&plat->cfg, priv);
1305 int fsl_esdhc_mmc_init(bd_t *bis)
1307 struct fsl_esdhc_cfg *cfg;
1309 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
1310 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
1311 cfg->sdhc_clk = gd->arch.sdhc_clk;
1312 return fsl_esdhc_initialize(bis, cfg);
1316 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1317 void mmc_adapter_card_type_ident(void)
1322 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
1323 gd->arch.sdhc_adapter = card_id;
1326 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
1327 value = QIXIS_READ(brdcfg[5]);
1328 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
1329 QIXIS_WRITE(brdcfg[5], value);
1331 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
1332 value = QIXIS_READ(pwr_ctl[1]);
1333 value |= QIXIS_EVDD_BY_SDHC_VS;
1334 QIXIS_WRITE(pwr_ctl[1], value);
1336 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
1337 value = QIXIS_READ(brdcfg[5]);
1338 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
1339 QIXIS_WRITE(brdcfg[5], value);
1341 case QIXIS_ESDHC_ADAPTER_TYPE_RSV:
1343 case QIXIS_ESDHC_ADAPTER_TYPE_MMC:
1345 case QIXIS_ESDHC_ADAPTER_TYPE_SD:
1347 case QIXIS_ESDHC_NO_ADAPTER:
1355 #ifdef CONFIG_OF_LIBFDT
1356 __weak int esdhc_status_fixup(void *blob, const char *compat)
1358 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
1359 if (!hwconfig("esdhc")) {
1360 do_fixup_by_compat(blob, compat, "status", "disabled",
1361 sizeof("disabled"), 1);
1368 void fdt_fixup_esdhc(void *blob, bd_t *bd)
1370 const char *compat = "fsl,esdhc";
1372 if (esdhc_status_fixup(blob, compat))
1375 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
1376 do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
1377 gd->arch.sdhc_clk, 1);
1379 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
1380 gd->arch.sdhc_clk, 1);
1382 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1383 do_fixup_by_compat_u32(blob, compat, "adapter-type",
1384 (u32)(gd->arch.sdhc_adapter), 1);
1389 #if CONFIG_IS_ENABLED(DM_MMC)
1390 #include <asm/arch/clock.h>
1391 __weak void init_clk_usdhc(u32 index)
1395 static int fsl_esdhc_probe(struct udevice *dev)
1397 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1398 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1399 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1400 const void *fdt = gd->fdt_blob;
1401 int node = dev_of_offset(dev);
1402 struct esdhc_soc_data *data =
1403 (struct esdhc_soc_data *)dev_get_driver_data(dev);
1404 #ifdef CONFIG_DM_REGULATOR
1405 struct udevice *vqmmc_dev;
1412 addr = dev_read_addr(dev);
1413 if (addr == FDT_ADDR_T_NONE)
1416 priv->esdhc_regs = (struct fsl_esdhc *)addr;
1420 priv->flags = data->flags;
1421 priv->caps = data->caps;
1424 val = dev_read_u32_default(dev, "bus-width", -1);
1426 priv->bus_width = 8;
1428 priv->bus_width = 4;
1430 priv->bus_width = 1;
1432 val = fdtdec_get_int(fdt, node, "fsl,tuning-step", 1);
1433 priv->tuning_step = val;
1434 val = fdtdec_get_int(fdt, node, "fsl,tuning-start-tap",
1435 ESDHC_TUNING_START_TAP_DEFAULT);
1436 priv->tuning_start_tap = val;
1437 val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target",
1438 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT);
1439 priv->strobe_dll_delay_target = val;
1441 if (dev_read_bool(dev, "non-removable")) {
1442 priv->non_removable = 1;
1444 priv->non_removable = 0;
1445 #ifdef CONFIG_DM_GPIO
1446 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
1451 priv->wp_enable = 1;
1453 #ifdef CONFIG_DM_GPIO
1454 ret = gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
1457 priv->wp_enable = 0;
1460 priv->vs18_enable = 0;
1462 #ifdef CONFIG_DM_REGULATOR
1464 * If emmc I/O has a fixed voltage at 1.8V, this must be provided,
1465 * otherwise, emmc will work abnormally.
1467 ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
1469 dev_dbg(dev, "no vqmmc-supply\n");
1471 ret = regulator_set_enable(vqmmc_dev, true);
1473 dev_err(dev, "fail to enable vqmmc-supply\n");
1477 if (regulator_get_value(vqmmc_dev) == 1800000)
1478 priv->vs18_enable = 1;
1482 if (fdt_get_property(fdt, node, "no-1-8-v", NULL))
1483 priv->caps &= ~(UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_HS400);
1487 * Because lack of clk driver, if SDHC clk is not enabled,
1488 * need to enable it first before this driver is invoked.
1490 * we use MXC_ESDHC_CLK to get clk freq.
1491 * If one would like to make this function work,
1492 * the aliases should be provided in dts as this:
1500 * Then if your board only supports mmc2 and mmc3, but we can
1501 * correctly get the seq as 2 and 3, then let mxc_get_clock
1505 init_clk_usdhc(dev->seq);
1507 if (IS_ENABLED(CONFIG_CLK)) {
1508 /* Assigned clock already set clock */
1509 ret = clk_get_by_name(dev, "per", &priv->per_clk);
1511 printf("Failed to get per_clk\n");
1514 ret = clk_enable(&priv->per_clk);
1516 printf("Failed to enable per_clk\n");
1520 priv->sdhc_clk = clk_get_rate(&priv->per_clk);
1522 priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
1523 if (priv->sdhc_clk <= 0) {
1524 dev_err(dev, "Unable to get clk for %s\n", dev->name);
1529 ret = fsl_esdhc_init(priv, plat);
1531 dev_err(dev, "fsl_esdhc_init failure\n");
1536 mmc->cfg = &plat->cfg;
1540 return esdhc_init_common(priv, mmc);
1543 #if CONFIG_IS_ENABLED(DM_MMC)
1544 static int fsl_esdhc_get_cd(struct udevice *dev)
1546 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1549 return esdhc_getcd_common(priv);
1552 static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1553 struct mmc_data *data)
1555 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1556 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1558 return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
1561 static int fsl_esdhc_set_ios(struct udevice *dev)
1563 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1564 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1566 return esdhc_set_ios_common(priv, &plat->mmc);
1569 static const struct dm_mmc_ops fsl_esdhc_ops = {
1570 .get_cd = fsl_esdhc_get_cd,
1571 .send_cmd = fsl_esdhc_send_cmd,
1572 .set_ios = fsl_esdhc_set_ios,
1573 #ifdef MMC_SUPPORTS_TUNING
1574 .execute_tuning = fsl_esdhc_execute_tuning,
1579 static struct esdhc_soc_data usdhc_imx7d_data = {
1580 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
1581 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
1583 .caps = UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_DDR_52MHz |
1584 MMC_MODE_HS_52MHz | MMC_MODE_HS,
1587 static const struct udevice_id fsl_esdhc_ids[] = {
1588 { .compatible = "fsl,imx6ul-usdhc", },
1589 { .compatible = "fsl,imx6sx-usdhc", },
1590 { .compatible = "fsl,imx6sl-usdhc", },
1591 { .compatible = "fsl,imx6q-usdhc", },
1592 { .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,},
1593 { .compatible = "fsl,imx7ulp-usdhc", },
1594 { .compatible = "fsl,esdhc", },
1598 #if CONFIG_IS_ENABLED(BLK)
1599 static int fsl_esdhc_bind(struct udevice *dev)
1601 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1603 return mmc_bind(dev, &plat->mmc, &plat->cfg);
1607 U_BOOT_DRIVER(fsl_esdhc) = {
1608 .name = "fsl-esdhc-mmc",
1610 .of_match = fsl_esdhc_ids,
1611 .ops = &fsl_esdhc_ops,
1612 #if CONFIG_IS_ENABLED(BLK)
1613 .bind = fsl_esdhc_bind,
1615 .probe = fsl_esdhc_probe,
1616 .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
1617 .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),