2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
5 * Based vaguely on the pxa mmc code:
7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
9 * SPDX-License-Identifier: GPL-2.0+
20 #include <fsl_esdhc.h>
21 #include <fdt_support.h>
24 DECLARE_GLOBAL_DATA_PTR;
26 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
28 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
29 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
30 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
34 uint dsaddr; /* SDMA system address register */
35 uint blkattr; /* Block attributes register */
36 uint cmdarg; /* Command argument register */
37 uint xfertyp; /* Transfer type register */
38 uint cmdrsp0; /* Command response 0 register */
39 uint cmdrsp1; /* Command response 1 register */
40 uint cmdrsp2; /* Command response 2 register */
41 uint cmdrsp3; /* Command response 3 register */
42 uint datport; /* Buffer data port register */
43 uint prsstat; /* Present state register */
44 uint proctl; /* Protocol control register */
45 uint sysctl; /* System Control Register */
46 uint irqstat; /* Interrupt status register */
47 uint irqstaten; /* Interrupt status enable register */
48 uint irqsigen; /* Interrupt signal enable register */
49 uint autoc12err; /* Auto CMD error status register */
50 uint hostcapblt; /* Host controller capabilities register */
51 uint wml; /* Watermark level register */
52 uint mixctrl; /* For USDHC */
53 char reserved1[4]; /* reserved */
54 uint fevt; /* Force event register */
55 uint admaes; /* ADMA error status register */
56 uint adsaddr; /* ADMA system address register */
57 char reserved2[100]; /* reserved */
58 uint vendorspec; /* Vendor Specific register */
59 char reserved3[59]; /* reserved */
60 uint hostver; /* Host controller version register */
61 char reserved4[4]; /* reserved */
62 uint dmaerraddr; /* DMA error address register */
63 char reserved5[4]; /* reserved */
64 uint dmaerrattr; /* DMA error attribute register */
65 char reserved6[4]; /* reserved */
66 uint hostcapblt2; /* Host controller capabilities register 2 */
67 char reserved7[8]; /* reserved */
68 uint tcr; /* Tuning control register */
69 char reserved8[28]; /* reserved */
70 uint sddirctl; /* SD direction control register */
71 char reserved9[712]; /* reserved */
72 uint scr; /* eSDHC control register */
75 /* Return the XFERTYP flags for a given command and data packet */
76 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
81 xfertyp |= XFERTYP_DPSEL;
82 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
83 xfertyp |= XFERTYP_DMAEN;
85 if (data->blocks > 1) {
86 xfertyp |= XFERTYP_MSBSEL;
87 xfertyp |= XFERTYP_BCEN;
88 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
89 xfertyp |= XFERTYP_AC12EN;
93 if (data->flags & MMC_DATA_READ)
94 xfertyp |= XFERTYP_DTDSEL;
97 if (cmd->resp_type & MMC_RSP_CRC)
98 xfertyp |= XFERTYP_CCCEN;
99 if (cmd->resp_type & MMC_RSP_OPCODE)
100 xfertyp |= XFERTYP_CICEN;
101 if (cmd->resp_type & MMC_RSP_136)
102 xfertyp |= XFERTYP_RSPTYP_136;
103 else if (cmd->resp_type & MMC_RSP_BUSY)
104 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
105 else if (cmd->resp_type & MMC_RSP_PRESENT)
106 xfertyp |= XFERTYP_RSPTYP_48;
108 #if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || defined(CONFIG_LS102XA)
109 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
110 xfertyp |= XFERTYP_CMDTYP_ABORT;
112 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
115 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
117 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
120 esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
122 struct fsl_esdhc_cfg *cfg = mmc->priv;
123 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
131 if (data->flags & MMC_DATA_READ) {
132 blocks = data->blocks;
135 timeout = PIO_TIMEOUT;
136 size = data->blocksize;
137 irqstat = esdhc_read32(®s->irqstat);
138 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)
141 printf("\nData Read Failed in PIO Mode.");
144 while (size && (!(irqstat & IRQSTAT_TC))) {
145 udelay(100); /* Wait before last byte transfer complete */
146 irqstat = esdhc_read32(®s->irqstat);
147 databuf = in_le32(®s->datport);
148 *((uint *)buffer) = databuf;
155 blocks = data->blocks;
156 buffer = (char *)data->src;
158 timeout = PIO_TIMEOUT;
159 size = data->blocksize;
160 irqstat = esdhc_read32(®s->irqstat);
161 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)
164 printf("\nData Write Failed in PIO Mode.");
167 while (size && (!(irqstat & IRQSTAT_TC))) {
168 udelay(100); /* Wait before last byte transfer complete */
169 databuf = *((uint *)buffer);
172 irqstat = esdhc_read32(®s->irqstat);
173 out_le32(®s->datport, databuf);
181 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
184 struct fsl_esdhc_cfg *cfg = mmc->priv;
185 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
189 wml_value = data->blocksize/4;
191 if (data->flags & MMC_DATA_READ) {
192 if (wml_value > WML_RD_WML_MAX)
193 wml_value = WML_RD_WML_MAX_VAL;
195 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
196 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
197 esdhc_write32(®s->dsaddr, (u32)data->dest);
200 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
201 flush_dcache_range((ulong)data->src,
202 (ulong)data->src+data->blocks
205 if (wml_value > WML_WR_WML_MAX)
206 wml_value = WML_WR_WML_MAX_VAL;
207 if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) {
208 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
212 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
214 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
215 esdhc_write32(®s->dsaddr, (u32)data->src);
219 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
221 /* Calculate the timeout period for data transactions */
223 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
224 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
225 * So, Number of SD Clock cycles for 0.25sec should be minimum
226 * (SD Clock/sec * 0.25 sec) SD Clock cycles
227 * = (mmc->clock * 1/4) SD Clock cycles
229 * => (2^(timeout+13)) >= mmc->clock * 1/4
230 * Taking log2 both the sides
231 * => timeout + 13 >= log2(mmc->clock/4)
232 * Rounding up to next power of 2
233 * => timeout + 13 = log2(mmc->clock/4) + 1
234 * => timeout + 13 = fls(mmc->clock/4)
236 timeout = fls(mmc->clock/4);
245 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
246 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
250 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
253 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
258 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
259 static void check_and_invalidate_dcache_range
260 (struct mmc_cmd *cmd,
261 struct mmc_data *data) {
262 unsigned start = (unsigned)data->dest ;
263 unsigned size = roundup(ARCH_DMA_MINALIGN,
264 data->blocks*data->blocksize);
265 unsigned end = start+size ;
266 invalidate_dcache_range(start, end);
271 * Sends a command out on the bus. Takes the mmc pointer,
272 * a command pointer, and an optional data pointer.
275 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
280 struct fsl_esdhc_cfg *cfg = mmc->priv;
281 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
283 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
284 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
288 esdhc_write32(®s->irqstat, -1);
292 /* Wait for the bus to be idle */
293 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
294 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
297 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
300 /* Wait at least 8 SD clock cycles before the next command */
302 * Note: This is way more than 8 cycles, but 1ms seems to
303 * resolve timing issues with some cards
307 /* Set up for a data transfer if we have one */
309 err = esdhc_setup_data(mmc, data);
314 /* Figure out the transfer arguments */
315 xfertyp = esdhc_xfertyp(cmd, data);
318 esdhc_write32(®s->irqsigen, 0);
320 /* Send the command */
321 esdhc_write32(®s->cmdarg, cmd->cmdarg);
322 #if defined(CONFIG_FSL_USDHC)
323 esdhc_write32(®s->mixctrl,
324 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F));
325 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000);
327 esdhc_write32(®s->xfertyp, xfertyp);
330 /* Wait for the command to complete */
331 while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE)))
334 irqstat = esdhc_read32(®s->irqstat);
336 if (irqstat & CMD_ERR) {
341 if (irqstat & IRQSTAT_CTOE) {
346 /* Switch voltage to 1.8V if CMD11 succeeded */
347 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
348 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
350 printf("Run CMD11 1.8V switch\n");
351 /* Sleep for 5 ms - max time for card to switch to 1.8V */
355 /* Workaround for ESDHC errata ENGcm03648 */
356 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
359 /* Poll on DATA0 line for cmd with busy signal for 250 ms */
360 while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
367 printf("Timeout waiting for DAT0 to go high!\n");
373 /* Copy the response to the response buffer */
374 if (cmd->resp_type & MMC_RSP_136) {
375 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
377 cmdrsp3 = esdhc_read32(®s->cmdrsp3);
378 cmdrsp2 = esdhc_read32(®s->cmdrsp2);
379 cmdrsp1 = esdhc_read32(®s->cmdrsp1);
380 cmdrsp0 = esdhc_read32(®s->cmdrsp0);
381 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
382 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
383 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
384 cmd->response[3] = (cmdrsp0 << 8);
386 cmd->response[0] = esdhc_read32(®s->cmdrsp0);
388 /* Wait until all of the blocks are transferred */
390 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
391 esdhc_pio_read_write(mmc, data);
394 irqstat = esdhc_read32(®s->irqstat);
396 if (irqstat & IRQSTAT_DTOE) {
401 if (irqstat & DATA_ERR) {
405 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
407 if (data->flags & MMC_DATA_READ)
408 check_and_invalidate_dcache_range(cmd, data);
413 /* Reset CMD and DATA portions on error */
415 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
417 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC)
421 esdhc_write32(®s->sysctl,
422 esdhc_read32(®s->sysctl) |
424 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
428 /* If this was CMD11, then notify that power cycle is needed */
429 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
430 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
433 esdhc_write32(®s->irqstat, -1);
438 static void set_sysctl(struct mmc *mmc, uint clock)
441 struct fsl_esdhc_cfg *cfg = mmc->priv;
442 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
443 int sdhc_clk = cfg->sdhc_clk;
446 if (clock < mmc->cfg->f_min)
447 clock = mmc->cfg->f_min;
449 if (sdhc_clk / 16 > clock) {
450 for (pre_div = 2; pre_div < 256; pre_div *= 2)
451 if ((sdhc_clk / pre_div) <= (clock * 16))
456 for (div = 1; div <= 16; div++)
457 if ((sdhc_clk / (div * pre_div)) <= clock)
463 clk = (pre_div << 8) | (div << 4);
465 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
467 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
471 clk = SYSCTL_PEREN | SYSCTL_CKEN;
473 esdhc_setbits32(®s->sysctl, clk);
476 static void esdhc_set_ios(struct mmc *mmc)
478 struct fsl_esdhc_cfg *cfg = mmc->priv;
479 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
481 /* Set the clock speed */
482 set_sysctl(mmc, mmc->clock);
484 /* Set the bus width */
485 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
487 if (mmc->bus_width == 4)
488 esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
489 else if (mmc->bus_width == 8)
490 esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
494 static int esdhc_init(struct mmc *mmc)
496 struct fsl_esdhc_cfg *cfg = mmc->priv;
497 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
500 /* Reset the entire host controller */
501 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
503 /* Wait until the controller is available */
504 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
508 /* Enable cache snooping */
509 esdhc_write32(®s->scr, 0x00000040);
512 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
514 /* Set the initial clock speed */
515 mmc_set_clock(mmc, 400000);
517 /* Disable the BRR and BWR bits in IRQSTAT */
518 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
520 /* Put the PROCTL reg back to the default */
521 esdhc_write32(®s->proctl, PROCTL_INIT);
523 /* Set timout to the maximum value */
524 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
529 static int esdhc_getcd(struct mmc *mmc)
531 struct fsl_esdhc_cfg *cfg = mmc->priv;
532 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
535 #ifdef CONFIG_ESDHC_DETECT_QUIRK
536 if (CONFIG_ESDHC_DETECT_QUIRK)
539 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
545 static void esdhc_reset(struct fsl_esdhc *regs)
547 unsigned long timeout = 100; /* wait max 100 ms */
549 /* reset the controller */
550 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
552 /* hardware clears the bit when it is done */
553 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
556 printf("MMC/SD: Reset never completed.\n");
559 static const struct mmc_ops esdhc_ops = {
560 .send_cmd = esdhc_send_cmd,
561 .set_ios = esdhc_set_ios,
563 .getcd = esdhc_getcd,
566 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
568 struct fsl_esdhc *regs;
570 u32 caps, voltage_caps;
575 regs = (struct fsl_esdhc *)cfg->esdhc_base;
577 /* First reset the eSDHC controller */
580 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
581 | SYSCTL_IPGEN | SYSCTL_CKEN);
583 writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
584 memset(&cfg->cfg, 0, sizeof(cfg->cfg));
587 caps = esdhc_read32(®s->hostcapblt);
589 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
590 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
591 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
594 /* T4240 host controller capabilities register should have VS33 bit */
595 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
596 caps = caps | ESDHC_HOSTCAPBLT_VS33;
599 if (caps & ESDHC_HOSTCAPBLT_VS18)
600 voltage_caps |= MMC_VDD_165_195;
601 if (caps & ESDHC_HOSTCAPBLT_VS30)
602 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
603 if (caps & ESDHC_HOSTCAPBLT_VS33)
604 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
606 cfg->cfg.name = "FSL_SDHC";
607 cfg->cfg.ops = &esdhc_ops;
608 #ifdef CONFIG_SYS_SD_VOLTAGE
609 cfg->cfg.voltages = CONFIG_SYS_SD_VOLTAGE;
611 cfg->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
613 if ((cfg->cfg.voltages & voltage_caps) == 0) {
614 printf("voltage not supported by controller\n");
618 cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC;
620 if (cfg->max_bus_width > 0) {
621 if (cfg->max_bus_width < 8)
622 cfg->cfg.host_caps &= ~MMC_MODE_8BIT;
623 if (cfg->max_bus_width < 4)
624 cfg->cfg.host_caps &= ~MMC_MODE_4BIT;
627 if (caps & ESDHC_HOSTCAPBLT_HSS)
628 cfg->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
630 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
631 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
632 cfg->cfg.host_caps &= ~MMC_MODE_8BIT;
635 cfg->cfg.f_min = 400000;
636 cfg->cfg.f_max = min(cfg->sdhc_clk, (u32)52000000);
638 cfg->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
640 mmc = mmc_create(&cfg->cfg, cfg);
647 int fsl_esdhc_mmc_init(bd_t *bis)
649 struct fsl_esdhc_cfg *cfg;
651 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
652 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
653 cfg->sdhc_clk = gd->arch.sdhc_clk;
654 return fsl_esdhc_initialize(bis, cfg);
657 #ifdef CONFIG_OF_LIBFDT
658 void fdt_fixup_esdhc(void *blob, bd_t *bd)
660 const char *compat = "fsl,esdhc";
662 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
663 if (!hwconfig("esdhc")) {
664 do_fixup_by_compat(blob, compat, "status", "disabled",
670 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
671 gd->arch.sdhc_clk, 1);
673 do_fixup_by_compat(blob, compat, "status", "okay",