2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
5 * Based vaguely on the pxa mmc code:
7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
9 * SPDX-License-Identifier: GPL-2.0+
20 #include <fsl_esdhc.h>
21 #include <fdt_support.h>
24 #include <asm-generic/gpio.h>
26 DECLARE_GLOBAL_DATA_PTR;
28 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
30 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
31 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
32 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
36 uint dsaddr; /* SDMA system address register */
37 uint blkattr; /* Block attributes register */
38 uint cmdarg; /* Command argument register */
39 uint xfertyp; /* Transfer type register */
40 uint cmdrsp0; /* Command response 0 register */
41 uint cmdrsp1; /* Command response 1 register */
42 uint cmdrsp2; /* Command response 2 register */
43 uint cmdrsp3; /* Command response 3 register */
44 uint datport; /* Buffer data port register */
45 uint prsstat; /* Present state register */
46 uint proctl; /* Protocol control register */
47 uint sysctl; /* System Control Register */
48 uint irqstat; /* Interrupt status register */
49 uint irqstaten; /* Interrupt status enable register */
50 uint irqsigen; /* Interrupt signal enable register */
51 uint autoc12err; /* Auto CMD error status register */
52 uint hostcapblt; /* Host controller capabilities register */
53 uint wml; /* Watermark level register */
54 uint mixctrl; /* For USDHC */
55 char reserved1[4]; /* reserved */
56 uint fevt; /* Force event register */
57 uint admaes; /* ADMA error status register */
58 uint adsaddr; /* ADMA system address register */
59 char reserved2[100]; /* reserved */
60 uint vendorspec; /* Vendor Specific register */
61 char reserved3[56]; /* reserved */
62 uint hostver; /* Host controller version register */
63 char reserved4[4]; /* reserved */
64 uint dmaerraddr; /* DMA error address register */
65 char reserved5[4]; /* reserved */
66 uint dmaerrattr; /* DMA error attribute register */
67 char reserved6[4]; /* reserved */
68 uint hostcapblt2; /* Host controller capabilities register 2 */
69 char reserved7[8]; /* reserved */
70 uint tcr; /* Tuning control register */
71 char reserved8[28]; /* reserved */
72 uint sddirctl; /* SD direction control register */
73 char reserved9[712]; /* reserved */
74 uint scr; /* eSDHC control register */
78 * struct fsl_esdhc_priv
80 * @esdhc_regs: registers of the sdhc controller
81 * @sdhc_clk: Current clk of the sdhc controller
82 * @bus_width: bus width, 1bit, 4bit or 8bit
85 * Following is used when Driver Model is enabled for MMC
86 * @dev: pointer for the device
87 * @non_removable: 0: removable; 1: non-removable
88 * @cd_gpio: gpio for card detection
90 struct fsl_esdhc_priv {
91 struct fsl_esdhc *esdhc_regs;
92 unsigned int sdhc_clk;
93 unsigned int bus_width;
94 struct mmc_config cfg;
98 struct gpio_desc cd_gpio;
101 /* Return the XFERTYP flags for a given command and data packet */
102 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
107 xfertyp |= XFERTYP_DPSEL;
108 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
109 xfertyp |= XFERTYP_DMAEN;
111 if (data->blocks > 1) {
112 xfertyp |= XFERTYP_MSBSEL;
113 xfertyp |= XFERTYP_BCEN;
114 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
115 xfertyp |= XFERTYP_AC12EN;
119 if (data->flags & MMC_DATA_READ)
120 xfertyp |= XFERTYP_DTDSEL;
123 if (cmd->resp_type & MMC_RSP_CRC)
124 xfertyp |= XFERTYP_CCCEN;
125 if (cmd->resp_type & MMC_RSP_OPCODE)
126 xfertyp |= XFERTYP_CICEN;
127 if (cmd->resp_type & MMC_RSP_136)
128 xfertyp |= XFERTYP_RSPTYP_136;
129 else if (cmd->resp_type & MMC_RSP_BUSY)
130 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
131 else if (cmd->resp_type & MMC_RSP_PRESENT)
132 xfertyp |= XFERTYP_RSPTYP_48;
134 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
135 xfertyp |= XFERTYP_CMDTYP_ABORT;
137 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
140 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
142 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
145 esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
147 struct fsl_esdhc_priv *priv = mmc->priv;
148 struct fsl_esdhc *regs = priv->esdhc_regs;
156 if (data->flags & MMC_DATA_READ) {
157 blocks = data->blocks;
160 timeout = PIO_TIMEOUT;
161 size = data->blocksize;
162 irqstat = esdhc_read32(®s->irqstat);
163 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)
166 printf("\nData Read Failed in PIO Mode.");
169 while (size && (!(irqstat & IRQSTAT_TC))) {
170 udelay(100); /* Wait before last byte transfer complete */
171 irqstat = esdhc_read32(®s->irqstat);
172 databuf = in_le32(®s->datport);
173 *((uint *)buffer) = databuf;
180 blocks = data->blocks;
181 buffer = (char *)data->src;
183 timeout = PIO_TIMEOUT;
184 size = data->blocksize;
185 irqstat = esdhc_read32(®s->irqstat);
186 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)
189 printf("\nData Write Failed in PIO Mode.");
192 while (size && (!(irqstat & IRQSTAT_TC))) {
193 udelay(100); /* Wait before last byte transfer complete */
194 databuf = *((uint *)buffer);
197 irqstat = esdhc_read32(®s->irqstat);
198 out_le32(®s->datport, databuf);
206 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
209 struct fsl_esdhc_priv *priv = mmc->priv;
210 struct fsl_esdhc *regs = priv->esdhc_regs;
211 #ifdef CONFIG_FSL_LAYERSCAPE
216 wml_value = data->blocksize/4;
218 if (data->flags & MMC_DATA_READ) {
219 if (wml_value > WML_RD_WML_MAX)
220 wml_value = WML_RD_WML_MAX_VAL;
222 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
223 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
224 #ifdef CONFIG_FSL_LAYERSCAPE
225 addr = virt_to_phys((void *)(data->dest));
226 if (upper_32_bits(addr))
227 printf("Error found for upper 32 bits\n");
229 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
231 esdhc_write32(®s->dsaddr, (u32)data->dest);
235 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
236 flush_dcache_range((ulong)data->src,
237 (ulong)data->src+data->blocks
240 if (wml_value > WML_WR_WML_MAX)
241 wml_value = WML_WR_WML_MAX_VAL;
242 if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) {
243 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
247 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
249 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
250 #ifdef CONFIG_FSL_LAYERSCAPE
251 addr = virt_to_phys((void *)(data->src));
252 if (upper_32_bits(addr))
253 printf("Error found for upper 32 bits\n");
255 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
257 esdhc_write32(®s->dsaddr, (u32)data->src);
262 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
264 /* Calculate the timeout period for data transactions */
266 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
267 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
268 * So, Number of SD Clock cycles for 0.25sec should be minimum
269 * (SD Clock/sec * 0.25 sec) SD Clock cycles
270 * = (mmc->clock * 1/4) SD Clock cycles
272 * => (2^(timeout+13)) >= mmc->clock * 1/4
273 * Taking log2 both the sides
274 * => timeout + 13 >= log2(mmc->clock/4)
275 * Rounding up to next power of 2
276 * => timeout + 13 = log2(mmc->clock/4) + 1
277 * => timeout + 13 = fls(mmc->clock/4)
279 * However, the MMC spec "It is strongly recommended for hosts to
280 * implement more than 500ms timeout value even if the card
281 * indicates the 250ms maximum busy length." Even the previous
282 * value of 300ms is known to be insufficient for some cards.
284 * => timeout + 13 = fls(mmc->clock/2)
286 timeout = fls(mmc->clock/2);
295 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
296 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
300 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
303 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
308 static void check_and_invalidate_dcache_range
309 (struct mmc_cmd *cmd,
310 struct mmc_data *data) {
313 unsigned size = roundup(ARCH_DMA_MINALIGN,
314 data->blocks*data->blocksize);
315 #ifdef CONFIG_FSL_LAYERSCAPE
318 addr = virt_to_phys((void *)(data->dest));
319 if (upper_32_bits(addr))
320 printf("Error found for upper 32 bits\n");
322 start = lower_32_bits(addr);
324 start = (unsigned)data->dest;
327 invalidate_dcache_range(start, end);
331 * Sends a command out on the bus. Takes the mmc pointer,
332 * a command pointer, and an optional data pointer.
335 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
340 struct fsl_esdhc_priv *priv = mmc->priv;
341 struct fsl_esdhc *regs = priv->esdhc_regs;
343 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
344 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
348 esdhc_write32(®s->irqstat, -1);
352 /* Wait for the bus to be idle */
353 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
354 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
357 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
360 /* Wait at least 8 SD clock cycles before the next command */
362 * Note: This is way more than 8 cycles, but 1ms seems to
363 * resolve timing issues with some cards
367 /* Set up for a data transfer if we have one */
369 err = esdhc_setup_data(mmc, data);
373 if (data->flags & MMC_DATA_READ)
374 check_and_invalidate_dcache_range(cmd, data);
377 /* Figure out the transfer arguments */
378 xfertyp = esdhc_xfertyp(cmd, data);
381 esdhc_write32(®s->irqsigen, 0);
383 /* Send the command */
384 esdhc_write32(®s->cmdarg, cmd->cmdarg);
385 #if defined(CONFIG_FSL_USDHC)
386 esdhc_write32(®s->mixctrl,
387 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
388 | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
389 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000);
391 esdhc_write32(®s->xfertyp, xfertyp);
394 /* Wait for the command to complete */
395 while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE)))
398 irqstat = esdhc_read32(®s->irqstat);
400 if (irqstat & CMD_ERR) {
405 if (irqstat & IRQSTAT_CTOE) {
410 /* Switch voltage to 1.8V if CMD11 succeeded */
411 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
412 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
414 printf("Run CMD11 1.8V switch\n");
415 /* Sleep for 5 ms - max time for card to switch to 1.8V */
419 /* Workaround for ESDHC errata ENGcm03648 */
420 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
423 /* Poll on DATA0 line for cmd with busy signal for 600 ms */
424 while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
431 printf("Timeout waiting for DAT0 to go high!\n");
437 /* Copy the response to the response buffer */
438 if (cmd->resp_type & MMC_RSP_136) {
439 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
441 cmdrsp3 = esdhc_read32(®s->cmdrsp3);
442 cmdrsp2 = esdhc_read32(®s->cmdrsp2);
443 cmdrsp1 = esdhc_read32(®s->cmdrsp1);
444 cmdrsp0 = esdhc_read32(®s->cmdrsp0);
445 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
446 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
447 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
448 cmd->response[3] = (cmdrsp0 << 8);
450 cmd->response[0] = esdhc_read32(®s->cmdrsp0);
452 /* Wait until all of the blocks are transferred */
454 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
455 esdhc_pio_read_write(mmc, data);
458 irqstat = esdhc_read32(®s->irqstat);
460 if (irqstat & IRQSTAT_DTOE) {
465 if (irqstat & DATA_ERR) {
469 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
472 * Need invalidate the dcache here again to avoid any
473 * cache-fill during the DMA operations such as the
474 * speculative pre-fetching etc.
476 if (data->flags & MMC_DATA_READ)
477 check_and_invalidate_dcache_range(cmd, data);
482 /* Reset CMD and DATA portions on error */
484 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
486 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC)
490 esdhc_write32(®s->sysctl,
491 esdhc_read32(®s->sysctl) |
493 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
497 /* If this was CMD11, then notify that power cycle is needed */
498 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
499 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
502 esdhc_write32(®s->irqstat, -1);
507 static void set_sysctl(struct mmc *mmc, uint clock)
510 struct fsl_esdhc_priv *priv = mmc->priv;
511 struct fsl_esdhc *regs = priv->esdhc_regs;
512 int sdhc_clk = priv->sdhc_clk;
515 if (clock < mmc->cfg->f_min)
516 clock = mmc->cfg->f_min;
518 if (sdhc_clk / 16 > clock) {
519 for (pre_div = 2; pre_div < 256; pre_div *= 2)
520 if ((sdhc_clk / pre_div) <= (clock * 16))
525 for (div = 1; div <= 16; div++)
526 if ((sdhc_clk / (div * pre_div)) <= clock)
529 pre_div >>= mmc->ddr_mode ? 2 : 1;
532 clk = (pre_div << 8) | (div << 4);
534 #ifdef CONFIG_FSL_USDHC
535 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
537 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
540 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
544 #ifdef CONFIG_FSL_USDHC
545 esdhc_clrbits32(®s->sysctl, SYSCTL_RSTA);
547 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
552 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
553 static void esdhc_clock_control(struct mmc *mmc, bool enable)
555 struct fsl_esdhc_priv *priv = mmc->priv;
556 struct fsl_esdhc *regs = priv->esdhc_regs;
560 value = esdhc_read32(®s->sysctl);
563 value |= SYSCTL_CKEN;
565 value &= ~SYSCTL_CKEN;
567 esdhc_write32(®s->sysctl, value);
570 value = PRSSTAT_SDSTB;
571 while (!(esdhc_read32(®s->prsstat) & value)) {
573 printf("fsl_esdhc: Internal clock never stabilised.\n");
582 static void esdhc_set_ios(struct mmc *mmc)
584 struct fsl_esdhc_priv *priv = mmc->priv;
585 struct fsl_esdhc *regs = priv->esdhc_regs;
587 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
588 /* Select to use peripheral clock */
589 esdhc_clock_control(mmc, false);
590 esdhc_setbits32(®s->scr, ESDHCCTL_PCS);
591 esdhc_clock_control(mmc, true);
593 /* Set the clock speed */
594 set_sysctl(mmc, mmc->clock);
596 /* Set the bus width */
597 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
599 if (mmc->bus_width == 4)
600 esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
601 else if (mmc->bus_width == 8)
602 esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
606 static int esdhc_init(struct mmc *mmc)
608 struct fsl_esdhc_priv *priv = mmc->priv;
609 struct fsl_esdhc *regs = priv->esdhc_regs;
612 /* Reset the entire host controller */
613 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
615 /* Wait until the controller is available */
616 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
620 /* Enable cache snooping */
621 esdhc_write32(®s->scr, 0x00000040);
624 #ifndef CONFIG_FSL_USDHC
625 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
628 /* Set the initial clock speed */
629 mmc_set_clock(mmc, 400000);
631 /* Disable the BRR and BWR bits in IRQSTAT */
632 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
634 /* Put the PROCTL reg back to the default */
635 esdhc_write32(®s->proctl, PROCTL_INIT);
637 /* Set timout to the maximum value */
638 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
640 #ifdef CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT
641 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
647 static int esdhc_getcd(struct mmc *mmc)
649 struct fsl_esdhc_priv *priv = mmc->priv;
650 struct fsl_esdhc *regs = priv->esdhc_regs;
653 #ifdef CONFIG_ESDHC_DETECT_QUIRK
654 if (CONFIG_ESDHC_DETECT_QUIRK)
659 if (priv->non_removable)
662 if (dm_gpio_is_valid(&priv->cd_gpio))
663 return dm_gpio_get_value(&priv->cd_gpio);
666 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
672 static void esdhc_reset(struct fsl_esdhc *regs)
674 unsigned long timeout = 100; /* wait max 100 ms */
676 /* reset the controller */
677 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
679 /* hardware clears the bit when it is done */
680 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
683 printf("MMC/SD: Reset never completed.\n");
686 static const struct mmc_ops esdhc_ops = {
687 .send_cmd = esdhc_send_cmd,
688 .set_ios = esdhc_set_ios,
690 .getcd = esdhc_getcd,
693 static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
694 struct fsl_esdhc_priv *priv)
699 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
700 priv->bus_width = cfg->max_bus_width;
701 priv->sdhc_clk = cfg->sdhc_clk;
706 static int fsl_esdhc_init(struct fsl_esdhc_priv *priv)
708 struct fsl_esdhc *regs;
710 u32 caps, voltage_caps;
715 regs = priv->esdhc_regs;
717 /* First reset the eSDHC controller */
720 #ifndef CONFIG_FSL_USDHC
721 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
722 | SYSCTL_IPGEN | SYSCTL_CKEN);
725 writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
726 memset(&priv->cfg, 0, sizeof(priv->cfg));
729 caps = esdhc_read32(®s->hostcapblt);
731 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
732 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
733 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
736 /* T4240 host controller capabilities register should have VS33 bit */
737 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
738 caps = caps | ESDHC_HOSTCAPBLT_VS33;
741 if (caps & ESDHC_HOSTCAPBLT_VS18)
742 voltage_caps |= MMC_VDD_165_195;
743 if (caps & ESDHC_HOSTCAPBLT_VS30)
744 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
745 if (caps & ESDHC_HOSTCAPBLT_VS33)
746 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
748 priv->cfg.name = "FSL_SDHC";
749 priv->cfg.ops = &esdhc_ops;
750 #ifdef CONFIG_SYS_SD_VOLTAGE
751 priv->cfg.voltages = CONFIG_SYS_SD_VOLTAGE;
753 priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
755 if ((priv->cfg.voltages & voltage_caps) == 0) {
756 printf("voltage not supported by controller\n");
760 if (priv->bus_width == 8)
761 priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
762 else if (priv->bus_width == 4)
763 priv->cfg.host_caps = MMC_MODE_4BIT;
765 priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
766 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
767 priv->cfg.host_caps |= MMC_MODE_DDR_52MHz;
770 if (priv->bus_width > 0) {
771 if (priv->bus_width < 8)
772 priv->cfg.host_caps &= ~MMC_MODE_8BIT;
773 if (priv->bus_width < 4)
774 priv->cfg.host_caps &= ~MMC_MODE_4BIT;
777 if (caps & ESDHC_HOSTCAPBLT_HSS)
778 priv->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
780 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
781 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
782 priv->cfg.host_caps &= ~MMC_MODE_8BIT;
785 priv->cfg.f_min = 400000;
786 priv->cfg.f_max = min(priv->sdhc_clk, (u32)52000000);
788 priv->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
790 mmc = mmc_create(&priv->cfg, priv);
799 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
801 struct fsl_esdhc_priv *priv;
807 priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
811 ret = fsl_esdhc_cfg_to_priv(cfg, priv);
813 debug("%s xlate failure\n", __func__);
818 ret = fsl_esdhc_init(priv);
820 debug("%s init failure\n", __func__);
828 int fsl_esdhc_mmc_init(bd_t *bis)
830 struct fsl_esdhc_cfg *cfg;
832 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
833 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
834 cfg->sdhc_clk = gd->arch.sdhc_clk;
835 return fsl_esdhc_initialize(bis, cfg);
838 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
839 void mmc_adapter_card_type_ident(void)
844 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
845 gd->arch.sdhc_adapter = card_id;
848 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
849 value = QIXIS_READ(brdcfg[5]);
850 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
851 QIXIS_WRITE(brdcfg[5], value);
853 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
854 value = QIXIS_READ(pwr_ctl[1]);
855 value |= QIXIS_EVDD_BY_SDHC_VS;
856 QIXIS_WRITE(pwr_ctl[1], value);
858 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
859 value = QIXIS_READ(brdcfg[5]);
860 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
861 QIXIS_WRITE(brdcfg[5], value);
863 case QIXIS_ESDHC_ADAPTER_TYPE_RSV:
865 case QIXIS_ESDHC_ADAPTER_TYPE_MMC:
867 case QIXIS_ESDHC_ADAPTER_TYPE_SD:
869 case QIXIS_ESDHC_NO_ADAPTER:
877 #ifdef CONFIG_OF_LIBFDT
878 void fdt_fixup_esdhc(void *blob, bd_t *bd)
880 const char *compat = "fsl,esdhc";
882 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
883 if (!hwconfig("esdhc")) {
884 do_fixup_by_compat(blob, compat, "status", "disabled",
890 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
891 do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
892 gd->arch.sdhc_clk, 1);
894 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
895 gd->arch.sdhc_clk, 1);
897 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
898 do_fixup_by_compat_u32(blob, compat, "adapter-type",
899 (u32)(gd->arch.sdhc_adapter), 1);
901 do_fixup_by_compat(blob, compat, "status", "okay",
907 #include <asm/arch/clock.h>
908 static int fsl_esdhc_probe(struct udevice *dev)
910 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
911 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
912 const void *fdt = gd->fdt_blob;
913 int node = dev->of_offset;
918 addr = dev_get_addr(dev);
919 if (addr == FDT_ADDR_T_NONE)
922 priv->esdhc_regs = (struct fsl_esdhc *)addr;
925 val = fdtdec_get_int(fdt, node, "bus-width", -1);
933 if (fdt_get_property(fdt, node, "non-removable", NULL)) {
934 priv->non_removable = 1;
936 priv->non_removable = 0;
937 gpio_request_by_name_nodev(fdt, node, "cd-gpios", 0,
938 &priv->cd_gpio, GPIOD_IS_IN);
943 * Because lack of clk driver, if SDHC clk is not enabled,
944 * need to enable it first before this driver is invoked.
946 * we use MXC_ESDHC_CLK to get clk freq.
947 * If one would like to make this function work,
948 * the aliases should be provided in dts as this:
956 * Then if your board only supports mmc2 and mmc3, but we can
957 * correctly get the seq as 2 and 3, then let mxc_get_clock
960 priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
961 if (priv->sdhc_clk <= 0) {
962 dev_err(dev, "Unable to get clk for %s\n", dev->name);
966 ret = fsl_esdhc_init(priv);
968 dev_err(dev, "fsl_esdhc_init failure\n");
972 upriv->mmc = priv->mmc;
977 static const struct udevice_id fsl_esdhc_ids[] = {
978 { .compatible = "fsl,imx6ul-usdhc", },
979 { .compatible = "fsl,imx6sx-usdhc", },
980 { .compatible = "fsl,imx6sl-usdhc", },
981 { .compatible = "fsl,imx6q-usdhc", },
982 { .compatible = "fsl,imx7d-usdhc", },
986 U_BOOT_DRIVER(fsl_esdhc) = {
987 .name = "fsl-esdhc-mmc",
989 .of_match = fsl_esdhc_ids,
990 .probe = fsl_esdhc_probe,
991 .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),