2 * (C) Copyright 2012 SAMSUNG Electronics
3 * Jaehoon Chung <jh80.chung@samsung.com>
5 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/dwmmc.h>
14 #include <asm/arch/clk.h>
15 #include <asm/arch/pinmux.h>
17 #include <asm-generic/errno.h>
19 #define DWMMC_MAX_CH_NUM 4
20 #define DWMMC_MAX_FREQ 52000000
21 #define DWMMC_MIN_FREQ 400000
22 #define DWMMC_MMC0_CLKSEL_VAL 0x03030001
23 #define DWMMC_MMC2_CLKSEL_VAL 0x03020001
26 * Function used as callback function to initialise the
27 * CLKSEL register for every mmc channel.
29 static void exynos_dwmci_clksel(struct dwmci_host *host)
31 dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val);
34 unsigned int exynos_dwmci_get_clk(struct dwmci_host *host)
40 * Since SDCLKIN is divided inside controller by the DIVRATIO
41 * value set in the CLKSEL register, we need to use the same output
42 * clock value to calculate the CLKDIV value.
43 * as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1)
45 clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT)
46 & DWMCI_DIVRATIO_MASK) + 1;
47 sclk = get_mmc_clk(host->dev_index);
50 * Assume to know divider value.
51 * When clock unit is broken, need to set "host->div"
53 return sclk / clk_div / (host->div + 1);
56 static void exynos_dwmci_board_init(struct dwmci_host *host)
58 if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) {
59 dwmci_writel(host, EMMCP_MPSBEGIN0, 0);
60 dwmci_writel(host, EMMCP_SEND0, 0);
61 dwmci_writel(host, EMMCP_CTRL0,
62 MPSCTRL_SECURE_READ_BIT |
63 MPSCTRL_SECURE_WRITE_BIT |
64 MPSCTRL_NON_SECURE_READ_BIT |
65 MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID);
69 static int exynos_dwmci_core_init(struct dwmci_host *host, int index)
72 unsigned long freq, sclk;
77 freq = DWMMC_MAX_FREQ;
79 /* request mmc clock vlaue of 52MHz. */
80 sclk = get_mmc_clk(index);
81 div = DIV_ROUND_UP(sclk, freq);
82 /* set the clock divisor for mmc */
83 set_mmc_clk(index, div);
85 host->name = "EXYNOS DWMMC";
86 #ifdef CONFIG_EXYNOS5420
87 host->quirks = DWMCI_QUIRK_DISABLE_SMU;
89 host->board_init = exynos_dwmci_board_init;
91 if (!host->clksel_val) {
93 host->clksel_val = DWMMC_MMC0_CLKSEL_VAL;
95 host->clksel_val = DWMMC_MMC2_CLKSEL_VAL;
98 host->clksel = exynos_dwmci_clksel;
99 host->dev_index = index;
100 host->get_mmc_clk = exynos_dwmci_get_clk;
101 /* Add the mmc channel to be registered with mmc core */
102 if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
103 debug("dwmmc%d registration failed\n", index);
110 * This function adds the mmc channel to be registered with mmc core.
111 * index - mmc channel number.
112 * regbase - register base address of mmc channel specified in 'index'.
113 * bus_width - operating bus width of mmc channel specified in 'index'.
114 * clksel - value to be written into CLKSEL register in case of FDT.
115 * NULL in case od non-FDT.
117 int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel)
119 struct dwmci_host *host = NULL;
121 host = malloc(sizeof(struct dwmci_host));
123 error("dwmci_host malloc fail!\n");
127 host->ioaddr = (void *)regbase;
128 host->buswidth = bus_width;
131 host->clksel_val = clksel;
133 return exynos_dwmci_core_init(host, index);
136 #ifdef CONFIG_OF_CONTROL
137 static struct dwmci_host dwmci_host[DWMMC_MAX_CH_NUM];
139 static int do_dwmci_init(struct dwmci_host *host)
141 int index, flag, err;
143 index = host->dev_index;
145 flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE;
146 err = exynos_pinmux_config(host->dev_id, flag);
148 debug("DWMMC not configure\n");
152 return exynos_dwmci_core_init(host, index);
155 static int exynos_dwmci_get_config(const void *blob, int node,
156 struct dwmci_host *host)
159 u32 base, clksel_val, timing[3];
161 /* Extract device id for each mmc channel */
162 host->dev_id = pinmux_decode_periph_id(blob, node);
164 /* Get the bus width from the device node */
165 host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
166 if (host->buswidth <= 0) {
167 debug("DWMMC: Can't get bus-width\n");
171 host->dev_index = fdtdec_get_int(blob, node, "index", host->dev_id);
172 if (host->dev_index == host->dev_id)
173 host->dev_index = host->dev_id - PERIPH_ID_SDMMC0;
175 /* Set the base address from the device node */
176 base = fdtdec_get_addr(blob, node, "reg");
178 debug("DWMMC: Can't get base address\n");
181 host->ioaddr = (void *)base;
183 /* Extract the timing info from the node */
184 err = fdtdec_get_int_array(blob, node, "samsung,timing", timing, 3);
186 debug("Can't get sdr-timings for devider\n");
190 clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) |
191 DWMCI_SET_DRV_CLK(timing[1]) |
192 DWMCI_SET_DIV_RATIO(timing[2]));
194 host->clksel_val = clksel_val;
196 host->fifoth_val = fdtdec_get_int(blob, node, "fifoth_val", 0);
197 host->bus_hz = fdtdec_get_int(blob, node, "bus_hz", 0);
198 host->div = fdtdec_get_int(blob, node, "div", 0);
203 static int exynos_dwmci_process_node(const void *blob,
204 int node_list[], int count)
206 struct dwmci_host *host;
209 for (i = 0; i < count; i++) {
213 host = &dwmci_host[i];
214 err = exynos_dwmci_get_config(blob, node, host);
216 debug("%s: failed to decode dev %d\n", __func__, i);
225 int exynos_dwmmc_init(const void *blob)
228 int node_list[DWMMC_MAX_CH_NUM];
231 compat_id = COMPAT_SAMSUNG_EXYNOS_DWMMC;
233 count = fdtdec_find_aliases_for_id(blob, "mmc",
234 compat_id, node_list, DWMMC_MAX_CH_NUM);
235 err = exynos_dwmci_process_node(blob, node_list, count);