drivers/mmc/dw_mmc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2012 SAMSUNG Electronics
   4  * Jaehoon Chung <jh80.chung@samsung.com>
   5  * Rajeshawari Shinde <rajeshwari.s@samsung.com>
   6  */
   7
   8 #include <bouncebuf.h>
   9 #include <common.h>
  10 #include <cpu_func.h>
  11 #include <errno.h>
  12 #include <log.h>
  13 #include <malloc.h>
  14 #include <memalign.h>
  15 #include <mmc.h>
  16 #include <dwmmc.h>
  17 #include <wait_bit.h>
  18 #include <asm/cache.h>
  19 #include <linux/delay.h>
  20 #include <power/regulator.h>
  21
  22 #define PAGE_SIZE 4096
  23
  24 static int dwmci_wait_reset(struct dwmci_host *host, u32 value)
  25 {
  26         unsigned long timeout = 1000;
  27         u32 ctrl;
  28
  29         dwmci_writel(host, DWMCI_CTRL, value);
  30
  31         while (timeout--) {
  32                 ctrl = dwmci_readl(host, DWMCI_CTRL);
  33                 if (!(ctrl & DWMCI_RESET_ALL))
  34                         return 1;
  35         }
  36         return 0;
  37 }
  38
  39 static void dwmci_set_idma_desc(struct dwmci_idmac *idmac,
  40                 u32 desc0, u32 desc1, u32 desc2)
  41 {
  42         struct dwmci_idmac *desc = idmac;
  43
  44         desc->flags = desc0;
  45         desc->cnt = desc1;
  46         desc->addr = desc2;
  47         desc->next_addr = (ulong)desc + sizeof(struct dwmci_idmac);
  48 }
  49
  50 static void dwmci_prepare_data(struct dwmci_host *host,
  51                                struct mmc_data *data,
  52                                struct dwmci_idmac *cur_idmac,
  53                                void *bounce_buffer)
  54 {
  55         unsigned long ctrl;
  56         unsigned int i = 0, flags, cnt, blk_cnt;
  57         ulong data_start, data_end;
  58
  59
  60         blk_cnt = data->blocks;
  61
  62         dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
  63
  64         /* Clear IDMAC interrupt */
  65         dwmci_writel(host, DWMCI_IDSTS, 0xFFFFFFFF);
  66
  67         data_start = (ulong)cur_idmac;
  68         dwmci_writel(host, DWMCI_DBADDR, (ulong)cur_idmac);
  69
  70         do {
  71                 flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ;
  72                 flags |= (i == 0) ? DWMCI_IDMAC_FS : 0;
  73                 if (blk_cnt <= 8) {
  74                         flags |= DWMCI_IDMAC_LD;
  75                         cnt = data->blocksize * blk_cnt;
  76                 } else
  77                         cnt = data->blocksize * 8;
  78
  79                 dwmci_set_idma_desc(cur_idmac, flags, cnt,
  80                                     (ulong)bounce_buffer + (i * PAGE_SIZE));
  81
  82                 cur_idmac++;
  83                 if (blk_cnt <= 8)
  84                         break;
  85                 blk_cnt -= 8;
  86                 i++;
  87         } while(1);
  88
  89         data_end = (ulong)cur_idmac;
  90         flush_dcache_range(data_start, roundup(data_end, ARCH_DMA_MINALIGN));
  91
  92         ctrl = dwmci_readl(host, DWMCI_CTRL);
  93         ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN;
  94         dwmci_writel(host, DWMCI_CTRL, ctrl);
  95
  96         ctrl = dwmci_readl(host, DWMCI_BMOD);
  97         ctrl |= DWMCI_BMOD_IDMAC_FB | DWMCI_BMOD_IDMAC_EN;
  98         dwmci_writel(host, DWMCI_BMOD, ctrl);
  99
 100         dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
 101         dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);
 102 }
 103
 104 static int dwmci_fifo_ready(struct dwmci_host *host, u32 bit, u32 *len)
 105 {
 106         u32 timeout = 20000;
 107
 108         *len = dwmci_readl(host, DWMCI_STATUS);
 109         while (--timeout && (*len & bit)) {
 110                 udelay(200);
 111                 *len = dwmci_readl(host, DWMCI_STATUS);
 112         }
 113
 114         if (!timeout) {
 115                 debug("%s: FIFO underflow timeout\n", __func__);
 116                 return -ETIMEDOUT;
 117         }
 118
 119         return 0;
 120 }
 121
 122 static unsigned int dwmci_get_timeout(struct mmc *mmc, const unsigned int size)
 123 {
 124         unsigned int timeout;
 125
 126         timeout = size * 8;     /* counting in bits */
 127         timeout *= 10;          /* wait 10 times as long */
 128         timeout /= mmc->clock;
 129         timeout /= mmc->bus_width;
 130         timeout /= mmc->ddr_mode ? 2 : 1;
 131         timeout *= 1000;        /* counting in msec */
 132         timeout = (timeout < 1000) ? 1000 : timeout;
 133
 134         return timeout;
 135 }
 136
 137 static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data)
 138 {
 139         struct mmc *mmc = host->mmc;
 140         int ret = 0;
 141         u32 timeout, mask, size, i, len = 0;
 142         u32 *buf = NULL;
 143         ulong start = get_timer(0);
 144         u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >>
 145                             RX_WMARK_SHIFT) + 1) * 2;
 146
 147         size = data->blocksize * data->blocks;
 148         if (data->flags == MMC_DATA_READ)
 149                 buf = (unsigned int *)data->dest;
 150         else
 151                 buf = (unsigned int *)data->src;
 152
 153         timeout = dwmci_get_timeout(mmc, size);
 154
 155         size /= 4;
 156
 157         for (;;) {
 158                 mask = dwmci_readl(host, DWMCI_RINTSTS);
 159                 /* Error during data transfer. */
 160                 if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
 161                         debug("%s: DATA ERROR!\n", __func__);
 162                         ret = -EINVAL;
 163                         break;
 164                 }
 165
 166                 if (host->fifo_mode && size) {
 167                         len = 0;
 168                         if (data->flags == MMC_DATA_READ &&
 169                             (mask & (DWMCI_INTMSK_RXDR | DWMCI_INTMSK_DTO))) {
 170                                 dwmci_writel(host, DWMCI_RINTSTS,
 171                                              mask & (DWMCI_INTMSK_RXDR |
 172                                                      DWMCI_INTMSK_DTO));
 173                                 while (size) {
 174                                         ret = dwmci_fifo_ready(host,
 175                                                         DWMCI_FIFO_EMPTY,
 176                                                         &len);
 177                                         if (ret < 0)
 178                                                 break;
 179
 180                                         len = (len >> DWMCI_FIFO_SHIFT) &
 181                                                     DWMCI_FIFO_MASK;
 182                                         len = min(size, len);
 183                                         for (i = 0; i < len; i++)
 184                                                 *buf++ =
 185                                                 dwmci_readl(host, DWMCI_DATA);
 186                                         size = size > len ? (size - len) : 0;
 187                                 }
 188                         } else if (data->flags == MMC_DATA_WRITE &&
 189                                    (mask & DWMCI_INTMSK_TXDR)) {
 190                                 while (size) {
 191                                         ret = dwmci_fifo_ready(host,
 192                                                         DWMCI_FIFO_FULL,
 193                                                         &len);
 194                                         if (ret < 0)
 195                                                 break;
 196
 197                                         len = fifo_depth - ((len >>
 198                                                    DWMCI_FIFO_SHIFT) &
 199                                                    DWMCI_FIFO_MASK);
 200                                         len = min(size, len);
 201                                         for (i = 0; i < len; i++)
 202                                                 dwmci_writel(host, DWMCI_DATA,
 203                                                              *buf++);
 204                                         size = size > len ? (size - len) : 0;
 205                                 }
 206                                 dwmci_writel(host, DWMCI_RINTSTS,
 207                                              DWMCI_INTMSK_TXDR);
 208                         }
 209                 }
 210
 211                 /* Data arrived correctly. */
 212                 if (mask & DWMCI_INTMSK_DTO) {
 213                         ret = 0;
 214                         break;
 215                 }
 216
 217                 /* Check for timeout. */
 218                 if (get_timer(start) > timeout) {
 219                         debug("%s: Timeout waiting for data!\n",
 220                               __func__);
 221                         ret = -ETIMEDOUT;
 222                         break;
 223                 }
 224         }
 225
 226         dwmci_writel(host, DWMCI_RINTSTS, mask);
 227
 228         return ret;
 229 }
 230
 231 static int dwmci_set_transfer_mode(struct dwmci_host *host,
 232                 struct mmc_data *data)
 233 {
 234         unsigned long mode;
 235
 236         mode = DWMCI_CMD_DATA_EXP;
 237         if (data->flags & MMC_DATA_WRITE)
 238                 mode |= DWMCI_CMD_RW;
 239
 240         return mode;
 241 }
 242
 243 #ifdef CONFIG_DM_MMC
 244 static int dwmci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 245                    struct mmc_data *data)
 246 {
 247         struct mmc *mmc = mmc_get_mmc_dev(dev);
 248 #else
 249 static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 250                 struct mmc_data *data)
 251 {
 252 #endif
 253         struct dwmci_host *host = mmc->priv;
 254         ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac,
 255                                  data ? DIV_ROUND_UP(data->blocks, 8) : 0);
 256         int ret = 0, flags = 0, i;
 257         unsigned int timeout = 500;
 258         u32 retry = 100000;
 259         u32 mask, ctrl;
 260         ulong start = get_timer(0);
 261         struct bounce_buffer bbstate;
 262
 263         while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
 264                 if (get_timer(start) > timeout) {
 265                         debug("%s: Timeout on data busy\n", __func__);
 266                         return -ETIMEDOUT;
 267                 }
 268         }
 269
 270         dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);
 271
 272         if (data) {
 273                 if (host->fifo_mode) {
 274                         dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
 275                         dwmci_writel(host, DWMCI_BYTCNT,
 276                                      data->blocksize * data->blocks);
 277                         dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
 278                 } else {
 279                         if (data->flags == MMC_DATA_READ) {
 280                                 ret = bounce_buffer_start(&bbstate,
 281                                                 (void*)data->dest,
 282                                                 data->blocksize *
 283                                                 data->blocks, GEN_BB_WRITE);
 284                         } else {
 285                                 ret = bounce_buffer_start(&bbstate,
 286                                                 (void*)data->src,
 287                                                 data->blocksize *
 288                                                 data->blocks, GEN_BB_READ);
 289                         }
 290
 291                         if (ret)
 292                                 return ret;
 293
 294                         dwmci_prepare_data(host, data, cur_idmac,
 295                                            bbstate.bounce_buffer);
 296                 }
 297         }
 298
 299         dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
 300
 301         if (data)
 302                 flags = dwmci_set_transfer_mode(host, data);
 303
 304         if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
 305                 return -EBUSY;
 306
 307         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
 308                 flags |= DWMCI_CMD_ABORT_STOP;
 309         else
 310                 flags |= DWMCI_CMD_PRV_DAT_WAIT;
 311
 312         if (cmd->resp_type & MMC_RSP_PRESENT) {
 313                 flags |= DWMCI_CMD_RESP_EXP;
 314                 if (cmd->resp_type & MMC_RSP_136)
 315                         flags |= DWMCI_CMD_RESP_LENGTH;
 316         }
 317
 318         if (cmd->resp_type & MMC_RSP_CRC)
 319                 flags |= DWMCI_CMD_CHECK_CRC;
 320
 321         flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG);
 322
 323         debug("Sending CMD%d\n",cmd->cmdidx);
 324
 325         dwmci_writel(host, DWMCI_CMD, flags);
 326
 327         for (i = 0; i < retry; i++) {
 328                 mask = dwmci_readl(host, DWMCI_RINTSTS);
 329                 if (mask & DWMCI_INTMSK_CDONE) {
 330                         if (!data)
 331                                 dwmci_writel(host, DWMCI_RINTSTS, mask);
 332                         break;
 333                 }
 334         }
 335
 336         if (i == retry) {
 337                 debug("%s: Timeout.\n", __func__);
 338                 return -ETIMEDOUT;
 339         }
 340
 341         if (mask & DWMCI_INTMSK_RTO) {
 342                 /*
 343                  * Timeout here is not necessarily fatal. (e)MMC cards
 344                  * will splat here when they receive CMD55 as they do
 345                  * not support this command and that is exactly the way
 346                  * to tell them apart from SD cards. Thus, this output
 347                  * below shall be debug(). eMMC cards also do not favor
 348                  * CMD8, please keep that in mind.
 349                  */
 350                 debug("%s: Response Timeout.\n", __func__);
 351                 return -ETIMEDOUT;
 352         } else if (mask & DWMCI_INTMSK_RE) {
 353                 debug("%s: Response Error.\n", __func__);
 354                 return -EIO;
 355         } else if ((cmd->resp_type & MMC_RSP_CRC) &&
 356                    (mask & DWMCI_INTMSK_RCRC)) {
 357                 debug("%s: Response CRC Error.\n", __func__);
 358                 return -EIO;
 359         }
 360
 361
 362         if (cmd->resp_type & MMC_RSP_PRESENT) {
 363                 if (cmd->resp_type & MMC_RSP_136) {
 364                         cmd->response[0] = dwmci_readl(host, DWMCI_RESP3);
 365                         cmd->response[1] = dwmci_readl(host, DWMCI_RESP2);
 366                         cmd->response[2] = dwmci_readl(host, DWMCI_RESP1);
 367                         cmd->response[3] = dwmci_readl(host, DWMCI_RESP0);
 368                 } else {
 369                         cmd->response[0] = dwmci_readl(host, DWMCI_RESP0);
 370                 }
 371         }
 372
 373         if (data) {
 374                 ret = dwmci_data_transfer(host, data);
 375
 376                 /* only dma mode need it */
 377                 if (!host->fifo_mode) {
 378                         if (data->flags == MMC_DATA_READ)
 379                                 mask = DWMCI_IDINTEN_RI;
 380                         else
 381                                 mask = DWMCI_IDINTEN_TI;
 382                         ret = wait_for_bit_le32(host->ioaddr + DWMCI_IDSTS,
 383                                                 mask, true, 1000, false);
 384                         if (ret)
 385                                 debug("%s: DWMCI_IDINTEN mask 0x%x timeout.\n",
 386                                       __func__, mask);
 387                         /* clear interrupts */
 388                         dwmci_writel(host, DWMCI_IDSTS, DWMCI_IDINTEN_MASK);
 389
 390                         ctrl = dwmci_readl(host, DWMCI_CTRL);
 391                         ctrl &= ~(DWMCI_DMA_EN);
 392                         dwmci_writel(host, DWMCI_CTRL, ctrl);
 393                         bounce_buffer_stop(&bbstate);
 394                 }
 395         }
 396
 397         udelay(100);
 398
 399         return ret;
 400 }
 401
 402 static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
 403 {
 404         u32 div, status;
 405         int timeout = 10000;
 406         unsigned long sclk;
 407
 408         if ((freq == host->clock) || (freq == 0))
 409                 return 0;
 410         /*
 411          * If host->get_mmc_clk isn't defined,
 412          * then assume that host->bus_hz is source clock value.
 413          * host->bus_hz should be set by user.
 414          */
 415         if (host->get_mmc_clk)
 416                 sclk = host->get_mmc_clk(host, freq);
 417         else if (host->bus_hz)
 418                 sclk = host->bus_hz;
 419         else {
 420                 debug("%s: Didn't get source clock value.\n", __func__);
 421                 return -EINVAL;
 422         }
 423
 424         if (sclk == freq)
 425                 div = 0;        /* bypass mode */
 426         else
 427                 div = DIV_ROUND_UP(sclk, 2 * freq);
 428
 429         dwmci_writel(host, DWMCI_CLKENA, 0);
 430         dwmci_writel(host, DWMCI_CLKSRC, 0);
 431
 432         dwmci_writel(host, DWMCI_CLKDIV, div);
 433         dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
 434                         DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
 435
 436         do {
 437                 status = dwmci_readl(host, DWMCI_CMD);
 438                 if (timeout-- < 0) {
 439                         debug("%s: Timeout!\n", __func__);
 440                         return -ETIMEDOUT;
 441                 }
 442         } while (status & DWMCI_CMD_START);
 443
 444         dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE |
 445                         DWMCI_CLKEN_LOW_PWR);
 446
 447         dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
 448                         DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
 449
 450         timeout = 10000;
 451         do {
 452                 status = dwmci_readl(host, DWMCI_CMD);
 453                 if (timeout-- < 0) {
 454                         debug("%s: Timeout!\n", __func__);
 455                         return -ETIMEDOUT;
 456                 }
 457         } while (status & DWMCI_CMD_START);
 458
 459         host->clock = freq;
 460
 461         return 0;
 462 }
 463
 464 #ifdef CONFIG_DM_MMC
 465 static int dwmci_set_ios(struct udevice *dev)
 466 {
 467         struct mmc *mmc = mmc_get_mmc_dev(dev);
 468 #else
 469 static int dwmci_set_ios(struct mmc *mmc)
 470 {
 471 #endif
 472         struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
 473         u32 ctype, regs;
 474
 475         debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock);
 476
 477         dwmci_setup_bus(host, mmc->clock);
 478         switch (mmc->bus_width) {
 479         case 8:
 480                 ctype = DWMCI_CTYPE_8BIT;
 481                 break;
 482         case 4:
 483                 ctype = DWMCI_CTYPE_4BIT;
 484                 break;
 485         default:
 486                 ctype = DWMCI_CTYPE_1BIT;
 487                 break;
 488         }
 489
 490         dwmci_writel(host, DWMCI_CTYPE, ctype);
 491
 492         regs = dwmci_readl(host, DWMCI_UHS_REG);
 493         if (mmc->ddr_mode)
 494                 regs |= DWMCI_DDR_MODE;
 495         else
 496                 regs &= ~DWMCI_DDR_MODE;
 497
 498         dwmci_writel(host, DWMCI_UHS_REG, regs);
 499
 500         if (host->clksel) {
 501                 int ret;
 502
 503                 ret = host->clksel(host);
 504                 if (ret)
 505                         return ret;
 506         }
 507
 508 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 509         if (mmc->vqmmc_supply) {
 510                 int ret;
 511
 512                 if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
 513                         regulator_set_value(mmc->vqmmc_supply, 1800000);
 514                 else
 515                         regulator_set_value(mmc->vqmmc_supply, 3300000);
 516
 517                 ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, true);
 518                 if (ret)
 519                         return ret;
 520         }
 521 #endif
 522
 523         return 0;
 524 }
 525
 526 static int dwmci_init(struct mmc *mmc)
 527 {
 528         struct dwmci_host *host = mmc->priv;
 529
 530         if (host->board_init)
 531                 host->board_init(host);
 532
 533         dwmci_writel(host, DWMCI_PWREN, 1);
 534
 535         if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
 536                 debug("%s[%d] Fail-reset!!\n", __func__, __LINE__);
 537                 return -EIO;
 538         }
 539
 540         /* Enumerate at 400KHz */
 541         dwmci_setup_bus(host, mmc->cfg->f_min);
 542
 543         dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
 544         dwmci_writel(host, DWMCI_INTMASK, 0);
 545
 546         dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF);
 547
 548         dwmci_writel(host, DWMCI_IDINTEN, 0);
 549         dwmci_writel(host, DWMCI_BMOD, 1);
 550
 551         if (!host->fifoth_val) {
 552                 uint32_t fifo_size;
 553
 554                 fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
 555                 fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
 556                 host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) |
 557                                 TX_WMARK(fifo_size / 2);
 558         }
 559         dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
 560
 561         dwmci_writel(host, DWMCI_CLKENA, 0);
 562         dwmci_writel(host, DWMCI_CLKSRC, 0);
 563
 564         if (!host->fifo_mode)
 565                 dwmci_writel(host, DWMCI_IDINTEN, DWMCI_IDINTEN_MASK);
 566
 567         return 0;
 568 }
 569
 570 #ifdef CONFIG_DM_MMC
 571 int dwmci_probe(struct udevice *dev)
 572 {
 573         struct mmc *mmc = mmc_get_mmc_dev(dev);
 574
 575         return dwmci_init(mmc);
 576 }
 577
 578 const struct dm_mmc_ops dm_dwmci_ops = {
 579         .send_cmd       = dwmci_send_cmd,
 580         .set_ios        = dwmci_set_ios,
 581 };
 582
 583 #else
 584 static const struct mmc_ops dwmci_ops = {
 585         .send_cmd       = dwmci_send_cmd,
 586         .set_ios        = dwmci_set_ios,
 587         .init           = dwmci_init,
 588 };
 589 #endif
 590
 591 void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host,
 592                 u32 max_clk, u32 min_clk)
 593 {
 594         cfg->name = host->name;
 595 #ifndef CONFIG_DM_MMC
 596         cfg->ops = &dwmci_ops;
 597 #endif
 598         cfg->f_min = min_clk;
 599         cfg->f_max = max_clk;
 600
 601         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 602
 603         cfg->host_caps = host->caps;
 604
 605         if (host->buswidth == 8) {
 606                 cfg->host_caps |= MMC_MODE_8BIT;
 607                 cfg->host_caps &= ~MMC_MODE_4BIT;
 608         } else {
 609                 cfg->host_caps |= MMC_MODE_4BIT;
 610                 cfg->host_caps &= ~MMC_MODE_8BIT;
 611         }
 612         cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
 613
 614         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 615 }
 616
 617 #ifdef CONFIG_BLK
 618 int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
 619 {
 620         return mmc_bind(dev, mmc, cfg);
 621 }
 622 #else
 623 int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
 624 {
 625         dwmci_setup_cfg(&host->cfg, host, max_clk, min_clk);
 626
 627         host->mmc = mmc_create(&host->cfg, host);
 628         if (host->mmc == NULL)
 629                 return -1;
 630
 631         return 0;
 632 }
 633 #endif