2 * (C) Copyright 2012 SAMSUNG Electronics
3 * Jaehoon Chung <jh80.chung@samsung.com>
4 * Rajeshawari Shinde <rajeshwari.s@samsung.com>
6 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm-generic/errno.h>
16 #define PAGE_SIZE 4096
18 static int dwmci_wait_reset(struct dwmci_host *host, u32 value)
20 unsigned long timeout = 1000;
23 dwmci_writel(host, DWMCI_CTRL, value);
26 ctrl = dwmci_readl(host, DWMCI_CTRL);
27 if (!(ctrl & DWMCI_RESET_ALL))
33 static void dwmci_set_idma_desc(struct dwmci_idmac *idmac,
34 u32 desc0, u32 desc1, u32 desc2)
36 struct dwmci_idmac *desc = idmac;
41 desc->next_addr = (unsigned int)desc + sizeof(struct dwmci_idmac);
44 static void dwmci_prepare_data(struct dwmci_host *host,
45 struct mmc_data *data,
46 struct dwmci_idmac *cur_idmac,
50 unsigned int i = 0, flags, cnt, blk_cnt;
51 ulong data_start, data_end;
54 blk_cnt = data->blocks;
56 dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
58 data_start = (ulong)cur_idmac;
59 dwmci_writel(host, DWMCI_DBADDR, (unsigned int)cur_idmac);
62 flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ;
63 flags |= (i == 0) ? DWMCI_IDMAC_FS : 0;
65 flags |= DWMCI_IDMAC_LD;
66 cnt = data->blocksize * blk_cnt;
68 cnt = data->blocksize * 8;
70 dwmci_set_idma_desc(cur_idmac, flags, cnt,
71 (u32)bounce_buffer + (i * PAGE_SIZE));
80 data_end = (ulong)cur_idmac;
81 flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN);
83 ctrl = dwmci_readl(host, DWMCI_CTRL);
84 ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN;
85 dwmci_writel(host, DWMCI_CTRL, ctrl);
87 ctrl = dwmci_readl(host, DWMCI_BMOD);
88 ctrl |= DWMCI_BMOD_IDMAC_FB | DWMCI_BMOD_IDMAC_EN;
89 dwmci_writel(host, DWMCI_BMOD, ctrl);
91 dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
92 dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);
95 static int dwmci_set_transfer_mode(struct dwmci_host *host,
96 struct mmc_data *data)
100 mode = DWMCI_CMD_DATA_EXP;
101 if (data->flags & MMC_DATA_WRITE)
102 mode |= DWMCI_CMD_RW;
107 static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
108 struct mmc_data *data)
110 struct dwmci_host *host = mmc->priv;
111 ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac,
112 data ? DIV_ROUND_UP(data->blocks, 8) : 0);
114 unsigned int timeout = 100000;
117 ulong start = get_timer(0);
118 struct bounce_buffer bbstate;
120 while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
121 if (get_timer(start) > timeout) {
122 printf("Timeout on data busy\n");
127 dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);
130 if (data->flags == MMC_DATA_READ) {
131 bounce_buffer_start(&bbstate, (void*)data->dest,
133 data->blocks, GEN_BB_WRITE);
135 bounce_buffer_start(&bbstate, (void*)data->src,
137 data->blocks, GEN_BB_READ);
139 dwmci_prepare_data(host, data, cur_idmac,
140 bbstate.bounce_buffer);
143 dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
146 flags = dwmci_set_transfer_mode(host, data);
148 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
151 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
152 flags |= DWMCI_CMD_ABORT_STOP;
154 flags |= DWMCI_CMD_PRV_DAT_WAIT;
156 if (cmd->resp_type & MMC_RSP_PRESENT) {
157 flags |= DWMCI_CMD_RESP_EXP;
158 if (cmd->resp_type & MMC_RSP_136)
159 flags |= DWMCI_CMD_RESP_LENGTH;
162 if (cmd->resp_type & MMC_RSP_CRC)
163 flags |= DWMCI_CMD_CHECK_CRC;
165 flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG);
167 debug("Sending CMD%d\n",cmd->cmdidx);
169 dwmci_writel(host, DWMCI_CMD, flags);
171 for (i = 0; i < retry; i++) {
172 mask = dwmci_readl(host, DWMCI_RINTSTS);
173 if (mask & DWMCI_INTMSK_CDONE) {
175 dwmci_writel(host, DWMCI_RINTSTS, mask);
183 if (mask & DWMCI_INTMSK_RTO) {
184 debug("Response Timeout..\n");
186 } else if (mask & DWMCI_INTMSK_RE) {
187 debug("Response Error..\n");
192 if (cmd->resp_type & MMC_RSP_PRESENT) {
193 if (cmd->resp_type & MMC_RSP_136) {
194 cmd->response[0] = dwmci_readl(host, DWMCI_RESP3);
195 cmd->response[1] = dwmci_readl(host, DWMCI_RESP2);
196 cmd->response[2] = dwmci_readl(host, DWMCI_RESP1);
197 cmd->response[3] = dwmci_readl(host, DWMCI_RESP0);
199 cmd->response[0] = dwmci_readl(host, DWMCI_RESP0);
205 mask = dwmci_readl(host, DWMCI_RINTSTS);
206 if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
207 debug("DATA ERROR!\n");
210 } while (!(mask & DWMCI_INTMSK_DTO));
212 dwmci_writel(host, DWMCI_RINTSTS, mask);
214 ctrl = dwmci_readl(host, DWMCI_CTRL);
215 ctrl &= ~(DWMCI_DMA_EN);
216 dwmci_writel(host, DWMCI_CTRL, ctrl);
218 bounce_buffer_stop(&bbstate);
226 static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
232 if ((freq == host->clock) || (freq == 0))
235 * If host->get_mmc_clk didn't define,
236 * then assume that host->bus_hz is source clock value.
237 * host->bus_hz should be set from user.
239 if (host->get_mmc_clk)
240 sclk = host->get_mmc_clk(host);
241 else if (host->bus_hz)
244 printf("Didn't get source clock value..\n");
249 div = 0; /* bypass mode */
251 div = DIV_ROUND_UP(sclk, 2 * freq);
253 dwmci_writel(host, DWMCI_CLKENA, 0);
254 dwmci_writel(host, DWMCI_CLKSRC, 0);
256 dwmci_writel(host, DWMCI_CLKDIV, div);
257 dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
258 DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
261 status = dwmci_readl(host, DWMCI_CMD);
263 printf("TIMEOUT error!!\n");
266 } while (status & DWMCI_CMD_START);
268 dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE |
269 DWMCI_CLKEN_LOW_PWR);
271 dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
272 DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
276 status = dwmci_readl(host, DWMCI_CMD);
278 printf("TIMEOUT error!!\n");
281 } while (status & DWMCI_CMD_START);
288 static void dwmci_set_ios(struct mmc *mmc)
290 struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
293 debug("Buswidth = %d, clock: %d\n",mmc->bus_width, mmc->clock);
295 dwmci_setup_bus(host, mmc->clock);
296 switch (mmc->bus_width) {
298 ctype = DWMCI_CTYPE_8BIT;
301 ctype = DWMCI_CTYPE_4BIT;
304 ctype = DWMCI_CTYPE_1BIT;
308 dwmci_writel(host, DWMCI_CTYPE, ctype);
310 regs = dwmci_readl(host, DWMCI_UHS_REG);
311 if (mmc->card_caps & MMC_MODE_DDR_52MHz)
312 regs |= DWMCI_DDR_MODE;
314 regs &= DWMCI_DDR_MODE;
316 dwmci_writel(host, DWMCI_UHS_REG, regs);
322 static int dwmci_init(struct mmc *mmc)
324 struct dwmci_host *host = mmc->priv;
326 if (host->board_init)
327 host->board_init(host);
329 dwmci_writel(host, DWMCI_PWREN, 1);
331 if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
332 debug("%s[%d] Fail-reset!!\n",__func__,__LINE__);
336 /* Enumerate at 400KHz */
337 dwmci_setup_bus(host, mmc->cfg->f_min);
339 dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
340 dwmci_writel(host, DWMCI_INTMASK, 0);
342 dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF);
344 dwmci_writel(host, DWMCI_IDINTEN, 0);
345 dwmci_writel(host, DWMCI_BMOD, 1);
347 if (host->fifoth_val) {
348 dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
351 dwmci_writel(host, DWMCI_CLKENA, 0);
352 dwmci_writel(host, DWMCI_CLKSRC, 0);
357 static const struct mmc_ops dwmci_ops = {
358 .send_cmd = dwmci_send_cmd,
359 .set_ios = dwmci_set_ios,
363 int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
365 host->cfg.name = host->name;
366 host->cfg.ops = &dwmci_ops;
367 host->cfg.f_min = min_clk;
368 host->cfg.f_max = max_clk;
370 host->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
372 host->cfg.host_caps = host->caps;
374 if (host->buswidth == 8) {
375 host->cfg.host_caps |= MMC_MODE_8BIT;
376 host->cfg.host_caps &= ~MMC_MODE_4BIT;
378 host->cfg.host_caps |= MMC_MODE_4BIT;
379 host->cfg.host_caps &= ~MMC_MODE_8BIT;
381 host->cfg.host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_HC;
383 host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
385 host->mmc = mmc_create(&host->cfg, host);
386 if (host->mmc == NULL)