drivers/mmc/ca_dw_mmc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2019 Cortina Access
   4  * Arthur Li <arthur.li@cortina-access.com>
   5  */
   6
   7 #include <common.h>
   8 #include <dwmmc.h>
   9 #include <fdtdec.h>
  10 #include <linux/libfdt.h>
  11 #include <malloc.h>
  12 #include <errno.h>
  13 #include <dm.h>
  14 #include <mapmem.h>
  15
  16 #define SD_CLK_SEL_MASK (0x3)
  17 #define SD_DLL_DEFAULT  (0x143000)
  18 #define SD_SCLK_MAX (200000000)
  19
  20 #define SD_CLK_SEL_200MHZ (0x2)
  21 #define SD_CLK_SEL_100MHZ (0x1)
  22
  23 #define IO_DRV_SD_DS_OFFSET (16)
  24 #define IO_DRV_SD_DS_MASK   (0xff << IO_DRV_SD_DS_OFFSET)
  25
  26 #define MIN_FREQ (400000)
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 struct ca_mmc_plat {
  31         struct mmc_config cfg;
  32         struct mmc mmc;
  33 };
  34
  35 struct ca_dwmmc_priv_data {
  36         struct dwmci_host host;
  37         void __iomem *sd_dll_reg;
  38         void __iomem *io_drv_reg;
  39         u8 ds;
  40 };
  41
  42 static void ca_dwmci_clksel(struct dwmci_host *host)
  43 {
  44         struct ca_dwmmc_priv_data *priv = host->priv;
  45         u32 val = readl(priv->sd_dll_reg);
  46
  47         if (host->bus_hz >= 200000000) {
  48                 val &= ~SD_CLK_SEL_MASK;
  49                 val |= SD_CLK_SEL_200MHZ;
  50         } else if (host->bus_hz >= 100000000) {
  51                 val &= ~SD_CLK_SEL_MASK;
  52                 val |= SD_CLK_SEL_100MHZ;
  53         } else {
  54                 val &= ~SD_CLK_SEL_MASK;
  55         }
  56
  57         writel(val, priv->sd_dll_reg);
  58 }
  59
  60 static void ca_dwmci_board_init(struct dwmci_host *host)
  61 {
  62         struct ca_dwmmc_priv_data *priv = host->priv;
  63         u32 val = readl(priv->io_drv_reg);
  64
  65         writel(SD_DLL_DEFAULT, priv->sd_dll_reg);
  66
  67         val &= ~IO_DRV_SD_DS_MASK;
  68         if (priv && priv->ds)
  69                 val |= priv->ds << IO_DRV_SD_DS_OFFSET;
  70         writel(val, priv->io_drv_reg);
  71 }
  72
  73 unsigned int ca_dwmci_get_mmc_clock(struct dwmci_host *host, uint freq)
  74 {
  75         struct ca_dwmmc_priv_data *priv = host->priv;
  76         u8 sd_clk_sel = readl(priv->sd_dll_reg) & SD_CLK_SEL_MASK;
  77         u8 clk_div;
  78
  79         switch (sd_clk_sel) {
  80         case 2:
  81                 clk_div = 1;
  82                 break;
  83         case 1:
  84                 clk_div = 2;
  85                 break;
  86         default:
  87                 clk_div = 4;
  88         }
  89
  90         return SD_SCLK_MAX / clk_div / (host->div + 1);
  91 }
  92
  93 static int ca_dwmmc_ofdata_to_platdata(struct udevice *dev)
  94 {
  95         struct ca_dwmmc_priv_data *priv = dev_get_priv(dev);
  96         struct dwmci_host *host = &priv->host;
  97         u32 tmp;
  98
  99         host->name = dev->name;
 100         host->dev_index = 0;
 101
 102         host->buswidth = dev_read_u32_default(dev, "bus-width", 1);
 103         if (host->buswidth != 1 && host->buswidth != 4)
 104                 return -EINVAL;
 105
 106         host->bus_hz = dev_read_u32_default(dev, "max-frequency", 50000000);
 107         priv->ds = dev_read_u32_default(dev, "io_ds", 0x33);
 108         host->fifo_mode = dev_read_bool(dev, "fifo-mode");
 109
 110         dev_read_u32(dev, "sd_dll_ctrl", &tmp);
 111         priv->sd_dll_reg = map_sysmem((uintptr_t)tmp, sizeof(uintptr_t));
 112         if (!priv->sd_dll_reg)
 113                 return -EINVAL;
 114
 115         dev_read_u32(dev, "io_drv_ctrl", &tmp);
 116         priv->io_drv_reg = map_sysmem((uintptr_t)tmp, sizeof(uintptr_t));
 117         if (!priv->io_drv_reg)
 118                 return -EINVAL;
 119
 120         host->ioaddr = dev_read_addr_ptr(dev);
 121         if (host->ioaddr == (void *)FDT_ADDR_T_NONE) {
 122                 printf("DWMMC: base address is invalid\n");
 123                 return -EINVAL;
 124         }
 125
 126         host->priv = priv;
 127
 128         return 0;
 129 }
 130
 131 struct dm_mmc_ops ca_dwmci_dm_ops;
 132
 133 static int ca_dwmmc_probe(struct udevice *dev)
 134 {
 135         struct ca_mmc_plat *plat = dev_get_platdata(dev);
 136         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 137         struct ca_dwmmc_priv_data *priv = dev_get_priv(dev);
 138         struct dwmci_host *host = &priv->host;
 139
 140         memcpy(&ca_dwmci_dm_ops, &dm_dwmci_ops, sizeof(struct dm_mmc_ops));
 141
 142         dwmci_setup_cfg(&plat->cfg, host, host->bus_hz, MIN_FREQ);
 143         if (host->buswidth == 1) {
 144                 (&plat->cfg)->host_caps &= ~MMC_MODE_8BIT;
 145                 (&plat->cfg)->host_caps &= ~MMC_MODE_4BIT;
 146         }
 147
 148         host->mmc = &plat->mmc;
 149         host->mmc->priv = &priv->host;
 150         upriv->mmc = host->mmc;
 151         host->mmc->dev = dev;
 152         host->clksel = ca_dwmci_clksel;
 153         host->board_init = ca_dwmci_board_init;
 154         host->get_mmc_clk = ca_dwmci_get_mmc_clock;
 155
 156         return dwmci_probe(dev);
 157 }
 158
 159 static int ca_dwmmc_bind(struct udevice *dev)
 160 {
 161         struct ca_mmc_plat *plat = dev_get_platdata(dev);
 162
 163         return dwmci_bind(dev, &plat->mmc, &plat->cfg);
 164 }
 165
 166 static const struct udevice_id ca_dwmmc_ids[] = {
 167         { .compatible = "snps,dw-cortina" },
 168         { }
 169 };
 170
 171 U_BOOT_DRIVER(ca_dwmmc_drv) = {
 172         .name           = "cortina_dwmmc",
 173         .id             = UCLASS_MMC,
 174         .of_match       = ca_dwmmc_ids,
 175         .ofdata_to_platdata = ca_dwmmc_ofdata_to_platdata,
 176         .bind           = ca_dwmmc_bind,
 177         .ops            = &ca_dwmci_dm_ops,
 178         .probe          = ca_dwmmc_probe,
 179         .priv_auto_alloc_size   = sizeof(struct ca_dwmmc_priv_data),
 180         .platdata_auto_alloc_size = sizeof(struct ca_mmc_plat),
 181 };