1 // SPDX-License-Identifier: GPL-2.0
3 * bcm2835 sdhost driver.
5 * The 2835 has two SD controllers: The Arasan sdhci controller
6 * (supported by the iproc driver) and a custom sdhost controller
7 * (supported by this driver).
9 * The sdhci controller supports both sdcard and sdio. The sdhost
10 * controller supports the sdcard only, but has better performance.
11 * Also note that the rpi3 has sdio wifi, so driving the sdcard with
12 * the sdhost controller allows to use the sdhci controller for wifi
15 * The configuration is done by devicetree via pin muxing. Both
16 * SD controller are available on the same pins (2 pin groups = pin 22
17 * to 27 + pin 48 to 53). So it's possible to use both SD controllers
18 * at the same time with different pin groups.
20 * This code was ported to U-Boot by
21 * Alexander Graf <agraf@suse.de>
22 * and is based on drivers/mmc/host/bcm2835.c in Linux which is written by
23 * Phil Elwell <phil@raspberrypi.org>
24 * Copyright (C) 2015-2016 Raspberry Pi (Trading) Ltd.
26 * mmc-bcm2835.c by Gellert Weisz
27 * which is, in turn, based on
28 * sdhci-bcm2708.c by Broadcom
29 * sdhci-bcm2835.c by Stephen Warren and Oleksandr Tymoshenko
30 * sdhci.c and sdhci-pci.c by Pierre Ossman
36 #include <asm/arch/msg.h>
37 #include <asm/arch/mbox.h>
38 #include <asm/unaligned.h>
39 #include <linux/compat.h>
41 #include <linux/iopoll.h>
42 #include <linux/sizes.h>
43 #include <mach/gpio.h>
44 #include <power/regulator.h>
46 #define msleep(a) udelay(a * 1000)
48 #define SDCMD 0x00 /* Command to SD card - 16 R/W */
49 #define SDARG 0x04 /* Argument to SD card - 32 R/W */
50 #define SDTOUT 0x08 /* Start value for timeout counter - 32 R/W */
51 #define SDCDIV 0x0c /* Start value for clock divider - 11 R/W */
52 #define SDRSP0 0x10 /* SD card response (31:0) - 32 R */
53 #define SDRSP1 0x14 /* SD card response (63:32) - 32 R */
54 #define SDRSP2 0x18 /* SD card response (95:64) - 32 R */
55 #define SDRSP3 0x1c /* SD card response (127:96) - 32 R */
56 #define SDHSTS 0x20 /* SD host status - 11 R/W */
57 #define SDVDD 0x30 /* SD card power control - 1 R/W */
58 #define SDEDM 0x34 /* Emergency Debug Mode - 13 R/W */
59 #define SDHCFG 0x38 /* Host configuration - 2 R/W */
60 #define SDHBCT 0x3c /* Host byte count (debug) - 32 R/W */
61 #define SDDATA 0x40 /* Data to/from SD card - 32 R/W */
62 #define SDHBLC 0x50 /* Host block count (SDIO/SDHC) - 9 R/W */
64 #define SDCMD_NEW_FLAG 0x8000
65 #define SDCMD_FAIL_FLAG 0x4000
66 #define SDCMD_BUSYWAIT 0x800
67 #define SDCMD_NO_RESPONSE 0x400
68 #define SDCMD_LONG_RESPONSE 0x200
69 #define SDCMD_WRITE_CMD 0x80
70 #define SDCMD_READ_CMD 0x40
71 #define SDCMD_CMD_MASK 0x3f
73 #define SDCDIV_MAX_CDIV 0x7ff
75 #define SDHSTS_BUSY_IRPT 0x400
76 #define SDHSTS_BLOCK_IRPT 0x200
77 #define SDHSTS_SDIO_IRPT 0x100
78 #define SDHSTS_REW_TIME_OUT 0x80
79 #define SDHSTS_CMD_TIME_OUT 0x40
80 #define SDHSTS_CRC16_ERROR 0x20
81 #define SDHSTS_CRC7_ERROR 0x10
82 #define SDHSTS_FIFO_ERROR 0x08
83 #define SDHSTS_DATA_FLAG 0x01
85 #define SDHSTS_CLEAR_MASK (SDHSTS_BUSY_IRPT | \
88 SDHSTS_REW_TIME_OUT | \
89 SDHSTS_CMD_TIME_OUT | \
90 SDHSTS_CRC16_ERROR | \
94 #define SDHSTS_TRANSFER_ERROR_MASK (SDHSTS_CRC7_ERROR | \
95 SDHSTS_CRC16_ERROR | \
96 SDHSTS_REW_TIME_OUT | \
99 #define SDHSTS_ERROR_MASK (SDHSTS_CMD_TIME_OUT | \
100 SDHSTS_TRANSFER_ERROR_MASK)
102 #define SDHCFG_BUSY_IRPT_EN BIT(10)
103 #define SDHCFG_BLOCK_IRPT_EN BIT(8)
104 #define SDHCFG_SDIO_IRPT_EN BIT(5)
105 #define SDHCFG_DATA_IRPT_EN BIT(4)
106 #define SDHCFG_SLOW_CARD BIT(3)
107 #define SDHCFG_WIDE_EXT_BUS BIT(2)
108 #define SDHCFG_WIDE_INT_BUS BIT(1)
109 #define SDHCFG_REL_CMD_LINE BIT(0)
111 #define SDVDD_POWER_OFF 0
112 #define SDVDD_POWER_ON 1
114 #define SDEDM_FORCE_DATA_MODE BIT(19)
115 #define SDEDM_CLOCK_PULSE BIT(20)
116 #define SDEDM_BYPASS BIT(21)
118 #define SDEDM_FIFO_FILL_SHIFT 4
119 #define SDEDM_FIFO_FILL_MASK 0x1f
120 static u32 edm_fifo_fill(u32 edm)
122 return (edm >> SDEDM_FIFO_FILL_SHIFT) & SDEDM_FIFO_FILL_MASK;
125 #define SDEDM_WRITE_THRESHOLD_SHIFT 9
126 #define SDEDM_READ_THRESHOLD_SHIFT 14
127 #define SDEDM_THRESHOLD_MASK 0x1f
129 #define SDEDM_FSM_MASK 0xf
130 #define SDEDM_FSM_IDENTMODE 0x0
131 #define SDEDM_FSM_DATAMODE 0x1
132 #define SDEDM_FSM_READDATA 0x2
133 #define SDEDM_FSM_WRITEDATA 0x3
134 #define SDEDM_FSM_READWAIT 0x4
135 #define SDEDM_FSM_READCRC 0x5
136 #define SDEDM_FSM_WRITECRC 0x6
137 #define SDEDM_FSM_WRITEWAIT1 0x7
138 #define SDEDM_FSM_POWERDOWN 0x8
139 #define SDEDM_FSM_POWERUP 0x9
140 #define SDEDM_FSM_WRITESTART1 0xa
141 #define SDEDM_FSM_WRITESTART2 0xb
142 #define SDEDM_FSM_GENPULSES 0xc
143 #define SDEDM_FSM_WRITEWAIT2 0xd
144 #define SDEDM_FSM_STARTPOWDOWN 0xf
146 #define SDDATA_FIFO_WORDS 16
148 #define FIFO_READ_THRESHOLD 4
149 #define FIFO_WRITE_THRESHOLD 4
150 #define SDDATA_FIFO_PIO_BURST 8
152 #define SDHST_TIMEOUT_MAX_USEC 100000
154 struct bcm2835_plat {
155 struct mmc_config cfg;
159 struct bcm2835_host {
160 void __iomem *ioaddr;
163 int clock; /* Current clock speed */
164 unsigned int max_clk; /* Max possible freq */
165 unsigned int blocks; /* remaining PIO blocks */
167 u32 ns_per_fifo_word;
169 /* cached registers */
173 struct mmc_cmd *cmd; /* Current command */
174 struct mmc_data *data; /* Current data request */
175 bool use_busy:1; /* Wait for busy interrupt */
179 struct bcm2835_plat *plat;
182 static void bcm2835_dumpregs(struct bcm2835_host *host)
184 dev_dbg(dev, "=========== REGISTER DUMP ===========\n");
185 dev_dbg(dev, "SDCMD 0x%08x\n", readl(host->ioaddr + SDCMD));
186 dev_dbg(dev, "SDARG 0x%08x\n", readl(host->ioaddr + SDARG));
187 dev_dbg(dev, "SDTOUT 0x%08x\n", readl(host->ioaddr + SDTOUT));
188 dev_dbg(dev, "SDCDIV 0x%08x\n", readl(host->ioaddr + SDCDIV));
189 dev_dbg(dev, "SDRSP0 0x%08x\n", readl(host->ioaddr + SDRSP0));
190 dev_dbg(dev, "SDRSP1 0x%08x\n", readl(host->ioaddr + SDRSP1));
191 dev_dbg(dev, "SDRSP2 0x%08x\n", readl(host->ioaddr + SDRSP2));
192 dev_dbg(dev, "SDRSP3 0x%08x\n", readl(host->ioaddr + SDRSP3));
193 dev_dbg(dev, "SDHSTS 0x%08x\n", readl(host->ioaddr + SDHSTS));
194 dev_dbg(dev, "SDVDD 0x%08x\n", readl(host->ioaddr + SDVDD));
195 dev_dbg(dev, "SDEDM 0x%08x\n", readl(host->ioaddr + SDEDM));
196 dev_dbg(dev, "SDHCFG 0x%08x\n", readl(host->ioaddr + SDHCFG));
197 dev_dbg(dev, "SDHBCT 0x%08x\n", readl(host->ioaddr + SDHBCT));
198 dev_dbg(dev, "SDHBLC 0x%08x\n", readl(host->ioaddr + SDHBLC));
199 dev_dbg(dev, "===========================================\n");
202 static void bcm2835_reset_internal(struct bcm2835_host *host)
206 writel(SDVDD_POWER_OFF, host->ioaddr + SDVDD);
207 writel(0, host->ioaddr + SDCMD);
208 writel(0, host->ioaddr + SDARG);
209 /* Set timeout to a big enough value so we don't hit it */
210 writel(0xf00000, host->ioaddr + SDTOUT);
211 writel(0, host->ioaddr + SDCDIV);
212 /* Clear status register */
213 writel(SDHSTS_CLEAR_MASK, host->ioaddr + SDHSTS);
214 writel(0, host->ioaddr + SDHCFG);
215 writel(0, host->ioaddr + SDHBCT);
216 writel(0, host->ioaddr + SDHBLC);
218 /* Limit fifo usage due to silicon bug */
219 temp = readl(host->ioaddr + SDEDM);
220 temp &= ~((SDEDM_THRESHOLD_MASK << SDEDM_READ_THRESHOLD_SHIFT) |
221 (SDEDM_THRESHOLD_MASK << SDEDM_WRITE_THRESHOLD_SHIFT));
222 temp |= (FIFO_READ_THRESHOLD << SDEDM_READ_THRESHOLD_SHIFT) |
223 (FIFO_WRITE_THRESHOLD << SDEDM_WRITE_THRESHOLD_SHIFT);
224 writel(temp, host->ioaddr + SDEDM);
225 /* Wait for FIFO threshold to populate */
227 writel(SDVDD_POWER_ON, host->ioaddr + SDVDD);
228 /* Wait for all components to go through power on cycle */
231 writel(host->hcfg, host->ioaddr + SDHCFG);
232 writel(host->cdiv, host->ioaddr + SDCDIV);
235 static int bcm2835_wait_transfer_complete(struct bcm2835_host *host)
237 ulong tstart_ms = get_timer(0);
242 edm = readl(host->ioaddr + SDEDM);
243 fsm = edm & SDEDM_FSM_MASK;
245 if ((fsm == SDEDM_FSM_IDENTMODE) ||
246 (fsm == SDEDM_FSM_DATAMODE))
249 if ((fsm == SDEDM_FSM_READWAIT) ||
250 (fsm == SDEDM_FSM_WRITESTART1) ||
251 (fsm == SDEDM_FSM_READDATA)) {
252 writel(edm | SDEDM_FORCE_DATA_MODE,
253 host->ioaddr + SDEDM);
257 /* Error out after ~1s */
258 ulong tlapse_ms = get_timer(tstart_ms);
259 if ( tlapse_ms > 1000 /* ms */ ) {
262 "wait_transfer_complete - still waiting after %lu ms\n",
264 bcm2835_dumpregs(host);
272 static int bcm2835_transfer_block_pio(struct bcm2835_host *host, bool is_read)
274 struct mmc_data *data = host->data;
275 size_t blksize = data->blocksize;
280 if (blksize % sizeof(u32))
283 buf = is_read ? (u32 *)data->dest : (u32 *)data->src;
286 data->dest += blksize;
288 data->src += blksize;
290 copy_words = blksize / sizeof(u32);
293 * Copy all contents from/to the FIFO as far as it reaches,
294 * then wait for it to fill/empty again and rewind.
297 int burst_words, words;
300 burst_words = min(SDDATA_FIFO_PIO_BURST, copy_words);
301 edm = readl(host->ioaddr + SDEDM);
303 words = edm_fifo_fill(edm);
305 words = SDDATA_FIFO_WORDS - edm_fifo_fill(edm);
307 if (words < burst_words) {
308 int fsm_state = (edm & SDEDM_FSM_MASK);
311 (fsm_state != SDEDM_FSM_READDATA &&
312 fsm_state != SDEDM_FSM_READWAIT &&
313 fsm_state != SDEDM_FSM_READCRC)) ||
315 (fsm_state != SDEDM_FSM_WRITEDATA &&
316 fsm_state != SDEDM_FSM_WRITEWAIT1 &&
317 fsm_state != SDEDM_FSM_WRITEWAIT2 &&
318 fsm_state != SDEDM_FSM_WRITECRC &&
319 fsm_state != SDEDM_FSM_WRITESTART1 &&
320 fsm_state != SDEDM_FSM_WRITESTART2))) {
321 hsts = readl(host->ioaddr + SDHSTS);
322 printf("fsm %x, hsts %08x\n", fsm_state, hsts);
323 if (hsts & SDHSTS_ERROR_MASK)
328 } else if (words > copy_words) {
334 /* Copy current chunk to/from the FIFO */
337 *(buf++) = readl(host->ioaddr + SDDATA);
339 writel(*(buf++), host->ioaddr + SDDATA);
347 static int bcm2835_transfer_pio(struct bcm2835_host *host)
353 is_read = (host->data->flags & MMC_DATA_READ) != 0;
354 ret = bcm2835_transfer_block_pio(host, is_read);
358 sdhsts = readl(host->ioaddr + SDHSTS);
359 if (sdhsts & (SDHSTS_CRC16_ERROR |
361 SDHSTS_FIFO_ERROR)) {
362 printf("%s transfer error - HSTS %08x\n",
363 is_read ? "read" : "write", sdhsts);
365 } else if ((sdhsts & (SDHSTS_CMD_TIME_OUT |
366 SDHSTS_REW_TIME_OUT))) {
367 printf("%s timeout error - HSTS %08x\n",
368 is_read ? "read" : "write", sdhsts);
375 static void bcm2835_prepare_data(struct bcm2835_host *host, struct mmc_cmd *cmd,
376 struct mmc_data *data)
385 host->blocks = data->blocks;
387 writel(data->blocksize, host->ioaddr + SDHBCT);
388 writel(data->blocks, host->ioaddr + SDHBLC);
391 static u32 bcm2835_read_wait_sdcmd(struct bcm2835_host *host)
395 int timeout_us = SDHST_TIMEOUT_MAX_USEC;
397 ret = readl_poll_timeout(host->ioaddr + SDCMD, value,
398 !(value & SDCMD_NEW_FLAG), timeout_us);
399 if (ret == -ETIMEDOUT)
400 printf("%s: timeout (%d us)\n", __func__, timeout_us);
405 static int bcm2835_send_command(struct bcm2835_host *host, struct mmc_cmd *cmd,
406 struct mmc_data *data)
412 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) {
413 printf("unsupported response type!\n");
417 sdcmd = bcm2835_read_wait_sdcmd(host);
418 if (sdcmd & SDCMD_NEW_FLAG) {
419 printf("previous command never completed.\n");
420 bcm2835_dumpregs(host);
426 /* Clear any error flags */
427 sdhsts = readl(host->ioaddr + SDHSTS);
428 if (sdhsts & SDHSTS_ERROR_MASK)
429 writel(sdhsts, host->ioaddr + SDHSTS);
431 bcm2835_prepare_data(host, cmd, data);
433 writel(cmd->cmdarg, host->ioaddr + SDARG);
435 sdcmd = cmd->cmdidx & SDCMD_CMD_MASK;
437 host->use_busy = false;
438 if (!(cmd->resp_type & MMC_RSP_PRESENT)) {
439 sdcmd |= SDCMD_NO_RESPONSE;
441 if (cmd->resp_type & MMC_RSP_136)
442 sdcmd |= SDCMD_LONG_RESPONSE;
443 if (cmd->resp_type & MMC_RSP_BUSY) {
444 sdcmd |= SDCMD_BUSYWAIT;
445 host->use_busy = true;
450 if (data->flags & MMC_DATA_WRITE)
451 sdcmd |= SDCMD_WRITE_CMD;
452 if (data->flags & MMC_DATA_READ)
453 sdcmd |= SDCMD_READ_CMD;
456 writel(sdcmd | SDCMD_NEW_FLAG, host->ioaddr + SDCMD);
461 static int bcm2835_finish_command(struct bcm2835_host *host)
463 struct mmc_cmd *cmd = host->cmd;
467 sdcmd = bcm2835_read_wait_sdcmd(host);
469 /* Check for errors */
470 if (sdcmd & SDCMD_NEW_FLAG) {
471 printf("command never completed.\n");
472 bcm2835_dumpregs(host);
474 } else if (sdcmd & SDCMD_FAIL_FLAG) {
475 u32 sdhsts = readl(host->ioaddr + SDHSTS);
477 /* Clear the errors */
478 writel(SDHSTS_ERROR_MASK, host->ioaddr + SDHSTS);
480 if (!(sdhsts & SDHSTS_CRC7_ERROR) ||
481 (host->cmd->cmdidx != MMC_CMD_SEND_OP_COND)) {
482 if (sdhsts & SDHSTS_CMD_TIME_OUT) {
485 printf("unexpected command %d error\n",
487 bcm2835_dumpregs(host);
495 if (cmd->resp_type & MMC_RSP_PRESENT) {
496 if (cmd->resp_type & MMC_RSP_136) {
499 for (i = 0; i < 4; i++) {
500 cmd->response[3 - i] =
501 readl(host->ioaddr + SDRSP0 + i * 4);
504 cmd->response[0] = readl(host->ioaddr + SDRSP0);
508 /* Processed actual command. */
514 static int bcm2835_check_cmd_error(struct bcm2835_host *host, u32 intmask)
518 if (!(intmask & SDHSTS_ERROR_MASK))
524 printf("sdhost_busy_irq: intmask %08x\n", intmask);
525 if (intmask & SDHSTS_CRC7_ERROR) {
527 } else if (intmask & (SDHSTS_CRC16_ERROR |
528 SDHSTS_FIFO_ERROR)) {
530 } else if (intmask & (SDHSTS_REW_TIME_OUT | SDHSTS_CMD_TIME_OUT)) {
533 bcm2835_dumpregs(host);
537 static int bcm2835_check_data_error(struct bcm2835_host *host, u32 intmask)
543 if (intmask & (SDHSTS_CRC16_ERROR | SDHSTS_FIFO_ERROR))
545 if (intmask & SDHSTS_REW_TIME_OUT)
549 printf("%s:%d %d\n", __func__, __LINE__, ret);
554 static int bcm2835_transmit(struct bcm2835_host *host)
556 u32 intmask = readl(host->ioaddr + SDHSTS);
559 /* Check for errors */
560 ret = bcm2835_check_data_error(host, intmask);
564 ret = bcm2835_check_cmd_error(host, intmask);
568 /* Handle wait for busy end */
569 if (host->use_busy && (intmask & SDHSTS_BUSY_IRPT)) {
570 writel(SDHSTS_BUSY_IRPT, host->ioaddr + SDHSTS);
571 host->use_busy = false;
572 bcm2835_finish_command(host);
575 /* Handle PIO data transfer */
577 ret = bcm2835_transfer_pio(host);
581 if (host->blocks == 0) {
582 /* Wait for command to complete for real */
583 ret = bcm2835_wait_transfer_complete(host);
586 /* Transfer complete */
594 static void bcm2835_set_clock(struct bcm2835_host *host, unsigned int clock)
598 /* The SDCDIV register has 11 bits, and holds (div - 2). But
599 * in data mode the max is 50MHz wihout a minimum, and only
600 * the bottom 3 bits are used. Since the switch over is
601 * automatic (unless we have marked the card as slow...),
602 * chosen values have to make sense in both modes. Ident mode
603 * must be 100-400KHz, so can range check the requested
604 * clock. CMD15 must be used to return to data mode, so this
607 * clock 250MHz -> 0->125MHz, 1->83.3MHz, 2->62.5MHz, 3->50.0MHz
608 * 4->41.7MHz, 5->35.7MHz, 6->31.3MHz, 7->27.8MHz
610 * 623->400KHz/27.8MHz
611 * reset value (507)->491159/50MHz
613 * BUT, the 3-bit clock divisor in data mode is too small if
614 * the core clock is higher than 250MHz, so instead use the
615 * SLOW_CARD configuration bit to force the use of the ident
616 * clock divisor at all times.
619 if (clock < 100000) {
620 /* Can't stop the clock, but make it as slow as possible
623 host->cdiv = SDCDIV_MAX_CDIV;
624 writel(host->cdiv, host->ioaddr + SDCDIV);
628 div = host->max_clk / clock;
631 if ((host->max_clk / div) > clock)
635 if (div > SDCDIV_MAX_CDIV)
636 div = SDCDIV_MAX_CDIV;
638 clock = host->max_clk / (div + 2);
639 host->mmc->clock = clock;
641 /* Calibrate some delays */
643 host->ns_per_fifo_word = (1000000000 / clock) *
644 ((host->mmc->card_caps & MMC_MODE_4BIT) ? 8 : 32);
647 writel(host->cdiv, host->ioaddr + SDCDIV);
649 /* Set the timeout to 500ms */
650 writel(host->mmc->clock / 2, host->ioaddr + SDTOUT);
653 static inline int is_power_of_2(u64 x)
655 return !(x & (x - 1));
658 static int bcm2835_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
659 struct mmc_data *data)
661 struct bcm2835_host *host = dev_get_priv(dev);
665 if (data && !is_power_of_2(data->blocksize)) {
666 printf("unsupported block size (%d bytes)\n", data->blocksize);
672 edm = readl(host->ioaddr + SDEDM);
673 fsm = edm & SDEDM_FSM_MASK;
675 if ((fsm != SDEDM_FSM_IDENTMODE) &&
676 (fsm != SDEDM_FSM_DATAMODE) &&
677 (cmd && cmd->cmdidx != MMC_CMD_STOP_TRANSMISSION)) {
678 printf("previous command (%d) not complete (EDM %08x)\n",
679 readl(host->ioaddr + SDCMD) & SDCMD_CMD_MASK, edm);
680 bcm2835_dumpregs(host);
689 ret = bcm2835_send_command(host, cmd, data);
690 if (!ret && !host->use_busy)
691 ret = bcm2835_finish_command(host);
694 /* Wait for completion of busy signal or data transfer */
695 while (host->use_busy || host->data) {
696 ret = bcm2835_transmit(host);
704 static int bcm2835_set_ios(struct udevice *dev)
706 struct bcm2835_host *host = dev_get_priv(dev);
707 struct mmc *mmc = mmc_get_mmc_dev(dev);
709 if (!mmc->clock || mmc->clock != host->clock) {
710 bcm2835_set_clock(host, mmc->clock);
711 host->clock = mmc->clock;
715 host->hcfg &= ~SDHCFG_WIDE_EXT_BUS;
716 if (mmc->bus_width == 4)
717 host->hcfg |= SDHCFG_WIDE_EXT_BUS;
719 host->hcfg |= SDHCFG_WIDE_INT_BUS;
721 /* Disable clever clock switching, to cope with fast core clocks */
722 host->hcfg |= SDHCFG_SLOW_CARD;
724 writel(host->hcfg, host->ioaddr + SDHCFG);
729 static void bcm2835_add_host(struct bcm2835_host *host)
731 struct mmc_config *cfg = &host->plat->cfg;
733 cfg->f_max = host->max_clk;
734 cfg->f_min = host->max_clk / SDCDIV_MAX_CDIV;
737 dev_dbg(dev, "f_max %d, f_min %d\n",
738 cfg->f_max, cfg->f_min);
740 /* host controller capabilities */
741 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_HS | MMC_MODE_HS_52MHz;
743 /* report supported voltage ranges */
744 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
746 /* Set interrupt enables */
747 host->hcfg = SDHCFG_BUSY_IRPT_EN;
749 bcm2835_reset_internal(host);
752 static int bcm2835_probe(struct udevice *dev)
754 struct bcm2835_plat *plat = dev_get_platdata(dev);
755 struct bcm2835_host *host = dev_get_priv(dev);
756 struct mmc *mmc = mmc_get_mmc_dev(dev);
757 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
762 upriv->mmc = &plat->mmc;
763 plat->cfg.name = dev->name;
765 host->phys_addr = devfdt_get_addr(dev);
766 if (host->phys_addr == FDT_ADDR_T_NONE)
769 host->ioaddr = devm_ioremap(dev, host->phys_addr, SZ_256);
773 host->max_clk = bcm2835_get_mmc_clock(BCM2835_MBOX_CLOCK_ID_CORE);
775 bcm2835_add_host(host);
777 dev_dbg(dev, "%s -> OK\n", __func__);
782 static const struct udevice_id bcm2835_match[] = {
783 { .compatible = "brcm,bcm2835-sdhost" },
787 static const struct dm_mmc_ops bcm2835_ops = {
788 .send_cmd = bcm2835_send_cmd,
789 .set_ios = bcm2835_set_ios,
792 static int bcm2835_bind(struct udevice *dev)
794 struct bcm2835_plat *plat = dev_get_platdata(dev);
796 return mmc_bind(dev, &plat->mmc, &plat->cfg);
799 U_BOOT_DRIVER(bcm2835_sdhost) = {
800 .name = "bcm2835-sdhost",
802 .of_match = bcm2835_match,
803 .bind = bcm2835_bind,
804 .probe = bcm2835_probe,
805 .priv_auto_alloc_size = sizeof(struct bcm2835_host),
806 .platdata_auto_alloc_size = sizeof(struct bcm2835_plat),