1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015 Atmel Corporation
4 * Wenyou.Yang <wenyou.yang@atmel.com>
12 #include <asm/arch/clk.h>
13 #include <asm/global_data.h>
15 #define ATMEL_SDHC_MIN_FREQ 400000
16 #define ATMEL_SDHC_GCK_RATE 240000000
18 #define ATMEL_SDHC_MC1R 0x204
19 #define ATMEL_SDHC_MC1R_FCD 0x80
22 int atmel_sdhci_init(void *regbase, u32 id)
24 struct sdhci_host *host;
25 u32 max_clk, min_clk = ATMEL_SDHC_MIN_FREQ;
27 host = (struct sdhci_host *)calloc(1, sizeof(struct sdhci_host));
29 printf("%s: sdhci_host calloc failed\n", __func__);
33 host->name = "atmel_sdhci";
34 host->ioaddr = regbase;
35 host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
36 max_clk = at91_get_periph_generated_clk(id);
38 printf("%s: Failed to get the proper clock\n", __func__);
42 host->max_clk = max_clk;
44 add_sdhci(host, 0, min_clk);
51 DECLARE_GLOBAL_DATA_PTR;
53 struct atmel_sdhci_plat {
54 struct mmc_config cfg;
58 static void atmel_sdhci_config_fcd(struct sdhci_host *host)
62 /* If nonremovable, assume that the card is always present.
64 * WA: SAMA5D2 doesn't drive CMD if using CD GPIO line.
66 if ((host->mmc->cfg->host_caps & MMC_CAP_NONREMOVABLE)
67 #if CONFIG_IS_ENABLED(DM_GPIO)
68 || dm_gpio_get_value(&host->cd_gpio) >= 0
71 sdhci_readb(host, ATMEL_SDHC_MC1R);
72 mc1r |= ATMEL_SDHC_MC1R_FCD;
73 sdhci_writeb(host, mc1r, ATMEL_SDHC_MC1R);
77 static int atmel_sdhci_deferred_probe(struct sdhci_host *host)
79 struct udevice *dev = host->mmc->dev;
82 ret = sdhci_probe(dev);
86 atmel_sdhci_config_fcd(host);
91 static const struct sdhci_ops atmel_sdhci_ops = {
92 .deferred_probe = atmel_sdhci_deferred_probe,
95 static int atmel_sdhci_probe(struct udevice *dev)
97 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
98 struct atmel_sdhci_plat *plat = dev_get_plat(dev);
99 struct sdhci_host *host = dev_get_priv(dev);
104 ret = clk_get_by_index(dev, 0, &clk);
108 ret = clk_enable(&clk);
112 host->name = dev->name;
113 host->ioaddr = dev_read_addr_ptr(dev);
115 host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
116 host->bus_width = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
119 ret = clk_get_by_index(dev, 1, &clk);
123 clk_set_rate(&clk, ATMEL_SDHC_GCK_RATE);
125 max_clk = clk_get_rate(&clk);
129 ret = clk_enable(&clk);
130 /* return error only if the clock really has a clock enable func */
131 if (ret && ret != -ENOSYS)
134 ret = mmc_of_parse(dev, &plat->cfg);
138 host->max_clk = max_clk;
139 host->mmc = &plat->mmc;
140 host->mmc->dev = dev;
142 ret = sdhci_setup_cfg(&plat->cfg, host, 0, ATMEL_SDHC_MIN_FREQ);
146 host->mmc->priv = host;
147 host->ops = &atmel_sdhci_ops;
148 upriv->mmc = host->mmc;
152 ret = sdhci_probe(dev);
156 atmel_sdhci_config_fcd(host);
161 static int atmel_sdhci_bind(struct udevice *dev)
163 struct atmel_sdhci_plat *plat = dev_get_plat(dev);
165 return sdhci_bind(dev, &plat->mmc, &plat->cfg);
168 static const struct udevice_id atmel_sdhci_ids[] = {
169 { .compatible = "atmel,sama5d2-sdhci" },
170 { .compatible = "microchip,sam9x60-sdhci" },
171 { .compatible = "microchip,sama7g5-sdhci" },
175 U_BOOT_DRIVER(atmel_sdhci_drv) = {
176 .name = "atmel_sdhci",
178 .of_match = atmel_sdhci_ids,
180 .bind = atmel_sdhci_bind,
181 .probe = atmel_sdhci_probe,
182 .priv_auto = sizeof(struct sdhci_host),
183 .plat_auto = sizeof(struct atmel_sdhci_plat),