1 // SPDX-License-Identifier: GPL-2.0+
3 * PCI emulation device which swaps the case of text
5 * Copyright (c) 2014 Google, Inc
6 * Written by Simon Glass <sjg@chromium.org>
14 #include <linux/ctype.h>
17 * struct swap_case_platdata - platform data for this device
19 * @command: Current PCI command value
20 * @bar: Current base address values
22 struct swap_case_platdata {
28 MEM_TEXT_SIZE = 0x100,
37 static struct pci_bar {
41 { PCI_BASE_ADDRESS_SPACE_IO, 1 },
42 { PCI_BASE_ADDRESS_MEM_TYPE_32, MEM_TEXT_SIZE },
49 struct swap_case_priv {
51 char mem_text[MEM_TEXT_SIZE];
54 static int sandbox_swap_case_use_ea(struct udevice *dev)
56 return !!ofnode_get_property(dev->node, "use-ea", NULL);
59 /* Please keep these macros in sync with ea_regs below */
60 #define PCI_CAP_ID_EA_SIZE (sizeof(ea_regs) + 4)
61 #define PCI_CAP_ID_EA_ENTRY_CNT 4
62 /* Hardcoded EA structure, excluding 1st DW. */
63 static const u32 ea_regs[] = {
64 /* BEI=0, ES=2, BAR0 32b Base + 32b MaxOffset, I/O space */
68 /* BEI=1, ES=2, BAR1 32b Base + 32b MaxOffset */
72 /* BEI=2, ES=3, BAR2 64b Base + 32b MaxOffset */
74 PCI_CAP_EA_BASE_LO2 | PCI_EA_IS_64,
77 /* BEI=4, ES=4, BAR4 64b Base + 64b MaxOffset */
79 PCI_CAP_EA_BASE_LO4 | PCI_EA_IS_64,
80 PCI_CAP_EA_SIZE_LO | PCI_EA_IS_64,
85 static int sandbox_swap_case_read_ea(struct udevice *emul, uint offset,
86 ulong *valuep, enum pci_size_t size)
90 offset = offset - PCI_CAP_ID_EA_OFFSET - 4;
91 reg = ea_regs[offset >> 2];
92 reg >>= (offset % 4) * 8;
98 static int sandbox_swap_case_read_config(struct udevice *emul, uint offset,
99 ulong *valuep, enum pci_size_t size)
101 struct swap_case_platdata *plat = dev_get_platdata(emul);
104 * The content of the EA capability structure is handled elsewhere to
105 * keep the switch/case below sane
107 if (offset > PCI_CAP_ID_EA_OFFSET + PCI_CAP_LIST_NEXT &&
108 offset < PCI_CAP_ID_EA_OFFSET + PCI_CAP_ID_EA_SIZE)
109 return sandbox_swap_case_read_ea(emul, offset, valuep, size);
113 *valuep = plat->command;
115 case PCI_HEADER_TYPE:
119 *valuep = SANDBOX_PCI_VENDOR_ID;
122 *valuep = SANDBOX_PCI_SWAP_CASE_EMUL_ID;
124 case PCI_CLASS_DEVICE:
125 if (size == PCI_SIZE_8) {
126 *valuep = SANDBOX_PCI_CLASS_SUB_CODE;
128 *valuep = (SANDBOX_PCI_CLASS_CODE << 8) |
129 SANDBOX_PCI_CLASS_SUB_CODE;
133 *valuep = SANDBOX_PCI_CLASS_CODE;
135 case PCI_BASE_ADDRESS_0:
136 case PCI_BASE_ADDRESS_1:
137 case PCI_BASE_ADDRESS_2:
138 case PCI_BASE_ADDRESS_3:
139 case PCI_BASE_ADDRESS_4:
140 case PCI_BASE_ADDRESS_5: {
144 barnum = pci_offset_to_barnum(offset);
145 bar = &plat->bar[barnum];
148 if (*bar == 0xffffffff) {
149 if (barinfo[barnum].type) {
150 result = (~(barinfo[barnum].size - 1) &
151 PCI_BASE_ADDRESS_IO_MASK) |
152 PCI_BASE_ADDRESS_SPACE_IO;
154 result = (~(barinfo[barnum].size - 1) &
155 PCI_BASE_ADDRESS_MEM_MASK) |
156 PCI_BASE_ADDRESS_MEM_TYPE_32;
159 debug("r bar %d=%x\n", barnum, result);
163 case PCI_CAPABILITY_LIST:
164 *valuep = PCI_CAP_ID_PM_OFFSET;
166 case PCI_CAP_ID_PM_OFFSET:
167 *valuep = (PCI_CAP_ID_EXP_OFFSET << 8) | PCI_CAP_ID_PM;
169 case PCI_CAP_ID_PM_OFFSET + PCI_CAP_LIST_NEXT:
170 *valuep = PCI_CAP_ID_EXP_OFFSET;
172 case PCI_CAP_ID_EXP_OFFSET:
173 *valuep = (PCI_CAP_ID_MSIX_OFFSET << 8) | PCI_CAP_ID_EXP;
175 case PCI_CAP_ID_EXP_OFFSET + PCI_CAP_LIST_NEXT:
176 *valuep = PCI_CAP_ID_MSIX_OFFSET;
178 case PCI_CAP_ID_MSIX_OFFSET:
179 if (sandbox_swap_case_use_ea(emul))
180 *valuep = (PCI_CAP_ID_EA_OFFSET << 8) | PCI_CAP_ID_MSIX;
182 *valuep = PCI_CAP_ID_MSIX;
184 case PCI_CAP_ID_MSIX_OFFSET + PCI_CAP_LIST_NEXT:
185 if (sandbox_swap_case_use_ea(emul))
186 *valuep = PCI_CAP_ID_EA_OFFSET;
190 case PCI_CAP_ID_EA_OFFSET:
191 *valuep = (PCI_CAP_ID_EA_ENTRY_CNT << 16) | PCI_CAP_ID_EA;
193 case PCI_CAP_ID_EA_OFFSET + PCI_CAP_LIST_NEXT:
196 case PCI_EXT_CAP_ID_ERR_OFFSET:
197 *valuep = (PCI_EXT_CAP_ID_VC_OFFSET << 20) | PCI_EXT_CAP_ID_ERR;
199 case PCI_EXT_CAP_ID_VC_OFFSET:
200 *valuep = (PCI_EXT_CAP_ID_DSN_OFFSET << 20) | PCI_EXT_CAP_ID_VC;
202 case PCI_EXT_CAP_ID_DSN_OFFSET:
203 *valuep = PCI_EXT_CAP_ID_DSN;
210 static int sandbox_swap_case_write_config(struct udevice *emul, uint offset,
211 ulong value, enum pci_size_t size)
213 struct swap_case_platdata *plat = dev_get_platdata(emul);
217 plat->command = value;
219 case PCI_BASE_ADDRESS_0:
220 case PCI_BASE_ADDRESS_1: {
224 barnum = pci_offset_to_barnum(offset);
225 bar = &plat->bar[barnum];
227 debug("w bar %d=%lx\n", barnum, value);
229 /* space indicator (bit#0) is read-only */
230 *bar |= barinfo[barnum].type;
238 static int sandbox_swap_case_find_bar(struct udevice *emul, unsigned int addr,
239 int *barnump, unsigned int *offsetp)
241 struct swap_case_platdata *plat = dev_get_platdata(emul);
244 for (barnum = 0; barnum < ARRAY_SIZE(barinfo); barnum++) {
245 unsigned int size = barinfo[barnum].size;
246 u32 base = plat->bar[barnum] & ~PCI_BASE_ADDRESS_SPACE;
248 if (addr >= base && addr < base + size) {
250 *offsetp = addr - base;
259 static void sandbox_swap_case_do_op(enum swap_case_op op, char *str, int len)
261 for (; len > 0; len--, str++) {
264 *str = toupper(*str);
267 *str = tolower(*str);
271 *str = tolower(*str);
273 *str = toupper(*str);
279 static int sandbox_swap_case_read_io(struct udevice *dev, unsigned int addr,
280 ulong *valuep, enum pci_size_t size)
282 struct swap_case_priv *priv = dev_get_priv(dev);
287 ret = sandbox_swap_case_find_bar(dev, addr, &barnum, &offset);
291 if (barnum == 0 && offset == 0)
292 *valuep = (*valuep & ~0xff) | priv->op;
297 static int sandbox_swap_case_write_io(struct udevice *dev, unsigned int addr,
298 ulong value, enum pci_size_t size)
300 struct swap_case_priv *priv = dev_get_priv(dev);
305 ret = sandbox_swap_case_find_bar(dev, addr, &barnum, &offset);
308 if (barnum == 0 && offset == 0)
314 static int pci_ea_bar2_magic = PCI_EA_BAR2_MAGIC;
315 static int pci_ea_bar4_magic = PCI_EA_BAR4_MAGIC;
317 static int sandbox_swap_case_map_physmem(struct udevice *dev,
318 phys_addr_t addr, unsigned long *lenp, void **ptrp)
320 struct swap_case_priv *priv = dev_get_priv(dev);
321 unsigned int offset, avail;
325 if (sandbox_swap_case_use_ea(dev)) {
327 * only support mapping base address in EA test for now, we
328 * don't handle mapping an offset inside a BAR. Seems good
329 * enough for the current test.
332 case (phys_addr_t)PCI_CAP_EA_BASE_LO0:
336 case (phys_addr_t)PCI_CAP_EA_BASE_LO1:
337 *ptrp = priv->mem_text;
338 *lenp = barinfo[1].size - 1;
340 case (phys_addr_t)((PCI_CAP_EA_BASE_HI2 << 32) |
341 PCI_CAP_EA_BASE_LO2):
342 *ptrp = &pci_ea_bar2_magic;
343 *lenp = PCI_CAP_EA_SIZE_LO;
345 case (phys_addr_t)((PCI_CAP_EA_BASE_HI4 << 32) |
346 PCI_CAP_EA_BASE_LO4):
347 *ptrp = &pci_ea_bar4_magic;
348 *lenp = (PCI_CAP_EA_SIZE_HI << 32) |
357 ret = sandbox_swap_case_find_bar(dev, addr, &barnum, &offset);
362 *ptrp = priv->mem_text + offset;
363 avail = barinfo[1].size - offset;
364 if (avail > barinfo[1].size)
367 *lenp = min(*lenp, (ulong)avail);
375 static int sandbox_swap_case_unmap_physmem(struct udevice *dev,
376 const void *vaddr, unsigned long len)
378 struct swap_case_priv *priv = dev_get_priv(dev);
380 sandbox_swap_case_do_op(priv->op, (void *)vaddr, len);
385 static struct dm_pci_emul_ops sandbox_swap_case_emul_ops = {
386 .read_config = sandbox_swap_case_read_config,
387 .write_config = sandbox_swap_case_write_config,
388 .read_io = sandbox_swap_case_read_io,
389 .write_io = sandbox_swap_case_write_io,
390 .map_physmem = sandbox_swap_case_map_physmem,
391 .unmap_physmem = sandbox_swap_case_unmap_physmem,
394 static const struct udevice_id sandbox_swap_case_ids[] = {
395 { .compatible = "sandbox,swap-case" },
399 U_BOOT_DRIVER(sandbox_swap_case_emul) = {
400 .name = "sandbox_swap_case_emul",
401 .id = UCLASS_PCI_EMUL,
402 .of_match = sandbox_swap_case_ids,
403 .ops = &sandbox_swap_case_emul_ops,
404 .priv_auto_alloc_size = sizeof(struct swap_case_priv),
405 .platdata_auto_alloc_size = sizeof(struct swap_case_platdata),
408 static struct pci_device_id sandbox_swap_case_supported[] = {
409 { PCI_VDEVICE(SANDBOX, SANDBOX_PCI_SWAP_CASE_EMUL_ID),
410 SWAP_CASE_DRV_DATA },
414 U_BOOT_PCI_DEVICE(sandbox_swap_case_emul, sandbox_swap_case_supported);