1 // SPDX-License-Identifier: GPL-2.0+
3 * PCI emulation device which swaps the case of text
5 * Copyright (c) 2014 Google, Inc
6 * Written by Simon Glass <sjg@chromium.org>
14 #include <linux/ctype.h>
17 * struct swap_case_platdata - platform data for this device
19 * @command: Current PCI command value
20 * @bar: Current base address values
22 struct swap_case_platdata {
28 MEM_TEXT_SIZE = 0x100,
37 static struct pci_bar {
41 { PCI_BASE_ADDRESS_SPACE_IO, 1 },
42 { PCI_BASE_ADDRESS_MEM_TYPE_32, MEM_TEXT_SIZE },
49 struct swap_case_priv {
51 char mem_text[MEM_TEXT_SIZE];
54 static int sandbox_swap_case_use_ea(struct udevice *dev)
56 return !!ofnode_get_property(dev->node, "use-ea", NULL);
59 /* Please keep these macros in sync with ea_regs below */
60 #define PCI_CAP_ID_EA_SIZE (sizeof(ea_regs) + 4)
61 #define PCI_CAP_ID_EA_ENTRY_CNT 4
62 /* Hardcoded EA structure, excluding 1st DW. */
63 static const u32 ea_regs[] = {
64 /* BEI=0, ES=2, BAR0 32b Base + 32b MaxOffset, I/O space */
68 /* BEI=1, ES=2, BAR1 32b Base + 32b MaxOffset */
72 /* BEI=2, ES=3, BAR2 64b Base + 32b MaxOffset */
74 PCI_CAP_EA_BASE_LO2 | PCI_EA_IS_64,
77 /* BEI=4, ES=4, BAR4 64b Base + 64b MaxOffset */
79 PCI_CAP_EA_BASE_LO4 | PCI_EA_IS_64,
80 PCI_CAP_EA_SIZE_LO | PCI_EA_IS_64,
85 static int sandbox_swap_case_read_ea(struct udevice *emul, uint offset,
86 ulong *valuep, enum pci_size_t size)
90 offset = offset - PCI_CAP_ID_EA_OFFSET - 4;
91 reg = ea_regs[offset >> 2];
92 reg >>= (offset % 4) * 8;
98 static int sandbox_swap_case_read_config(struct udevice *emul, uint offset,
99 ulong *valuep, enum pci_size_t size)
101 struct swap_case_platdata *plat = dev_get_platdata(emul);
104 * The content of the EA capability structure is handled elsewhere to
105 * keep the switch/case below sane
107 if (offset > PCI_CAP_ID_EA_OFFSET + PCI_CAP_LIST_NEXT &&
108 offset < PCI_CAP_ID_EA_OFFSET + PCI_CAP_ID_EA_SIZE)
109 return sandbox_swap_case_read_ea(emul, offset, valuep, size);
113 *valuep = plat->command;
115 case PCI_HEADER_TYPE:
119 *valuep = SANDBOX_PCI_VENDOR_ID;
122 *valuep = SANDBOX_PCI_SWAP_CASE_EMUL_ID;
124 case PCI_CLASS_DEVICE:
125 if (size == PCI_SIZE_8) {
126 *valuep = SANDBOX_PCI_CLASS_SUB_CODE;
128 *valuep = (SANDBOX_PCI_CLASS_CODE << 8) |
129 SANDBOX_PCI_CLASS_SUB_CODE;
133 *valuep = SANDBOX_PCI_CLASS_CODE;
135 case PCI_BASE_ADDRESS_0:
136 case PCI_BASE_ADDRESS_1:
137 case PCI_BASE_ADDRESS_2:
138 case PCI_BASE_ADDRESS_3:
139 case PCI_BASE_ADDRESS_4:
140 case PCI_BASE_ADDRESS_5: {
144 barnum = pci_offset_to_barnum(offset);
145 bar = &plat->bar[barnum];
147 *valuep = sandbox_pci_read_bar(*bar, barinfo[barnum].type,
148 barinfo[barnum].size);
151 case PCI_CAPABILITY_LIST:
152 *valuep = PCI_CAP_ID_PM_OFFSET;
154 case PCI_CAP_ID_PM_OFFSET:
155 *valuep = (PCI_CAP_ID_EXP_OFFSET << 8) | PCI_CAP_ID_PM;
157 case PCI_CAP_ID_PM_OFFSET + PCI_CAP_LIST_NEXT:
158 *valuep = PCI_CAP_ID_EXP_OFFSET;
160 case PCI_CAP_ID_EXP_OFFSET:
161 *valuep = (PCI_CAP_ID_MSIX_OFFSET << 8) | PCI_CAP_ID_EXP;
163 case PCI_CAP_ID_EXP_OFFSET + PCI_CAP_LIST_NEXT:
164 *valuep = PCI_CAP_ID_MSIX_OFFSET;
166 case PCI_CAP_ID_MSIX_OFFSET:
167 if (sandbox_swap_case_use_ea(emul))
168 *valuep = (PCI_CAP_ID_EA_OFFSET << 8) | PCI_CAP_ID_MSIX;
170 *valuep = PCI_CAP_ID_MSIX;
172 case PCI_CAP_ID_MSIX_OFFSET + PCI_CAP_LIST_NEXT:
173 if (sandbox_swap_case_use_ea(emul))
174 *valuep = PCI_CAP_ID_EA_OFFSET;
178 case PCI_CAP_ID_EA_OFFSET:
179 *valuep = (PCI_CAP_ID_EA_ENTRY_CNT << 16) | PCI_CAP_ID_EA;
181 case PCI_CAP_ID_EA_OFFSET + PCI_CAP_LIST_NEXT:
184 case PCI_EXT_CAP_ID_ERR_OFFSET:
185 *valuep = (PCI_EXT_CAP_ID_VC_OFFSET << 20) | PCI_EXT_CAP_ID_ERR;
187 case PCI_EXT_CAP_ID_VC_OFFSET:
188 *valuep = (PCI_EXT_CAP_ID_DSN_OFFSET << 20) | PCI_EXT_CAP_ID_VC;
190 case PCI_EXT_CAP_ID_DSN_OFFSET:
191 *valuep = PCI_EXT_CAP_ID_DSN;
198 static int sandbox_swap_case_write_config(struct udevice *emul, uint offset,
199 ulong value, enum pci_size_t size)
201 struct swap_case_platdata *plat = dev_get_platdata(emul);
205 plat->command = value;
207 case PCI_BASE_ADDRESS_0:
208 case PCI_BASE_ADDRESS_1: {
212 barnum = pci_offset_to_barnum(offset);
213 bar = &plat->bar[barnum];
215 debug("w bar %d=%lx\n", barnum, value);
217 /* space indicator (bit#0) is read-only */
218 *bar |= barinfo[barnum].type;
226 static int sandbox_swap_case_find_bar(struct udevice *emul, unsigned int addr,
227 int *barnump, unsigned int *offsetp)
229 struct swap_case_platdata *plat = dev_get_platdata(emul);
232 for (barnum = 0; barnum < ARRAY_SIZE(barinfo); barnum++) {
233 unsigned int size = barinfo[barnum].size;
234 u32 base = plat->bar[barnum] & ~PCI_BASE_ADDRESS_SPACE;
236 if (addr >= base && addr < base + size) {
238 *offsetp = addr - base;
247 static void sandbox_swap_case_do_op(enum swap_case_op op, char *str, int len)
249 for (; len > 0; len--, str++) {
252 *str = toupper(*str);
255 *str = tolower(*str);
259 *str = tolower(*str);
261 *str = toupper(*str);
267 static int sandbox_swap_case_read_io(struct udevice *dev, unsigned int addr,
268 ulong *valuep, enum pci_size_t size)
270 struct swap_case_priv *priv = dev_get_priv(dev);
275 ret = sandbox_swap_case_find_bar(dev, addr, &barnum, &offset);
279 if (barnum == 0 && offset == 0)
280 *valuep = (*valuep & ~0xff) | priv->op;
285 static int sandbox_swap_case_write_io(struct udevice *dev, unsigned int addr,
286 ulong value, enum pci_size_t size)
288 struct swap_case_priv *priv = dev_get_priv(dev);
293 ret = sandbox_swap_case_find_bar(dev, addr, &barnum, &offset);
296 if (barnum == 0 && offset == 0)
302 static int pci_ea_bar2_magic = PCI_EA_BAR2_MAGIC;
303 static int pci_ea_bar4_magic = PCI_EA_BAR4_MAGIC;
305 static int sandbox_swap_case_map_physmem(struct udevice *dev,
306 phys_addr_t addr, unsigned long *lenp, void **ptrp)
308 struct swap_case_priv *priv = dev_get_priv(dev);
309 unsigned int offset, avail;
313 if (sandbox_swap_case_use_ea(dev)) {
315 * only support mapping base address in EA test for now, we
316 * don't handle mapping an offset inside a BAR. Seems good
317 * enough for the current test.
320 case (phys_addr_t)PCI_CAP_EA_BASE_LO0:
324 case (phys_addr_t)PCI_CAP_EA_BASE_LO1:
325 *ptrp = priv->mem_text;
326 *lenp = barinfo[1].size - 1;
328 case (phys_addr_t)((PCI_CAP_EA_BASE_HI2 << 32) |
329 PCI_CAP_EA_BASE_LO2):
330 *ptrp = &pci_ea_bar2_magic;
331 *lenp = PCI_CAP_EA_SIZE_LO;
333 case (phys_addr_t)((PCI_CAP_EA_BASE_HI4 << 32) |
334 PCI_CAP_EA_BASE_LO4):
335 *ptrp = &pci_ea_bar4_magic;
336 *lenp = (PCI_CAP_EA_SIZE_HI << 32) |
345 ret = sandbox_swap_case_find_bar(dev, addr, &barnum, &offset);
350 *ptrp = priv->mem_text + offset;
351 avail = barinfo[1].size - offset;
352 if (avail > barinfo[1].size)
355 *lenp = min(*lenp, (ulong)avail);
363 static int sandbox_swap_case_unmap_physmem(struct udevice *dev,
364 const void *vaddr, unsigned long len)
366 struct swap_case_priv *priv = dev_get_priv(dev);
368 sandbox_swap_case_do_op(priv->op, (void *)vaddr, len);
373 static struct dm_pci_emul_ops sandbox_swap_case_emul_ops = {
374 .read_config = sandbox_swap_case_read_config,
375 .write_config = sandbox_swap_case_write_config,
376 .read_io = sandbox_swap_case_read_io,
377 .write_io = sandbox_swap_case_write_io,
378 .map_physmem = sandbox_swap_case_map_physmem,
379 .unmap_physmem = sandbox_swap_case_unmap_physmem,
382 static const struct udevice_id sandbox_swap_case_ids[] = {
383 { .compatible = "sandbox,swap-case" },
387 U_BOOT_DRIVER(sandbox_swap_case_emul) = {
388 .name = "sandbox_swap_case_emul",
389 .id = UCLASS_PCI_EMUL,
390 .of_match = sandbox_swap_case_ids,
391 .ops = &sandbox_swap_case_emul_ops,
392 .priv_auto_alloc_size = sizeof(struct swap_case_priv),
393 .platdata_auto_alloc_size = sizeof(struct swap_case_platdata),
396 static struct pci_device_id sandbox_swap_case_supported[] = {
397 { PCI_VDEVICE(SANDBOX, SANDBOX_PCI_SWAP_CASE_EMUL_ID),
398 SWAP_CASE_DRV_DATA },
402 U_BOOT_PCI_DEVICE(sandbox_swap_case_emul, sandbox_swap_case_supported);