2 * Copyright (C) 2013 Spreadtrum Communications Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 *************************************************
15 * Automatically generated C header: do not edit *
16 *************************************************
19 #ifndef __ANA_REGS_EFUSE_H__
20 #define __ANA_REGS_EFUSE_H__
22 #define ANA_REGS_EFUSE
24 /* registers definitions for controller ANA_REGS_EFUSE */
25 #define ANA_REG_EFUSE_GLB_CTRL SCI_ADDR(ANA_REGS_EFUSE_BASE, 0x0000)
26 #define ANA_REG_EFUSE_DATA_RD SCI_ADDR(ANA_REGS_EFUSE_BASE, 0x0004)
27 #define ANA_REG_EFUSE_DATA_WR SCI_ADDR(ANA_REGS_EFUSE_BASE, 0x0008)
28 #define ANA_REG_EFUSE_BLOCK_INDEX SCI_ADDR(ANA_REGS_EFUSE_BASE, 0x000c)
29 #define ANA_REG_EFUSE_MODE_CTRL SCI_ADDR(ANA_REGS_EFUSE_BASE, 0x0010)
30 #define ANA_REG_EFUSE_STATUS SCI_ADDR(ANA_REGS_EFUSE_BASE, 0x0014)
31 #define ANA_REG_EFUSE_WR_TIMING_CTRL SCI_ADDR(ANA_REGS_EFUSE_BASE, 0x0028)
32 #define ANA_REG_EFUSE_RD_TIMING_CTRL SCI_ADDR(ANA_REGS_EFUSE_BASE, 0x002c)
33 #define ANA_REG_EFUSE_EFUSE_DEB_CTRL SCI_ADDR(ANA_REGS_EFUSE_BASE, 0x0030)
35 /* bits definitions for register ANA_REG_EFUSE_GLB_CTRL */
36 /* Efuse SW programme enable.
38 #define BIT_EFUSE_PGM_EN ( BIT(0) )
39 /* Efuse type select, 00:TSMC, 01, 1x reserved.
41 #define BITS_EFUSE_TYPE(_x_) ( (_x_) << 1 & (BIT(1)|BIT(2)) )
43 /* bits definitions for register ANA_REG_EFUSE_DATA_RD */
44 #define BITS_EFUSE_DATA_RD(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
46 /* bits definitions for register ANA_REG_EFUSE_DATA_WR */
47 #define BITS_EFUSE_DATA_WR(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
49 /* bits definitions for register ANA_REG_EFUSE_BLOCK_INDEX */
50 #define BITS_READ_WRITE_INDEX(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
52 #define SHFT_READ_WRITE_INDEX ( 0 )
53 #define MASK_READ_WRITE_INDEX ( BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4) )
55 /* bits definitions for register ANA_REG_EFUSE_MODE_CTRL */
56 /* Write 1 to this bit start A_PGM mode(array PGM mode).
57 * This bit is self-clear, read this bit will always get 0.
59 #define BIT_PG_START ( BIT(0) )
60 #define BIT_RD_START ( BIT(1) )
61 #define BIT_STANDBY_START ( BIT(2) )
63 /* bits definitions for register ANA_REG_EFUSE_STATUS */
64 #define BIT_PGM_BUSY ( BIT(0) )
65 #define BIT_READ_BUSY ( BIT(1) )
66 #define BIT_STANDBY_BUSY ( BIT(2) )
68 /* bits definitions for register ANA_REG_EFUSE_WR_TIMING_CTRL */
69 #define BITS_EFUSE_WR_TIMING(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
71 /* bits definitions for register ANA_REG_EFUSE_RD_TIMING_CTRL */
72 #define BITS_EFUSE_RD_TIMING(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
74 /* bits definitions for register ANA_REG_EFUSE_EFUSE_DEB_CTRL */
75 #define BIT_MARGIN_MODE_EN ( BIT(1) )
76 #define BIT_DOUBLE_BIT_DISABLE ( BIT(0) )
78 /* vars definitions for controller ANA_REGS_EFUSE */
79 #define EFUSE_MAGIC_NUMBER ( 0x2723 )
81 #endif /* __ANA_REGS_EFUSE_H__ */